Semiconductor device and method of manufacturing the same, storage system

Abstract

The application provides a semiconductor device and a manufacturing method thereof, and a storage system. The method comprises the following steps: forming a plurality of channel lines extending along a first direction and a second direction in a semiconductor layer, wherein the first direction intersects the second direction; forming a plurality of first grooves and a plurality of second grooves extending along the first direction and arranged along the second direction in the semiconductor layer, wherein the plurality of first grooves and the plurality of second grooves intersect the plurality of channel lines, a plurality of channel structures are formed, the size of the first groove along the second direction is smaller than the size of the second groove along the second direction; and forming a conductive layer in the plurality of first grooves and the plurality of second grooves, removing part of the conductive layer, the remaining conductive layer in the plurality of first grooves forms a plurality of conductive shielding structures respectively, and the remaining conductive layer in the plurality of second grooves forms a plurality of gate lines respectively. The method can simplify the manufacturing process of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method, and a memory system. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is an important type of memory. A DRAM storage cell mainly consists of a storage capacitor and a transistor connected in series with the storage capacitor. The storage capacitor stores data, and the transistor controls the storage of data within the capacitor.

[0003] Currently, the manufacturing process of dynamic random access memory (DRAM) is complex, and how to simplify the manufacturing process of DRAM is a technical problem that needs to be solved. Summary of the Invention

[0004] The purpose of this application is to provide a semiconductor device and its manufacturing method, as well as a storage system, to simplify the manufacturing method of the semiconductor device.

[0005] In a first aspect, this application provides a method for manufacturing a semiconductor device, the method comprising:

[0006] Multiple channel lines extending along a first direction and a second direction are formed in the semiconductor layer, wherein the first direction intersects the second direction;

[0007] A plurality of first grooves and a plurality of second grooves extending along the first direction and arranged along the second direction are formed in the semiconductor layer. The plurality of first grooves and the plurality of second grooves intersect with a plurality of channel lines to form a plurality of channel structures. The dimension of the first groove along the second direction is smaller than the dimension of the second groove along the second direction.

[0008] Conductive layers are formed in a plurality of first grooves and a plurality of second grooves. A portion of the conductive layers is removed. The remaining conductive layers in the plurality of first grooves form a plurality of conductive shielding structures, and the remaining conductive layers in the plurality of second grooves form a plurality of gate lines.

[0009] In some embodiments of a semiconductor device manufacturing method, forming a plurality of first grooves and a plurality of second grooves extending along the first direction and arranged along the second direction in the semiconductor layer includes:

[0010] A plurality of first initial grooves and a plurality of second initial grooves are formed in the semiconductor layer, extending along the first direction and a third direction and alternately arranged along the second direction. In the third direction, the size of the first initial groove is smaller than the size of the second initial groove, and the third direction intersects the first direction and the second direction.

[0011] A sacrificial layer is filled in a plurality of first initial grooves and a plurality of second initial grooves;

[0012] The sacrificial layer in the plurality of second initial grooves is removed, and the dimensions of the second initial grooves along the first and second directions are enlarged to form a plurality of second grooves; and

[0013] The sacrificial layer in the plurality of first initial grooves is removed to form a plurality of first grooves.

[0014] In some embodiments of a method for manufacturing a semiconductor device, prior to removing the sacrificial layer from the plurality of second initial trenches, the method further includes:

[0015] Remove portions of the sacrificial layer from the plurality of the first initial grooves; and

[0016] A cover layer is formed on the remaining sacrificial layer in the plurality of first initial grooves.

[0017] In some embodiments of a method for manufacturing a semiconductor device, prior to removing portions of the sacrificial layer in a plurality of first initial trenches, the method further includes:

[0018] A protective layer is formed on one side of the semiconductor layer in the first direction, covering the sacrificial layer in a plurality of second initial grooves.

[0019] In some embodiments of a method for manufacturing a semiconductor device, prior to forming a conductive layer in a plurality of first trenches and a plurality of second trenches, the method further includes:

[0020] An isolation layer is formed in the first groove on the sidewall of the channel structure, and a gate insulating layer is formed in the second groove on the sidewall of the channel structure.

[0021] In some embodiments of a semiconductor device manufacturing method, forming a conductive layer in a plurality of first grooves and a plurality of second grooves includes:

[0022] A first conductive layer is formed that covers the isolation layer and fills the first groove, and covers the gate insulating layer in the second groove.

[0023] In some embodiments of a semiconductor device manufacturing method, forming a conductive layer in a plurality of first grooves and a plurality of second grooves includes:

[0024] A first conductive layer is formed that covers the isolation layer and fills the first groove, and covers the gate insulating layer in the second groove; and

[0025] A second conductive layer is formed in the second groove and covers the first conductive layer in the second groove, wherein the material of the second conductive layer is different from the material of the first conductive layer.

[0026] In some embodiments of a semiconductor device manufacturing method, forming a conductive layer in a plurality of first grooves and a plurality of second grooves includes:

[0027] Forming a first conductive layer covering the isolation layer in the first groove and the gate insulating layer in the second groove; and

[0028] A second conductive layer is formed that covers the first conductive layer in the first groove and fills the first groove, and covers the first conductive layer in the second groove, wherein the material of the second conductive layer is different from the material of the first conductive layer.

[0029] In some embodiments of a semiconductor device manufacturing method, after forming a plurality of second grooves and before forming a plurality of first grooves, the method further includes:

[0030] An insulating pad is formed at the bottom of the second groove. The insulating pad includes an insulating top surface away from the bottom surface of the second groove. In the first direction, the insulating top surface is located on the side of the bottom surface of the first initial groove near the opening of the first initial groove.

[0031] In some embodiments of a method for manufacturing a semiconductor device, the method further includes: forming lead-out conductive structures connected to a plurality of the conductive shielding structures.

[0032] Secondly, this application also provides a semiconductor device, comprising:

[0033] Multiple channel structures extending along a first direction;

[0034] Multiple gate lines extending along the first direction, with one gate line located between adjacent channel structures in a second direction, the second direction intersecting the first direction; and

[0035] A plurality of conductive shielding structures extending along the first direction, wherein the plurality of conductive shielding structures and the plurality of gate lines are spaced apart along the second direction, and in the second direction one of the conductive shielding structures is located between adjacent channel structures;

[0036] Wherein, the dimension of the conductive shielding structure along the second direction is less than twice the dimension of a gate line along the second direction.

[0037] In some embodiments of the semiconductor device, the semiconductor device further includes: an insulating pad portion located on one side of the gate line in the first direction and in contact with the gate line;

[0038] In the first direction, the conductive shielding structure includes a bottom conductive shielding surface and a top conductive shielding surface facing each other, with the bottom conductive shielding surface disposed close to the insulating pad. The gate line includes a bottom gate line surface that contacts the insulating pad, and the bottom conductive shielding surface is located on the side of the bottom gate line surface away from the top conductive shielding surface.

[0039] In some embodiments of the semiconductor device, the semiconductor device further includes: a gate insulating layer located between the gate line and the sidewall of the channel structure; and

[0040] An isolation layer is located between the conductive shielding structure and the sidewall of the channel structure. The thickness of the isolation layer is the same as the thickness of the gate insulating layer, and the material of the isolation layer is the same as that of the gate insulating layer.

[0041] In some embodiments of the semiconductor device, the conductive shielding structure includes a first conductive shielding layer, and the isolation layer is located between the first conductive shielding layer and the sidewall of the channel structure;

[0042] The gate line includes a first gate layer, and the gate insulating layer is located between the first gate layer and the sidewall of the channel structure. The material of the first gate layer is the same as the material of the first conductive shielding layer.

[0043] In some embodiments of the semiconductor device, the conductive shielding structure includes a first conductive shielding layer, and the isolation layer is located between the first conductive shielding layer and the sidewall of the channel structure;

[0044] The gate line includes a first gate layer and a second gate layer made of different materials. The first gate layer is located between the second gate layer and the sidewall of the channel structure. The gate insulating layer is located between the first gate layer and the sidewall of the channel structure. The material of the first gate layer is the same as the material of the first conductive shielding layer.

[0045] In some embodiments of the semiconductor device, the conductive shielding structure includes a first conductive shielding layer and a second conductive shielding layer made of different materials, the first conductive shielding layer being located between the second conductive shielding layer and the sidewall of the channel structure, and the isolation layer being located between the first conductive shielding layer and the sidewall of the channel structure;

[0046] The gate line includes a first gate layer and a second gate layer made of different materials. The first gate layer is located between the second gate layer and the sidewall of the channel structure. The gate insulating layer is located between the first gate layer and the sidewall of the channel structure. The material of the first gate layer is the same as the material of the first conductive shielding layer, and the material of the second gate layer is the same as the material of the second conductive shielding layer.

[0047] In some embodiments of the semiconductor device, the semiconductor device further includes: an exposed conductive structure connected to the conductive shielding structure.

[0048] Thirdly, this application also provides a storage system, comprising:

[0049] Memory, the memory including the semiconductor devices of any of the above embodiments; and

[0050] A controller, connected to the memory, is used to control the memory.

[0051] The beneficial effects of some embodiments of this application include: First, forming a plurality of first and second grooves intersecting with multiple channel lines, wherein the dimension of the first groove along the second direction is smaller than the dimension of the second groove along the second direction. Next, forming conductive layers in the plurality of first and second grooves. Finally, removing a portion of the conductive layer, the remaining conductive layer in the plurality of first grooves respectively forms a plurality of conductive shielding structures, and the remaining conductive layer in the plurality of second grooves respectively forms a plurality of gate lines. This manufacturing method, utilizing the dimensional difference between the first and second grooves, simultaneously manufactures conductive shielding structures and gate lines, simplifying the semiconductor device manufacturing process. Attached Figure Description

[0052] Figure 1 This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments of this application;

[0053] Figure 2A This is a schematic diagram of the planar structure of a semiconductor layer, a first insulating layer on the semiconductor layer, and a mask layer on the first insulating layer, according to some embodiments of this application.

[0054] Figure 2B For along Figure 2A A schematic diagram of the cross-sectional structure taken by the AA tangent;

[0055] Figure 3A This is a schematic diagram of a planar structure in which multiple channel lines and a first dielectric layer are formed in a semiconductor layer, as shown in some embodiments of this application.

[0056] Figure 3B For along Figure 3A A schematic diagram of the cross-sectional structure taken by the BB tangent;

[0057] Figure 4A This is a planar schematic diagram of a first initial groove and a second initial groove intersecting with multiple channel lines in some embodiments of this application;

[0058] Figure 4B For along Figure 4A A schematic diagram of the cross-sectional structure intercepted by the CC tangent;

[0059] Figure 4C This is a schematic plan view of the formation of a second insulating layer and a sacrificial layer in a first initial groove and a second initial groove in some embodiments of this application;

[0060] Figure 4D For along Figure 4C A schematic diagram of the cross-sectional structure taken by the DD tangent;

[0061] Figure 4E This is a schematic diagram of a planar structure in some embodiments of the present application, in which a protective layer is formed on the sacrificial layer in the second initial groove and a covering layer is formed on the remaining sacrificial layer in the first initial groove.

[0062] Figure 4F For along Figure 4E A schematic diagram of the cross-sectional structure taken by the EE tangent;

[0063] Figure 4G This is a cross-sectional schematic diagram showing the formation of a second groove and an insulating pad portion within the second groove in some embodiments of this application;

[0064] Figure 4H This is a schematic diagram of a planar structure formed by removing the sacrificial layer from a plurality of first initial grooves in some embodiments of this application;

[0065] Figure 4I For along Figure 4H A schematic diagram of the cross-sectional structure taken by the FF tangent;

[0066] Figure 5A This is a schematic diagram of a planar structure in which a conductive layer is formed in the first groove and the second groove in some embodiments of this application;

[0067] Figure 5B For along Figure 5A A schematic diagram of the cross-sectional structure taken by the GG tangent;

[0068] Figure 5C This is a planar schematic diagram showing the removal of a portion of the conductive layer in some embodiments of this application;

[0069] Figure 5D For along Figure 5C A schematic diagram of the cross-sectional structure taken by the HH tangent;

[0070] Figure 6A This is a cross-sectional schematic diagram of the conductive layer formed in the first and second grooves in some other embodiments of this application;

[0071] Figure 6B This is a cross-sectional view of a structure with a portion of the conductive layer removed in some other embodiments of this application;

[0072] Figure 7A This is a cross-sectional schematic diagram of the conductive layer formed in the first and second grooves in some other embodiments of this application;

[0073] Figure 7B This is a cross-sectional structural diagram showing the removal of a portion of the conductive layer in some other embodiments of this application;

[0074] Figure 8A This is a schematic diagram of a planar structure in some embodiments of this application in which a capacitor is formed and the second surface of the semiconductor layer is thinned;

[0075] Figure 8B For along Figure 8A A schematic diagram of the cross-sectional structure taken by the tangent of JJ in the diagram;

[0076] Figure 8C For along Figure 8A A schematic diagram of the cross-sectional structure obtained by the KK tangent;

[0077] Figure 9A This is a schematic diagram of the planar structure of a semiconductor device according to some embodiments of this application;

[0078] Figure 9B This is a schematic diagram of the cross-sectional structure taken along the LL tangent in Figure 9;

[0079] Figure 10 This is a block diagram of a storage system according to some embodiments of this application;

[0080] Figure 11 This is a block diagram of a storage system according to other embodiments of this application;

[0081] Figure 12 This is a block diagram of an electronic device according to some embodiments of this application.

[0082] The attached figures are labeled as follows:

[0083] z, first direction; y, second direction; x, third direction;

[0084] 11, Semiconductor layer; 11a, First surface; 11b, Second surface; 11c, Recess; 11d, Third surface; 112, Channel line; 113, Pillar semiconductor structure; 114, Channel structure;

[0085] 121, First insulating layer; 122, First dielectric layer; 123, Second insulating layer; 124, Sacrificial layer; 125, Protective layer; 126, Cover layer; 127, Isolation layer; 128, Gate insulating layer; 129, Second dielectric layer; 130, Third dielectric layer;

[0086] 131, Mask layer; 132, Mask pattern;

[0087] 141, First initial groove; 141a, Bottom surface of the first groove; 142, Second initial groove; 143, First groove; 143a, Bottom surface of the second groove; 144, Second groove;

[0088] 15, gate line; 151, first gate layer; 152, second gate layer; 15a, bottom surface of gate line; 15b, top surface of gate line;

[0089] 16, conductive shielding structure; 161, first conductive shielding layer; 16a, bottom surface of conductive shielding; 16b, top surface of conductive shielding.

[0090] 17, Insulating raised portion; 17a, Insulating top surface; 171, Insulating outer layer; 172, Insulating core;

[0091] 18, conductive layer; 181, first conductive layer; 182, second conductive layer; 18a, notch;

[0092] 191, First insulating filler portion; 192, Second insulating filler portion;

[0093] 201, First electrode; 202, Second electrode; 203, Connecting contact point; 204, Capacitor; 205 Lead-out conductive structure; 206, Isolation section;

[0094] 100, Semiconductor device; 200, Memory; 300, Controller; 400, Storage system; 500, Electronic device; 600, Host. Detailed Implementation

[0095] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0096] Please see Figure 1 The diagram shown is a flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments of this application. The method for manufacturing a semiconductor device includes the following steps:

[0097] Step S101: Form multiple channel lines extending along a first direction and a second direction in the semiconductor layer, wherein the first direction and the second direction intersect.

[0098] Step S102: A plurality of first grooves and a plurality of second grooves extending along a first direction and arranged along a second direction are formed in the semiconductor layer. The plurality of first grooves and the plurality of second grooves intersect with a plurality of channel lines to form a plurality of channel structures. The size of the first groove along the second direction is smaller than the size of the second groove along the second direction.

[0099] Step S103: A conductive layer is formed in a plurality of first grooves and a plurality of second grooves. Part of the conductive layer is removed. The remaining conductive layers in the plurality of first grooves form a plurality of conductive shielding structures, and the remaining conductive layers in the plurality of second grooves form a plurality of gate lines.

[0100] In some embodiments of this application, after forming a first groove and a second groove of different sizes, a conductive layer is formed in the first groove and the second groove, and then a portion of the conductive layer is removed. Simultaneously, a conductive shielding structure is formed in the first groove, and a gate line is formed in the second groove. This manufacturing method, which utilizes the dimensional difference between the first groove and the second groove in a second direction and simultaneously forms the gate line and the conductive shielding structure in one step, simplifies the manufacturing process of semiconductor devices.

[0101] In some related technologies, air gaps are provided between adjacent channel structures to improve the coupling effect between them. However, since the size of the air gaps is difficult to control, the uniformity of the size of multiple air gaps is difficult to control, and some air gaps may not meet the requirements for electrical isolation. In some embodiments of this application, the size of the conductive shielding structure obtained by the above method is easier to control, and it can better improve the coupling effect between adjacent channel structures.

[0102] The following describes in detail the manufacturing methods of semiconductor devices according to some embodiments of this application.

[0103] In some embodiments, see Figure 2A and Figure 2B As shown, before performing step S101 above, the semiconductor device manufacturing method further includes:

[0104] Provide semiconductor layer 11; and

[0105] A first insulating layer 121 is formed on the semiconductor layer 11.

[0106] The semiconductor layer 11 includes a first surface 11a and a second surface 11b opposite each other in the first direction z. The material of the semiconductor layer 11 includes, but is not limited to, elemental semiconductor materials such as single-crystal silicon. Specifically, the semiconductor layer 11 includes a silicon wafer.

[0107] A first insulating layer 121 is disposed on the first surface 11a of the semiconductor layer 11. During the processing of the semiconductor layer 11, the first insulating layer 121 protects the semiconductor layer 11. The material of the first insulating layer 121 includes, but is not limited to, insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. Specifically, the material of the first insulating layer 121 includes silicon oxide to ensure that it can better adhere to the semiconductor layer 11.

[0108] In some embodiments, please continue reading Figure 2A and Figure 2B As shown, after forming a first insulating layer 121 on the semiconductor layer 11, the method for manufacturing a semiconductor device further includes forming a mask layer 131 on the surface of the first insulating layer 121 away from the semiconductor layer 11.

[0109] The material of the mask layer 131 may include at least one of inorganic insulating materials and organic insulating materials. Inorganic insulating materials include, but are not limited to, silicon nitride. Organic insulating materials include, but are not limited to, photoresist.

[0110] Next, refer to Figure 3A and Figure 3B As shown, by performing the above step S101, multiple channel lines 112 extending along the first direction z and the second direction y are formed in the semiconductor layer 11, and the first direction z intersects the second direction y.

[0111] In some embodiments, forming multiple channel lines 112 extending along a first direction z and a second direction y in the semiconductor layer 11 includes forming multiple recesses 11c in the semiconductor layer 11, and the remaining semiconductor layer 11 includes multiple channel lines 112.

[0112] Multiple recesses 11c are recessed from the first surface 11a toward the second surface 11b. The multiple recesses 11c also extend along the second direction y and are spaced apart along the third direction x, which intersects the second direction y. The depth of the recesses 11c in the semiconductor layer 11 is less than the thickness of the semiconductor layer 11. The cross-sectional shape of the multiple recesses 11c parallel to the first direction z and the third direction x can be rectangular or inverted trapezoidal.

[0113] Multiple channel lines 112 are arranged at intervals along the third direction x. A channel line 112 is located between two adjacent recesses 11c. The shape of the cross section of the channel line 112 parallel to the first direction z and the third direction x can be rectangular or trapezoidal.

[0114] The first direction z is the thickness direction of the semiconductor layer 11, but it is not limited to this. The angle between the first direction z and the thickness direction of the semiconductor layer 11 can also be an acute angle. The first direction z is perpendicular to both the second direction y and the third direction x, but it is not limited to this. The second direction y is perpendicular to the third direction x, but it is not limited to this. The angle between the second direction y and the third direction x can also be an obtuse angle or an acute angle.

[0115] In some embodiments, forming a plurality of recesses 11c in the semiconductor layer 11 includes: patterning the mask layer 131 to obtain a mask pattern 132; and

[0116] Using the mask pattern 132 as a mask, a portion of the first insulating layer 121 and a portion of the semiconductor layer 11 are removed to form a plurality of recesses 11c. The plurality of recesses 11c penetrate the first insulating layer 121 along the first direction z and extend into the semiconductor layer 11.

[0117] In some embodiments, please continue reading Figure 3A and Figure 3B As shown, after forming a plurality of recesses 11c in the semiconductor layer 11, the method for manufacturing a semiconductor device further includes forming a first dielectric layer 122 in the plurality of recesses 11c.

[0118] Specifically, forming a first dielectric layer in the plurality of recesses 11c includes: forming a first initial dielectric layer that fills the plurality of recesses 11c and covers the mask pattern 132; and

[0119] The first initial dielectric layer on the mask pattern 132 is removed, and the remaining first initial dielectric layer constitutes the first dielectric layer 122.

[0120] For example, chemical mechanical polishing is used to remove the first initial dielectric layer on the mask pattern 132, but it is not limited thereto.

[0121] In some embodiments, the material of the first dielectric layer 122 includes, but is not limited to, insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0122] Next, refer to Figures 4A to 4I As shown, by performing the above step S102, a plurality of first grooves 143 and a plurality of second grooves 144 extending along the first direction z and arranged along the second direction y are formed in the semiconductor layer 11. The plurality of first grooves 143 and the plurality of second grooves 144 intersect with a plurality of channel lines 112 to form a plurality of channel structures 114. The size of the first groove 143 along the second direction y is smaller than the size of the second groove 144 along the second direction y.

[0123] In some embodiments, see Figures 4A to 4IAs shown, forming a plurality of first grooves 143 and a plurality of second grooves 144 extending along a first direction z and arranged along a second direction y in the semiconductor layer 11 includes:

[0124] A plurality of first initial grooves 141 and a plurality of second initial grooves 142 are formed in the semiconductor layer 11, extending along a first direction z and a third direction x, and alternately arranged along a second direction y. The size of the first initial groove 141 in the third direction x is smaller than the size of the second initial groove 142.

[0125] A sacrificial layer 124 is filled in a plurality of first initial grooves 141 and a plurality of second initial grooves 142;

[0126] The sacrificial layer 124 in the plurality of second initial grooves 142 is removed, and the dimensions of the second initial grooves 142 along the first direction z and the second direction y are enlarged to form a plurality of second grooves 144; and

[0127] The sacrificial layer 124 in the plurality of first initial grooves 141 is removed to form a plurality of first grooves 143.

[0128] In some embodiments, see Figure 4A and Figure 4B As shown, forming a plurality of first initial grooves 141 and a plurality of second initial grooves 142 extending along a first direction z and a third direction x and alternating along a second direction y in a semiconductor layer 11 includes: removing a portion of a first dielectric layer 122 and a portion of a channel line 112 to form a plurality of first initial grooves 141 and a plurality of second initial grooves 142 extending along the first direction z and a third direction x and alternating along the second direction x, the remaining channel line 112 including a plurality of columnar semiconductor structures 113, and both the first initial grooves 141 and the second initial grooves 142 being recessed from the first surface 11a to the second surface 11b.

[0129] The first initial groove 141 and the second initial groove 142 both intersect with the channel line 112, and the multiple first initial grooves 141 and the multiple second initial grooves 142 are alternately arranged in a one-to-one manner along the second direction y.

[0130] In the third direction x, the size of the first initial groove 141 is smaller than the size of the second initial groove 142, and the two ends of the second initial groove 142 protrude from the first initial groove 141 in the third direction x. With this design, when the first initial groove 141 is processed to obtain the first groove 143 (hereinafter referred to as the first groove), and the second initial groove 142 is processed to obtain the second groove 144 (hereinafter referred to as the second groove), the size of the first groove 143 in the third direction x is smaller than the size of the second groove 144 in the third direction x. Correspondingly, the size of the gate line 15 formed in the second groove 144 in the third direction x is larger than the size of the conductive shielding structure 16 formed in the first groove 143 in the third direction x.

[0131] The first initial groove 141 and the second initial groove 142 have the same dimensions along the second direction y, and the first initial groove 141 and the second initial groove 142 have the same depth along the first direction x, so as to facilitate the simultaneous manufacture of the first initial groove 141 and the second initial groove 142, thereby simplifying the manufacturing process of semiconductor devices.

[0132] In some embodiments, see Figure 4C and Figure 4D As shown, a second insulating layer 123 is formed on the sidewall of the columnar semiconductor structure 113. The second insulating layer 123 repairs the sidewall of the columnar semiconductor structure 113. The material of the second insulating layer 123 includes insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0133] For example, silicon on the sidewalls of the columnar semiconductor structure 113 is oxidized under oxygen atmosphere and heating conditions to form a second insulating layer 123; or, a thin film deposition process is used to form the second insulating layer 123 in the sidewalls of the first initial groove 141 and the sidewalls of the second initial groove 142.

[0134] In some embodiments, please continue reading Figure 4C and Figure 4D As shown, the method for manufacturing a semiconductor device further includes filling a sacrificial layer 124 into a plurality of first initial grooves 141 and a plurality of second initial grooves 142. The material of the sacrificial layer 124 includes, but is not limited to, spin-on carbon (SOC).

[0135] In some embodiments, see Figure 4E and Figure 4F As shown, after filling the sacrificial layer 124 in the plurality of first initial grooves 141 and the plurality of second initial grooves 142, the method of manufacturing a semiconductor device further includes forming a protective layer 125 covering the sacrificial layer 124 in the plurality of second initial grooves 142 on one side of the semiconductor layer 11 in the first direction z.

[0136] The protective layer 125 protects the sacrificial layer 124 in the second initial groove 142. The materials of the protective layer 125 include, but are not limited to, organic and inorganic insulating materials. Organic insulating materials include, but are not limited to, photoresist. Inorganic insulating materials include, but are not limited to, silicon nitride.

[0137] In some embodiments, please continue to refer to Figure 4E and Figure 4F As shown, after forming the protective layer 125, the method for manufacturing the semiconductor device further includes: removing a portion of the sacrificial layer 124 in a plurality of first initial grooves 141; and forming a cover layer 126 on the remaining sacrificial layer 124 in the plurality of first initial grooves 141.

[0138] In some embodiments, the material of the cover layer 126 is the same as the material of the mask layer 131. In other embodiments, the material of the cover layer 126 may be different from the material of the mask layer 131. In some embodiments, the material of the cover layer 126 includes, but is not limited to, silicon nitride, silicon oxide, or silicon oxynitride.

[0139] It should be noted that, since the protective layer 125 protects the sacrificial layer 124 in the second initial groove 142, the sacrificial layer 124 in the second initial groove 142 will not be affected during the removal of some of the sacrificial layers 124 in the multiple first initial grooves 141. Furthermore, when removing the sacrificial layer 124 in the second initial groove 142, the covering layer 126 protects the remaining sacrificial layer 124 in the first initial groove 141, and the remaining sacrificial layer 124 in the first initial groove 141 will not be affected.

[0140] In some embodiments, see Figure 4G As shown, the sacrificial layer 124 in the plurality of second initial grooves 142 is removed, and the size of the second initial grooves 142 along the first direction z and the second direction y is enlarged to form a plurality of second grooves 144, and the remaining semiconductor layer 11 includes a plurality of channel structures 114.

[0141] Specifically, the protective layer 125 is removed, and then the sacrificial layer 124 in the plurality of second initial grooves 142 is removed. Next, a portion of the first dielectric layer 122 and a portion of the columnar semiconductor structure 113 are removed to form a plurality of second grooves 144, and the remaining columnar semiconductor structure 113 forms a channel structure 114.

[0142] In other embodiments, while increasing the size of the second initial groove 142 along the first direction z and the second direction y, the size of the second initial groove 142 along the third direction x can also be increased simultaneously to form a plurality of second grooves 144.

[0143] In some embodiments, a plurality of channel structures 114 extend along a first direction z and are arranged in an array along a second direction y and a third direction x.

[0144] In some embodiments, please continue reading Figure 4G As shown, after forming a plurality of second grooves 144 and before removing the sacrificial layer 124 in a plurality of first initial grooves 141, the method of manufacturing a semiconductor device further includes: forming an insulating pad 17 at the bottom of the plurality of second grooves 144, the insulating pad 17 including an insulating top surface 17a away from the bottom surface of the second groove 144, the insulating top surface 17a being located on the side of the first bottom surface 141a of the first initial groove 141 near the opening of the first initial groove 141 in the first direction z.

[0145] The insulating pad 17 isolates the semiconductor layer 11 from the gate line 15. Furthermore, by adjusting the height of the insulating pad 17, the dimensions of the gate line 15 in the first direction z can be controlled. Additionally, by ensuring that the insulating top surface 17a includes a plane, it can be guaranteed that the gate line 15 is formed on a plane, thereby ensuring that the dimensions of the gate line 15 in the first direction z are controllable.

[0146] In some embodiments of this application, the insulating top surface 17a in the first direction z is located on the side of the bottom surface 141a of the first initial groove 141 near the opening of the first initial groove 141. This design allows the gate line 15 formed on the insulating raised portion 17 to have a smaller dimension in the first direction z than the conductive shielding structure 16 in the first direction z, further ensuring the improved coupling effect of the conductive shielding structure 16 between adjacent channel structures.

[0147] In some embodiments, the insulating pad 17 includes an insulating outer layer 171 and an insulating core 172, the insulating outer layer 171 covering the sidewalls and bottom surface of the insulating core 172. The insulating outer layer 172 is located at the bottom of the second groove 144 and on the sidewalls of the second groove 144. The material of the insulating outer layer 172 is different from the material of the insulating core 172. Exemplarily, the material of the insulating outer layer 172 includes silicon oxide, and the material of the insulating core 172 includes silicon nitride, but is not limited thereto. In other embodiments, the insulating pad 17 may also include only the insulating core 172.

[0148] In some embodiments, see Figure 4H and Figure 4I As shown, after the insulating pad 17 is formed, the sacrificial layer 124 in the plurality of first initial grooves 141 is removed to form a plurality of first grooves 143.

[0149] Specifically, the cover layer 126 and the remaining sacrificial layer 124 located in the plurality of first initial grooves 141 are removed to form a plurality of first grooves 143.

[0150] In some embodiments of this application, the second initial groove 142 is widened to form a second groove 144. The sacrificial layer 124 in a plurality of first initial grooves 141 is removed to form a plurality of first grooves 143. Through this method, a plurality of second grooves 144 and a plurality of first grooves 143 are alternately arranged along the second direction y. The dimension of the second groove 144 along the first direction z is larger than the dimension of the first groove 143 along the first direction z; the dimension of the second groove 144 along the second direction y is larger than the dimension of the first groove 143 along the first direction z; and the dimension of the second groove 144 along the third direction x is also larger than the dimension of the first groove 143 along the third direction x.

[0151] In some embodiments, see Figure 4I As shown, in the first direction z, the distance d between the insulating top surface 17a of the insulating pad 17 and the second bottom surface 143a of the first groove 143 is greater than or equal to 70 nanometers and less than or equal to 100 nanometers. With this design, the bottom surface 15a of the gate line 15 that contacts the insulating pad 17 is located above the bottom surface 16a of the conductive shielding structure 16. When the gate voltage applied by the gate line 15 acts on the channel structure 114, the conductive shielding structure 16 can better shield the coupling effect between adjacent channel structures 114 in the second direction y.

[0152] In some embodiments, please refer to Figure 5A and Figure 5B As shown, before forming conductive layers in the plurality of first grooves 143 and the plurality of second grooves 144, the method of manufacturing a semiconductor device further includes: forming an isolation layer 127 in the first grooves 143 on the sidewall of the channel structure 114, and forming a gate insulating layer 128 in the second grooves 144 on the sidewall of the channel structure 114.

[0153] The isolation layer 127 serves to isolate the channel structure 114 from the conductive shielding structure 16. The gate insulating layer 128 serves to isolate the channel structure 114 from the gate line 15.

[0154] In some embodiments, the material of the isolation layer 127 is the same as that of the gate insulating layer 128, and the thickness of the isolation layer 127 is the same as that of the gate insulating layer 128. With this design, the isolation layer 127 and the gate insulating layer 128 can be formed in one step, further simplifying the manufacturing process of the semiconductor device.

[0155] In some embodiments, the sidewalls of the channel structure 114 may be oxidized to form an isolation layer 127 and a gate insulating layer 128, respectively. In other embodiments, insulating layers may also be deposited on the sidewalls of the first groove 143 and the second groove 144 using a thin-film deposition process to form the isolation layer 127 and the gate insulating layer 128, respectively.

[0156] Finally, see Figures 5A to 5D , Figure 6A and Figure 6B as well as Figure 7A and Figure 7B As shown, in step S103, conductive layers 18 are formed in multiple first grooves 143 and multiple second grooves 144. Part of the conductive layers 18 are removed. The remaining conductive layers 18 in the multiple first grooves 143 form multiple conductive shielding structures 16, and the remaining conductive layers 18 in the multiple second grooves 144 form multiple gate lines 15.

[0157] In some embodiments, see Figure 5A and Figure 5B As shown, forming a conductive layer in a plurality of first grooves 143 and a plurality of second grooves 144 includes: forming a first conductive layer 181 that covers the insulating layer 127 and fills the first grooves 143, and covers the gate insulating layer 128 in the second grooves 144 and the sidewalls of the second grooves 144; and

[0158] A second conductive layer 182 is formed in the second groove 144 and covers the first conductive layer 181 in the second groove 144. The material of the second conductive layer 182 is different from the material of the first conductive layer 181.

[0159] In some embodiments of this application, the dimension of the first groove 143 along the second direction y is smaller than the dimension of the second groove 144 along the second direction y. Therefore, during the formation of the first conductive layer 181, while the first conductive layer 181 fills the first groove 143, there are still gaps in the second groove 144 where the first conductive layer 181 is formed, that is, the second groove 144 is not completely filled.

[0160] In some embodiments, the materials of the first conductive layer 181 and the second conductive layer 182 include metallic and non-metallic conductive materials. Metals include, but are not limited to, tungsten, cobalt, copper, nickel, and their alloys. Non-metallic conductive materials include, but are not limited to, titanium nitride.

[0161] For example, the material of the first conductive layer 181 includes titanium nitride, and the material of the second conductive layer 182 includes tungsten. With this design, both the second conductive layer 182 and the first conductive layer 181 are conductive, so as to ensure the conductivity of the gate line 15 and the conductive shielding structure 16, while the first conductive layer 181 prevents the second conductive layer 182 from diffusing into the channel structure 114.

[0162] In some embodiments, see Figure 5C and Figure 5D As shown, removing part of the conductive layer 18 includes: removing the conductive layer 18 outside the first groove 143 and the second groove 144, and removing part of the conductive layer 18 in the first groove 143 and the second groove 144, the remaining conductive layer 18 in the first groove 143 forming a conductive shielding structure 16; and forming a notch 18a on the remaining conductive layer 18 in the second groove 144, and forming two gate lines 15 in the second groove 144.

[0163] In some embodiments, please continue reading Figure 5C and Figure 5D As shown, gate line 15 includes a first gate layer 151 and a second gate layer 152 made of different materials, and conductive shielding structure 16 includes a first conductive shielding layer 161. The first gate layer 151 is located between the second gate layer 152 and the sidewall of the channel structure 114. A gate insulating layer 128 is located between the first gate layer 151 and the sidewall of the channel structure 114. An isolation layer 127 is located between the first conductive shielding layer 161 and the sidewall of the channel structure 114. The material of the first gate layer 151 is the same as the material of the first conductive shielding layer 161. The dimension of the first conductive shielding layer 161 along the second direction y is less than or equal to twice the dimension of the first gate layer 151 along the second direction y.

[0164] In other embodiments, see Figure 6A As shown, forming a conductive layer 18 in a plurality of first grooves 143 and a plurality of second grooves 144 includes forming a first conductive layer 181 that covers an isolation layer 127 and fills the first grooves 143 and covers the gate insulating layer 128 in the second grooves 144.

[0165] In other embodiments, see Figure 6B As shown, gate line 15 includes a first gate layer 151, and conductive shielding structure 16 includes a first conductive shielding layer 161. Gate insulating layer 128 is located between the first gate layer 151 and the sidewall of channel structure 114. Isolation layer 127 is located between the first conductive shielding layer 161 and the sidewall of channel structure 114. The material of the first gate layer 151 is the same as the material of the first conductive shielding layer 161. The dimension of the first conductive shielding layer 161 along the second direction y is less than twice the dimension of the first gate layer 151 along the second direction y.

[0166] In some other embodiments, see [reference] Figure 7AAs shown, forming a conductive layer 18 in a plurality of first recesses 143 and a plurality of second recesses 144 includes: forming a first conductive layer 181 covering the isolation layer 127 in the first recesses 143 and the sidewalls of the first recesses 143, and the gate insulating layer 128 in the second recesses 144 and the sidewalls of the second recesses 144; and

[0167] A second conductive layer 182 is formed to cover and fill the first conductive layer 181 in the first groove 143 and to cover the first conductive layer 181 in the second groove 144. The material of the second conductive layer 182 is different from the material of the first conductive layer 181.

[0168] In some other embodiments, see [reference] Figure 7B As shown, gate line 15 includes a first gate layer 151 and a second gate layer 152 made of different materials, and conductive shielding structure 16 includes a first conductive shielding layer 161 and a second conductive shielding layer 162 made of different materials. The first gate layer 151 is located between the second gate layer 152 and the sidewall of the channel structure 114. A gate insulating layer 128 is located between the first gate layer 151 and the sidewall of the channel structure 114. The first conductive shielding layer 161 is located between the second conductive shielding layer 162 and the sidewall of the channel structure 114. An isolation layer 127 is located between the first conductive shielding layer 161 and the sidewall of the channel structure 114. The material of the first gate layer 151 is the same as the material of the first conductive shielding layer 161. The material of the second gate layer 152 is the same as the material of the second conductive shielding layer 162. The dimension of the first conductive shielding layer 161 along the second direction y is equal to twice the dimension of the first gate layer 151 along the second direction y, and the dimension of the second conductive shielding layer 162 along the second direction y is less than twice the dimension of the second gate layer 152 along the second direction y.

[0169] In some other embodiments of this application, if the first conductive layer 181 cannot fill the first groove 143, the second conductive layer 182 can be used to continue filling the first groove 143.

[0170] In some embodiments of this application, combined with Figure 5D , Figure 6B as well as Figure 7B It can be seen that the dimension of the conductive shielding structure 16 along the second direction y is less than twice the dimension of a gate line 15 along the second direction y.

[0171] See Figure 5D , Figure 6B as well as Figure 7BAs shown, the gate line 15 includes a bottom surface 15a and a top surface 15b opposite each other in the first direction z. The bottom surface 15a and the top surface 15b are planar, allowing for greater controllability of the gate line 15's dimensions in the first direction z. The bottom surface 15a contacts the insulating pad 17. The conductive shielding structure 16 includes a conductive shielding bottom surface 16a and a conductive shielding top surface 16b opposite each other in the first direction z, with the bottom surface 16a disposed near the insulating pad 17. The bottom surface 16a is curved, and the top surface 16b is planar.

[0172] In some embodiments, the top surface 15b of the gate line and the top surface 16b of the conductive shield are flush in the second direction y, so as to simultaneously form the gate line 15 and the conductive shield structure 16 after removing part of the conductive layer in one step, thereby simplifying the manufacturing process of the semiconductor device.

[0173] It should be noted that, in this application, the alignment of the top surface 15b of the gate line with the top surface 16b of the conductive shield is within a certain error range.

[0174] In some embodiments, in the first direction z, the bottom end face 15a of the gate line is located between the bottom end face 16a and the top end face 16b of the conductive shield. With this design, when the gate voltage output from the gate line 15 acts on the channel structure 114, the area of ​​action of the gate voltage on the channel structure 114 can be covered by the conductive shield structure 16, ensuring that the conductive shield structure 16 can better improve the coupling effect between adjacent channel structures 114 in the second direction.

[0175] In some embodiments, the size of the gate line 15 in the first direction z is greater than or equal to 100 nanometers and less than or equal to 200 nanometers.

[0176] In some embodiments, please continue reading Figure 5D , Figure 6B as well as Figure 7B As shown, after forming the gate line 15 and the conductive shielding structure 16, the method for manufacturing the semiconductor device further includes: forming a first insulating filler portion 191 that covers the gate line 15 and fills the second groove 144, and forming a second insulating filler portion 192 that covers the conductive shielding structure 16 and fills the first groove 143.

[0177] In some embodiments of this application, the first insulating filler portion 191 and the second insulating filler portion 192 are formed in one step, further simplifying the manufacturing process of semiconductor devices.

[0178] In some embodiments, the materials of the first insulating filler portion 191 and the second insulating filler portion 192 include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0179] In some embodiments, see Figure 8A and Figure 8B As shown, after forming the first insulating fill portion 191 and the second insulating fill portion 192, the semiconductor device manufacturing method further includes: performing ion implantation on one end of the channel structure 114 away from the bottom end face 15a of the gate line to form a first electrode 201.

[0180] In some embodiments, please continue reading Figure 8A and Figure 8B As shown, the method for manufacturing a semiconductor device further includes: forming a connection contact 203 connected to the first electrode 201; forming a capacitor 204 connected to the first electrode 201; and filling a second dielectric layer 129 between the plurality of capacitors 204.

[0181] In some embodiments, see Figures 8A to 8C As shown, the method for manufacturing a semiconductor device further includes: thinning the second surface 11b of the semiconductor layer 11 to expose the first dielectric layer 122 and forming a third surface 11d; and performing ion implantation on the end of the channel structure 114 away from the first electrode 201 to form a second electrode 202.

[0182] It should be noted that one of the first electrode 201 and the second electrode 202 is the source electrode, and the other of the first electrode 201 and the second electrode 202 is the drain electrode.

[0183] In some embodiments, see Figure 9A and Figure 9B As shown, the method for manufacturing a semiconductor device further includes: forming a lead-out conductive structure 205 connected to a plurality of conductive shielding structures 16; and forming an isolation portion 206 located between the lead-out conductive structure 205 and the channel structure 114.

[0184] In some embodiments of this application, the lead-out conductive structure 205 is grounded, or a negative potential is applied to the lead-out conductive structure 205, so that the conductive shielding structure 16 connected to the lead-out conductive structure 205 is also grounded or a negative potential is applied, and the conductive shielding structure 16 plays a shielding role against the coupling effect between adjacent channel structures 114 in the second direction.

[0185] The isolation section 206 serves to isolate the conductive lead-out structure 205 from the second electrode 202.

[0186] In some embodiments, please continue reading Figure 9A and Figure 9B As shown, a third dielectric layer 130 is formed covering the conductive structure 205.

[0187] Based on the same inventive concept, this application also provides a semiconductor device 100 manufactured by the above method. (See also...) Figure 9A and Figure 9B As shown, the semiconductor device 100 includes multiple channel structures 114, multiple gate lines 15, multiple conductive shielding structures 16, a capacitor 204, an isolation layer 127, a gate insulating layer 128, and a lead-out conductive structure 205.

[0188] Multiple channel structures 114 extend along a first direction z and are arranged in an array along a second direction y and a third direction x. Any two of the first direction z, the second direction y, and the third direction x intersect each other. Specifically, the first direction z is perpendicular to the second direction y and the third direction x, and the second direction y is perpendicular to the third direction x, but is not limited thereto.

[0189] Each channel structure 114 has a first electrode 201 and a second electrode 202 respectively disposed at opposite ends in the first direction z. One of the first electrode 201 and the second electrode 202 is the source electrode, and the other of the first electrode 201 and the second electrode 202 is the drain electrode.

[0190] Multiple gate lines 15 extend along a first direction z and a third direction x, and are spaced apart along a second direction y. Each gate line 15 includes a bottom end face 15a and a top end face 15b opposite each other in the first direction z. A gate insulating layer 128 is located between the gate lines 15 and the sidewalls of the channel structure 114.

[0191] In some embodiments, two spaced gate lines 15 are provided between two adjacent rows of channel structures 114 in the second direction y. In other embodiments, only one gate line 15 may be provided between two adjacent rows of channel structures 114 in the second direction y.

[0192] Multiple conductive shielding structures 16 extend along a first direction z and a third direction x, and are spaced apart along a second direction y. The multiple conductive shielding structures 16 and multiple gate lines 15 are spaced apart along the second direction y. In the second direction y, one conductive shielding structure 16 is located between two adjacent rows of channel structures 114, and one conductive shielding structure 16 is located on the side of the adjacent channel structure 114 facing away from the gate line 115. In the first direction z, the conductive shielding structure 16 includes opposing conductive shielding bottom surface 16a and conductive shielding top surface 16b. An isolation layer 127 is located between the conductive shielding structures 16 and the sidewalls of the channel structures 114.

[0193] In some embodiments, the dimension of the conductive shielding structure 16 along the second direction y is less than twice the dimension of a gate line 15 along the second direction y, that is, the thickness of the conductive shielding structure 16 along the second direction is less than twice the thickness of a gate line 15 along the second direction y. With this design, based on the formation of the aforementioned differentiated first and second grooves, the conductive shielding structure 16 and the gate line 15 can be formed simultaneously in one step, simplifying the manufacturing process of the semiconductor device 100.

[0194] In some embodiments, the thickness of the isolation layer 127 is the same as the thickness of the gate insulating layer 128, and the material of the isolation layer 127 is the same as the material of the gate insulating layer 128. This design facilitates the simultaneous formation of the isolation layer 127 and the gate insulating layer 128 in a single step, further simplifying the manufacturing process of the semiconductor device 100.

[0195] In some embodiments, the semiconductor device 100 further includes an insulating pad 17, which is located on one side of the gate line 15 and in contact with the gate line 15 in a first direction z. A conductive shield bottom surface 16a is disposed near the insulating pad 17. The gate line bottom surface 15a is in contact with the insulating pad 17.

[0196] In some embodiments, in the first direction z, the gate line top surface 15b and the conductive shield top surface 16b are flush, which facilitates the formation of the gate line top surface 15b and the conductive shield top surface 16b in one step, further simplifying the manufacturing process of the semiconductor device.

[0197] In some embodiments, in the first direction z, the conductive shield bottom surface 16a is located on the side of the gate line bottom surface 15a away from the conductive shield top surface 16b, that is, the gate line bottom surface 15a is located between the conductive shield bottom surface 16a and the conductive shield top surface 16b. With this design, the area of ​​effect of the gate voltage transmitted by the gate line 15 on the channel structure 114 is covered by the conductive shield structure 16, thereby better improving the coupling effect between adjacent channel structures 114 in the second direction under the action of the gate voltage.

[0198] In some embodiments, such as Figure 9BAs shown, the gate line 15 includes a first gate layer 151 and a second gate layer 152 made of different materials, and the conductive shielding structure 16 includes a first conductive shielding layer 161. The first gate layer 151 is located between the second gate layer 152 and the sidewall of the channel structure 114. A gate insulating layer 128 is located between the first gate layer 151 and the sidewall of the channel structure 114. An isolation layer 127 is located between the first conductive shielding layer 161 and the sidewall of the channel structure 114. The material of the first gate layer 151 is the same as the material of the first conductive shielding layer 161. The dimension of the first conductive shielding layer 161 along the second direction y is less than or equal to twice the dimension of the first gate layer 151 along the second direction y, such that the dimension of the conductive shielding structure 16 along the second direction y is less than twice the dimension of a gate line 15 along the second direction y.

[0199] In other embodiments, the gate line 15 includes a first gate layer 151, and the conductive shielding structure 16 includes a first conductive shielding layer 161. A gate insulating layer 128 is located between the first gate layer 151 and the sidewall of the channel structure 114. An isolation layer 127 is located between the first conductive shielding layer 161 and the sidewall of the channel structure 114. The material of the first gate layer 151 is the same as the material of the first conductive shielding layer 161. Therefore, the dimension of the first conductive shielding layer 161 along the second direction y is less than twice the dimension of the first gate layer 151 along the second direction y, such that the dimension of the conductive shielding structure 16 along the second direction y is less than twice the dimension of a gate line 15 along the second direction y.

[0200] In some embodiments, the gate line 15 includes a first gate layer 151 and a second gate layer 152 made of different materials, and the conductive shielding structure 16 includes a first conductive shielding layer 161 and a second conductive shielding layer 162 made of different materials. The first gate layer 151 is located between the second gate layer 152 and the sidewall of the channel structure 114. A gate insulating layer 128 is located between the first gate layer 151 and the sidewall of the channel structure 114. The first conductive shielding layer 161 is located between the second conductive shielding layer 162 and the sidewall of the channel structure 114. An isolation layer 127 is located between the first conductive shielding layer 161 and the sidewall of the channel structure 114. The material of the first gate layer 151 is the same as the material of the first conductive shielding layer 161. The material of the second gate layer 152 is the same as the material of the second conductive shielding layer 162. The dimension of the first conductive shielding layer 161 along the second direction y is equal to twice the dimension of the first gate layer 151 along the second direction y, and the dimension of the second conductive shielding layer 162 along the second direction y is less than twice the dimension of the second gate layer 152 along the second direction y, so that the dimension of the conductive shielding structure 16 along the second direction y is less than twice the dimension of a gate line 15 along the second direction y.

[0201] It should be noted that, due to differences in the manufacturing process, when forming the gate line 15 and the conductive shielding structure 16 in one step, the composition of the conductive layer of the gate line 15 and the conductive layer of the conductive shielding structure 16 may be the same or different.

[0202] In addition, see Figure 10 and Figure 11 As shown, based on the same inventive concept, this application also provides a storage system 400, which includes a memory 200 and a controller 300. The controller 300 is connected to the memory 200 and is used to control the memory 200. The memory 200 includes the semiconductor device 100 of any of the embodiments described above.

[0203] The storage system 400 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device having storage therein.

[0204] In some embodiments, refer to Figure 10 As shown, the storage system 400 includes a memory 200 and a controller 300. The storage system 400 can be integrated into a 3D memory card.

[0205] Among them, 3D memory cards include any one of the following: PC card (PCMCIA, the International Association for Personal Computer 3D Memory Cards), Compact Flash (CF) card, Smart Media (SM) card, 3D memory, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0206] In other embodiments, reference is made to Figure 11 As shown, the storage system 400 includes multiple memory units 200 and a controller 300. The storage system 400 is integrated into a solid-state drive (SSD).

[0207] In some embodiments, in the storage system 400, the controller 300 is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0208] In other embodiments, in storage system 400, controller 300 is configured to operate in high duty cycle environments in SSDs or eMMCs used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0209] In some embodiments, the controller 300 may be configured to manage data stored in the memory 200 and to communicate with external devices (e.g., a host). In some embodiments, the controller 300 may also be configured to control operations of the memory 200, such as read, erase, and program operations. In some embodiments, the controller 300 may also be configured to manage various functions relating to data stored or to be stored in the memory 200, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, the controller 300 is also configured to process error correction codes relating to data read from or written to the memory 200.

[0210] Of course, controller 300 can also perform any other suitable functions, such as formatting memory 200; for example, controller 300 can communicate with external devices (e.g., hosts) through at least one of various interface protocols.

[0211] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0212] Please refer to Figure 12 Some embodiments of this application also provide an electronic device 500. The electronic device 500 can be any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc.

[0213] Electronic device 500 may include the aforementioned storage system 400 and host 600, wherein host 600 includes at least one of a central processing unit (CPU) and a cache.

[0214] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The method includes: Multiple channel lines extending along a first direction and a second direction are formed in the semiconductor layer, wherein the first direction intersects the second direction; A plurality of first grooves and a plurality of second grooves extending along the first direction and arranged along the second direction are formed in the semiconductor layer. The plurality of first grooves and the plurality of second grooves intersect with a plurality of channel lines to form a plurality of channel structures. The dimension of the first groove along the second direction is smaller than the dimension of the second groove along the second direction. Conductive layers are formed in a plurality of first grooves and a plurality of second grooves. A portion of the conductive layers is removed. The remaining conductive layers in the plurality of first grooves form a plurality of conductive shielding structures, and the remaining conductive layers in the plurality of second grooves form a plurality of gate lines.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The formation of a plurality of first grooves and a plurality of second grooves extending along the first direction and arranged along the second direction in the semiconductor layer includes: A plurality of first initial grooves and a plurality of second initial grooves are formed in the semiconductor layer, extending along the first direction and a third direction and alternately arranged along the second direction. In the third direction, the size of the first initial groove is smaller than the size of the second initial groove, and the third direction intersects the first direction and the second direction. A sacrificial layer is filled in a plurality of first initial grooves and a plurality of second initial grooves; The sacrificial layer in the plurality of second initial grooves is removed, and the dimensions of the second initial grooves along the first and second directions are enlarged to form a plurality of second grooves; and The sacrificial layer in the plurality of first initial grooves is removed to form a plurality of first grooves.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, Prior to removing the sacrificial layer from the plurality of second initial grooves, the method further includes: Remove portions of the sacrificial layer from the plurality of the first initial grooves; and A cover layer is formed on the remaining sacrificial layer in the plurality of first initial grooves.

4. The method for manufacturing a semiconductor device according to claim 3, characterized in that, Prior to removing portions of the sacrificial layer from the plurality of first initial grooves, the method further includes: A protective layer is formed on one side of the semiconductor layer in the first direction, covering the sacrificial layer in a plurality of second initial grooves.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Before forming a conductive layer in the plurality of first grooves and the plurality of second grooves, the method further includes: An isolation layer is formed in the first groove on the sidewall of the channel structure, and a gate insulating layer is formed in the second groove on the sidewall of the channel structure.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that, The formation of a conductive layer in the plurality of first grooves and the plurality of second grooves includes: A first conductive layer is formed that covers the isolation layer and fills the first groove, and covers the gate insulating layer in the second groove.

7. The method for manufacturing a semiconductor device according to claim 5, characterized in that, The formation of a conductive layer in the plurality of first grooves and the plurality of second grooves includes: A first conductive layer is formed that covers the isolation layer and fills the first groove, and covers the gate insulating layer in the second groove; and A second conductive layer is formed in the second groove and covers the first conductive layer in the second groove, wherein the material of the second conductive layer is different from the material of the first conductive layer.

8. The method for manufacturing a semiconductor device according to claim 5, characterized in that, The formation of a conductive layer in the plurality of first grooves and the plurality of second grooves includes: Forming a first conductive layer covering the isolation layer in the first groove and the gate insulating layer in the second groove; and A second conductive layer is formed that covers the first conductive layer in the first groove and fills the first groove, and covers the first conductive layer in the second groove, wherein the material of the second conductive layer is different from the material of the first conductive layer.

9. The method for manufacturing a semiconductor device according to claim 2, characterized in that, After forming the plurality of second grooves, and before forming the plurality of first grooves, the method further includes: An insulating pad is formed at the bottom of the second groove. The insulating pad includes an insulating top surface away from the bottom surface of the second groove. In the first direction, the insulating top surface is located on the side of the bottom surface of the first initial groove near the opening of the first initial groove.

10. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The method further includes: forming lead-out conductive structures connected to the plurality of said conductive shielding structures.

11. A semiconductor device, characterized in that, include: Multiple channel structures extending along a first direction; Multiple gate lines extending along the first direction, with one gate line located between adjacent channel structures in the second direction, the second direction intersecting the first direction; as well as A plurality of conductive shielding structures extending along the first direction, wherein the plurality of conductive shielding structures and the plurality of gate lines are spaced apart along the second direction, and in the second direction one of the conductive shielding structures is located between adjacent channel structures; Wherein, the dimension of the conductive shielding structure along the second direction is less than twice the dimension of a gate line along the second direction.

12. The semiconductor device according to claim 11, characterized in that, The semiconductor device further includes: an insulating padding portion located on one side of the gate line in the first direction and in contact with the gate line; In the first direction, the conductive shielding structure includes a bottom conductive shielding surface and a top conductive shielding surface, with the bottom conductive shielding surface disposed near the insulating pad. The gate line includes a bottom end face that contacts the insulating pad portion, and the conductive shield bottom end face is located on the side of the gate line bottom end face away from the conductive shield top end face.

13. The semiconductor device according to claim 11, characterized in that, The semiconductor device further includes: a gate insulating layer, the gate insulating layer being located between the gate line and the sidewall of the channel structure; and... An isolation layer is located between the conductive shielding structure and the sidewall of the channel structure. The thickness of the isolation layer is the same as the thickness of the gate insulating layer, and the material of the isolation layer is the same as that of the gate insulating layer.

14. The semiconductor device according to claim 13, characterized in that, The conductive shielding structure includes a first conductive shielding layer, and the isolation layer is located between the first conductive shielding layer and the sidewall of the channel structure. The gate line includes a first gate layer, and the gate insulating layer is located between the first gate layer and the sidewall of the channel structure. The material of the first gate layer is the same as the material of the first conductive shielding layer.

15. The semiconductor device according to claim 13, characterized in that, The conductive shielding structure includes a first conductive shielding layer, and the isolation layer is located between the first conductive shielding layer and the sidewall of the channel structure. The gate line includes a first gate layer and a second gate layer made of different materials. The first gate layer is located between the second gate layer and the sidewall of the channel structure. The gate insulating layer is located between the first gate layer and the sidewall of the channel structure. The material of the first gate layer is the same as the material of the first conductive shielding layer.

16. The semiconductor device according to claim 13, characterized in that, The conductive shielding structure includes a first conductive shielding layer and a second conductive shielding layer made of different materials. The first conductive shielding layer is located between the second conductive shielding layer and the sidewall of the channel structure, and the isolation layer is located between the first conductive shielding layer and the sidewall of the channel structure. The gate line includes a first gate layer and a second gate layer made of different materials. The first gate layer is located between the second gate layer and the sidewall of the channel structure. The gate insulating layer is located between the first gate layer and the sidewall of the channel structure. The material of the first gate layer is the same as the material of the first conductive shielding layer, and the material of the second gate layer is the same as the material of the second conductive shielding layer.

17. The semiconductor device according to claim 11, characterized in that, The semiconductor device further includes: an outgoing conductive structure connected to the conductive shielding structure.

18. A storage system, characterized in that, include: The memory includes the semiconductor device as described in any one of claims 11-17; as well as A controller, connected to the memory, is used to control the memory.

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