A method of forming a split-gate memory

Abstract

The application improves a forming method of a split-gate memory, which comprises: forming a floating gate layer, a gate dielectric layer, a control gate layer and a first opening mask layer on a substrate; forming a first side wall and a second opening in the first opening, the second opening exposing a surface of the control gate layer; implanting ions into the control gate layer with a partial thickness through the second opening; etching the control gate layer using a gray table and a gas capable of etching silicon material to remove the control gate layer with a partial thickness and etch the control gate layer under a part of the first side wall, so that the remaining control gate layer forms a groove with a slope shape, and a notch is formed at the junction of the first side wall and the control gate layer; removing the control gate layer exposed by the second opening and the gate dielectric layer with a partial thickness; forming a second side wall, the second side wall filling the notch; removing the remaining gate dielectric layer and the floating gate layer not covered by the second side wall; forming a third side wall and a source line opening; and forming a source line in the source line opening.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a gate-type memory. Background Technology

[0002] Flash memory cells offer advantages such as high storage density, high reliability, and portability, making them widely used in mobile and communication devices such as mobile phones, laptops, and USB flash drives since their invention. Flash memory cells generally include two structures: stacked gate and split gate structures, with the split gate structure currently being more widely used.

[0003] Figures 1 to 3 The diagram shows the structural schematics corresponding to the steps in the formation method of the existing gate-type memory, such as... Figure 1 As shown, a gate oxide layer 112, a floating gate layer 113, and a gate dielectric layer are sequentially formed on a substrate 111. The gate dielectric layer includes a first oxide layer 114, a nitride layer 115, and a second oxide layer 116. A control gate layer 117 and a mask layer 118 are formed on the second oxide layer 116, and a first opening penetrating the mask layer 118 is formed. A first sidewall 119 is also formed on the sidewall of the mask layer 118 within the first opening. Figure 2 As shown, the control gate layer 117, the second oxide layer 116, and the nitride layer 115 exposed within the first opening are etched, exposing the surface of the first oxide layer 114. The remaining sidewalls of the control gate layer 117 are vertical, with right angles at the tips. Next, please refer to... Figure 3 A second sidewall 120 is formed, covering the sidewalls of the control gate layer 117, the second oxide layer 116, and the nitride layer 115. The first oxide layer 114 and the floating gate layer 113 are etched to expose the surface of the gate oxide layer 112, forming a third sidewall 121. The third sidewall 121 partially covers the first sidewall 119, the sidewalls of the first oxide layer 114, and the sidewalls of the floating gate layer 113, thereby forming a source line opening. Finally, a source line is formed within the source line opening.

[0004] However, as Figure 4 As shown, Figure 4 This is a schematic diagram of an electron microscope structure of a gate-type memory. Since the sharp corner of the control gate layer 117 is a right angle and is relatively sharp, and the second sidewall 120 is relatively thin, the sharp corner of the control gate layer 117 may break through the second sidewall 120, causing the second sidewall 120 to break, resulting in leakage and breakdown of the device, and reducing the reliability of the memory. Summary of the Invention

[0005] The purpose of this invention is to provide a method for forming a grid-type memory, which can reduce the risk of second sidewall breakage, reduce the risk of device leakage and breakdown, and improve the reliability of the memory.

[0006] To achieve the above objectives, the present invention provides a method for forming a grid-type memory, comprising:

[0007] A substrate is provided on which a floating gate layer, a gate dielectric layer, a control gate layer and a mask layer having a first opening are sequentially formed, wherein the first opening exposes a portion of the surface of the control gate layer.

[0008] A first sidewall is formed within the first opening, the first sidewall covering the sidewall of the mask layer, and the first sidewall forming a second opening, the second opening exposing a portion of the surface of the control gate layer;

[0009] Ions are injected into the control gate layer, which has a certain thickness, through the second opening;

[0010] The control gate layer is etched using an ashing machine and a gas capable of etching silicon to remove a portion of the control gate layer and etch a portion of the control gate layer below the first sidewall, so that the remaining control gate layer forms a groove in the shape of a slope, and a gap is formed at the junction of the first sidewall and the control gate layer.

[0011] Remove the control gate layer and a portion of the gate dielectric layer exposed by the second opening;

[0012] A second sidewall is formed, which covers the first sidewall, the sidewall of the control gate layer, and part of the sidewall of the gate dielectric layer, while the second sidewall fills the gap.

[0013] Remove the remaining gate dielectric layer and floating gate layer not covered by the second sidewall;

[0014] A third sidewall is formed, which covers the second sidewall, the sidewall of the gate dielectric layer, and the sidewall of the floating gate layer, and forms a source line opening;

[0015] A source line is formed within the source line opening.

[0016] Optionally, in the method for forming the gated memory, the substrate includes a wafer.

[0017] Optionally, in the method of forming the segmented memory, arsenic ions are injected into the control gate layer of a certain thickness through the second opening.

[0018] Optionally, in the method for forming the segmented gate memory, the materials of both the floating gate layer and the control gate layer include polysilicon.

[0019] Optionally, in the method for forming the gate-type memory, the gate dielectric layer includes a first oxide layer, a nitride layer, and a second oxide layer stacked sequentially.

[0020] Optionally, the method for forming the gate-type memory further includes: forming a gate oxide layer on the surface of the substrate, the gate oxide layer being located between the substrate and the floating gate layer.

[0021] Optionally, in the method for forming the gate-type memory, the method for forming the source line within the source line opening includes:

[0022] A polysilicon layer is filled into the opening of the source line;

[0023] The surface of the polysilicon layer is ground to form a source line.

[0024] Optionally, in the method for forming the segmented gate memory, after forming the source line within the source line opening, the method further includes:

[0025] Remove the mask layer and the control gate layer, gate dielectric layer and floating gate layer located below the mask layer.

[0026] Optionally, in the method for forming the segmented gate memory, the control gate layer and a portion of the gate dielectric layer exposed by the second opening are etched away.

[0027] Optionally, in the method for forming the segmented gate memory, the remaining gate dielectric layer and floating gate layer not covered by the second sidewall are etched away.

[0028] The method for forming a multi-gate memory provided by the present invention includes: providing a substrate; sequentially forming a floating gate layer, a gate dielectric layer, a control gate layer, and a mask layer having a first opening on the substrate, wherein the first opening exposes a portion of the surface of the control gate layer; forming a first sidewall within the first opening, the first sidewall covering the sidewall of the mask layer, the first sidewall forming a second opening, the second opening exposing a portion of the surface of the control gate layer; implanting ions into a partial thickness of the control gate layer through the second opening; and etching the control gate layer using an ashing machine and a gas capable of etching silicon to remove a portion of the control gate layer and etch a portion of the first... The control gate layer below the sidewall forms a sloping groove, and a gap is formed at the junction of the first sidewall and the control gate layer. The control gate layer and a portion of the gate dielectric layer exposed by the second opening are removed. A second sidewall is formed, covering the first sidewall, the sidewall of the control gate layer, and a portion of the sidewall of the gate dielectric layer, while filling the gap. The remaining gate dielectric layer and floating gate layer not covered by the second sidewall are removed. A third sidewall is formed, covering the second sidewall, the sidewall of the gate dielectric layer, and the sidewall of the floating gate layer, and forming a source line opening. A source line is formed within the source line opening. In this invention, the remaining control gate layer forms a sloping groove, a gap is formed at the junction of the first sidewall and the control gate layer, and when the second sidewall covers the first sidewall, the sidewall of the control gate layer, and a portion of the sidewall of the gate dielectric layer, the second sidewall fills the gap. The corners of the control gate in this invention will not break through the second sidewall, reducing the probability of the second sidewall breaking, reducing the probability of device leakage and breakdown, and improving the reliability of the memory. Attached Figure Description

[0029] Figures 1 to 2 This is a schematic diagram of the structure corresponding to the steps of the existing gate-type memory formation method;

[0030] Figure 3 This is a schematic diagram of an electron microscope structure for a gate-type memory.

[0031] Figure 4 This is a flowchart of a method for forming a grid-type memory according to an embodiment of the present invention;

[0032] Figures 5 to 11 This is a schematic diagram of the structure corresponding to the corresponding steps of the method for forming a grid-type memory according to an embodiment of the present invention;

[0033] In the figure: 111-substrate, 112-gate oxide layer, 113-floating gate layer, 114-first oxide layer, 115-nitride layer, 116-second oxide layer, 117-control gate layer, 118-mask layer, 119-first sidewall, 120-second sidewall, 121-third sidewall, 211-substrate, 212-gate oxide layer, 213-floating gate layer, 214-first oxide layer, 215-nitride layer, 216-second oxide layer, 217-control gate layer, 218-mask layer, 219-first sidewall, 220-second sidewall, 221-third sidewall, 222-source line. Detailed Implementation

[0034] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0035] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described herein may be added to the method.

[0036] Furthermore, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be located directly on another layer or substrate, and / or intercalation layers may also be present. Additionally, it should be understood that when a layer is referred to as being "under" another layer, it can be located directly under that layer, and / or one or more intercalation layers may also be present. Furthermore, references to "on" and "under" the layers may be made based on the accompanying drawings.

[0037] Please refer to Figure 4 The present invention provides a method for forming a grid-type memory, comprising:

[0038] S11: Provide a substrate, and sequentially form a floating gate layer, a gate dielectric layer, a control gate layer and a mask layer with a first opening on the substrate, wherein the first opening exposes a portion of the surface of the control gate layer;

[0039] S12: A first sidewall is formed in the first opening, the first sidewall covers the sidewall of the mask layer, the first sidewall forms a second opening, and the second opening exposes part of the surface of the control gate layer;

[0040] S13: Ions are injected into a partial thickness of the control gate layer through the second opening;

[0041] S14: The control gate layer is etched using an ashing machine and a gas capable of etching silicon material to remove part of the control gate layer and etch part of the control gate layer below the first sidewall, so that the remaining control gate layer forms a groove in the shape of a slope, and a gap is formed at the junction of the first sidewall and the control gate layer.

[0042] S15: Remove the control gate layer and part of the gate dielectric layer exposed by the second opening;

[0043] S16: Form a second sidewall, which covers the first sidewall, the sidewall of the control gate layer, and part of the sidewall of the gate dielectric layer. At the same time, the second sidewall fills the gap.

[0044] S17: Remove the remaining gate dielectric layer and floating gate layer not covered by the second sidewall;

[0045] S18: Form a third sidewall, which covers the second sidewall, the sidewall of the gate dielectric layer and the sidewall of the floating gate layer, and forms a source line opening;

[0046] S19: A source line is formed within the source line opening.

[0047] Please refer to Figure 5 First, a substrate 211 is provided. The substrate 211 can be a silicon substrate, such as a wafer. Next, a gate oxide layer 212 is formed on the surface of the substrate 211. The gate oxide layer 212 can be made of silicon dioxide and can be formed by deposition. Next, a floating gate layer 213 is formed on the surface of the gate oxide layer 212. The floating gate layer 213 can be made of polysilicon and can be formed by deposition. Next, a gate dielectric layer is formed on the surface of the floating gate layer 213. The gate dielectric layer includes a first oxide layer 214, a nitride layer 215, and a second oxide layer 216. The first oxide layer 214 and the second oxide layer 216 can be made of silicon dioxide, and the nitride layer 215 can be made of silicon nitride. The gate dielectric layer can be formed by sequentially depositing the first oxide layer 214, the nitride layer 215, and the second oxide layer 216. Next, a control gate layer 217 and a mask layer 218 are formed on the surface of the second oxide layer 216. The control gate layer 217 is made of polysilicon. The etched mask layer 218 forms a first opening that penetrates the mask layer 218. Then, a first sidewall 219 is formed on the sidewall of the mask layer 218 within the first opening.

[0048] Next, please refer to Figure 6 and Figure 7Ions are injected into the shallow surface layer of the control gate layer 217 through the first opening, so that a portion of the control gate layer 217 contains ions. In addition to injecting ions perpendicular to the surface of the control gate layer 217, ions can also be injected at an angle to the surface of the control gate layer 217, thereby also containing ions in the shallow surface layer of the control gate layer 217 at the bottom of the first sidewall 219. In this embodiment, the injected ions can be arsenic ions. Next, the control gate layer 217 is etched using an ashing machine and a gas capable of etching silicon. Because the control gate layer 217 becomes amorphous after the previous ion injection, the etching speed of the control gate layer 217 is increased. Therefore, this etching can remove a portion of the control gate layer 217 and etch a portion of the control gate layer 217 below the sidewall, so that the remaining control gate layer 217 forms a sloping groove.

[0049] Next, please refer to Figure 9 The remaining portion of the control gate layer 217, second oxide layer 216, and nitride layer 215 not covered by the first sidewall 219 within the first opening is etched, exposing the surface of the first oxide layer 214. The remaining control gate layer 217 does not have vertical sharp corners; instead, it is sloped at the original sharp corners. Next, a second sidewall 220 is formed, covering the sidewalls of the control gate layer 217, the second oxide layer 216, and the nitride layer 215. Because the control gate layer 217 does not have vertical sharp corners, the height of its sharp corners is reduced compared to the height of sharp corners in the prior art. Therefore, the thickness of the corresponding second sidewall 220 is increased, reducing the probability of the control gate corners breaking through the second sidewall 220 and reducing the probability of the second sidewall breaking. Next, please refer to... Figure 10 The first oxide layer 214 and the floating gate layer 213 are etched to expose the surface of the gate oxide layer 212, forming a third sidewall 221. The third sidewall 221 covers part of the first sidewall 219, the sidewall of the first oxide layer 214 and the sidewall of the floating gate layer 213, thereby forming a source line opening.

[0050] Next, please refer to Figure 11 Polysilicon is filled into the source line opening, and the surface of the polysilicon is ground to form source line 222 in the source line opening.

[0051] In summary, the method for forming a gate-type memory provided in this embodiment of the invention includes: providing a substrate; sequentially forming a floating gate layer, a gate dielectric layer, a control gate layer, and a mask layer with a first opening on the substrate, the first opening exposing a portion of the surface of the control gate layer; forming a first sidewall within the first opening, the first sidewall covering the sidewall of the mask layer, the first sidewall forming a second opening, the second opening exposing a portion of the surface of the control gate layer; implanting ions into a control gate layer of a certain thickness through the second opening; and etching the control gate layer using an ashing machine and a gas capable of etching silicon to remove a portion of the control gate layer and etch a portion of the control gate layer. The control gate layer below the first sidewall is divided into a sloping groove, and a gap is formed at the junction of the first sidewall and the control gate layer. The control gate layer and a portion of the gate dielectric layer exposed by the second opening are removed. A second sidewall is formed, covering the first sidewall, the sidewall of the control gate layer, and a portion of the sidewall of the gate dielectric layer, while filling the gap. The remaining gate dielectric layer and floating gate layer not covered by the second sidewall are removed. A third sidewall is formed, covering the second sidewall, the sidewall of the gate dielectric layer, and the sidewall of the floating gate layer, and forming a source line opening. A source line is formed within the source line opening. In this invention, the remaining control gate layer forms a sloping groove, a gap is formed at the junction of the first sidewall and the control gate layer, and the second sidewall fills the gap when it covers the first sidewall, the sidewall of the control gate layer, and a portion of the sidewall of the gate dielectric layer. The corners of the control gate in this invention will not break through the second sidewall, reducing the probability of the second sidewall breaking, reducing the probability of device leakage and breakdown, and improving the reliability of the memory.

[0052] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A method for forming a grid-type memory, characterized in that, include: A substrate is provided on which a floating gate layer, a gate dielectric layer, a control gate layer and a mask layer having a first opening are sequentially formed, wherein the first opening exposes a portion of the surface of the control gate layer. A first sidewall is formed within the first opening, the first sidewall covering the sidewall of the mask layer, and the first sidewall forming a second opening, the second opening exposing a portion of the surface of the control gate layer; Ions are injected into the control gate layer, which has a certain thickness, through the second opening; The control gate layer is etched using an ashing machine and a gas capable of etching silicon to remove a portion of the control gate layer and etch a portion of the control gate layer below the first sidewall, so that the remaining control gate layer forms a groove in the shape of a slope, and a gap is formed at the junction of the first sidewall and the control gate layer. Remove the control gate layer and a portion of the gate dielectric layer exposed by the second opening; A second sidewall is formed, which covers the first sidewall, the sidewall of the control gate layer, and part of the sidewall of the gate dielectric layer, while the second sidewall fills the gap. Remove the remaining gate dielectric layer and floating gate layer not covered by the second sidewall; A third sidewall is formed, which covers the second sidewall, the sidewall of the gate dielectric layer, and the sidewall of the floating gate layer, and forms a source line opening; A source line is formed within the source line opening.

2. The method for forming a grid-type memory as described in claim 1, characterized in that, The substrate includes a wafer.

3. The method for forming a grid-type memory as described in claim 1, characterized in that, Arsenic ions are injected into the control gate layer, which has a certain thickness, through the second opening.

4. The method for forming a grid-type memory as described in claim 1, characterized in that, Both the floating gate layer and the control gate layer are made of polycrystalline silicon.

5. The method for forming a grid-type memory as described in claim 1, characterized in that, The gate dielectric layer comprises a first oxide layer, a nitride layer, and a second oxide layer stacked sequentially.

6. The method for forming a grid-type memory as described in claim 1, characterized in that, Also includes: A gate oxide layer is formed on the surface of the substrate, the gate oxide layer being located between the substrate and the floating gate layer.

7. The method for forming a grid-type memory as described in claim 1, characterized in that, The method for forming a source line within the source line opening includes: A polysilicon layer is filled into the opening of the source line; The surface of the polysilicon layer is ground to form a source line.

8. The method for forming a grid-type memory as described in claim 1, characterized in that, After the source line is formed within the source line opening, the process further includes: Remove the mask layer and the control gate layer, gate dielectric layer and floating gate layer located below the mask layer.

9. The method for forming a grid-type memory as described in claim 1, characterized in that, The control gate layer and a portion of the gate dielectric layer exposed by the second opening are etched away.

10. The method for forming a grid-type memory as described in claim 1, characterized in that, The remaining gate dielectric layer and floating gate layer not covered by the second sidewall are etched away.

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