Semiconductor device, memory system, and method for manufacturing semiconductor device

Abstract

The disclosure provides a semiconductor device, a storage system and a preparation method of the semiconductor device, relates to the technical field of semiconductor chips, and aims to solve the problem of performance reduction of a semiconductor device caused by leakage current in the semiconductor device. The semiconductor device comprises a stacking structure, a channel structure, a lead-out structure, a conductive layer and a partition part. The stacking structure comprises a plurality of gate layers arranged in layers; the stacking structure comprises a first surface and a second surface. The channel structure penetrates through the stacking structure and protrudes from the first surface of the stacking structure. The lead-out structure penetrates from the second surface to the corresponding gate layer and is connected with the corresponding gate layer. The conductive layer is arranged on the first surface; the conductive layer covers the channel structure and is connected with the channel structure. The partition part is arranged between the channel structure and the lead-out structure; the partition part disconnects the conductive layer, and the material of the partition part is an insulating material. The semiconductor device is applied to the storage system to realize data reading and writing operations.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor device, a memory system, and a method for fabricating a semiconductor device. Background Technology

[0002] As the feature size of memory cells approaches the lower limit of the process, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed three-dimensional memory (3D NAND), which increases storage density by arranging storage cells three-dimensionally on a substrate. Improving the electrical performance of 3D memory is a key challenge that needs to be addressed. Summary of the Invention

[0004] The embodiments of this disclosure provide a semiconductor device, a memory system, and a method for fabricating a semiconductor device, aiming to solve the leakage current problem in semiconductor devices in order to improve the electrical performance and reliability of semiconductor devices.

[0005] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0006] On one hand, a semiconductor device is provided. The semiconductor device includes a stacked structure, a channel structure, a lead-out structure, a conductive layer, and a blocking portion.

[0007] The stacked structure includes multiple gate layers stacked together. The stacked structure includes a first surface and a second surface disposed opposite each other in a third-direction orientation, where the third-direction orientation is the direction in which the multiple gate layers are stacked. A channel structure penetrates the stacked structure and protrudes from the first surface. A lead-out structure extends from the second surface to the corresponding gate layer and is connected to the corresponding gate layer. A conductive layer is disposed on the first surface; the conductive layer covers the channel structure and is connected to the channel structure. A partition is disposed between the channel structure and the lead-out structure; the partition disconnects the conductive layer, and the material of the partition includes an insulating material.

[0008] This embodiment of the present disclosure provides a partition portion that disconnects and electrically insulates the portion of the conductive layer located on the channel structure from the portion of the conductive layer located on the lead-out structure. This prevents the conductive layer from transmitting electrical signals to the conductive layer on the lead-out structure during the transmission of source signals to the channel structure. This avoids the formation of a loop between the gate layer near the lead-out structure and the portion of the conductive layer located on the lead-out structure, thereby preventing leakage current and effectively improving the stability of the threshold voltage in the memory cell string of the semiconductor device. This, in turn, improves the electrical performance and reliability of the semiconductor device.

[0009] In some embodiments, the semiconductor device further includes a plurality of virtual channel structures. These virtual channel structures are disposed between the channel structure and the lead-out structure, and extend through the stacked structure. In the orthographic projection onto the second surface, the partition portion at least partially overlaps with at least one virtual channel structure.

[0010] In some embodiments, at least one end of a virtual channel structure protrudes from a first surface, and the protruding end of the virtual channel structure has a recess, which is filled by a partition portion; and / or, the end face of at least one end of the virtual channel structure is flush with or recessed relative to the first surface, and a portion of the partition portion covers the end face of the virtual channel structure.

[0011] That is, a portion or all of the end of the virtual channel structure protruding from the first surface is removed, and the removed portion of the virtual channel structure is replaced by a partition. This disconnects the portion of the conductive layer located on the channel structure and the portion located on the lead-out structure, while removing other structures corresponding to the disconnection location of the conductive layer (e.g., a portion or all of the end of the virtual channel structure protruding from the first surface). This prevents the two disconnected portions of the conductive layer from being connected through other conductive structures (e.g., through the semiconductor channel layer of the virtual channel structure), thus ensuring that the conductive layer is fully disconnected and further reducing the leakage risk of the semiconductor device.

[0012] In some embodiments, the semiconductor device further includes a gate line isolation structure. This gate line isolation structure extends through the stacked structure along a first direction, which is parallel to the second surface. A partition portion extends along a second direction, which is parallel to the second surface and intersects the first direction. In an orthographic projection onto the second surface, the partition portion intersects the gate line isolation structure, thereby allowing the partition portion to cut the conductive layer into two parts in a direction perpendicular to the extension of the gate line. This ensures that one part of the cut conductive layer is located in the storage region, and the other part is located in the interconnect region.

[0013] In some embodiments, one end of the gate wire isolation structure protrudes from the first surface, and the end of the gate wire isolation structure protruding from the first surface is provided with a notch. The partition portion fills the notch, thereby ensuring that the conductive layer is fully disconnected.

[0014] In some embodiments, the semiconductor device includes a memory region and a connection region, the connection region being disposed on at least one side of the memory region. A channel structure is disposed in the memory region, a lead-out structure is disposed in the connection region, and a partition portion is disposed in the connection region near the memory region.

[0015] By placing the partition portion in the connection area near the storage area, it is ensured that one part of the conductive layer disconnected by the partition portion is located in the storage area and the other part is located in the connection area. That is, it is ensured that the part of the conductive layer located on the channel structure and the part located on the lead-out structure are disconnected from each other, thereby enabling the transmission of electrical signals (such as source signals) in the channel structure while avoiding leakage problems in the semiconductor device.

[0016] In some embodiments, the stacked structure further includes multiple first dielectric layers and multiple sacrificial layers, wherein the multiple first dielectric layers and multiple gate layers are alternately stacked, and one gate layer and one sacrificial layer are disposed on the same layer; the first dielectric layers are located at least in the memory region, and the sacrificial layers are located in the interconnect region. The lead-out structure includes a first sub-part and a second sub-part. The first sub-part is embedded in the sacrificial layer disposed on the same layer as the corresponding gate layer and is connected to the corresponding gate layer; the second sub-part extends from a second surface through to the sacrificial layer disposed on the same layer as the corresponding gate layer and is connected to the first sub-part. A partition is located between the position where the first sub-part is connected to the corresponding gate layer and the channel structure.

[0017] That is, the isolation part disconnects the conductive layer at the location between the channel structure and the leakage location (the location where the lead-out structure is connected to the corresponding gate layer), thereby solving the leakage problem of semiconductor devices and improving the electrical performance and reliability of semiconductor devices.

[0018] In some embodiments, the minimum distance between the partition and the channel structure along the first direction is greater than or equal to 15 μm.

[0019] By setting the minimum spacing between the partition and the channel structure to be greater than or equal to 15μm, it is ensured that the partition is located between the channel structure and the lead-out structure. On the other hand, the disconnection position of the conductive layer is controlled to avoid affecting the normal storage function of the memory cell string in the storage area.

[0020] In some embodiments, the semiconductor device further includes a first insulating layer. The first insulating layer is disposed on the side of the conductive layer away from the stacked structure and covers the storage region and connection region of the semiconductor device. The partition portion is integrally disposed with the first insulating layer.

[0021] The first insulating layer is used to realize the external connection of the lead-out structure. By making the partition part integral with the first insulating layer, the process of preparing the partition part can be compatible with the process of preparing the external connection structure of the lead-out structure, thereby simplifying the semiconductor device preparation process and improving the semiconductor device preparation efficiency.

[0022] In some embodiments, the semiconductor device further includes a contact post. The contact post penetrates the first insulating layer and is connected to the lead-out structure, thereby facilitating external connection of the lead-out structure.

[0023] On the other hand, a method for fabricating a semiconductor device is provided, the method comprising: forming a stacked structure; the stacked structure including multiple gate layers; the stacked structure including a first surface and a second surface disposed opposite each other in a third direction, the third direction being the direction in which the multiple gate layers are stacked; forming a channel structure; the channel structure penetrating the stacked structure and protruding from the first surface of the stacked structure; forming a lead-out structure; penetrating from the second surface to a corresponding gate layer and connected to the corresponding gate layer; forming a conductive layer; the conductive layer disposed on the first surface; the conductive layer covering the channel structure and connected to the channel structure; disconnecting the conductive layer; forming a trench between the two disconnected portions of the conductive layer; the trench being located between the channel structure and the lead-out structure; filling the trench to form a partition portion; the material of the partition portion having electrical insulation properties.

[0024] It is understood that the beneficial effects that the semiconductor device fabrication method provided in the above embodiments of this disclosure can achieve can be referred to the beneficial effects brought about by the semiconductor device design method described above, and will not be repeated here.

[0025] In some embodiments, the fabrication method further includes: simultaneously disconnecting the conductive layer and etching the conductive layer to form a first via; the first via exposing the lead-out structure. An insulating layer is formed; the insulating layer is disposed on the side of the conductive layer away from the stacked structure and covers the storage region and connection region of the semiconductor device; the insulating layer fills the first via and the trench, and the portion of the insulating layer filling the trench forms a partition. A contact post is formed; the contact post penetrates the insulating layer and is connected to the lead-out structure.

[0026] By making the fabrication process of the external interconnect structure (including forming the first via and fabricating the insulating layer) compatible with the fabrication process of the partition, the fabrication process of semiconductor devices can be simplified and the fabrication efficiency of semiconductor devices can be improved.

[0027] In another aspect, a storage system is provided. This storage system includes a controller and a semiconductor device as provided in any of the foregoing embodiments. The controller is coupled to the semiconductor device, and controls the semiconductor device to store data.

[0028] It is understood that the beneficial effects that the storage system provided by the above embodiments of this disclosure can achieve can be referred to the beneficial effects brought about by the semiconductor device design method described above, and will not be repeated here. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0030] Figure 1 This is a schematic diagram of the structure of a storage system according to some embodiments;

[0031] Figure 2 This is a schematic diagram of a semiconductor device according to some embodiments;

[0032] Figure 3 for Figure 2 Enlarged view of the structure corresponding to dashed box A in the image;

[0033] Figure 4 For along Figure 3 A cross-sectional view of section line B-B' in the diagram;

[0034] Figure 5 This is a schematic diagram of another structure of a semiconductor device according to some embodiments;

[0035] Figure 6 for Figure 5 The equivalent circuit diagram of the semiconductor devices in the diagram;

[0036] Figure 7 For the corresponding edge during the preparation process Figure 3 A cross-sectional view along section line C-C' in the diagram;

[0037] Figure 8 For along Figure 3 Another cross-sectional view of section line B-B' in the diagram;

[0038] Figure 9 For along Figure 3 Another cross-sectional view of section line B-B' in the diagram;

[0039] Figure 10 For along Figure 3 A cross-sectional view of section line E-E' in the diagram;

[0040] Figure 11 and Figure 12 This is a flowchart illustrating the fabrication process of a semiconductor device according to some embodiments;

[0041] Figures 13-26 These are cross-sectional views corresponding to each fabrication step of a semiconductor device. Detailed Implementation

[0042] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0043] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0044] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0045] In the description of this specification, the terms "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0046] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0047] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0048] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0049] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0050] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0051] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0052] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0053] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0054] This disclosure provides an electronic device, which can be, for example, a mobile phone, tablet computer, personal digital assistant (PDA), television, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners), drones, radar, aerospace equipment, in-vehicle equipment, vehicles, and other different types of user equipment or terminal devices; the electronic device can also be a network device such as a base station. This application does not impose any special limitations on the specific form of the electronic device.

[0055] The electronic device includes a storage system 1000 (see reference). Figure 1 This is to enable the storage of relevant data in electronic devices.

[0056] For example, the electronic device 1000 may also include at least one of a central processing unit (CPU) and a cache.

[0057] This disclosure also provides a storage system. Figure 1 This is a schematic diagram of the structure of a storage system 1000 provided in an embodiment of the present disclosure.

[0058] like Figure 1 As shown, the storage system 1000 includes a semiconductor device 100 and a controller 200. The controller 200 is coupled to the semiconductor device 100 to control the semiconductor device 100 to store data.

[0059] The storage system 1000 can be applied to the aforementioned electronic devices. For example, it can be integrated or packaged in electronic devices. For example, it can be packaged in electronic devices using Universal Flash Storage (UFS) or Embedded Multi Media Card (eMMC).

[0060] Alternatively, the storage system 1000 can also be integrated into a card-type memory. This card-type memory can include any of the following: PC card (PCMCIA, Personal Computer 3D Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, 3D memory, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0061] Alternatively, the storage system 1000 can also be integrated into a solid state drive (SSD).

[0062] For example, the storage system 1000 may include one semiconductor device 100, or may include multiple semiconductor devices 100 (such as...). Figure 1 (As shown).

[0063] For example, the aforementioned controller 200 may be configured to manage data stored in the semiconductor device 100 and communicate with external devices (e.g., a host).

[0064] For example, the controller 200 can also be configured to control the operation of the semiconductor device 100, such as controlling the semiconductor device 100 to perform read, erase and program operations.

[0065] For example, the controller 200 may also be configured to manage various functions regarding data stored or to be stored in the semiconductor device 100, including at least one of bad block management, garbage collection, logic-to-physical address translation, and wear leveling.

[0066] For example, the controller 200 may also be configured to process error correction codes for data read from or written to the semiconductor device 100.

[0067] Of course, the controller 200 can also perform any other suitable functions, such as formatting the semiconductor device 100. For example, the controller 200 can also communicate with external devices (e.g., a host) through at least one of various interface protocols.

[0068] It should be noted that the interface protocol may include at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0069] For example, the aforementioned semiconductor device 100 may be a three-dimensional memory. Alternatively, the aforementioned semiconductor device 100 may be part of a three-dimensional memory.

[0070] It should be noted that the "three-dimensional memory" can refer to a device formed by arraying strings of memory cell transistors (such as NAND memory cell strings) on the main surface of a substrate and extending in a direction perpendicular to the substrate.

[0071] This disclosure also provides a semiconductor device 100, Figure 2 This is a top view of the semiconductor device 100 provided in an embodiment of this disclosure. Figure 3 for Figure 2 The enlarged view corresponding to the dashed box A in the image. Figure 4 For along Figure 3 A cross-sectional view of section line B-B' in the diagram.

[0072] The semiconductor device 100 can be used in the aforementioned storage system 1000, or it can be used as a standalone device in other electronic devices. This disclosure does not limit its specific application scenarios.

[0073] like Figure 2 As shown, the semiconductor device 100 includes a storage region C and a connection region S. The storage region C is a region for setting up strings of memory cells to achieve storage functionality, and the connection region S is a region for connecting the strings of memory cells in the storage region C to external locations. The connection region S is located on at least one side of the storage region C. For example, the connection region S may be located on one side of the storage region C; or, alternatively, the connection region S may be located on opposite sides of the storage region. Figure 2 The diagram illustrates a scenario where the connection area S is located on one side of the storage area C. Furthermore, as shown... Figure 2 As shown, two adjacent storage areas C can share a single connection area S.

[0074] like Figure 3 and Figure 4 As shown, the semiconductor device 100 includes a stacked structure 10, a channel structure 20, a lead-out structure 30, a conductive layer 40, and a blocking portion 50.

[0075] Among them, see Figure 4 The stacked structure 10 may include multiple gate layers 11 stacked together.

[0076] See Figure 4 The multilayer gate layer 11 is stacked along the third direction Z layer, and adjacent gate layers 11 are spaced apart.

[0077] It is understood that the gate layer 11 can be stacked in multiple layers, such as 4, 16, 32, 64, 128 or more layers, and the embodiments disclosed herein do not limit this.

[0078] For example, each gate layer 11 may include multiple gate lines 111 arranged along the second direction Y. Figure 3 The structure of the gate layer 11 is illustrated by taking only one gate line 111 as an example.

[0079] See Figure 3 The gate line 111 extends along the first direction X and extends from the storage area C to the connection area S.

[0080] Wherein, both the first direction X and the second direction Y are parallel to the plane where the gate layer 11 is located (e.g., parallel to the plane where the gate layer 11 is located). Figure 4 The first surface 1a or the second surface 1b is shown, and the first direction X and the second direction Y intersect each other. For example, the first direction X and the second direction Y can be perpendicular to each other. The third direction Z is perpendicular to the first direction X and the second direction Y.

[0081] For example, the material of the gate line 111 includes a conductive material, such as at least one of tungsten, cobalt, copper, aluminum, doped silicon, and metal silicide.

[0082] For example, see Figure 4 The stacked structure 10 may also include a first dielectric layer 12 that is alternately stacked with the gate layer 11, the first dielectric layer 12 extending from the memory region C to the connection region S.

[0083] For example, the material of the first dielectric layer 12 may include an insulating material, such as at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxide (e.g., aluminum oxide, hafnium dioxide, etc.), silicate, and organic insulating material.

[0084] The first dielectric layer 12 can electrically insulate the two adjacent gate layers 11, preventing short circuits between the gate lines 111 in the two gate layers 11, thereby ensuring the stability of the semiconductor device 100.

[0085] For example, see Figure 4 The stacked structure 10 may further include a sacrificial layer 13. The sacrificial layer 13 is disposed on the same layer as the gate layer 11. The sacrificial layer 13 is located in the connection region S.

[0086] For example, the material of the sacrificial layer 13 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, amorphous silicon, amorphous carbon, and polycrystalline silicon.

[0087] For example, see Figure 4 The stacked structure 10 also includes a second dielectric layer 113, which covers the aforementioned adhesive layer 112 to enhance the insulation between the channel structure 20 and the gate line 111, thereby preventing leakage between them and the resulting degradation of the electrical performance of the semiconductor device 100, such as causing the threshold voltage of the semiconductor device 100 to drift, thus affecting the electrical performance and stability of the semiconductor device 100.

[0088] For example, the material of the second dielectric layer 113 may include a material with a high dielectric constant, such as a material with a dielectric constant greater than or equal to 7, such as at least one of alumina, hafnium oxide and tantalum oxide.

[0089] For example, see Figure 4 The stacked structure 10 may also include an adhesive layer 112 that covers the gate line 111 and is configured to improve the adhesion between the gate line 111 and the second dielectric layer 113.

[0090] For example, the material of the adhesive layer 112 includes at least one of titanium nitride, tantalum nitride, and tungsten carbide.

[0091] See Figure 4 The stacked structure 10 includes a first surface 1a and a second surface 1b disposed opposite each other in the third direction Z.

[0092] Among them, the third direction Z is the direction of the stacking of the multilayer gate layer 11.

[0093] See Figure 4 The channel structure 20 extends through the stacked structure 10 and protrudes from the first surface 1a of the stacked structure 10, i.e., it extends from the first surface 1a. At least a portion of the channel structure 20 is used to store data in order to realize the storage function of the semiconductor device 100.

[0094] Understandably, the number of channel structures 20 can be multiple to increase the storage capacity of the semiconductor device 100. The shape of the channel structure 20 can be cylindrical, frustum-shaped, or prism-shaped, etc., and the embodiments of this disclosure do not further limit the shape of the channel structure 20.

[0095] For example, such as Figure 4 As shown, the channel structure 20 may include, for example, a semiconductor channel layer 21 and a memory function layer 22, with the memory function layer 22 surrounding the semiconductor channel layer 21.

[0096] For example, the material of the semiconductor channel layer 21 may include semiconductor materials, which may include monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials.

[0097] For example, see Figure 4 The storage functional layer 22 may include, for example, a barrier layer 221, a charge trapping layer 222, and a tunneling layer 223. The materials of the barrier layer 221, the charge trapping layer 222, the tunneling layer 223, and the semiconductor channel layer 21 may be silicon oxide, silicon nitride, silicon oxide, and polysilicon, respectively, to form an "ONOP" structure.

[0098] It is understood that the embodiments disclosed herein are merely illustrative examples of the ONOP structure and some materials of the structure, and do not limit the specific structure thereto. It is understood that the channel structure 20 may also include other membrane layers, or more or fewer membrane layers than those exemplified above, or the materials of the membrane layers may include other materials not mentioned.

[0099] For example, see Figure 4 The storage layer 22 extends from the second surface 1b of the stacked structure 10 to the first surface 1a of the stacked structure 10. The semiconductor channel layer 21 extends through the stacked structure 10 and protrudes from the first surface 1a of the stacked structure 10 at one end.

[0100] For example, see Figure 4 The channel structure 20 may also include a channel filling layer 23, which is disposed on the side of the semiconductor channel layer 21 away from the memory function layer 22 to provide mechanical support.

[0101] For example, the channel filling layer 23 may include voids to reduce structural stress on the semiconductor device 100.

[0102] For example, the material of the channel filling layer 23 includes an insulating material, such as at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxide (e.g., aluminum oxide, hafnium dioxide, etc.) and its silicates, and organic insulating materials.

[0103] The aforementioned stacked structure 10 and the aforementioned channel structure 20 can form multiple memory cell strings M. Figure 5 This is a schematic diagram of the structure of the storage unit string M provided in an embodiment of this disclosure. Figure 6 This is the equivalent circuit diagram corresponding to the memory cell string M.

[0104] For example, see Figure 5 and Figure 6The storage cell string M can include multiple transistors T, one transistor T (e.g., Figure 6 T1 to T6 in the transistors can be set as a storage cell, and these transistors T are connected together to form a storage cell string M.

[0105] A transistor T can be formed by a channel structure 20 and a gate line 111 surrounding the channel structure 20, wherein the two ends of the channel structure 20 in the memory cell string M are electrically connected to the source line SL and the bit line BL, respectively, and the gate line 111 is configured to control the conduction state of the transistor T, that is, to control the conduction state between the source line SL and the bit line BL.

[0106] For example, along the third direction Z, the gate line 111 closest to the first surface 1a in the stacked structure 10 is configured as a source select gate (SGS), which is configured to control the conduction state of transistor T6, thereby controlling the conduction state of the source channel in the memory cell string M. The gate line 111 closest to the second surface 1b in the stacked structure 10 (e.g., the gate line 111 furthest from the source select gate SGS among multiple gate lines 111) is configured as a drain select gate (SGD), which is configured to control the conduction state of transistor T1, thereby controlling the conduction state of the drain channel in the memory cell string M. The gate lines 111 located in the middle portion of the stacked structure 10 can be configured as multiple word lines WL, such as word lines WL0, WL1, WL2, and WL3. By writing different voltages on the word line WL, data writing, reading, and erasing of each memory cell (e.g., transistors T2, T3, T4, T5) in the memory cell string M can be completed.

[0107] See Figure 4 The lead-out structure 30 extends from the second surface 1b to the corresponding gate layer 11 and is connected to the corresponding gate layer 11. Specifically, the lead-out structure 30 is connected to the gate line 111 in its corresponding gate layer 11.

[0108] The lead-out structure 30 is used to lead out the gate line 111 so as to transmit external gate signals to the gate line 111 in the gate layer 11, thereby realizing the control of the channel structure 20.

[0109] It should be noted that the "corresponding gate layer 11" here refers to the gate layer 11 that needs to transmit electrical signals through a certain lead-out structure 30. For example, the third gate layer 11 in the direction from the second surface 1b to the first surface 1a corresponds to the lead-out structure 30 connected to it. Then, the lead-out structure 30 will pass through the film layers where the first and second gate layers 11 of the stacked structure 10 are located and connect to the third gate layer 11.

[0110] It is understandable that there can be multiple lead-out structures 30, and each gate line 111 can correspond to one lead-out structure 30.

[0111] For example, see Figure 4 The lead-out structure 30 is located in the connection region S.

[0112] For example, the lead-out structure 30 can be a self-aligned contact (SCT) structure.

[0113] For example, see Figure 4 The lead-out structure 30 may include a first sub-part 31 and a second sub-part 32 that are connected.

[0114] Among them, see Figure 4 The first sub-section 31 is disposed on the same layer as and connected to the corresponding gate layer 11, for example, see [reference]. Figure 4 The first sub-part 31 is embedded in the sacrificial layer 13 which is disposed on the same layer as the corresponding gate layer 11. That is, the first sub-part 31, the corresponding gate layer 11, and the corresponding sacrificial layer 13 (i.e., the sacrificial layer 13 in which the first sub-part 31 is embedded) are disposed on the same layer.

[0115] See Figure 4 The second sub-part 32 extends from the second surface 1b to the sacrificial layer 13 disposed on the same layer as the corresponding gate layer 11, and is connected to the first sub-part 31. That is, the second sub-part 32 extends to the corresponding sacrificial layer 13 so as to connect with the first sub-part 31.

[0116] The end of the second sub-section 32 that is away from the first sub-section 31 is used to connect to a conductive structure (e.g., word line) outside the stacked structure 10 so that external electrical signals can be transmitted sequentially through the second sub-section 32 and the first sub-section 31 to the gate line 111 in the gate layer 11.

[0117] For example, the thickness of the first sub-part 31 is the same as or approximately the same as the thickness of a gate layer 11.

[0118] For example, the materials of the first sub-section 31 and the second sub-section 32 may each include at least one of tungsten, cobalt, copper, aluminum, doped polysilicon, and metal silicides. The materials of the first sub-section 31 and the second sub-section 32 may be the same as or different from those of the gate layer 11.

[0119] For example, the first sub-part 31 and the second sub-part 32 can be an integrally formed structure in order to improve the reliability of the electrical contact between the first sub-part 31 and the second sub-part 32.

[0120] For example, see Figure 4The lead-out structure 30 may also include an electrical isolation layer 33 located between the second sub-section 32 and the stacked structure 10, so as to improve the electrical insulation between the lead-out structure 30 and other gate layers 11 except for the corresponding gate layer 11, thereby improving the reliability of the lead-out structure 30 in the semiconductor device 100.

[0121] For example, the material of the electrical isolation layer 33 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxide (e.g., aluminum oxide, hafnium dioxide, etc.) and its silicates, and organic insulating materials.

[0122] For example, see Figure 4 The lead-out structure 30 may also include a receiving cavity 34 formed by the second sub-part 32. Exemplarily, the receiving cavity 34 is filled with an insulating material.

[0123] For example, the cavity 34 is filled with insulating material, which can provide mechanical support for the lead-out structure 30, improve the mechanical strength of the electrical contact between the first sub-part 31 and the second sub-part 32, and thus improve the reliability of the semiconductor device 100.

[0124] For example, the insulating material filling the cavity 34 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxide (e.g., aluminum oxide, hafnium dioxide, etc.) and its silicates, and organic insulating materials.

[0125] For example, the aforementioned receiving cavity 34 may also have an air gap.

[0126] Understandably, there can be one or more air gaps. In some embodiments, air gaps may be formed when filling the receiving cavity 34 with insulating material to reduce the structural stress of the lead-out structure 30 and improve the reliability of the semiconductor device 100.

[0127] It is understood that the structure of the lead-out structure 30 is only described by way of example in this disclosure. The lead-out structure 30 may also be other structures, shapes or materials that can realize the external connection of the gate line 111. This disclosure does not limit this.

[0128] See Figure 4 The conductive layer 40 is disposed on the first surface 1a.

[0129] For example, the material of the conductive layer 40 may include semiconductor materials, such as single-crystal silicon, single-crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials.

[0130] For example, the conductive layer 40 may be partially or completely doped. For instance, the conductive layer 40 may include doped regions doped with P-type or N-type dopants. The conductive layer 40 may also include undoped regions.

[0131] See Figure 4 The conductive layer 40 covers the channel structure 20 and is connected to the channel structure 20.

[0132] For example, see Figure 4 The semiconductor channel layer 21 of the channel structure 20 penetrates the stacked structure 10 and protrudes from the first surface 1a of the stacked structure 10, thereby exposing the source end of the memory cell string M (e.g., equivalent to exposing the source end of the transistor T6). At least part of the conductive layer 40 covers and is attached to the surface of the semiconductor channel layer 21, thereby achieving coupling with the source end of the memory cell string M.

[0133] See Figure 3 and Figure 4 The conductive layer 40 at least partially covers the first surface 1a of the stacked structure 10, and at least a portion of the conductive layer 40 contacts the protruding ends of the plurality of channel structures 20 on the first surface 1a, thereby enabling the plurality of channel structures 20 to achieve a common source.

[0134] For example, see Figure 4 The conductive layer 40 may include a first sublayer 41 and a second sublayer 42. The second sublayer 42 is located between the first sublayer 41 and the stacked structure 10.

[0135] For example, the first sub-layer 41 can serve as a source layer (i.e., source line SL). For instance, the first sub-layer 41 covers and is connected to the channel structure 20 (e.g., connected to the semiconductor channel layer 21 of the channel structure 20) in order to transmit source signals to the memory cell string M.

[0136] For example, the material of the second sublayer 42 can be polycrystalline silicon.

[0137] For example, see Figure 4 The second sublayer 42 is disposed on the first surface 1a of the stacked structure 10, and the channel structure 20 penetrates the second sublayer 42. The second sublayer 42 can increase the mechanical strength of the semiconductor device 100 and improve its reliability. On the other hand, during the removal of the memory function layer 22 protruding from the first surface 1a of the channel structure 20, it can serve as an etching stop layer to avoid damage to the stacked structure 10 and the portion of the channel structure 20 located in the stacked structure 10.

[0138] For example, the first sublayer 41 and the second sublayer 42 can be crystallized into one piece after a subsequent annealing process, together serving as the source layer of the semiconductor device 100.

[0139] For example, see Figure 3 The semiconductor device 100 also includes a virtual channel structure 60. The virtual channel structure 60 may be located in the connection region S.

[0140] For example, see Figure 4 At least part of the virtual channel structure 60 can have the same structure as the channel structure 20. For example, see [reference needed]. Figure 4 The virtual channel structure 60 may also include a semiconductor channel layer and a memory function layer, with the memory function layer surrounding the semiconductor channel layer.

[0141] For example, the virtual channel structure 60 can be integrally formed with the channel structure 20. The virtual channel structure 60 can provide mechanical support for areas of the semiconductor device 100 that do not need to have storage functions (such as the connection area S), so as to prevent the stacked structure 10 in the area from collapsing.

[0142] For example, see Figure 4 The semiconductor channel layer of the virtual channel structure 60 penetrates the stacked structure 10 and one end protrudes from the first surface 1a of the stacked structure 10. At least part of the aforementioned conductive layer 40 covers and is attached to the surface of the semiconductor channel layer. That is, both the virtual channel structure 60 and the channel structure 20 are electrically connected to the conductive layer 40.

[0143] It should be noted that the aforementioned “channel structure 20” can be understood as a structure located in storage area C that can realize storage function. Although the aforementioned “virtual channel structure 60” can have the same structure as channel structure 20, it does not play the role of storing information.

[0144] See Figure 3 and Figure 4 The partition 50 is disposed between the channel structure 20 and the lead-out structure 30. The partition 50 disconnects the conductive layer 40, and the material of the partition 50 includes an insulating material.

[0145] That is, the partition 50 is used to disconnect the portion of the conductive layer 40 located on the channel structure 20 and the portion of the conductive layer 40 located on the lead-out structure 30, and to make the two portions of the conductive layer 40 electrically insulated.

[0146] For example, the material of the partition portion 50 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxide (e.g., aluminum oxide, hafnium dioxide, etc.), silicate, and organic insulating materials, or may include other materials with electrical insulating properties.

[0147] Understandably, see Figure 4When the conductive layer 40 includes a first sublayer 41 and a second sublayer 42, the partition 50 disconnects the first sublayer 41 and also disconnects the second sublayer 42.

[0148] For example, the aforementioned "located between the channel structure 20 and the lead-out structure 30" can be understood as the partition 50 being located between the region where the multiple channel structures 20 are located and the region where the multiple lead-out structures 30 are located, or it can also be understood as each lead-out structure 30 having a partition 50 between it and the channel structure 20 corresponding to the gate layer 11 to which it is electrically connected (i.e., the channel structure 20 that penetrates the gate layer 11).

[0149] For example, see Figure 3 The partition 50 may be elongated, or it may be zigzag or other shapes that meet the aforementioned conditions (located between the channel structure 20 and the lead-out structure 30). This application does not limit its specific shape.

[0150] For example, the partition portion 50 may be located on the first surface 1a, that is, the partition portion 50 extends from the upper surface of the conductive layer 40 through the conductive layer 40 to the first surface 1a, thereby ensuring that the conductive layer 40 is fully disconnected.

[0151] Alternatively, by way of example, the side surface of the partition portion 50 facing the second surface 1b may be substantially flush with the side surface of the lead-out structure 30 away from the second surface 1b, for example, flush with the upper surface of the first sub-portion 31, thereby forming a contact post above the etched lead-out structure 30 (see reference). Figure 8 During the process of making the contact post 90 in the lead-out structure 30 externally connected, the conductive layer 40 can be etched simultaneously to form the isolation part 50. That is, the external connection structure of the lead-out structure 30 and the isolation part 50 can be fabricated simultaneously, reducing the fabrication difficulty of the semiconductor device 100 and improving the fabrication efficiency.

[0152] Figure 7 During the preparation of lead-out structure 30, along Figure 3 The cross-sectional view of section line C-C' in the figure.

[0153] like Figure 7 As shown, during the fabrication of the lead-out structure 30, it is necessary to penetrate at least a portion of the stacked structure 10 and remove a portion of the sacrificial layer 13 to form a space 30' that can fill the lead-out structure 30. The sacrificial layer 13 can be removed by etching; see [reference needed]. Figure 7During the etching process, the etching solution may penetrate into the gate layer 11, which is disposed in the same layer as the sacrificial layer 13, thereby thinning or even etching away the second dielectric layer 113 around the gate line 111 adjacent to the lead-out structure 30. This significantly reduces the electrical insulation around the gate line 111, making it easy for leakage to occur between the gate line 111 and its adjacent conductive structure (such as the semiconductor channel layer of the virtual channel structure 60) (the location of the leakage can be found in [reference]). Figure 7 The leakage current (as shown in the dashed box D) can severely affect the storage function of the semiconductor device 100. For example, leakage current can cause the threshold voltage of the transistor T in the channel structure 20 to drift, affecting the electrical performance and stability of the semiconductor device 100.

[0154] This embodiment of the present disclosure provides a partition 50 to disconnect and electrically insulate the portion of the conductive layer 40 located on the channel structure 20 from the portion of the conductive layer 40 located on the lead-out structure 30. This prevents the conductive layer 40 from transmitting electrical signals to the conductive layer 40 on the lead-out structure 30 during the transmission of source signals to the channel structure 20. This avoids the formation of a loop between the gate layer 11 near the lead-out structure 30 and the portion of the conductive layer 40 located on the lead-out structure 30, thereby preventing leakage current and effectively improving the stability of the threshold voltage in the memory cell string M of the semiconductor device 100, thus improving the electrical performance and reliability of the semiconductor device 100.

[0155] Figure 8 and Figure 9 For along Figure 3 Another cross-sectional view of section line B-B' in the diagram.

[0156] In some embodiments, such as Figure 8 and Figure 9 As shown, the semiconductor device 100 also includes a plurality of virtual channel structures 60 located between the channel structure 20 and the lead-out structure 30, the plurality of virtual channel structures 60 extending through the stacked structure 10.

[0157] See Figure 3 In the orthographic projection on the second surface 1b, the partition portion 50 at least partially overlaps with at least one virtual channel structure 60. That is, the orthographic projection of the partition portion 50 on the second surface 1b at least partially overlaps with the orthographic projection of at least one virtual channel structure 60 on the second surface 1b.

[0158] For example, see Figure 3 , Figure 4 , Figure 8 and Figure 9 At least a portion of the aforementioned partition 50 may be disposed on a virtual channel structure 60 located between the channel structure 20 and the lead-out structure 30.

[0159] For example, such as Figure 4 , Figure 8 and Figure 9 As shown, the structure of at least part of the aforementioned virtual channel structure 60 is the same as the structure of the aforementioned channel structure 60.

[0160] Alternatively, by way of example, the structure of at least a portion of the aforementioned virtual channel structure 60 may differ from the structure of the channel structure 20. For example, at least a portion of the virtual channel structure 60 may be filled with at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxide (e.g., aluminum oxide, hafnium dioxide, etc.) and its silicates, and organic insulating materials. This disclosure does not limit the specific structure of the virtual channel structure 60.

[0161] For example, such as Figure 8 As shown, at least one end of the virtual channel structure 60 protrudes from the first surface 1a, and the end of the virtual channel structure 60 protruding from the first surface 1a has a recess U1, which is filled by the partition portion 50.

[0162] Or, for example, such as Figure 9 As shown, at least one end face of the virtual channel structure 60 is flush with or recessed relative to the first surface 1a, and part of the partition portion 50 covers the end face of the virtual channel structure 60.

[0163] That is, the portion or all of the end of the virtual channel structure 60 protruding from the first surface 1a is removed, and the removed portion of the virtual channel structure 60 is replaced by the partition portion 50. This disconnects the portion of the conductive layer 40 located on the channel structure 20 and the portion located on the lead-out structure 30, while removing other structures corresponding to the disconnection position of the conductive layer 40 (e.g., the portion or all of the end of the virtual channel structure 60 protruding from the first surface 1a). This prevents the two disconnected portions of the conductive layer 40 from being connected through other conductive structures (e.g., through the semiconductor channel layer of the virtual channel structure 60), so as to ensure that the conductive layer 40 is fully disconnected and further reduce the leakage risk of the semiconductor device 100.

[0164] Figure 10 For along Figure 3 Another cross-sectional view of section line E-E' in the diagram.

[0165] In some embodiments, such as Figure 10 As shown, the semiconductor device 100 also includes a gate isolation structure 70.

[0166] See Figure 2 and Figure 3 The grid isolation structure 70 extends along the first direction X. (See also...) Figure 4The gate isolation structure 70 is set through the stacked structure 10.

[0167] For example, see Figure 3 The gate isolation structure 70 extends from the storage area C to the connection area S.

[0168] For example, the grid isolation structure 70 can be disposed between two adjacent grid lines 111 disposed along the second direction Y, thereby facilitating the independent transmission of electrical signals by the two grid lines 111.

[0169] For example, the gate isolation structure 70 may include an insulating material disposed on the sidewalls, and a conductive material filled within a cavity formed by the insulating material. The insulating material on the sidewalls provides electrical isolation to the conductive material within the cavity, allowing the conductive material within the cavity to make electrical contact with the conductive layer 40, so that electrical signals on the conductive layer 40 can be transmitted through the gate isolation structure 70.

[0170] For example, the insulating material on the aforementioned sidewall may include at least one of silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxides (e.g., aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials. The conductive material filling the aforementioned cavity may include at least one of tungsten, cobalt, copper, aluminum, doped polycrystalline silicon, and metal silicides.

[0171] See Figure 3 The aforementioned partition portion 50 extends along the second direction Y. (See also...) Figure 10 In the orthographic projection on the second surface 1b, the partition portion 50 intersects with the grid line isolation structure 70.

[0172] That is, the extending direction of the partition portion 50 intersects the extending direction of the grid line isolation structure 70. For example, the extending directions of the two can be perpendicular to each other, and the orthographic projection of the partition portion 50 on the second surface 1b overlaps with the orthographic projection of the grid line isolation structure 70 on the second surface 1b.

[0173] For example, see Figure 4 At least a portion of the partition 50 may be disposed above the grid isolation structure 70.

[0174] It is understandable that the size of the partition portion 50 in the second direction Y is approximately the same as the size of the conductive layer 40 in the second direction Y, so that the partition portion 50 completely disconnects the conductive layer 40, thereby achieving sufficient insulation between the portion of the conductive layer 40 located on the channel structure 20 and the portion located on the lead-out structure 30.

[0175] By setting the extension direction of the partition portion 50 to intersect the extension direction of the gate line isolation structure 70, and setting the orthographic projection of the partition portion 50 on the second surface 1b to overlap with the orthographic projection of the gate line isolation structure 70 on the second surface 1b, the partition portion 50 can cut the conductive layer 40 into two parts in the extension direction perpendicular to the gate line 111. This makes it easier for one part of the two parts of the conductive layer 40 to be located in the storage region C and the other part to be located in the connection region S. That is, it ensures that the part of the conductive layer 40 located on the channel structure 20 and the part located on the lead-out structure 30 are disconnected from each other, thereby ensuring that the aforementioned leakage problem in the semiconductor device 100 can be solved and improving the electrical performance and reliability of the semiconductor device 100.

[0176] For example, one end of the grid isolation structure 70 protrudes from the first surface 1a, and the end of the grid isolation structure 70 protruding from the first surface 1a is provided with a notch U2, which is filled by the partition portion 50.

[0177] That is, the partition portion 50 extends from the upper surface of the conductive layer 40 (the side surface away from the second surface 1b) through the conductive layer 40 and part of the gate line isolation structure 70, all the way to the first surface 1a, thereby ensuring that the conductive layer 40 is fully disconnected.

[0178] In some embodiments, such as Figure 2 , Figure 3 , Figure 4 , Figure 8 and Figure 9 As shown, the semiconductor device 100 includes a storage region C and a connection region S. The connection region S is disposed on at least one side of the storage region C (for example, the connection region S can be disposed on both the left and right sides of a storage region C). The aforementioned channel structure 20 is disposed in the storage region C, and the aforementioned lead-out structure 30 is disposed in the connection region S.

[0179] See Figure 3 The aforementioned partition 50 is located in the connection area S near the storage area C. Specifically, the partition 50 is located in the connection area S, and is located closer to the storage area C than the lead-out structure 30.

[0180] By placing the partition 50 in the connection area S near the storage area C, it is ensured that one part of the two parts of the conductive layer 40 that are disconnected by the partition 50 is located in the storage area C and the other part is located in the connection area S. That is, it is ensured that the part of the conductive layer 40 located on the channel structure 20 and the part located on the lead-out structure 30 are disconnected from each other. This allows the transmission of electrical signals (e.g., source signals) in the channel structure 20 to be realized while avoiding leakage problems in the semiconductor device 100.

[0181] In some embodiments, see Figure 3Along the first direction X, the minimum distance d between the partition portion 50 and the channel structure 20 is greater than or equal to 15 μm. That is, the distance between the partition portion 50 and the channel structure 20 closest to the partition portion 50 along the first direction X is greater than or equal to 15 μm. For example, the distance can be 15 μm, 18.3 μm, 25.75 μm or 30 μm.

[0182] By setting the minimum spacing d between the partition 50 and the channel structure 20 to be greater than or equal to 15μm, it ensures that the partition 50 is located between the channel structure 20 and the lead-out structure 30, and controls the disconnection position of the conductive layer 40 to avoid affecting the normal storage function of the storage cell string M in the storage area C.

[0183] In some embodiments, the partition 50 is disposed between the lead-out structure 30 and the corresponding gate layer 11, and between the partition 50 and the channel structure 20. For example, see [reference needed]. Figure 4 The partition portion 50 is disposed at the position where the first sub-part 31 is connected to the corresponding gate layer 11, and between the channel structure 20.

[0184] That is, the isolation portion 50 disconnects the conductive layer 40 at the position between the channel structure 20 and the leakage position (the position where the lead-out structure 30 is connected to the corresponding gate layer 11), thereby solving the leakage problem of the semiconductor device 100 and improving the electrical performance and reliability of the semiconductor device 100.

[0185] In some embodiments, the orthographic projection of the partition portion 50 on the second surface 1b covers the orthographic projection of the location where the lead-out structure 30 is connected to the corresponding gate layer 11 on the second surface 1b. That is, the conductive layer 40 located at the location where the lead-out structure 30 is connected to the corresponding gate layer 11 (i.e., the leakage location) is removed, thereby avoiding leakage problems in the semiconductor device 100.

[0186] In some embodiments, such as Figure 8 , Figure 9 and Figure 10 As shown, the semiconductor device 100 also includes a first insulating layer 81 disposed on the side of the conductive layer 40 away from the stacked structure 10, and covers the storage region C and the connection region S of the semiconductor device 100.

[0187] See Figure 8 , Figure 9 and Figure 10 The partition 50 is embedded in the first insulating layer 81.

[0188] For example, the partition portion 50 may be made of the same material as the first insulating layer 81, in which case the partition portion 50 is integrally formed with the first insulating layer 81.

[0189] The first insulating layer 81 is used to cover the conductive layer 40 to prevent the conductive layer 40 and other conductive structures from having unexpected electrical connections. The partition portion 50 is integrally formed with the first insulating layer 81, which can improve the stability of the partition portion 50 on the one hand, and on the other hand, the two can be integrally formed, thereby reducing the manufacturing difficulty of the partition portion 50 and improving the manufacturing efficiency.

[0190] For example, the material of the first insulating layer 81 is an electrically insulating material. For instance, the material of the first insulating layer 81 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxide (e.g., aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials, but this disclosure is not limited thereto.

[0191] In some embodiments, such as Figure 8 and Figure 9 As shown, the semiconductor device 100 also includes a contact post 90. The contact post 90 penetrates the aforementioned first insulating layer 81 and is connected to the lead-out structure 30. The contact post 90 is used to realize the external connection of the lead-out structure 30.

[0192] For example, see Figure 8 and Figure 9 In the case where the lead-out structure 30 includes a first sub-part 31 and a second sub-part 32, the contact post 90 is disposed on the side of the first sub-part 31 away from the second surface 1b and is electrically connected to the first sub-part 31.

[0193] For example, it can be understood that each lead-out structure 30 is provided with a corresponding contact post 90.

[0194] It is understood that the contact post 90 has conductive properties. For example, the material of the contact post 90 may include at least one of tungsten, cobalt, copper, aluminum, and metal silicides, or may be other conductive materials.

[0195] In some embodiments, see Figure 4 , Figure 8 and Figure 9 The semiconductor device 100 may also include peripheral devices 101.

[0196] The peripheral device 101 may include at least peripheral circuitry. This peripheral circuitry can be any suitable digital, analog, and / or mixed-signal control and sensing circuitry, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., gate line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry may also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., processors and programmable logic devices (PLDs)) or memory circuitry (e.g., static random-access memory (SRAM)).

[0197] The aforementioned storage cell string M and other structures are all connected to the peripheral device 101, which is used to control access to the storage cell string M. For example, the peripheral device 101 can control the writing of data to the storage cell string M or control the reading of data from the storage cell string M.

[0198] For example, peripheral device 101 may include word line selection circuit, bit line selection circuit, control circuit, and read / write circuit.

[0199] When performing read and write operations on the memory cell string M, the read and write circuit transmits control signals to the word line selection circuit and the bit line selection circuit through the control circuit. The word line selection circuit selects a column of transistors T, and the bit line selection circuit selects a row of transistors T. The word line selection circuit and the bit line selection circuit jointly determine the address of the transistor T to be accessed.

[0200] In order to obtain the above-mentioned semiconductor device 100, this disclosure also provides a method for preparing the semiconductor device 100.

[0201] Figure 11 and Figure 12 This is a flowchart illustrating the fabrication process of the semiconductor device 100 provided in this embodiment of the disclosure. Figures 13-26 This is a cross-sectional view corresponding to each fabrication step of the semiconductor device 100.

[0202] like Figure 11 As shown, the method for fabricating the semiconductor device 100 includes the following steps S1 to S6:

[0203] S1: As Figure 13 , Figure 15 and Figure 16 As shown, a stacked structure 10 is formed.

[0204] For example, see Figure 16The stacked structure 10 includes multiple first dielectric layers 12, multiple gate layers 11, and multiple sacrificial layers 13.

[0205] Among them, see Figure 16 The multilayer first dielectric layer 12 and the multilayer gate layer 11 are alternately stacked, and the gate layer 11 and the sacrificial layer 13 are disposed on the same layer.

[0206] For example, see Figures 13-26 The semiconductor device 100 includes a storage region C and a connection region S, wherein the aforementioned gate layer 11 is located at least in the storage region C, and the aforementioned sacrificial layer 13 is located in the connection region S.

[0207] See Figures 13-26 The aforementioned stacked structure 10 includes a first surface 1a and a second surface 1b disposed opposite each other in the third direction Z, where the third direction Z is the direction in which the multilayer gate layers 11 are stacked.

[0208] For example, the step of forming the stacked structure 10 (i.e., step S1) may include the following steps S11 to S13:

[0209] S11: As Figure 13 As shown, an initial stacked structure 2 is formed on substrate 1.

[0210] For example, the aforementioned substrate 1 can be a single-layer substrate. Alternatively, in some embodiments, substrate 1 can also be a composite substrate. For instance, substrate 1 may include a polysilicon layer and a silicon oxide layer alternately stacked along the third direction Z.

[0211] For example, a composite substrate can be formed by ion implantation.

[0212] See Figure 13 The initial stack structure 2 has a storage area C and a connection area S.

[0213] See Figure 13 The initial stacked structure 2 includes a first dielectric layer 12 and a sacrificial layer 13 stacked along the third direction Z.

[0214] In this process, at least the portion of the sacrificial layer 13 located in the memory region C will be replaced by the gate layer 11 in a subsequent process.

[0215] For example, an initial stacked structure 2 can be formed on one side of the substrate 1 using any of the following thin film deposition processes: chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0216] For example, before forming the initial stacked structure 2, step S1 may further include forming at least one etch stop layer on the substrate 1.

[0217] For example, see Figure 13 A first etch stop layer 3A and a second etch stop layer 3B (i.e. the aforementioned second sublayer 42) are formed on the substrate 1.

[0218] The first etch stop layer 3A can serve as an etch stop layer during subsequent removal of the substrate 1, which helps to control the process uniformity during the removal of the substrate 1 and can protect the stacked structure 10 from damage during the removal of the substrate 1.

[0219] The material of the first etch stop layer 3A may include an insulating material, such as at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxide (e.g., aluminum oxide, hafnium dioxide, etc.) and its silicates, and organic insulating materials.

[0220] For example, the material of the first etch stop layer 3A can be the same as the material of any of the aforementioned storage functional layers 22, such as the material of the barrier layer in the storage functional layer 22. For example, the materials of the first etch stop layer 3A and the barrier layer in the storage functional layer 22 are both silicon oxide.

[0221] The second etch stop layer 3B can serve as an etch stop layer when removing the portions of the channel structure 20 and the virtual channel structure 60 that protrude from the stacked structure 10. It also helps to control process uniformity and can protect the stacked structure 10 from damage during the process.

[0222] The material of the second etch stop layer 3B includes semiconductor materials, such as monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials.

[0223] For example, the second etch stop layer 3B can be made of the same material as the source line SL (i.e., the aforementioned first sublayer 41). For instance, both the second etch stop layer 3B and the source line SL are made of polysilicon.

[0224] S12: As Figure 15 As shown, a gate gap 4 is formed, and etching fluid is injected through the gate gap 4 to etch at least a portion of the sacrificial layer 13 located in the storage region C to form a cavity U'.

[0225] For example, see Figure 15 The gate gap 4 penetrates the initial stacked structure 2 in a direction perpendicular to the substrate 1, and the gate gap 4 is an opening facing away from the first surface 1a.

[0226] By injecting etching solution into the opening, part of the sacrificial layer 13 is removed. It is understood that the etching range and etching location of the sacrificial layer 13 can be controlled by controlling the volume of etching solution injected into the opening of the gate slot 4.

[0227] For example, the process of forming the gate gap 4 may include wet etching or dry etching, etc.

[0228] For example, see Figure 15 The portion of the sacrificial layer 13 located in the connecting region S can also be etched to form a cavity U'.

[0229] For example, see Figure 15 The portion of the sacrificial layer 13 located in the connection region S is retained, which facilitates the subsequent formation of the lead-out structure 30.

[0230] S13: As Figure 16 As shown, the cavity U' is filled with gate material to form a gate layer 11, and the gate gap 4 is filled to form a gate line isolation structure 70.

[0231] For example, see Figure 16 The gate layer 11 formed is disposed on the same layer as the sacrificial layer 13 that has not been etched away.

[0232] For example, step S13 may further include filling the cavity U' with material multiple times to sequentially form the adhesive layer 112, the second dielectric layer 113 and the grid line 111.

[0233] For example, the gate material can be filled into the cavity U' through the opening of the aforementioned gate gap 4. The gate layer 11 can be fabricated using any thin film deposition process, such as ALD, CVD, PVD, etc.

[0234] For example, see Figure 16 The resulting gate isolation structure 70 penetrates the stack structure 10 and can divide the stack structure 10 into multiple storage blocks.

[0235] For example, the step of forming the gate isolation structure 70 may include coating the inner wall of the gate gap 4 with an insulating material after forming the gate layer 11, and then filling the gate gap 4 with a conductive material to form the gate isolation structure 70.

[0236] S2: As Figure 14 As shown, a channel structure 20 is formed.

[0237] See Figure 16 The channel structure 20 penetrates the stacked structure 10 and protrudes from the first surface 1a of the stacked structure 10.

[0238] For example, the channel structure 20 includes a semiconductor channel layer 21 and a storage function layer 22. For the specific structure, please refer to the description of the semiconductor device 100 in the foregoing embodiments, which will not be repeated here.

[0239] It is understood that the preparation order of the aforementioned steps S1 and S2 can overlap. For example, step S2 can be performed before step S12 and after step S11. That is, the channel structure 20 can be prepared after the initial stacked structure 2 is formed. See [reference needed]. Figure 14 The formed channel structure 20 penetrates the initial stacked structure 2.

[0240] For example, see Figure 14 Step S2 may further include forming a virtual channel structure 60. Exemplarily, the virtual channel structure 60 may have the same structure as the channel structure 20.

[0241] For example, the step of forming the channel structure 20 may include forming a memory channel via in a direction perpendicular to the substrate 1, the memory channel via penetrating the initial stacked structure 2. A memory functional layer 22 and a semiconductor channel layer 21 are sequentially formed in the memory channel via, and a channel filling layer 23 is filled within the accommodating space enclosed by the semiconductor channel layer 21.

[0242] For example, the memory channel can be formed using either a dry etching process or a wet etching process, and the memory functional layer 22 and the semiconductor channel layer 21 can be formed using any of the thin film deposition processes of CVD, PVD and ALD.

[0243] S3: As Figure 17 As shown, lead-out structure 30 is formed.

[0244] See Figure 17 The lead-out structure 30 extends from the second surface 1b to the corresponding gate layer 11 and is connected to the corresponding gate layer 11.

[0245] For example, the lead-out structure 30 can be formed using any of the thin film deposition processes of CVD, PVD, and ALD.

[0246] For example, see Figure 17 The lead-out structure 30 may include a first sub-part 31 and a second sub-part 32. When the lead-out structure 30 includes a first sub-part 31 and a second sub-part 32, the aforementioned step S3 may include:

[0247] The stacked structure 10 is etched to form a contact hole that penetrates at least a portion of the stacked structure 10.

[0248] For example, a photoresist layer is formed on the side of the stacked structure 10 away from the substrate 1, and vias are formed on the photoresist layer using an exposure and development process. Based on the patterned photoresist layer, the stacked structure 10 is etched to form contact holes.

[0249] It should be noted that there can be multiple contact holes, each exposing a corresponding sacrificial layer 13 (the sacrificial layer 13 disposed on the same layer as the gate layer 11 to be connected to the lead-out structure 30). It is understood that the contact hole is used to form the lead-out structure 30 in the subsequent process, and each lead-out structure 30 will correspond to and be electrically connected to a gate layer 11.

[0250] An electrical isolation layer 33 is formed inside the contact hole, and the electrical isolation layer 33 covers the sidewalls and bottom of the contact hole (to...). Figure 17 (The orientation in the middle is for reference).

[0251] It should be noted that the electrical isolation layer 33 is used to prevent the subsequently formed lead-out structure 30 from being electrically connected to the gate layer 11 corresponding to the sidewall of the contact hole.

[0252] Remove the portion of the electrical isolation layer 33 located at the bottom of the contact hole to expose the sacrificial layer 13 corresponding to the contact hole.

[0253] Etching fluid is injected through the contact hole to remove at least a portion of the sacrificial layer 13 corresponding to the contact hole, forming an etching cavity.

[0254] It is understandable that the etching cavity is disposed on the same layer as the gate layer, and the etching cavity exposes the sidewall of the gate layer 11 so that the first sub-part 31 filled subsequently can make electrical contact with the gate layer 11.

[0255] The etching cavity is filled with conductive material to form the first sub-section 31.

[0256] The contact hole is filled with conductive material to form the second sub-part 32.

[0257] For example, forming the second sub-part 32 may include:

[0258] A conductive material is filled into the contact hole to form an initial second sub-part. The initial second sub-part is etched to form a receiving cavity 34. An insulating material is filled into the receiving cavity 34. The top of the receiving cavity 34 is sealed with a conductive material, and the sealed portion together with the sidewall of the receiving cavity 34 forms the second sub-part 32.

[0259] It is understood that the foregoing embodiments of this disclosure are merely illustrative of the preparation process of the lead-out structure 30 and do not constitute a limitation on the specific preparation process of the lead-out structure 30. Any other preparation process capable of preparing the lead-out structure 30 is within the protection scope of this disclosure.

[0260] For example, the preparation order of S1 to S3 can be arranged arbitrarily if feasible, and this application does not impose any restrictions on it.

[0261] For example, the method for fabricating the aforementioned semiconductor device 100 may further include:

[0262] Q1: As Figure 18 As shown, peripheral device 101 is formed.

[0263] For example, the peripheral device 101 can be bonded to the structure obtained in step S3 above using X-tacking technology.

[0264] For example, in some embodiments, prior to bonding, a process of applying treatment to the bonding surfaces may be included, such as plasma treatment, wet treatment and / or heat treatment, to improve the bonding effect.

[0265] For example, prior to forming the peripheral device 101, an array interconnect layer 300 may also be formed (see [reference]). Figure 18 The array interconnect layer 300 can be coupled to the memory cell string M (see, for example, [reference needed]). Figure 18 (The array interconnect layer 300 is coupled to one end of the channel structure 20 near the peripheral device 101) so as to transmit electrical signals to the memory cell string M.

[0266] For example, the array interconnect layer 300 may include at least one interconnect conductor layer. The interconnect conductor layer may include multiple interconnect lines, such as bit lines BL for transmitting drain signals to the memory cell string M, or word line interconnect lines coupled to word lines WL0 to WL3.

[0267] For example, the array interconnect layer 300 may also include one or more interlayer insulating layers and a plurality of local contacts R that are insulated from each other by these interlayer insulating layers. The local contacts R may include, for example, bit line contacts for coupling with bit lines BL in the interconnect conductor layer, or may include drain select gate contacts for coupling with drain select gates.

[0268] The interconnect conductor layer and the interconnect conductor layer can be made of conductive materials, which may include at least one of tungsten, cobalt, copper, aluminum, and metal silicides, or other suitable materials.

[0269] The aforementioned peripheral device 101 and the aforementioned stacked structure 10 can be bonded together through the array interconnect layer 300. During the bonding process, the bonding contacts in the peripheral device 101 and the contacts in the array interconnect layer 300 can be aligned and made into contact with each other, thereby achieving electrical connection between the channel structure 20 and the peripheral device 101.

[0270] For example, the method for fabricating the aforementioned semiconductor device 100 may further include:

[0271] Q2: As Figure 19 As shown, the substrate 1 is removed, and the portion of the storage function layer 22 protruding from the first surface 1a of the channel structure 20 and the virtual channel structure 60 is removed.

[0272] See Figure 19 After removing the substrate 1 and the storage function layer 22, the semiconductor channel layer 21 of the channel structure 20 and the virtual channel structure 60 can be exposed, which facilitates the electrical connection between the semiconductor channel layer 21 and the source line SL (i.e., the conductive layer 40) in subsequent processes.

[0273] It is understood that the aforementioned steps Q1 and Q2 can be set after step S3, and the order of steps Q1 and Q2 can be interchanged. In step Q2, the order of removing substrate 1 and removing the memory functional layer can be interchanged. This application does not impose any restrictions on this.

[0274] For example, in the aforementioned step Q2, the first etch stop layer 3A can be used as an etch stop layer when removing the substrate 1, thereby avoiding damage to the stacked structure 10 and other structures during the removal of the substrate 1.

[0275] For example, in step Q2 described above, the portion of the channel structure 20 extending out of the stacked structure 10 and the portion of the virtual channel structure 60 extending out of the stacked structure 10 can be etched using either dry etching or wet etching processes. For instance, using a wet etching process, the portions of the channel structure 20 and the virtual channel structure 60 extending out of the stacked structure 10 are isotropically etched, thereby exposing the semiconductor channel layer of the channel structure 20 and the semiconductor channel layer 21 of the virtual channel structure 60.

[0276] For example, the second etch stop layer 3B can be used as an etch stop layer when removing the storage function layer 22 of the channel structure 20 and the virtual channel structure 60, thereby avoiding damage to the stacked structure 10 and other structures during the process.

[0277] For example, when the material of the second etch stop layer 3B is the same as the material of any one of the barrier layer 221, charge trapping layer 222 and tunneling layer 223 in the storage functional layer, for example, when the material of the second etch stop layer 3B is the same as the material of the barrier layer 221, at least a portion of the second etch stop layer 3B may also be removed in step Q2.

[0278] For example, after removing the storage function layer 22 of the channel structure 20 and the virtual channel structure 60, the fabrication method of the aforementioned semiconductor device 100 may further include: ion doping the semiconductor channel layer 21.

[0279] For example, a plasma implantation process can be used to implant ions into the semiconductor channel layer 21 to improve the adhesion and conductivity between the source line SL and the semiconductor channel layer 21. The implanted ions may include metal ions, such as tungsten ions.

[0280] For example, see Figure 19 At least the portion of the semiconductor channel layer 21 protruding from the first surface 1a is ion implanted.

[0281] S4: As Figure 20 As shown, a conductive layer 40 is formed.

[0282] See Figure 20 A conductive layer 40 is disposed on the first surface 1a. The conductive layer 40 covers the channel structure 20 and is connected to the channel structure 20.

[0283] For example, see Figure 20 The conductive layer 40 covers the semiconductor channel layer 21 of the channel structure 20, realizing electrical connection with the semiconductor channel layer 21, thereby facilitating the transmission of electrical signals to the channel structure 20, such as the transmission of source signals.

[0284] For example, see Figure 20 The conductive layer 40 also covers the virtual channel structure 60 and is electrically connected to the virtual channel structure 60.

[0285] For example, see Figure 20 In the case where the conductive layer 40 includes a first sublayer 41 and a second sublayer 42, the second sublayer 42 is formed in step S4. This second sublayer 42 serves as a source line SL covering the first sublayer 41, the channel structure 20, and the virtual channel structure 60. The first sublayer 41 can be at least a portion of the remaining second etch stop layer 3B from step Q2.

[0286] For example, see Figure 20 In some embodiments, the thickness of the second sublayer 42 is uniform. For example, the second sublayer 42 can be formed using any of the following thin film deposition processes: chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0287] Exemplarily, in other embodiments, the surface of the second sublayer 42 that is away from the stacked structure 10 is parallel to the first surface 1a of the stacked structure 10. For example, the initial source layer can be formed using any of the thin film deposition processes of CVD, PVD, and ALD, and then the surface of the initial source layer can be planarized using a planarization process to form the second sublayer 42.

[0288] S5: As Figure 21 He Ru Figure 22 As shown, the conductive layer 40 is disconnected.

[0289] See Figure 22 A trench V is formed between the two disconnected portions of the conductive layer 40. The trench V is located between the channel structure 20 and the lead-out structure 30.

[0290] For example, see Figure 22 The groove V can be located on the virtual channel structure 60 and replaces the portion of the virtual channel structure 60 that protrudes from the first surface 1a.

[0291] For example, see Figure 22 In the case where the conductive layer 40 includes a first sublayer 41 and a second sublayer 42, the first sublayer 41 is disconnected and the second sublayer 42 is also disconnected in step S5.

[0292] For example, see Figure 21 and Figure 22 Step S5 may include:

[0293] S51: As Figure 21 As shown, a second insulating layer 82 and a mask P are formed.

[0294] Among them, see Figure 21 The second insulating layer 82 covers the side of the conductive layer 40 away from the stacked structure 10, and the mask P is disposed on the side of the second insulating layer 82 away from the conductive layer 40.

[0295] See Figure 21 The mask P has an opening that exposes the location to be etched, so that the conductive layer 40 can be etched subsequently to disconnect the conductive layer 40.

[0296] For example, see Figure 21 Step S51 may also include forming a third etch stop layer 3C.

[0297] See Figure 21 The third etch stop layer 3C is disposed between the conductive layer 40 and the second insulating layer 82. The third etch stop layer 3C is used to protect the conductive layer 40 from damage during the subsequent removal of the second insulating layer 82.

[0298] S52: As Figure 22As shown, etching is performed according to mask P to disconnect the conductive layer 40 and remove the second insulating layer 82.

[0299] For example, see Figure 22 During the etching process based on the mask P, the etching depth can extend into the stacked structure 10 to ensure that the conductive layer 40 is fully disconnected.

[0300] For example, see Figure 23 and Figure 24 After disconnecting the conductive layer 40, the method for fabricating the semiconductor device 100 may further include:

[0301] Remove the third etch stop layer 3C and anneal the conductive layer 40.

[0302] For example, this step may include:

[0303] S53: See also Figure 23 Remove the portion of the third etch stop layer 3C that is parallel to the first surface 1a.

[0304] By step S53, the surface of the conductive layer 40 that is away from the first surface 1a can be exposed, so that the conductive layer 40 can be heat-treated in the future.

[0305] S54: See also Figure 24 The conductive layer 40 is heat-treated to remove the residual third etch stop layer 3C.

[0306] For example, see Figure 24 By heat-treating the conductive layer 40, including annealing, sintering or other processes, the conductive layer 40 can be silicided, thereby improving its conductivity.

[0307] For example, see Figure 23 and Figure 24 When the conductive layer 40 includes a first sub-layer 41 and a second sub-layer 42, after the conductive layer 40 is heat-treated in step S54, the first sub-layer 41 and the second sub-layer 42 can be bonded together, further improving the stability and conductivity of the conductive layer 40.

[0308] By step S53, only the portion of the third etch stop layer 3C parallel to the first surface 1a is removed, exposing the conductive layer 40 so that the conductive layer 40 can be heat-treated. At the same time, the portion of the third etch stop layer 3C located on the sidewall of the channel structure 20 and the virtual channel structure 60 is retained. This prevents the portions of the channel structure 20 and the virtual channel structure 60 protruding from the first surface 1a from collapsing during the heat treatment of the conductive layer 40.

[0309] S6: As Figure 25 As shown, the groove V is filled to form the partition portion 50.

[0310] The material of the partition 50 is electrically insulating, thereby achieving electrical insulation between the two disconnected parts of the conductive layer 40.

[0311] The semiconductor device 100 obtained by this fabrication method has a partition 50 that disconnects and electrically insulates the portion of the conductive layer 40 located on the channel structure 20 from the portion of the conductive layer 40 located on the lead-out structure 30. This prevents the conductive layer 40 from transmitting electrical signals to the conductive layer 40 on the lead-out structure 30 during the transmission of source signals to the channel structure 20. This avoids the formation of a loop between the gate layer 11 near the lead-out structure 30 and the portion of the conductive layer 40 located on the lead-out structure 30, thereby preventing leakage current and effectively improving the stability of the threshold voltage in the memory cell string M of the semiconductor device 100. This, in turn, improves the electrical performance and reliability of the semiconductor device 100.

[0312] In some embodiments, such as Figure 12 As shown, the method for fabricating the semiconductor device 100 may further include the following steps S7 to S9:

[0313] S7: As Figure 22 As shown, while disconnecting the conductive layer 40, the conductive layer 40 is etched to form the first through hole H1.

[0314] That is, the step of disconnecting the conductive layer 40 (i.e. step S5) can be performed simultaneously with the step of forming the first via H1, thereby simplifying the fabrication process of the semiconductor device 100 and improving the fabrication efficiency of the semiconductor device 100.

[0315] See Figure 22 The first through hole H1 exposes the lead-out structure 30. For example, the first through hole H1 exposes the first sub-part 31 in the lead-out structure 30, thereby facilitating the subsequent external connection of the lead-out structure 30.

[0316] For example, see Figure 22 When both the trench V and the first through hole H1 are formed simultaneously, the depths of the trench V and the first through hole H1 can be approximately the same. For example, the bottom of both can reach the plane of the side surface of the first sub-part 31 that is away from the second surface 1b.

[0317] It is understood that the foregoing embodiments are merely illustrative of the depths of the trench V and the first through hole H1, and the embodiments disclosed herein do not impose any limitations on them. For example, the depths of the trench V and the first through hole H1 may be different. The bottom of the trench V may reach the first surface 1a, and the depth of the first through hole H1 may reach the plane on the side of the first sub-part 31 that is away from the second surface 1b.

[0318] S8: As Figure 25 As shown, an insulating layer 80 is formed.

[0319] See Figure 25 The insulating layer 80 is disposed on the side of the conductive layer 40 away from the stacked structure 10, and covers the storage region C and the connection region S of the semiconductor device 100.

[0320] See Figure 25 The insulating layer 80 fills the first through-hole H1 and the trench V, wherein the portion of the insulating layer 80 filling the trench V forms the partition portion 50. The portion of the insulating layer 80 filling the first through-hole H1 can prevent the lead-out structure 30 from having an unexpected electrical connection.

[0321] For example, the insulating layer 80 can be formed using any of the thin film deposition processes of CVD, PVD, and ALD.

[0322] It is understandable that the portion of the insulating layer 80 other than the partition portion 50 can be equivalent to the aforementioned first insulating layer 81.

[0323] By simultaneously fabricating the isolation portion 50 during the fabrication of the insulating layer 80, that is, by incorporating the fabrication process of the isolation portion 50 into the fabrication process of the external interconnection structure of the lead-out structure 30, the fabrication process of the semiconductor device 100 can be simplified and the fabrication efficiency of the semiconductor device 100 can be improved.

[0324] S9: such as Figure 26 As shown, a contact post 90 is formed.

[0325] See Figure 26 The contact post 90 penetrates the insulation layer 80 and is connected to the lead-out structure 30.

[0326] For example, before forming the contact post 90, the preparation method may further include forming a second through hole through the insulating layer 80, the second through hole being located on the side of the lead-out structure 30 away from the stacked structure 10, for exposing the lead-out structure 30, after the aforementioned contact post 90 is filled in the second through hole, it is electrically connected to the lead-out structure 30.

[0327] For example, the diameter of the second through hole is smaller than the diameter of the first through hole H1, so that some insulating material is retained on the sidewall of the first through hole H1, thereby preventing the contact post 90 from contacting the conductive structure such as the conductive layer 40.

[0328] For example, see Figure 26 The orthographic projection of the contact post 90 on the second surface 1b is located within the range of the orthographic projection of the lead-out structure 30 on the second surface 1b. That is, the contact post 90 is positioned above the lead-out structure 30, thereby facilitating the external connection of the lead-out structure 30 by the contact post 90.

[0329] For example, other conductive structures can also be formed simultaneously in this step. For instance, a source contact can be formed on the side of the conductive layer 40 away from the stacked structure 10, and it penetrates the insulating layer 80 and is electrically connected to the conductive layer 40 so as to realize the external connection of the conductive layer 40.

[0330] For example, the source contact may be located in one of the two disconnected portions of the conductive layer 40, covering the portion of the channel structure 20, thereby facilitating the transmission of the source signal to the channel structure 20.

[0331] Understandably, see Figure 26 At least a portion of the insulating layer 80 is disposed on the side of the lead-out structure 30 away from the second surface 1b of the stacked structure 10. The orthographic projection of the contact post 90 on the second surface 1b is located within the range of the orthographic projection of the lead-out structure 30 on the second surface 1b, thereby facilitating the connection of the contact post 90 to the lead-out structure 30 after penetrating the insulating layer 80, thereby facilitating the transmission of external signals from the external structure to the lead-out structure 30.

[0332] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: A stacked structure includes multiple gate layers stacked together; the stacked structure includes a first surface and a second surface disposed opposite each other in a third direction, the third direction being the direction in which the multiple gate layers are stacked. A channel structure extends through the stacked structure and protrudes from the first surface of the stacked structure; An outgoing structure extends from the second surface through to the corresponding gate layer and is connected to the corresponding gate layer; A conductive layer is disposed on the first surface; the conductive layer covers the channel structure and is connected to the channel structure; A partition is provided between the channel structure and the lead-out structure; the partition disconnects the conductive layer, and the material of the partition includes an insulating material.

2. The semiconductor device according to claim 1, characterized in that, Also includes: A plurality of virtual channel structures are disposed between the channel structure and the lead-out structure, the plurality of virtual channel structures penetrating the stacked structure; In the orthographic projection on the second surface, the partition portion at least partially overlaps with at least one of the virtual channel structures.

3. The semiconductor device according to claim 2, characterized in that, At least one end of the virtual channel structure protrudes from the first surface, and the end of the virtual channel structure protruding from the first surface has a recess, which is filled by the partition portion. And / or, At least one end face of the virtual channel structure is flush with or recessed relative to the first surface, and a portion of the partition portion covers the end face of the virtual channel structure.

4. The semiconductor device according to claim 1, characterized in that, Also includes: A grid isolation structure extends through the stacked structure and along a first direction; The first direction is parallel to the second surface; The partition extends along a second direction, which is parallel to the second surface and intersects the first direction. In the orthographic projection on the second surface, the partition portion intersects with the grid line isolation structure.

5. The semiconductor device according to claim 4, characterized in that, One end of the grid isolation structure protrudes from the first surface, and the end of the grid isolation structure protruding from the first surface is provided with a notch, which is filled by the partition portion.

6. The semiconductor device according to claim 1, characterized in that, include: A storage area and a connection area, wherein the connection area is located on at least one side of the storage area; The channel structure is located in the storage area, the lead-out structure is located in the connection area, and the partition is located in the connection area near the storage area.

7. The semiconductor device according to claim 6, characterized in that, The stacked structure further includes multiple first dielectric layers and multiple sacrificial layers, wherein the multiple first dielectric layers are alternately stacked with multiple gate layers, and one gate layer and one sacrificial layer are disposed on the same layer; the first dielectric layers are located at least in the memory region, and the sacrificial layers are located in the interconnect region; The lead-out structure includes a first sub-part and a second sub-part. The first sub-part is embedded in a sacrificial layer disposed in the same layer as the corresponding gate layer and is connected to the corresponding gate layer. The second sub-part extends from the second surface to the sacrificial layer disposed in the same layer as the corresponding gate layer and is connected to the first sub-part. The partition is located between the first sub-part and the corresponding gate layer, and the channel structure.

8. The semiconductor device according to claim 1, characterized in that, Along the first direction, the minimum distance between the partition and the channel structure is greater than or equal to 15 μm.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that, Also includes: A first insulating layer is disposed on the side of the conductive layer away from the stacked structure and covers the storage region and connection region of the semiconductor device; The partition is integrally formed with the first insulating layer.

10. The semiconductor device according to claim 9, characterized in that, Also includes: The contact post penetrates the first insulating layer and is connected to the lead-out structure.

11. A method for fabricating a semiconductor device, characterized in that, include: A stacked structure is formed; the stacked structure includes multiple gate layers; the stacked structure includes a first surface and a second surface disposed opposite each other in a third direction, the third direction being the direction in which the multiple gate layers are stacked. A channel structure is formed; the channel structure penetrates the stacked structure and protrudes from the first surface of the stacked structure; A lead-out structure is formed; it extends from the second surface to the corresponding gate layer and is connected to the corresponding gate layer; Form a conductive layer; The conductive layer is disposed on the first surface; the conductive layer covers the channel structure and is connected to the channel structure; The conductive layer is disconnected; a trench is formed between the two disconnected portions of the conductive layer; the trench is located between the channel structure and the lead-out structure. The groove is filled to form a partition; the material of the partition is electrically insulating.

12. The preparation method according to claim 11, characterized in that, Also includes: While disconnecting the conductive layer, the conductive layer is etched to form a first through-hole; The first through hole exposes the lead-out structure; Form an insulating layer; The insulating layer is disposed on the side of the conductive layer away from the stacked structure and covers the storage area and connection area of ​​the semiconductor device; the insulating layer fills the first via and the trench, and the portion of the insulating layer filling the trench forms the partition portion; Forming contact columns; The contact post penetrates the insulation layer and is connected to the lead-out structure.

13. A storage system, characterized in that, include: The semiconductor device as described in any one of claims 1 to 10; A controller is coupled to the semiconductor device to control the semiconductor device to store data.

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