A power device and a method for manufacturing the same

Abstract

The present invention discloses a power device and a preparation method thereof, wherein the power device comprises: an epitaxial structure comprises an active region and an edge region, wherein the edge region surrounds the active region; the edge region comprises a first edge region and a second edge region, wherein the first edge region of the epitaxial structure is an electrical isolation region; a conductive channel is provided at an interface between a channel layer and a barrier layer in the second edge region; a doped nitride semiconductor layer comprises a first region and a second region connected to each other; the first region covers a portion of the active region of the epitaxial structure, a vertical projection of the second region on the barrier layer is located in the conductive channel of the second edge region, and a distance between an edge of the conductive channel of the second edge region and a vertical projection of an edge of the second region on the barrier layer is greater than a first preset value; a passivation layer comprises a first groove and a second groove; a source electrode is located in the first groove, and a drain electrode is located in the second groove. The present invention can reduce gate leakage and improve the reliability of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power device and a preparation method thereof. Background Art

[0002] During the preparation process of power devices, there may be problems such as gate leakage and reduced device reliability. Summary of the invention

[0003] The invention provides a power device and a preparation method thereof, which can reduce gate leakage and improve the reliability of the device.

[0004] According to one aspect of the present invention, there is provided a power device, comprising:

[0005] An epitaxial structure, the epitaxial structure comprises a substrate, a buffer layer, a channel layer and a barrier layer which are stacked in sequence; the epitaxial structure comprises an active region and an edge region, the edge region surrounds the active region; the edge region comprises a first edge region and a second edge region, the first edge region of the epitaxial structure is an electrical isolation region; a conductive channel is provided at an interface between the channel layer and the barrier layer in the second edge region;

[0006] A doped nitride semiconductor layer, the doped nitride semiconductor layer is located on a side of the barrier layer away from the substrate; the doped nitride semiconductor layer includes a first region and a second region connected to each other; the first region covers a portion of the active region of the epitaxial structure, a vertical projection of the second region on the barrier layer is located in a conductive channel of the second edge region, and a distance between an edge of the conductive channel of the second edge region and a vertical projection of an edge of the second region on the barrier layer is greater than a first preset value;

[0007] A passivation layer, the passivation layer is located on a side of the doped nitride semiconductor layer away from the epitaxial structure; the passivation layer comprises a first trench and a second trench, a vertical projection of the first trench on the epitaxial structure overlaps with the active area, and a vertical projection of the second trench on the epitaxial structure overlaps with the active area;

[0008] A source electrode and a drain electrode, wherein the source electrode is located in the first trench and the drain electrode is located in the second trench.

[0009] Optionally, the first preset value is greater than 25 nm.

[0010] Optionally, the vertical projection of the doped nitride semiconductor layer on the epitaxial structure is in the shape of a ring;

[0011] The vertical projection of the first trench on the epitaxial structure is located in the central area of ​​the ring, and the vertical projection of the second trench on the epitaxial structure is located on one side of the ring.

[0012] Optionally, the power device further includes:

[0013] The gate is located at a side of the doped nitride semiconductor layer away from the epitaxial structure; the gate at least covers a portion of the doped nitride semiconductor layer.

[0014] Optionally, the doped nitride semiconductor layer includes a P-type GaN layer or a P-type AlGaN layer.

[0015] According to one aspect of the present invention, there is provided a method for preparing a power device, comprising:

[0016] An epitaxial structure is formed; the epitaxial structure comprises a substrate, a buffer layer, a channel layer and a barrier layer which are stacked in sequence; the epitaxial structure comprises an active region and an edge region, the edge region surrounds the active region; the edge region comprises a first edge region and a second edge region;

[0017] A doped nitride semiconductor layer is formed on a side of the barrier layer away from the substrate; the doped nitride semiconductor layer includes a first region and a second region connected to each other; the first region covers a portion of the active region of the epitaxial structure, and a vertical projection of the second region on the barrier layer is located in the second edge region;

[0018] A passivation layer is formed on a side of the doped nitride semiconductor layer away from the epitaxial structure; the passivation layer includes a first trench and a second trench, a vertical projection of the first trench on the epitaxial structure overlaps with the active area, and a vertical projection of the second trench on the epitaxial structure overlaps with the active area;

[0019] forming a source electrode at one side of the first trench and forming a drain electrode in the second trench;

[0020] A protective layer is formed on a side of the passivation layer away from the epitaxial structure; a vertical projection of the protective layer on the epitaxial structure covers an active area of ​​the epitaxial structure, and a vertical projection of the protective layer on an edge region of the epitaxial structure overlaps with a second edge region; a distance between a vertical projection of an edge of the second region of the doped nitride semiconductor layer on the epitaxial structure and a vertical projection of an edge of the protective layer on the epitaxial structure is greater than a second preset value;

[0021] The epitaxial structure is processed so that a first edge region of the epitaxial structure is an electrical isolation region; and a distance between an edge of a conductive channel in a second edge region and an edge of a second region of the doped nitride semiconductor layer projected vertically on the barrier layer is greater than a first preset value;

[0022] Remove the protective layer.

[0023] Optionally, the first preset value is greater than 25 nm; the second preset value is greater than 25 nm.

[0024] Optionally, forming a protective layer on a side of the passivation layer away from the epitaxial structure includes:

[0025] forming a protective material layer on a side of the passivation layer away from the epitaxial structure;

[0026] The protective material layer is patterned and etched to form a protective layer.

[0027] Optionally, forming a doped nitride semiconductor layer on the barrier layer away from the substrate includes:

[0028] forming a doped nitride semiconductor material layer on one side of the epitaxial structure;

[0029] The doped nitride semiconductor material layer is pattern-etched to form a doped nitride semiconductor layer; wherein the vertical projection shape of the doped nitride semiconductor layer on the epitaxial structure is a ring.

[0030] Optionally, forming a passivation layer on a side of the doped nitride semiconductor layer away from the epitaxial structure includes:

[0031] forming a passivation layer on a side of the doped nitride semiconductor layer away from the epitaxial structure; the passivation layer covers the doped nitride semiconductor layer and the epitaxial structure not covered by the doped nitride semiconductor layer;

[0032] The passivation layer is etched to form a first groove and a second groove; wherein the vertical projection of the first groove on the epitaxial structure is located in the central area of ​​the ring, and the vertical projection of the second groove on the epitaxial structure is located on one side of the ring.

[0033] Optionally, after forming a doped nitride semiconductor layer on a side of the barrier layer away from the substrate, the method further includes:

[0034] A gate is formed on a side of the doped nitride semiconductor layer away from the epitaxial structure; the gate at least covers a portion of the doped nitride semiconductor layer.

[0035] Optionally, the epitaxial structure is processed so that the first edge region of the epitaxial structure is an electrical isolation region, including:

[0036] The epitaxial structure is subjected to ion bombardment, so that a first edge region of the epitaxial structure is an electrical isolation region.

[0037] Optionally, the ion source of the ion bombardment is at least one of nitrogen, fluorine, oxygen, and argon.

[0038] The power device provided by the technical solution of the embodiment of the present invention includes: an epitaxial structure, the epitaxial structure includes a substrate, a buffer layer, a channel layer and a barrier layer which are stacked in sequence; the epitaxial structure includes an active area and an edge area, the edge area surrounds the active area; the edge area includes a first edge area and a second edge area, the first edge area of ​​the epitaxial structure is an electrical isolation area; a conductive channel is provided at the interface between the channel layer and the barrier layer in the second edge area; a doped nitride semiconductor layer, the doped nitride semiconductor layer is located on a side of the barrier layer away from the substrate; the doped nitride semiconductor layer includes a first area and a second area connected to each other; the first The region covers part of the active area of ​​the epitaxial structure, the vertical projection of the second region on the barrier layer is located in the conductive channel of the second edge region, and the distance between the edge of the conductive channel of the second edge region and the vertical projection of the edge of the second region on the barrier layer is greater than a first preset value; a passivation layer, the passivation layer is located on the side of the doped nitride semiconductor layer away from the epitaxial structure; the passivation layer includes a first trench and a second trench, the vertical projection of the first trench on the epitaxial structure overlaps with the active area, and the vertical projection of the second trench on the epitaxial structure overlaps with the active area; a source and a drain, the source is located in the first trench, and the drain is located in the second trench. In the embodiment of the present invention, the vertical projection of the second region on the barrier layer is located in the conductive channel of the second edge region, and the distance between the vertical projection of the edge of the second region on the barrier layer and the edge of the conductive channel of the second edge region is greater than a first preset value; it can avoid damaging the doped nitride semiconductor layer when forming an electrical isolation region for the first edge region, thereby reducing gate leakage and improving the reliability of the device.

[0039] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 It is a schematic diagram of the structure of a power device provided by an embodiment of the present invention.

[0042] Figure 2 yes Figure 1 A schematic diagram of a cross-sectional structure along section line A1A2.

[0043] Figure 3 It is a flow chart of a method for preparing a power device provided by an embodiment of the present invention.

[0044] Figure 4-Figure 10 It is a schematic diagram of an intermediate structure of a power device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0045] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0046] It should be noted that the terms "first", "second", etc. in the present invention are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0047] An embodiment of the present invention provides a power device, Figure 1 is a schematic diagram of the structure of a power device provided by an embodiment of the present invention, Figure 2 yes Figure 1 A schematic cross-sectional structure diagram along the section line A1A2, the power device includes:

[0048] The epitaxial structure 10 includes a substrate 11, a buffer layer 12, a channel layer 13 and a barrier layer 14 which are stacked in sequence; the epitaxial structure 10 includes an active area 01 and an edge area 02, and the edge area 02 surrounds the active area 01; the edge area 02 includes a first edge area 03 and a second edge area 04, and the first edge area 03 of the epitaxial structure 10 is an electrical isolation area; a conductive channel is provided at the interface between the channel layer 13 and the barrier layer 14 in the second edge area 04.

[0049] A doped nitride semiconductor layer 20, the doped nitride semiconductor layer 20 is located on a side of the barrier layer 14 away from the substrate 11; the doped nitride semiconductor layer 20 includes a first region 21 and a second region 22 connected to each other; the first region 21 covers a portion of the active area 01 of the epitaxial structure 10, the vertical projection of the second region 22 on the barrier layer 14 is located in the conductive channel of the second edge region 04, and the distance D1 between the edge of the conductive channel of the second edge region 04 and the vertical projection of the edge of the second region 22 on the barrier layer 14 is greater than a first preset value; a passivation layer 40, the passivation layer 40 is located on a side of the doped nitride semiconductor layer 20 away from the epitaxial structure 10; the passivation layer 40 includes a first trench 41 and a second trench 42, the vertical projection of the first trench 41 on the epitaxial structure 10 overlaps with the active area 01, and the vertical projection of the second trench 42 on the epitaxial structure 10 overlaps with the active area 01.

[0050] The source 50 and the drain 60 are located in the first trench 41 and the drain 60 is located in the second trench 42 .

[0051] Among them, the power device in the embodiment of the present invention can be a gallium nitride high electron mobility transistor (HEMT); the channel layer 13 can be a gallium nitride layer, and the barrier layer 14 can be an AlGaN layer. The HEMT device can form a two-dimensional electron gas at the interface where the channel layer 13 and the barrier layer 14 contact in the active region 01, forming a conductive channel, so that the device is turned on. The doped nitride semiconductor layer 20 includes a P-type GaN layer or a P-type AlGaN layer; the material of the passivation layer 40 can be silicon oxide or silicon nitride, and the passivation layer 40 is used to isolate the source 50, the drain 60 and the undoped nitride semiconductor layer 20. The source 50 and the drain 60 are made of the same material, and can both be metal materials. In the length direction X, if the doped nitride semiconductor layer 20 is set to have the same length dimension as the active area 01, due to the influence of process errors in the preparation process of the power device, it will cause gate leakage when the device is turned off, thereby reducing the reliability of the device; therefore, it is necessary to set the length dimension of the doped nitride semiconductor layer 20 to be larger than the length dimension of the active area 01, which can reduce gate leakage, allow the doped nitride semiconductor layer 20 to change the electric field distribution, improve the pressure-bearing capacity of the device, and at the same time enhance the ability to control the current between the source and drain of the device.

[0052] Specifically, in order to reduce gate leakage, the length dimension of the doped nitride semiconductor layer 20 is set to be larger than the length dimension of the active area 01, the area of ​​the doped nitride semiconductor layer 20 located outside the active area 01 coincides with the second edge area 04 in the vertical projection of the epitaxial structure 10, and a conductive channel is provided at the interface between the channel layer 13 and the barrier layer 14 in the second edge area 04; since there is no need for excess uncontrolled two-dimensional electron gas to exist in the invalid first edge area 03, it is necessary to destroy the electrons in the first edge area 03 by ion bombardment, so that the first edge area 03 has no conductive channel, so that the first edge area 03 is an electrically isolated area; if the second area 22 coincides with the conductive channel in the vertical projection of the barrier layer 14 or the conductive channel is located in the vertical projection of the second area 22 in the barrier layer 14, when the epitaxial structure 10 is subjected to ion bombardment, the second area 22 of the doped nitride semiconductor layer 20 will be damaged, resulting in the channel below the doped nitride semiconductor layer 20 being unable to be pinched off when the device is turned off, resulting in device leakage. Therefore, in the embodiment of the present invention, the vertical projection of the second region 22 on the barrier layer 14 is located within the conductive channel of the second edge area 04, and the distance D1 between the vertical projection of the edge of the second region 22 on the barrier layer 14 and the edge of the conductive channel of the second edge area 04 is greater than a first preset value; when the edge area 02 is processed, the second region 22 of the doped nitride semiconductor layer 20 will not be damaged, thereby reducing gate leakage and improving the reliability of the device.

[0053] The power device provided by the technical solution of the embodiment of the present invention includes: an epitaxial structure 10, the epitaxial structure 10 includes a substrate 11, a buffer layer 12, a channel layer 13 and a barrier layer 14 which are stacked in sequence; the epitaxial structure 10 includes an active area 01 and an edge area 02, the edge area 02 surrounds the active area 01; the edge area 02 includes a first edge area 03 and a second edge area 04, the first edge area 03 of the epitaxial structure 10 is an electrical isolation area; a conductive channel is provided at the interface between the channel layer 13 and the barrier layer 14 in the second edge area 04; a doped nitride semiconductor layer 20, the doped nitride semiconductor layer 20 is located on a side of the barrier layer 14 away from the substrate 11; the doped nitride semiconductor layer 20 includes a first region 21 and a second region 22 which are connected to each other; the first region 2 1 covers a portion of the active area 01 of the epitaxial structure 10, a vertical projection of the second area 22 on the barrier layer 14 is located in the conductive channel of the second edge area 04, and a distance D1 between an edge of the conductive channel of the second edge area 04 and a vertical projection of an edge of the second area 22 on the barrier layer 14 is greater than a first preset value; a passivation layer 40, the passivation layer 40 is located on a side of the doped nitride semiconductor layer 20 away from the epitaxial structure 10; the passivation layer 40 includes a first trench 41 and a second trench 42, a vertical projection of the first trench 41 on the epitaxial structure 10 overlaps with the active area 01, and a vertical projection of the second trench 42 on the epitaxial structure 10 overlaps with the active area 01; a source 50 and a drain 60, the source 50 is located in the first trench 41, and the drain 60 is located in the second trench 42. In the embodiment of the present invention, the vertical projection of the second region 22 on the barrier layer 14 is arranged to be located within the conductive channel of the second edge region 04, and the distance D1 between the vertical projection of the edge of the second region 22 on the barrier layer 14 and the edge of the conductive channel of the second edge region 04 is greater than a first preset value; this can avoid damaging the doped nitride semiconductor layer 20 when forming an electrical isolation region for the first edge region 03, thereby reducing gate leakage and improving device reliability.

[0054] Optional, reference Figure 1 , the first preset value is greater than 25nm.

[0055] Among them, if the first preset value is less than or equal to 25nm, the process is difficult to implement, and the distance between the edge of the second region 22 at the vertical projection of the barrier layer 14 and the edge of the conductive channel of the second edge area 04 is too small, which will cause the second region 22 of the doped nitride semiconductor layer 20 to be damaged when the epitaxial structure 10 is ion bombarded, resulting in device leakage; therefore, the first preset value is set to be greater than 25nm, and along the width direction Y of the doped nitride semiconductor layer 20, the width of the second edge area 04 is at least 50nm larger than the width of the doped nitride semiconductor layer 20. When the edge area 02 is processed, the second region 22 of the doped nitride semiconductor layer 20 will not be damaged, thereby reducing gate leakage and improving device reliability.

[0056] Optional, reference Figure 1 and Figure 2 The vertical projection of the doped nitride semiconductor layer 20 on the epitaxial structure 10 is in the shape of a ring; the vertical projection of the first trench 41 on the epitaxial structure 10 is located in the central area of ​​the ring, and the vertical projection of the second trench 42 on the epitaxial structure 10 is located on one side of the ring.

[0057] Among them, the vertical projection shape of the doped nitride semiconductor layer 20 on the epitaxial structure 10 is annular. The annular nitride semiconductor layer 20 is arranged around the source 50, which can alleviate the electric field concentration, improve the voltage resistance of the device, enhance the control ability of the channel, improve the device performance, and thus improve the stability and reliability of the device.

[0058] Optional, reference Figure 1 and Figure 2 The power device further includes: a gate 30 , which is located on a side of the doped nitride semiconductor layer 20 away from the epitaxial structure 10 ; the gate 30 at least covers a portion of the doped nitride semiconductor layer 20 .

[0059] Among them, a gate 30 is formed on a side of the doped nitride semiconductor layer 20 away from the epitaxial structure 10; the gate 30 at least covers a portion of the doped nitride semiconductor layer 20, so that the vertical projection of the gate 30 on the epitaxial structure 10 is located within the vertical projection of the doped nitride semiconductor layer 20 on the epitaxial structure 10, which can reduce the leakage of the gate 30 and improve the reliability of the device; and by adjusting the gate voltage, the doped nitride semiconductor layer 20 can change the electric field distribution of the two-dimensional electron gas in the conductive channel, improve the pressure-bearing capacity of the device, and can accurately control the electron concentration of the two-dimensional electron gas, thereby enhancing the device's ability to control current.

[0060] Optional, reference Figure 1 and Figure 2 The doped nitride semiconductor layer 20 includes a P-type GaN layer or a P-type AlGaN layer.

[0061] Among them, the doped nitride semiconductor layer 20 includes a P-type GaN layer or a P-type AlGaN layer, and the P-type GaN layer or the P-type AlGaN layer can change the electric field distribution, improve the pressure-bearing capacity of the device, and enhance the controllability of the current between the source 50 and the drain 60 of the device.

[0062] The embodiment of the present invention provides a method for preparing a power device based on the above embodiment. The method of the embodiment of the present invention is used to prepare the power device described in any embodiment of the present invention. Figure 3 is a flow chart of a method for preparing a power device provided by an embodiment of the present invention, Figure 4-Figure 10is a schematic diagram of an intermediate structure of a power device provided by an embodiment of the present invention, with reference to Figure 3-Figure 10 , the preparation method comprises:

[0063] S110, forming an epitaxial structure; the epitaxial structure includes a substrate, a buffer layer, a channel layer and a barrier layer stacked in sequence; the epitaxial structure includes an active area and an edge area, and the edge area surrounds the active area; the edge area includes a first edge area and a second edge area.

[0064] The power device in the embodiment of the present invention may be a gallium nitride high electron mobility transistor (HEMT); Figure 4 , a buffer layer 12, a channel layer 13 and a barrier layer 14 can be sequentially formed on a substrate 11 through a deposition process to form an epitaxial structure 10. The epitaxial structure 10 includes an active region 01 and an edge region 02, wherein the edge region 02 surrounds the active region 01; the channel layer 13 can be a gallium nitride layer, and the barrier layer 14 can be an AlGaN layer. The HEMT device forms a two-dimensional electron gas at the interface where the channel layer 12 and the barrier layer 14 contact, forming a conductive channel, thereby turning on the device.

[0065] S120, forming a doped nitride semiconductor layer on a side of the barrier layer away from the substrate; the doped nitride semiconductor layer includes a first region and a second region connected to each other; the first region covers a portion of the active area of ​​the epitaxial structure, and a vertical projection of the second region on the barrier layer is located within the second edge region.

[0066] Among them, reference Figure 4 , a doped nitride semiconductor material layer 21 may be formed on the side of the barrier layer 14 away from the substrate 11; Figure 5 , the doped nitride semiconductor material layer 21 is patterned and etched to form a doped nitride semiconductor layer 20; the doped nitride semiconductor layer 20 includes a P-type GaN layer or a P-type AlGaN layer; refer to Fig. 9 The doped nitride semiconductor layer 20 includes a first region 21 and a second region 22 that are connected to each other; the first region 21 covers a portion of the active region 01 of the epitaxial structure 10, and the second region 22 covers a portion of the edge region 02 of the epitaxial structure 10; in the length direction X, if the doped nitride semiconductor layer 20 is set to have the same length dimension as the active region 01, due to the influence of process errors in the preparation process of the power device, the device will cause gate leakage when it is turned off, thereby reducing the reliability of the device; since there is no need for excess uncontrolled two-dimensional electron gas to exist in the invalid first edge region 03, it is necessary to set the length dimension of the doped nitride semiconductor layer 20 to be larger than the length dimension of the active region 01, which can reduce gate leakage, so that the doped nitride semiconductor layer 20 can change the electric field distribution, improve the pressure-bearing capacity of the device, and at the same time enhance the control capability of the current between the source and drain of the device.

[0067] S130, forming a passivation layer on a side of the doped nitride semiconductor layer away from the epitaxial structure; the passivation layer includes a first trench and a second trench, a vertical projection of the first trench on the epitaxial structure overlaps with the active area, and a vertical projection of the second trench on the epitaxial structure overlaps with the active area.

[0068] Among them, reference Figure 6 A passivation layer 40 may be formed on a side of the doped nitride semiconductor layer 20 away from the epitaxial structure 10, referring to Figure 7 , the passivation layer 40 is etched to form a first trench 41 and a second trench 42 ; the material of the passivation layer 40 may be silicon oxide or silicon nitride, and the passivation layer 40 is used to isolate the source, the drain and the doped nitride semiconductor layer 20 .

[0069] S140, forming a source electrode on one side of the first trench, and forming a drain electrode in the second trench.

[0070] Among them, reference Figure 8 The source electrode 50 and the drain electrode 60 are formed at the same time, which can simplify the process steps and save process time. The source electrode 50 and the drain electrode 60 are made of the same material, which can be a metal material. Figure 8 and Figure 2 The structure is different in Figure 2 The first edge region is an electrical isolation region, Figure 8 The first edge region has not yet formed an electrical isolation region.

[0071] S150. Form a protective layer on a side of the passivation layer away from the epitaxial structure; a vertical projection of the protective layer on the epitaxial structure covers an active area of ​​the epitaxial structure, and a vertical projection of the protective layer on an edge area of ​​the epitaxial structure coincides with a second edge area, and a distance between a vertical projection of an edge of the second area of ​​the doped nitride semiconductor layer on the epitaxial structure and a vertical projection of an edge of the protective layer on the epitaxial structure is greater than a second preset value.

[0072] Among them, reference Fig. 9 and Fig.10 , Fig. 9 is a schematic diagram of an intermediate structure of a power device including a protective layer 70, Fig.10 yes Fig. 9 In the cross-sectional view along the section line B1B2, the material of the protective layer 70 includes photoresist or metal titanium; the protective layer 70 is used to protect the active area 01 and the doped nitride semiconductor layer 20. The protective layer 70 can be removed by wet etching later without affecting the passivation layer 40, and the photoresist and titanium processes are mature.

[0073] Specifically, since the length dimension of the doped nitride semiconductor layer 20 is larger than the length dimension of the active area 01, in order to reduce gate leakage, it is necessary to destroy the electrons in the first edge area 03 through ion bombardment, so that there is no conductive channel in the first edge area 03, thereby reducing gate leakage and improving device reliability; however, since the second region 22 of the doped nitride semiconductor layer 20 is located in the second edge area 04, when the epitaxial structure 10 is ion bombarded, if the vertical projection of the second region 22 on the barrier layer 14 coincides with the vertical projection of the protective layer 70 on the barrier layer 14, or the vertical projection of the protective layer 70 on the barrier layer 14 is located within the vertical projection of the second region 22 on the barrier layer 14, the second region 22 of the doped nitride semiconductor layer 20 will be damaged, resulting in the channel under the doped nitride semiconductor layer 20 being unable to be pinched off when the device is turned off, resulting in device leakage.

[0074] S160, processing the epitaxial structure so that the first edge region of the epitaxial structure is an electrical isolation region; and making the distance between the edge of the conductive channel in the second edge region and the edge of the second region of the doped nitride semiconductor layer in the barrier layer vertically projected to be greater than a first preset value.

[0075] Among them, reference Figure 1 , Figure 2 , Fig. 9 and Fig.10 After forming the protective layer 70, the epitaxial structure 10 can be subjected to ion bombardment. The electrons in the first edge region 03 need to be destroyed by ion bombardment so that there is no conductive channel in the first edge region 03, and the first edge region 03 of the epitaxial structure 10 is an electrically isolated region, thereby reducing gate leakage and improving device reliability.

[0076] In the embodiment of the present invention, before ion bombardment is performed on the edge region 02, a protective layer 70 is provided to protect the doped nitride semiconductor layer 20 in the edge region 02, the vertical projection of the second region 22 of the doped nitride semiconductor layer 20 in the epitaxial structure 10 is located inside the vertical projection of the protective layer 70 in the epitaxial structure 10, and the distance D2 between the vertical projection of the edge of the doped nitride semiconductor layer 20 in the epitaxial structure 10 and the vertical projection of the edge of the protective layer 70 in the epitaxial structure 10 is greater than a second preset value, which can be expressed as the vertical projection of the protective layer 70 in the edge region 02 and the vertical projection of the second region 22 of the doped nitride semiconductor layer 20 in the edge region 02 have the same shape, the area of ​​the vertical projection of the protective layer 70 in the edge region 02 is greater than the area of ​​the vertical projection of the second region 22 of the doped nitride semiconductor layer 20 in the edge region 02, and the vertical projections of all edges of the protective layer 70 in the edge region 02 are aligned with the vertical projections of all edges of the second region 22 of the doped nitride semiconductor layer 20. The vertical projections of the edges in the edge area 02 do not overlap, and the distance between the vertical projection of the edge of the doped nitride semiconductor layer 20 on the epitaxial structure 10 and the vertical projection of the corresponding edge of the protective layer 70 on the epitaxial structure 10 is greater than a second preset value; illustratively, the second preset value can be greater than 25nm; so that the protective layer 70 can completely cover the doped nitride semiconductor layer 20, and because the vertical projection of the protective layer 70 in the edge area of ​​the epitaxial structure 10 coincides with the second edge area 04, the distance D1 between the edge of the conductive channel of the second edge area 04 and the edge of the second region 22 of the doped nitride semiconductor layer 20 at the vertical projection of the barrier layer 14 and the edge of the conductive channel of the second edge area is greater than the first preset value, thereby avoiding damage to the doped nitride semiconductor layer 20 when processing the edge area 02 and forming an electrical isolation area in the first edge area 03, and avoiding the doped nitride semiconductor layer 20 from being bombarded by ions, thereby reducing gate leakage and improving device reliability.

[0077] S170, removing the protective layer.

[0078] in, Fig. 9 Remove the protective layer 70 to form Figure 1 In the structure, the protective layer 70 can be removed by wet etching. Figure 1 and Figure 2 The structure in the figure is the structure after ion bombardment.

[0079] The method for preparing a power device provided by the technical solution of the embodiment of the present invention sets the vertical projection of the second region 22 on the barrier layer 14 to be located within the conductive channel of the second edge area 04, and the distance D1 between the vertical projection of the edge of the second region 22 on the barrier layer 14 and the edge of the conductive channel of the second edge area 04 is greater than a first preset value; damage to the doped nitride semiconductor layer 20 can be avoided when forming an electrical isolation region in the first edge area 03, thereby reducing gate leakage and improving device reliability.

[0080] Optional, reference Figure 1 and Fig. 9 , the first preset value is greater than 25nm; the second preset value is greater than 25nm.

[0081] Among them, the first preset value is the same as the second preset value. If the first preset value or the second preset value is less than or equal to 25nm, the process is difficult to implement, and the distance between the edge of the second region 22 at the vertical projection of the barrier layer 14 and the edge of the conductive channel of the second edge area 04 is too small, which will cause the second region 22 of the doped nitride semiconductor layer 20 to be damaged when the edge area 02 is ion bombarded, resulting in device leakage; therefore, the first preset value is set to be greater than 25nm, and the second preset value is greater than 25nm. Along the width direction Y of the doped nitride semiconductor layer 20, the width of the second edge area 04 is at least 50nm larger than the width of the doped nitride semiconductor layer 20. When the edge area 02 is processed, the second region 22 of the doped nitride semiconductor layer 20 will not be damaged, thereby reducing gate leakage and improving device reliability.

[0082] Optionally, based on the above embodiment, S150 can be refined. S150: forming a protective layer on the side of the passivation layer away from the epitaxial structure, specifically including: S151: forming a protective material layer on the side of the passivation layer away from the epitaxial structure; S152: patterning and etching the protective material layer to form a protective layer.

[0083] Specifically, an embodiment of the present invention provides a method for preparing a power device, which specifically includes:

[0084] S110, forming an epitaxial structure; the epitaxial structure includes a substrate, a buffer layer, a channel layer and a barrier layer stacked in sequence; the epitaxial structure includes an active area and an edge area, and the edge area surrounds the active area; the edge area includes a first edge area and a second edge area.

[0085] S120, forming a doped nitride semiconductor layer on one side of the epitaxial structure; the doped nitride semiconductor layer includes a first region and a second region connected to each other; the first region covers a portion of the active region of the epitaxial structure, and a vertical projection of the second region on the barrier layer is located within the second edge region.

[0086] S130, forming a passivation layer on a side of the doped nitride semiconductor layer away from the epitaxial structure; the passivation layer includes a first trench and a second trench, a vertical projection of the first trench on the epitaxial structure overlaps with the active area, and a vertical projection of the second trench on the epitaxial structure overlaps with the active area.

[0087] S140, forming a source electrode on one side of the first trench, and forming a drain electrode in the second trench.

[0088] S151, forming a protective material layer on a side of the passivation layer away from the epitaxial structure.

[0089] The material of the protective material layer may include photoresist or titanium. The protective material layer is formed on the side of the passivation layer away from the epitaxial structure. The vertical projection of the protective material layer on the epitaxial structure covers the active area and edge area of ​​the epitaxial structure.

[0090] S152, pattern-etching the protective material layer to form a protective layer.

[0091] Among them, a protective layer is formed by patterning and etching the protective material layer. The protective layer covers the active area of ​​the epitaxial structure and the second edge area in the vertical projection of the epitaxial structure. This can avoid damaging the doped nitride semiconductor layer when processing the epitaxial structure, thereby reducing gate leakage and improving device reliability.

[0092] S160, processing the epitaxial structure so that the first edge region of the epitaxial structure is an electrical isolation region; and making the distance between the edge of the conductive channel in the second edge region and the edge of the second region of the doped nitride semiconductor layer in the barrier layer vertically projected to be greater than a first preset value.

[0093] S170, removing the protective layer.

[0094] Optionally, based on the above-mentioned embodiment, S120 can be refined, S120, forming a doped nitride semiconductor layer on the side of the barrier layer away from the substrate, specifically including: S121, forming a doped nitride semiconductor material layer on one side of the epitaxial structure; S122, patterning and etching the doped nitride semiconductor material layer to form a doped nitride semiconductor layer; wherein the vertical projection shape of the doped nitride semiconductor layer on the epitaxial structure is a ring.

[0095] Specifically, an embodiment of the present invention provides a method for preparing a power device, which specifically includes:

[0096] S110, forming an epitaxial structure; the epitaxial structure includes a substrate, a buffer layer, a channel layer and a barrier layer stacked in sequence; the epitaxial structure includes an active area and an edge area, and the edge area surrounds the active area; the edge area includes a first edge area and a second edge area, and a conductive channel is provided at the interface between the channel layer and the barrier layer in the second edge area.

[0097] S121. Form a doped nitride semiconductor material layer on one side of the epitaxial structure.

[0098] Among them, reference Figure 4 , a doped nitride semiconductor material layer 21 is formed on one side of the epitaxial structure 10 through a deposition process.

[0099] S122, pattern-etching the doped nitride semiconductor material layer to form a doped nitride semiconductor layer; wherein the vertical projection shape of the doped nitride semiconductor layer on the epitaxial structure is a ring.

[0100] Among them, reference Figure 5 , the doped nitride semiconductor material layer 21 is patterned and etched to form a doped nitride semiconductor layer 20, the doped nitride semiconductor layer is in the shape of a ring in the vertical projection of the epitaxial structure, for example, refer to Figure 1 The vertical projection of the doped nitride semiconductor layer 20 on the epitaxial structure 10 is in the shape of a ring. The ring-shaped nitride semiconductor layer 20 is arranged around the source electrode 50, which can alleviate the electric field concentration, improve the withstand voltage capability of the device, enhance the control capability of the channel, improve the device performance, and thus improve the stability and reliability of the device;

[0101] S130, forming a passivation layer on a side of the doped nitride semiconductor layer away from the epitaxial structure; the passivation layer includes a first trench and a second trench, a vertical projection of the first trench on the epitaxial structure overlaps with the active area, and a vertical projection of the second trench on the epitaxial structure overlaps with the active area.

[0102] S140, forming a source electrode on one side of the first trench, and forming a drain electrode in the second trench.

[0103] S150. Form a protective layer on a side of the passivation layer away from the epitaxial structure; a vertical projection of the protective layer on the epitaxial structure covers an active area of ​​the epitaxial structure, and a vertical projection of the protective layer on an edge area of ​​the epitaxial structure coincides with a second edge area, and a distance between a vertical projection of an edge of the second area of ​​the doped nitride semiconductor layer on the epitaxial structure and a vertical projection of an edge of the protective layer on the epitaxial structure is greater than a second preset value.

[0104] S160, processing the epitaxial structure so that the edge region of the epitaxial structure is an electrically isolated region; and making the distance between the edge of the conductive channel in the second edge region and the edge of the second region of the doped nitride semiconductor layer in the barrier layer vertically projected to be greater than a first preset value.

[0105] S170, removing the protective layer.

[0106] Optionally, S130, forming a passivation layer on a side of the doped nitride semiconductor layer away from the epitaxial structure, comprising:

[0107] S131, forming a passivation layer on a side of the doped nitride semiconductor layer away from the epitaxial structure; the passivation layer covers the doped nitride semiconductor layer and the epitaxial structure not covered by the doped nitride semiconductor layer.

[0108] Wherein, a passivation layer may be formed on a side of the doped nitride semiconductor layer away from the epitaxial structure through a deposition process.

[0109] S132, etching the passivation layer to form a first groove and a second groove; wherein the vertical projection of the first groove on the epitaxial structure is located in the central area of ​​the ring, and the vertical projection of the second groove on the epitaxial structure is located on one side of the ring.

[0110] Among them, reference Fig. 9 and Fig.10 The vertical projection of the first groove 41 on the epitaxial structure 10 is located in the central area of ​​the ring, which means that when the source 50 is subsequently prepared in the first groove 41, the doped nitride semiconductor layer 20 is arranged around the source 50, which can alleviate the electric field concentration, improve the voltage resistance of the device, enhance the control ability of the channel, improve the device performance, and thus improve the stability and reliability of the device; the vertical projection of the second groove 42 on the epitaxial structure is located on one side of the ring, and the drain 60 is subsequently prepared in the second groove 42 to achieve device conduction.

[0111] An embodiment of the present invention provides a method for preparing a power device based on the above embodiment, and the method comprises:

[0112] S110, forming an epitaxial structure; the epitaxial structure includes a substrate, a buffer layer, a channel layer and a barrier layer stacked in sequence; the epitaxial structure includes an active area and an edge area, and the edge area surrounds the active area; the edge area includes a first edge area and a second edge area, and a conductive channel is provided at the interface between the channel layer and the barrier layer in the second edge area.

[0113] S120, forming a doped nitride semiconductor layer on one side of the epitaxial structure; the doped nitride semiconductor layer includes a first region and a second region connected to each other; the first region covers a portion of the active region of the epitaxial structure, and a vertical projection of the second region on the barrier layer is located within the second edge region.

[0114] S210, forming a gate on a side of the doped nitride semiconductor layer away from the epitaxial structure; the gate at least covers a portion of the doped nitride semiconductor layer.

[0115] Among them, reference Figure 5 , a gate 30 is formed on a side of the doped nitride semiconductor layer 20 away from the epitaxial structure 10; the gate 30 at least covers a portion of the doped nitride semiconductor layer 20, so that the vertical projection of the gate 30 on the epitaxial structure 10 is located inside the vertical projection of the doped nitride semiconductor layer 20 on the epitaxial structure 10, which can reduce the leakage of the gate 30 and improve the reliability of the device; and by adjusting the gate voltage, the doped nitride semiconductor layer 20 can change the electric field distribution of the two-dimensional electron gas in the conductive channel, improve the pressure-bearing capacity of the device, and can accurately control the electron concentration of the two-dimensional electron gas, thereby enhancing the device's ability to control current.

[0116] S130, forming a passivation layer on a side of the gate away from the epitaxial structure; the passivation layer includes a first trench and a second trench, a vertical projection of the first trench on the epitaxial structure overlaps with the active area, and a vertical projection of the second trench on the epitaxial structure overlaps with the active area.

[0117] S140, forming a source electrode on one side of the first trench, and forming a drain electrode in the second trench.

[0118] S150. Form a protective layer on a side of the passivation layer away from the epitaxial structure; a vertical projection of the protective layer on the epitaxial structure covers an active area of ​​the epitaxial structure, and a vertical projection of the protective layer on an edge area of ​​the epitaxial structure coincides with a second edge area, and a distance between a vertical projection of an edge of the second area of ​​the doped nitride semiconductor layer on the epitaxial structure and a vertical projection of an edge of the protective layer on the epitaxial structure is greater than a second preset value.

[0119] S160, processing the epitaxial structure so that the first edge region of the epitaxial structure is an electrical isolation region; and making the distance between the edge of the conductive channel in the second edge region and the edge of the second region of the doped nitride semiconductor layer in the barrier layer vertically projected to be greater than a first preset value.

[0120] Optionally, processing the epitaxial structure so that the first edge region of the epitaxial structure is an electrical isolation region includes: performing ion bombardment on the epitaxial structure so that the first edge region of the epitaxial structure is an electrical isolation region.

[0121] The epitaxial structure is subjected to ion bombardment, and the ion energy of the ion bombardment can be set according to requirements, so that the first edge region of the epitaxial structure is an electrical isolation region, thereby reducing gate leakage and improving device reliability.

[0122] Optionally, the ion source of the ion bombardment is at least one of nitrogen, fluorine, oxygen, and argon.

[0123] Among them, the ion source of ion bombardment is at least one of nitrogen, fluorine, oxygen, and argon, and nitrogen, fluorine, oxygen, and argon are all heavy atoms. By setting the ion source to at least one of nitrogen, fluorine, oxygen, and argon, the electrons in the edge area can be damaged, so that there is no conductive channel outside the active area, so that the edge area of ​​the epitaxial structure is an electrically isolated area, thereby reducing gate leakage and improving the reliability of the device.

[0124] The method for preparing the power device provided in the embodiment of the present invention has the same beneficial effects as the power device described in any embodiment of the present invention.

[0125] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0126] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A power device, characterized in that: include: An epitaxial structure, the epitaxial structure comprising a substrate, a buffer layer, a channel layer and a barrier layer stacked in sequence; the epitaxial structure comprising an active region and an edge region, the edge region surrounding the active region; the edge region comprising a first edge region and a second edge region, the first edge region of the epitaxial structure being an electrical isolation region; a conductive channel is provided at an interface between the channel layer and the barrier layer in the second edge region; a doped nitride semiconductor layer, the doped nitride semiconductor layer being located on a side of the barrier layer away from the substrate; the doped nitride semiconductor layer comprising a first region and a second region connected to each other; the first region covering a portion of the active region of the epitaxial structure, a vertical projection of the second region on the barrier layer being located within a conductive channel of the second edge region, and a distance between an edge of the conductive channel of the second edge region and an edge of the second region on the barrier layer being greater than a first preset value; A passivation layer, the passivation layer is located on a side of the doped nitride semiconductor layer away from the epitaxial structure; the passivation layer comprises a first trench and a second trench, a vertical projection of the first trench on the epitaxial structure overlaps with the active area, and a vertical projection of the second trench on the epitaxial structure overlaps with the active area; A source and a drain, wherein the source is located in the first trench, and the drain is located in the second trench.

2. The power device according to claim 1, characterized in that: The first preset value is greater than 25 nm.

3. The power device according to claim 1, characterized in that: The vertical projection of the doped nitride semiconductor layer on the epitaxial structure is in the shape of a ring; The vertical projection of the first trench on the epitaxial structure is located in the central area of ​​the ring, and the vertical projection of the second trench on the epitaxial structure is located on one side of the ring.

4. The power device according to claim 1, characterized in that: Also includes: A gate is located on a side of the doped nitride semiconductor layer away from the epitaxial structure; the gate at least covers a portion of the doped nitride semiconductor layer.

5. The power device according to claim 1, characterized in that: The doped nitride semiconductor layer includes a P-type GaN layer or a P-type AlGaN layer.

6. A method for preparing a power device, characterized in that: include: forming an epitaxial structure; the epitaxial structure comprises a substrate, a buffer layer, a channel layer and a barrier layer stacked in sequence; the epitaxial structure comprises an active region and an edge region, the edge region surrounds the active region; the edge region comprises a first edge region and a second edge region; A doped nitride semiconductor layer is formed on a side of the barrier layer away from the substrate; the doped nitride semiconductor layer includes a first region and a second region connected to each other; the first region covers a portion of the active region of the epitaxial structure, and a vertical projection of the second region on the barrier layer is located within the second edge region; A passivation layer is formed on a side of the doped nitride semiconductor layer away from the epitaxial structure; the passivation layer comprises a first trench and a second trench, wherein a vertical projection of the first trench on the epitaxial structure overlaps with the active area, and a vertical projection of the second trench on the epitaxial structure overlaps with the active area; forming a source electrode on one side of the first trench, and forming a drain electrode in the second trench; forming a protective layer on a side of the passivation layer away from the epitaxial structure; a vertical projection of the protective layer on the epitaxial structure covers an active area of ​​the epitaxial structure, and a vertical projection of the protective layer on an edge area of ​​the epitaxial structure coincides with the second edge area, and a distance between a vertical projection of an edge of the second area of ​​the doped nitride semiconductor layer on the epitaxial structure and a vertical projection of an edge of the protective layer on the epitaxial structure is greater than a second preset value; Processing the epitaxial structure so that a first edge region of the epitaxial structure is an electrical isolation region and a distance between an edge of a conductive channel of the second edge region and an edge of a second region of the doped nitride semiconductor layer and a vertical projection of the barrier layer is greater than a first preset value; The protective layer is removed.

7. The method for preparing a power device according to claim 6, characterized in that: The first preset value is greater than 25 nm; the second preset value is greater than 25 nm.

8. The method for preparing a power device according to claim 6, characterized in that: Forming a protective layer on a side of the passivation layer away from the epitaxial structure comprises: forming a protective material layer on a side of the passivation layer away from the epitaxial structure; The protective material layer is patterned and etched to form a protective layer.

9. The method for preparing a power device according to claim 6, characterized in that: The method further comprises forming a doped nitride semiconductor layer on the barrier layer away from the substrate, comprising: forming a doped nitride semiconductor material layer on one side of the epitaxial structure; The doped nitride semiconductor material layer is pattern-etched to form a doped nitride semiconductor layer; wherein the vertical projection of the doped nitride semiconductor layer on the epitaxial structure is in the shape of a ring.

10. The method for preparing a power device according to claim 9, characterized in that: Forming a passivation layer on a side of the doped nitride semiconductor layer away from the epitaxial structure, comprising: forming a passivation layer on a side of the doped nitride semiconductor layer away from the epitaxial structure; the passivation layer covers the doped nitride semiconductor layer and the epitaxial structure not covered by the doped nitride semiconductor layer; The passivation layer is etched to form a first groove and a second groove; wherein the vertical projection of the first groove on the epitaxial structure is located in the central area of ​​the ring, and the vertical projection of the second groove on the epitaxial structure is located on one side of the ring.

11. The method for preparing a power device according to claim 6, characterized in that: After forming a doped nitride semiconductor layer on a side of the barrier layer away from the substrate, the method further comprises: A gate is formed on a side of the doped nitride semiconductor layer away from the epitaxial structure; the gate at least covers a portion of the doped nitride semiconductor layer.

12. The method for preparing a power device according to claim 6, characterized in that: Processing the epitaxial structure so that a first edge region of the epitaxial structure is an electrical isolation region includes: Ion bombardment is performed on the epitaxial structure so that a first edge region of the epitaxial structure becomes an electrical isolation region.

13. The method for preparing a power device according to claim 12, characterized in that: The ion source of the ion bombardment is at least one of nitrogen, fluorine, oxygen and argon.

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