A gallium nitride device and a method for preparing the same

Abstract

The present invention discloses a gallium nitride device and a preparation method. The gallium nitride device includes: a substrate, a channel layer and a composite barrier layer, the composite barrier layer includes a first barrier layer, a second barrier layer, a third barrier layer and a fourth barrier layer; the first barrier layer is located on the side of the channel layer away from the substrate; the second barrier layer is located on the side of the first barrier layer away from the channel layer; the bond energy of the covalent bond of the second barrier layer is greater than the bond energy of the covalent bond of the first barrier layer; the third barrier layer is located on the side of the second barrier layer away from the first barrier layer; the fourth barrier layer is located on the side of the second barrier layer away from the first barrier layer; or, the fourth barrier layer is located on the side of the third barrier layer away from the second barrier layer. The above technical solution improves the surface quality of the barrier layer on one side of the channel layer and reduces its interface defects, thereby improving the electrical performance of the gallium nitride device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a gallium nitride device and a preparation method thereof. Background Art

[0002] Gallium nitride devices have excellent electrical properties because of the presence of a large concentration of two-dimensional electron gas (2DEG) in the heterojunction formed by the channel layer and the barrier layer.

[0003] In existing GaN devices, the barrier layer has poor quality and too many interface defects, which affects the electrical performance of the device. Summary of the invention

[0004] The present invention provides a gallium nitride device and a preparation method thereof, so as to improve the surface quality of a barrier layer on one side of a channel layer and reduce its interface defects, thereby improving the electrical performance of the gallium nitride device.

[0005] According to one aspect of the present invention, there is provided a gallium nitride device, comprising:

[0006] substrate;

[0007] A channel layer, located on one side of the substrate;

[0008] A composite barrier layer, comprising a first barrier layer, a second barrier layer, a third barrier layer and a fourth barrier layer; the first barrier layer is located on a side of the channel layer away from the substrate; the second barrier layer is located on a side of the first barrier layer away from the channel layer; the bond energy of the covalent bond of the second barrier layer is greater than the bond energy of the covalent bond of the first barrier layer; the third barrier layer is located on a side of the second barrier layer away from the first barrier layer;

[0009] a doped III-V group semiconductor layer, located on a side of the third barrier layer away from the second barrier layer;

[0010] A gate, located on a side of the doped III-V semiconductor layer away from the third barrier layer;

[0011] When the vertical projection area of ​​the third barrier layer is equal to the vertical projection area of ​​the doped III-V semiconductor layer on the substrate, the fourth barrier layer is located on a side of the second barrier layer away from the first barrier layer; or, when the vertical projection area of ​​the third barrier layer is equal to the vertical projection area of ​​the second barrier layer on the substrate, the fourth barrier layer is located on a side of the third barrier layer away from the second barrier layer;

[0012] A source electrode, located at a side of the fourth barrier layer away from the channel layer;

[0013] The drain is located on a side of the fourth barrier layer away from the channel layer.

[0014] According to another aspect of the present invention, there is provided a method for preparing a gallium nitride device, comprising:

[0015] providing a substrate;

[0016] forming a channel layer on one side of the substrate;

[0017] forming a first barrier layer on a side of the channel layer away from the substrate;

[0018] forming a second barrier layer on a side of the first barrier layer away from the channel layer, wherein the bond energy of the covalent bonds of the second barrier layer is greater than the bond energy of the covalent bonds of the first barrier layer;

[0019] forming a third barrier layer on a side of the second barrier layer away from the first barrier layer;

[0020] forming a doped III-V semiconductor layer on a side of the third barrier layer away from the second barrier layer;

[0021] Patterning the doped III-V semiconductor layer so that the vertical projection area of ​​the third barrier layer on the substrate is equal to the vertical projection area of ​​the doped III-V semiconductor layer on the substrate, or the vertical projection area of ​​the third barrier layer on the substrate is equal to the vertical projection area of ​​the second barrier layer on the substrate;

[0022] When the vertical projection area of ​​the substrate is equal to the vertical projection area of ​​the doped III-V semiconductor layer on the substrate, the third barrier layer forms a fourth barrier layer on the side of the second barrier layer away from the first barrier layer; or, when the vertical projection area of ​​the third barrier layer is equal to the vertical projection area of ​​the second barrier layer on the substrate, the fourth barrier layer is formed on the side of the third barrier layer away from the second barrier layer; the first barrier layer, the second barrier layer, the third barrier layer and the fourth barrier layer constitute a composite barrier layer;

[0023] forming a source electrode on a side of the fourth barrier layer away from the channel layer;

[0024] forming a drain electrode on a side of the fourth barrier layer away from the channel layer;

[0025] Before patterning the doped III-V semiconductor layer, a gate is formed on a side of the doped III-V semiconductor layer away from the third barrier layer; or, after forming a drain on a side of the fourth barrier layer away from the channel layer, a gate is formed on a side of the doped III-V semiconductor layer away from the third barrier layer.

[0026] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 is a schematic structural diagram of a gallium nitride device provided by an embodiment of the present invention;

[0029] Figure 2 is a schematic structural diagram of another gallium nitride device provided by an embodiment of the present invention;

[0030] Figure 3 yes Figure 1 A schematic diagram of the structure of the GaN device including a passivation layer;

[0031] Figure 4 yes Figure 2 A schematic diagram of the structure of the GaN device including a passivation layer;

[0032] Figure 5 is a flow chart of a method for preparing a gallium nitride device provided by an embodiment of the present invention;

[0033] Figure 6-Figure 17 It is a structural schematic diagram of the relevant steps of a method for preparing a gallium nitride device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solution in the embodiment of the present invention will be described clearly and completely in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0035] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or devices is not necessarily limited to those steps or devices that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0036] In order to improve the surface quality of the barrier layer on one side of the channel layer and reduce its interface defects, thereby improving the electrical performance of the gallium nitride device, the embodiment of the present invention provides the following technical solutions:

[0037] like Figure 1 and Figure 2 As shown, Figure 1 is a schematic structural diagram of a gallium nitride device provided by an embodiment of the present invention, Figure 2 1 is a schematic diagram of the structure of another gallium nitride device provided by an embodiment of the present invention, the gallium nitride device comprising: a substrate 100; a channel layer 101, located on one side of the substrate 100; a composite barrier layer 200, comprising a first barrier layer 201, a second barrier layer 202, a third barrier layer 203 and a fourth barrier layer 204; the first barrier layer 201 is located on a side of the channel layer 101 away from the substrate 100; the second barrier layer 202 is located on a side of the first barrier layer 201 away from the substrate 100; The second barrier layer 202 has a covalent bond energy greater than the covalent bond energy of the first barrier layer 201; the third barrier layer 203 is located on a side of the second barrier layer 202 away from the first barrier layer 201; the doped III-V semiconductor layer 300 is located on a side of the third barrier layer 203 away from the second barrier layer 202; the gate 400 is located on a side of the doped III-V semiconductor layer 300 away from the third barrier layer 203; Figure 1 As shown, when the vertical projection area of ​​the third barrier layer 203 on the substrate 100 is equal to the vertical projection area of ​​the doped III-V semiconductor layer 300 on the substrate 100, the fourth barrier layer 204 is located on the side of the second barrier layer 202 away from the first barrier layer 201; or, Figure 2As shown, when the vertical projection area of ​​the third barrier layer 203 on the substrate 100 is equal to the vertical projection area of ​​the second barrier layer 202 on the substrate 100, the fourth barrier layer 204 is located on the side of the third barrier layer 203 away from the second barrier layer 202; the source 401 is located on the side of the fourth barrier layer 204 away from the channel layer 101; and the drain 402 is located on the side of the fourth barrier layer 204 away from the channel layer 101.

[0038] It should be noted that during the patterning process of the doped III-V semiconductor layer 300, the third barrier layer 203 is easily overetched. Figure 1 The gallium nitride device shown is a schematic structural diagram in which the third barrier layer 203 is completely overetched. Figure 2 The gallium nitride device shown is a schematic structural diagram in which the third barrier layer 203 is not completely overetched.

[0039] Exemplarily, the gallium nitride device further includes a buffer layer 102, which is used to alleviate the lattice mismatch problem between the substrate 100 and the channel layer 101. The channel layer 101 includes one or more of a GaN layer, an AlGaN layer, and an InGaN layer. The first barrier layer 201, the third barrier layer 203, and the fourth barrier layer 204 can be one or more of an AlGaN layer, an AlN layer, and an InGaN layer. The doped III-V semiconductor layer 300 is pGaN. The gallium nitride device in the embodiment of the present invention is an enhancement mode GaN high electron mobility transistor (HEMT).

[0040] The technical solution provided by the embodiment of the present invention is that the composite barrier layer 200 includes a first barrier layer 201, a second barrier layer 202, a third barrier layer 203 and a fourth barrier layer 204. During the patterning process of the doped III-V semiconductor layer 300, the third barrier layer 203 is easily over-etched and has too many interface defects. The regrown fourth barrier layer 204 is formed after the doped III-V semiconductor layer 300 is patterned. The fourth barrier layer 204 is formed by a re-growth process and is not affected by the patterning process of the doped III-V semiconductor layer 300. There is no problem of poor quality and many interface defects, which increases the saturation current of the device, reduces the gate leakage current, and improves the electrical performance of the device. During the formation of the fourth barrier layer 204 by a re-growth process such as metal organic chemical vapor deposition (MOCVD), the temperature is relatively high. Since the bond energy of the covalent bond of the second barrier layer 202 is greater than the bond energy of the covalent bond of the first barrier layer 201, the covalent bond of the second barrier layer 202 is less likely to break during the re-growth of the fourth barrier layer 204 than the covalent bond of the first barrier layer 201. And since the third barrier layer 203 will be overetched during the patterning of the doped III-V semiconductor layer 300, even if there is a remaining third barrier layer 203 at the channel, the film thickness is relatively thin. Therefore, the covalent bond of the second barrier layer 202 is less likely to break during the re-growth of the fourth barrier layer 204 than the covalent bond of the first barrier layer 201, which can provide good surface quality for the formation of the fourth barrier layer 204, avoid the presence of defects such as holes in the fourth barrier layer 204, and thus improve the formation quality of the fourth barrier layer 204, which helps the fourth barrier layer 204 to play the role of increasing the device saturation current and reducing the gate leakage current. It should be noted that when the third barrier layer 203 at the channel is completely overetched, the fourth barrier layer 204 grows again on the surface of the second barrier layer 202 , and the second barrier layer 202 provides a better surface quality for the formation of the fourth barrier layer 204 .

[0041] Optionally, based on the above technical solution, Figure 2 As shown, when the vertical projection area of ​​the third barrier layer 203 on the substrate 100 is equal to the vertical projection area of ​​the second barrier layer 202 on the substrate 100, the third barrier layer 203 includes a first part 2031, a second part 2032 and a third part 2033, the first part 2031 covers the area between the doped III-V semiconductor layer 300 and the source 401, the second part 2032 covers the area between the doped III-V semiconductor layer 300 and the drain 402, the third part 2033 is located between the doped III-V semiconductor layer 300 and the third barrier layer 203, the thickness of the first part 2031 is less than the thickness of the third part 2033, and the thickness of the second part 2032 is less than the thickness of the third part 2033.

[0042] Specifically, during the patterning process of the doped III-V semiconductor layer 300 , the third barrier layer 203 will be over-etched, and there will be a remaining third barrier layer 203 at the channel, but the film thickness is relatively thin.

[0043] Optionally, based on the above technical solution, Figure 3 and Figure 4 As shown, Figure 3 yes Figure 1 The schematic diagram of the structure of the GaN device including the passivation layer, Figure 4 yes Figure 2 The gallium nitride device in the figure includes a structural schematic diagram of a passivation layer, and the gallium nitride device also includes a passivation layer 500; the passivation layer 500 covers the side wall of the doped III-V semiconductor layer 300, the side wall of the third barrier layer 203, and the side of the doped III-V semiconductor layer 300 away from the third barrier layer 203; the passivation layer 500 is in contact with the fourth barrier layer 204; the passivation layer 500 is provided with an opening structure, and the gate 400 is located in the opening structure.

[0044] Specifically, the provision of the passivation layer 500 can further reduce the gate leakage current and improve the electrical performance of the device.

[0045] Optionally, based on the above technical solution, Figure 1-Figure 4 As shown, the first barrier layer 201 includes at least AlGaN, and the second barrier layer 202 includes aluminum nitride.

[0046] Specifically, the bond energy of the N-Al covalent bond in aluminum nitride is greater than the bond energy of the N-Ga covalent bond, and the temperature is relatively high during the formation of the fourth barrier layer 204 through a re-growth process such as metal organic chemical vapor deposition (MOCVD). In this process, the N-Al covalent bond is less likely to break, and the second barrier layer 202 can provide a good surface quality for the formation of the fourth barrier layer 204, thereby improving the formation quality of the fourth barrier layer 204, avoiding the presence of defects such as holes in the fourth barrier layer 204, and helping the fourth barrier layer 204 to play the role of increasing the device saturation current and reducing the gate leakage current. In addition, the bandgap width of aluminum nitride is greater than the bandgap width of AlGaN, which can further reduce the gate leakage current and enhance the reliability of the device.

[0047] Optionally, based on the above technical solution, Figure 1-Figure 4 As shown, the first barrier layer 201 includes at least AlGaN; the second barrier layer 202 includes AlGaN, and the content of Al atoms in the second barrier layer 202 is greater than the content of Al atoms in the first barrier layer 201 .

[0048] Specifically, the content of Al atoms in the second barrier layer 202 is greater than the content of Al atoms in the first barrier layer 201, which proves that the ratio of N-Al covalent bonds in the second barrier layer 202 is higher than the ratio of N-Al covalent bonds in the second barrier layer 202. The bond energy of N-Al covalent bonds is greater than the bond energy of N-Ga covalent bonds. During the formation of the fourth barrier layer 204 by a re-growth process such as metal organic chemical vapor deposition (MOCVD), the temperature is relatively high. In this process, the N-Al covalent bond is less likely to break, and the second barrier layer 202 can provide a good surface quality for the formation of the fourth barrier layer 204, thereby improving the formation quality of the fourth barrier layer 204, avoiding the presence of defects such as holes in the fourth barrier layer 204, and helping the fourth barrier layer 204 to play the role of increasing the device saturation current and reducing the gate leakage current. In addition, the content of Al atoms in the second barrier layer 202 is higher, and its bandgap is greater than the bandgap of the first barrier layer 201, which can further reduce the gate leakage current and enhance the reliability of the device.

[0049] Optionally, based on the above technical solution, Figure 1-Figure 4 As shown, the thickness of the second barrier layer 202 is greater than or equal to 0.1 nm and less than or equal to 3 nm, which can provide good surface quality for the formation of the fourth barrier layer 204 on the one hand, and on the other hand, avoid reducing the on-resistance of the device due to excessive thickness setting.

[0050] The present invention also provides a method for preparing a gallium nitride device. Figure 5 As shown, Figure 5 1 is a flow chart of a method for preparing a gallium nitride device provided by an embodiment of the present invention. The method for preparing a gallium nitride device comprises the following steps:

[0051] S110 , providing a substrate.

[0052] like Figure 6 As shown, a substrate 100 is provided.

[0053] S120 , forming a channel layer on one side of the substrate.

[0054] like Figure 6 As shown, a channel layer 101 is formed on one side of the substrate 100. The channel layer 101 includes one or more of a GaN layer, an AlGaN layer, and an InGaN layer. In other optional embodiments, a buffer layer 102 may be formed on one side of the substrate 100 before forming the channel layer 101, and the buffer layer 102 is used to alleviate the lattice mismatch problem between the substrate 100 and the channel layer 101.

[0055] S130 , forming a first barrier layer on a side of the channel layer away from the substrate.

[0056] like Figure 6 As shown, a first barrier layer 201 is formed on a side of the channel layer 101 away from the substrate 100 by an epitaxial process.

[0057] S140 , forming a second barrier layer on a side of the first barrier layer away from the channel layer, wherein the bond energy of covalent bonds of the second barrier layer is greater than the bond energy of covalent bonds of the first barrier layer.

[0058] like Figure 6 As shown, the second barrier layer 202 is formed on the side of the first barrier layer 201 away from the channel layer 101 by an epitaxial process, and the bond energy of the covalent bond of the second barrier layer 202 is greater than the bond energy of the covalent bond of the first barrier layer 201 .

[0059] S150 , forming a third barrier layer on a side of the second barrier layer away from the first barrier layer.

[0060] like Figure 6 As shown, the third barrier layer 203 is formed on a side of the second barrier layer 202 away from the first barrier layer 201 by an epitaxial process.

[0061] S160 , forming a doped III-V group semiconductor layer on a side of the third barrier layer away from the second barrier layer.

[0062] like Figure 6 As shown, a doped III-V semiconductor layer 300 is formed on a side of the third barrier layer 203 away from the second barrier layer 202 by an epitaxial process.

[0063] S170. Pattern the doped III-V semiconductor layer so that the vertical projection area of ​​the third barrier layer on the substrate is equal to the vertical projection area of ​​the doped III-V semiconductor layer on the substrate, or the vertical projection area of ​​the third barrier layer on the substrate is equal to the vertical projection area of ​​the second barrier layer on the substrate.

[0064] The doped III-V semiconductor layer 300 is patterned. During the patterning of the doped III-V semiconductor layer 300, the third barrier layer 203 is overetched, such as Figure 7-Figure 8 As shown, and Fig.10 As shown, the third barrier layer 203 at the channel is completely overetched, so that the vertical projection area of ​​the third barrier layer 203 on the substrate is equal to the vertical projection area of ​​the doped III-V semiconductor layer on the substrate. Figure 2 As shown, in the process of patterning the doped III-V semiconductor layer 300 , the third barrier layer 203 is not completely over-etched, and the vertical projection area of ​​the third barrier layer 203 on the substrate 100 is equal to the vertical projection area of ​​the second barrier layer 202 on the substrate 100 .

[0065] S180. When the vertical projection area of ​​the third barrier layer on the substrate is equal to the vertical projection area of ​​the doped III-V semiconductor layer on the substrate, a fourth barrier layer is formed on the side of the second barrier layer away from the first barrier layer; or, when the vertical projection area of ​​the third barrier layer on the substrate is equal to the vertical projection area of ​​the second barrier layer on the substrate, a fourth barrier layer is formed on the side of the third barrier layer away from the second barrier layer; the first barrier layer, the second barrier layer, the third barrier layer and the fourth barrier layer constitute a composite barrier layer.

[0066] like Fig. 9 and Fig.11 As shown, when the vertical projection area of ​​the third barrier layer 203 on the substrate 100 is equal to the vertical projection area of ​​the doped III-V semiconductor layer 300 on the substrate 100, the fourth barrier layer 204 is formed on the side of the second barrier layer 202 away from the first barrier layer 201. The first barrier layer 201, the second barrier layer 202, the third barrier layer 203 and the fourth barrier layer 204 constitute a composite barrier layer 200.

[0067] Or, if Figure 2 As shown, when the vertical projection area of ​​the third barrier layer 203 on the substrate 100 is equal to the vertical projection area of ​​the second barrier layer 202 on the substrate 100, the fourth barrier layer 204 is formed on the side of the third barrier layer 203 away from the second barrier layer 202. The first barrier layer 201, the second barrier layer 202, the third barrier layer 203 and the fourth barrier layer 204 constitute a composite barrier layer 200.

[0068] S190 , forming a source electrode on a side of the fourth barrier layer away from the channel layer.

[0069] like Figure 1 and Fig.12 As shown, a source 401 is formed on a side of the fourth barrier layer 204 away from the channel layer 101 .

[0070] S200 , forming a drain on a side of the fourth barrier layer away from the channel layer.

[0071] like Figure 1 and Fig.12 As shown, a drain 402 is formed on a side of the fourth barrier layer 204 away from the channel layer 101 .

[0072] It should be noted that the process of forming the gate 400 includes two methods: Method 1: Before patterning the doped III-V semiconductor layer, a gate is formed on a side of the doped III-V semiconductor layer away from the third barrier layer.

[0073] like Figure 7-Figure 9 as well as Figure 1As shown, before patterning the doped III-V semiconductor layer 300 , a gate 400 is formed on a side of the doped III-V semiconductor layer 300 away from the third barrier layer 203 .

[0074] Alternatively, in the second method: S200 , after forming a drain on a side of the fourth barrier layer away from the channel layer, a gate is formed on a side of the doped III-V group semiconductor layer away from the third barrier layer.

[0075] like Figure 10-12 as well as Figure 1 As shown, after the drain 402 is formed on the side of the fourth barrier layer 204 away from the channel layer 101 , the gate 400 is formed on the side of the doped III-V group semiconductor layer 300 away from the third barrier layer 203 .

[0076] The first barrier layer 201, the third barrier layer 203 and the fourth barrier layer 204 may be one or more of an AlGaN layer, an AlN layer and an InGaN layer. The doped III-V semiconductor layer 300 is pGaN. The gallium nitride device in the embodiment of the present invention is an enhancement mode GaN high electron mobility transistor (HEMT).

[0077] The technical solution provided by the embodiment of the present invention is that the composite barrier layer 200 includes a first barrier layer 201, a second barrier layer 202, a third barrier layer 203 and a fourth barrier layer 204. During the patterning process of the doped III-V semiconductor layer 300, the third barrier layer 203 is easily over-etched and has too many interface defects. The regrown fourth barrier layer 204 is formed after the doped III-V semiconductor layer 300 is patterned. The fourth barrier layer 204 is formed by a re-growth process and is not affected by the patterning process of the doped III-V semiconductor layer 300. There is no problem of poor quality and many interface defects, which increases the saturation current of the device, reduces the gate leakage current, and improves the electrical performance of the device. During the formation of the fourth barrier layer 204 by a re-growth process such as metal organic chemical vapor deposition (MOCVD), the temperature is relatively high. Since the bond energy of the covalent bond of the second barrier layer 202 is greater than the bond energy of the covalent bond of the first barrier layer 201, the covalent bond of the second barrier layer 202 is less likely to break during the re-growth of the fourth barrier layer 204 than the covalent bond of the first barrier layer 201. And since the third barrier layer 203 will be overetched during the patterning of the doped III-V semiconductor layer 300, even if there is a remaining third barrier layer 203 at the channel, the film thickness is relatively thin. Therefore, the covalent bond of the second barrier layer 202 is less likely to break during the re-growth of the fourth barrier layer 204 than the covalent bond of the first barrier layer 201, which can provide good surface quality for the formation of the fourth barrier layer 204, avoid the presence of defects such as holes in the fourth barrier layer 204, and thus improve the formation quality of the fourth barrier layer 204, which helps the fourth barrier layer 204 to play the role of increasing the device saturation current and reducing the gate leakage current. It should be noted that when the third barrier layer 203 at the channel is completely overetched, the fourth barrier layer 204 grows again on the surface of the second barrier layer 202 , and the second barrier layer 202 provides a better surface quality for the formation of the fourth barrier layer 204 .

[0078] Optionally, based on the above technical solution, Figure 2As shown, in the patterned doped III-V semiconductor layer 300, the third barrier layer 203 at the channel is not completely over-etched, so that the vertical projection area of ​​the third barrier layer 203 on the substrate 100 is equal to the vertical projection area of ​​the second barrier layer 202 on the substrate 100. The third barrier layer 203 includes a first part 2031, a second part 2032 and a third part 2033. The first part 2031 covers the area between the doped III-V semiconductor layer 300 and the source 401, the second part 2032 covers the area between the doped III-V semiconductor layer 300 and the drain 402, and the third part 2033 is located between the doped III-V semiconductor layer 300 and the third barrier layer 203. The thickness of the first part 2031 is less than the thickness of the third part 2033, and the thickness of the second part 2032 is less than the thickness of the third part 2033.

[0079] Specifically, during the patterning process of the doped III-V semiconductor layer 300 , the third barrier layer 203 will be over-etched, and there will be a remaining third barrier layer 203 at the channel, but the film thickness is relatively thin.

[0080] Optionally, based on the above technical solution, after S170 patterning the doped III-V semiconductor layer, the method further includes:

[0081] A passivation layer is formed on the side wall of the doped III-V semiconductor layer, the side wall of the third barrier layer, and a side of the doped III-V semiconductor layer away from the third barrier layer, and the passivation layer is in contact with the fourth barrier layer; the passivation layer is provided with an opening structure, and the gate is located in the opening structure.

[0082] like Fig.13 and Fig.14 , Figure 15-17 as well as Figure 3 and Figure 4 As shown, a passivation layer 500 is formed on the sidewalls of the doped III-V semiconductor layer 300, the sidewalls of the third barrier layer 203, and a side of the doped III-V semiconductor layer 300 away from the third barrier layer 203, and the passivation layer 500 is in contact with the fourth barrier layer 204; the passivation layer 500 is provided with an opening structure, and the gate 400 is located in the opening structure.

[0083] Specifically, the provision of the passivation layer 500 can further reduce the gate leakage current and improve the electrical performance of the device.

[0084] It should be noted that Fig.13 and Fig.14 Before the patterned doped III-V semiconductor layer 300 is formed, a gate 400 is formed on a side of the doped III-V semiconductor layer 300 away from the third barrier layer 203 . Fig.13 and Fig.14 and Figure 8 and Fig. 9 The difference is that Fig.13 and Fig.14 A passivation layer 500 is formed on the sidewalls of the doped III-V semiconductor layer 300 , the sidewalls of the third barrier layer 203 , and a side of the doped III-V semiconductor layer 300 away from the third barrier layer 203 .

[0085] Figure 15-17 It is shown that after the drain 402 is formed on the side of the fourth barrier layer 204 away from the channel layer, the gate 400 is formed on the side of the doped III-V group semiconductor layer 300 away from the third barrier layer 203 . Figure 15-17 and Figure 10-12 The difference is that Figure 15-17 A passivation layer 500 is formed on the sidewalls of the doped III-V semiconductor layer 300 , the sidewalls of the third barrier layer 203 , and a side of the doped III-V semiconductor layer 300 away from the third barrier layer 203 .

[0086] Optionally, based on the above technical solution, S140 forming a second barrier layer on a side of the first barrier layer away from the channel layer includes:

[0087] A second barrier layer including aluminum nitride is formed on a side of the first barrier layer away from the channel layer, wherein the first barrier layer includes at least AlGaN.

[0088] like Figure 6 As shown, a second barrier layer 202 including aluminum nitride is formed on a side of the first barrier layer 201 away from the channel layer 101 , wherein the first barrier layer 201 includes at least AlGaN.

[0089] Specifically, the bond energy of the N-Al covalent bond in aluminum nitride is greater than the bond energy of the N-Ga covalent bond, and the temperature is relatively high during the formation of the fourth barrier layer 204 through a re-growth process such as metal organic chemical vapor deposition (MOCVD). In this process, the N-Al covalent bond is less likely to break, and the second barrier layer 202 can provide a good surface quality for the formation of the fourth barrier layer 204, thereby improving the formation quality of the fourth barrier layer 204, avoiding the presence of defects such as holes in the fourth barrier layer 204, and helping the fourth barrier layer 204 to play the role of increasing the device saturation current and reducing the gate leakage current. In addition, the bandgap width of aluminum nitride is greater than the bandgap width of AlGaN, which can further reduce the gate leakage current and enhance the reliability of the device.

[0090] Optionally, based on the above technical solution, S140 forming a second barrier layer on a side of the first barrier layer away from the channel layer includes:

[0091] A second barrier layer including AlGaN is formed on a side of the first barrier layer away from the channel layer, wherein the first barrier layer at least includes AlGaN, and a content of Al atoms in the second barrier layer is greater than a content of Al atoms in the first barrier layer.

[0092] like Figure 6 As shown, a second barrier layer 202 including AlGaN is formed on a side of the first barrier layer 201 away from the channel layer 101 , wherein the first barrier layer 201 at least includes AlGaN, and the content of Al atoms in the second barrier layer 202 is greater than that in the first barrier layer 201 .

[0093] Specifically, the content of Al atoms in the second barrier layer 202 is greater than the content of Al atoms in the first barrier layer 201, which proves that the ratio of N-Al covalent bonds in the second barrier layer 202 is higher than the ratio of N-Al covalent bonds in the second barrier layer 202. The bond energy of N-Al covalent bonds is greater than the bond energy of N-Ga covalent bonds. During the formation of the fourth barrier layer 204 by a re-growth process such as metal organic chemical vapor deposition (MOCVD), the temperature is relatively high. In this process, the N-Al covalent bond is less likely to break, and the second barrier layer 202 can provide a good surface quality for the formation of the fourth barrier layer 204, thereby improving the formation quality of the fourth barrier layer 204, avoiding the presence of defects such as holes in the fourth barrier layer 204, and helping the fourth barrier layer 204 to play the role of increasing the device saturation current and reducing the gate leakage current. In addition, the content of Al atoms in the second barrier layer 202 is higher, and its bandgap is greater than the bandgap of the first barrier layer 201, which can further reduce the gate leakage current and enhance the reliability of the device.

[0094] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0095] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A gallium nitride device, characterized in that: include: substrate; A channel layer, located on one side of the substrate; A composite barrier layer, comprising a first barrier layer, a second barrier layer, a third barrier layer and a fourth barrier layer; the first barrier layer is located on a side of the channel layer away from the substrate; the second barrier layer is located on a side of the first barrier layer away from the channel layer; the bond energy of the covalent bond of the second barrier layer is greater than the bond energy of the covalent bond of the first barrier layer; the third barrier layer is located on a side of the second barrier layer away from the first barrier layer; a doped III-V group semiconductor layer, located on a side of the third barrier layer away from the second barrier layer; A gate, located on a side of the doped III-V semiconductor layer away from the third barrier layer; When the vertical projection area of ​​the third barrier layer is equal to the vertical projection area of ​​the doped III-V semiconductor layer on the substrate, the fourth barrier layer is located on a side of the second barrier layer away from the first barrier layer; or, when the vertical projection area of ​​the third barrier layer is equal to the vertical projection area of ​​the second barrier layer on the substrate, the fourth barrier layer is located on a side of the third barrier layer away from the second barrier layer; A source electrode, located at a side of the fourth barrier layer away from the channel layer; The drain is located on a side of the fourth barrier layer away from the channel layer.

2. The gallium nitride device according to claim 1, characterized in that: When the vertical projection area of ​​the third barrier layer on the substrate is equal to the vertical projection area of ​​the second barrier layer on the substrate, the third barrier layer includes a first part, a second part and a third part, the first part covers the area between the doped III-V semiconductor layer and the source, the second part covers the area between the doped III-V semiconductor layer and the drain, the third part is located between the doped III-V semiconductor layer and the third barrier layer, the thickness of the first part is smaller than the thickness of the third part, and the thickness of the second part is smaller than the thickness of the third part.

3. The gallium nitride device according to claim 1 or 2, characterized in that: It also includes a passivation layer; the passivation layer covers the sidewalls of the doped III-V semiconductor layer, the sidewalls of the third barrier layer, and a side away from the doped III-V semiconductor layer and away from the third barrier layer; The passivation layer is in contact with the fourth barrier layer; The passivation layer is provided with an opening structure, and the gate is located in the opening structure.

4. The gallium nitride device according to claim 1, characterized in that: The first barrier layer includes at least AlGaN, and the second barrier layer includes aluminum nitride.

5. The gallium nitride device according to claim 1, characterized in that: The first barrier layer comprises at least AlGaN; The second barrier layer includes AlGaN, and a content of Al atoms in the second barrier layer is greater than a content of Al atoms in the first barrier layer.

6. The gallium nitride device according to claim 1, characterized in that: The thickness of the second barrier layer is greater than or equal to 0.1 nm and less than or equal to 3 nm.

7. A method for preparing a gallium nitride device, characterized in that: include: providing a substrate; forming a channel layer on one side of the substrate; forming a first barrier layer on a side of the channel layer away from the substrate; forming a second barrier layer on a side of the first barrier layer away from the channel layer, wherein the bond energy of the covalent bonds of the second barrier layer is greater than the bond energy of the covalent bonds of the first barrier layer; forming a third barrier layer on a side of the second barrier layer away from the first barrier layer; forming a doped III-V semiconductor layer on a side of the third barrier layer away from the second barrier layer; Patterning the doped III-V semiconductor layer so that the vertical projection area of ​​the third barrier layer on the substrate is equal to the vertical projection area of ​​the doped III-V semiconductor layer on the substrate, or the vertical projection area of ​​the third barrier layer on the substrate is equal to the vertical projection area of ​​the second barrier layer on the substrate; When the vertical projection area of ​​the substrate is equal to the vertical projection area of ​​the doped III-V semiconductor layer on the substrate, the third barrier layer forms a fourth barrier layer on the side of the second barrier layer away from the first barrier layer; or, when the vertical projection area of ​​the third barrier layer is equal to the vertical projection area of ​​the second barrier layer on the substrate, the fourth barrier layer is formed on the side of the third barrier layer away from the second barrier layer; the first barrier layer, the second barrier layer, the third barrier layer and the fourth barrier layer constitute a composite barrier layer; forming a source electrode on a side of the fourth barrier layer away from the channel layer; forming a drain electrode on a side of the fourth barrier layer away from the channel layer; Before patterning the doped III-V semiconductor layer, a gate is formed on a side of the doped III-V semiconductor layer away from the third barrier layer; or, after forming a drain on a side of the fourth barrier layer away from the channel layer, a gate is formed on a side of the doped III-V semiconductor layer away from the third barrier layer.

8. The method for preparing a gallium nitride device according to claim 7, characterized in that: The doped III-V semiconductor layer is patterned so that when the vertical projection area of ​​the third barrier layer on the substrate is equal to the vertical projection area of ​​the second barrier layer on the substrate, the third barrier layer includes a first part, a second part and a third part, the first part covers the area between the doped III-V semiconductor layer and the source, the second part covers the area between the doped III-V semiconductor layer and the drain, the third part is located between the doped III-V semiconductor layer and the third barrier layer, the thickness of the first part is less than the thickness of the third part, and the thickness of the second part is less than the thickness of the third part.

9. The method for preparing a gallium nitride device according to claim 7 or 8, characterized in that: After patterning the doped III-V semiconductor layer, the method further comprises: A passivation layer is formed on the sidewalls of the doped III-V semiconductor layer, the sidewalls of the third barrier layer, and a side away from the doped III-V semiconductor layer and away from the third barrier layer, and the passivation layer is in contact with the fourth barrier layer; the passivation layer is provided with an opening structure, and the gate is located in the opening structure.

10. The method for preparing a gallium nitride device according to claim 7, characterized in that: Forming a second barrier layer on a side of the first barrier layer away from the channel layer comprises: A second barrier layer including aluminum nitride is formed on a side of the first barrier layer away from the channel layer, wherein the first barrier layer includes at least AlGaN.

11. The method for preparing a gallium nitride device according to claim 7, characterized in that: Forming a second barrier layer on a side of the first barrier layer away from the channel layer comprises: A second barrier layer including AlGaN is formed on a side of the first barrier layer away from the channel layer, wherein the first barrier layer includes at least AlGaN, and a content of Al atoms in the second barrier layer is greater than a content of Al atoms in the first barrier layer.

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