A semiconductor power module

Abstract

The application relates to a semiconductor power module, belonging to the technical field of device packaging. The module comprises a heat dissipation base plate, an insulating substrate, a metal layer, power terminals, signal terminals, chips and temperature sensing resistors. The insulating substrate is arranged on the surface of the heat dissipation base plate, the metal layer is arranged on the surface of the insulating substrate, and the power terminals, the signal terminals, the chips and the temperature sensing resistors are all arranged on the insulating substrate and electrically connected with the metal layer. Part of the chips form a lower bridge in the middle region of the insulating substrate, and the other part of the chips form upper bridges on both sides of the lower bridge; the number of the upper bridge chips is equal to that of the lower bridge chips. The power terminals, the upper bridge chips and the lower bridge chips jointly form power loops with equal size and opposite direction in the power module. The application can solve the problems of overhigh temperature of individual chips caused by uneven current distribution and electromagnetic interference caused by excessive parasitic parameters.

Description

Technical Field

[0001] This invention belongs to the field of electronic device packaging technology and relates to a semiconductor power module. Background Technology

[0002] In today's rapidly evolving technological landscape, emerging industries such as renewable energy, electric vehicles, high-speed rail, and data centers are placing increasingly stringent demands on power electronic systems. These systems not only pursue higher efficiency and performance but also desire smaller size and longer lifespans. This trend has directly driven innovation in power semiconductor device technology, particularly the shift from traditional silicon (Si)-based materials to third-generation semiconductor materials such as silicon carbide (SiC). SiC power devices, due to their superior physical properties, such as high temperature resistance, high breakdown voltage, low on-resistance, and extremely high switching speed, have become one of the key technologies for improving the efficiency of power electronic systems.

[0003] However, the high performance of SiC power devices also brings new challenges, particularly placing more stringent demands on packaging technology and power module design. Because SiC devices switch much faster than Si devices, their sensitivity to parasitic parameters in the circuit increases dramatically during switching. Among these, parasitic inductance is a significant factor affecting the performance and reliability of SiC devices. At the instant of rapid device turn-off, the inductance in the commutation circuit can induce overvoltage. The magnitude of this overvoltage is proportional to the switching speed, making SiC devices more susceptible to overvoltage surges than Si devices. If the overvoltage exceeds the device's withstand voltage limit, it will directly damage the device and affect the stable operation of the entire system.

[0004] To address this challenge, existing solutions typically include: 1) Selecting devices with higher voltage ratings. While this increases the system's safety margin, high-voltage devices are expensive and may not always be necessary, thus increasing the overall system cost. 2) Slowing down the switching speed by adjusting the control strategy or adding additional circuitry. While this effectively reduces overvoltage, it sacrifices the inherent high-speed switching advantage of SiC devices, leading to increased switching losses and reduced efficiency. 3) Adding buffer absorption circuits, such as using RCD absorption circuits or active clamping circuits, to absorb overvoltage energy. While effective, these methods increase system complexity and cost, and may introduce new loss points.

[0005] Therefore, it is necessary to start with the design of the power module circuit structure and optimize its structure to effectively reduce parasitic inductance, thereby ensuring the reliability of the power module operation. Summary of the Invention

[0006] In view of this, the purpose of the present invention is to provide a semiconductor power module that solves the problems of uneven current distribution leading to excessively high temperature of individual chips and electromagnetic interference caused by excessive parasitic parameters in existing semiconductor power devices.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] A semiconductor power module includes: a heat sink, an insulating substrate, a metal layer, power terminals, signal terminals, a chip, and a temperature-sensing resistor. The insulating substrate is disposed on the surface of the heat sink, the metal layer is disposed on the surface of the insulating substrate, and the power terminals, signal terminals, chip, and temperature-sensing resistor are all disposed on the insulating substrate and electrically connected to the metal layer.

[0009] Furthermore, a portion of the chips are connected in parallel to form an upper bridge, and another portion of the chips are connected in parallel to form a lower bridge, with the number of upper bridge chips and lower bridge chips being equal. The lower bridge chips are arranged in an array in the middle region of the insulating substrate, and the upper bridge chips are symmetrically distributed on both sides of the lower bridge chips.

[0010] Furthermore, the power terminals include a first DC positive terminal, a second DC positive terminal, a DC negative terminal, and an AC terminal, with the first DC positive terminal and the second DC positive terminal located on either side of the DC negative terminal.

[0011] In this circuit, the first DC positive terminal is connected to the drain of one side of the chips in the upper bridge chip, and the second DC positive terminal is connected to the drain of the other side of the chips in the upper bridge chip. The AC terminal is connected to the source of all chips in the upper bridge chip, thus forming a power loop from the DC positive terminal to the AC terminal. The AC terminal is connected to the drain of all chips in the lower bridge chip, and the DC negative terminal is connected to the source of all chips in the lower bridge chip, thus forming a power loop from the AC terminal to the DC negative terminal. The currents in these two power loops are equal in magnitude but opposite in direction, and the power loop length is relatively short. Therefore, the parasitic inductance of the loops can be reduced based on the principle of magnetic field cancellation.

[0012] Furthermore, the power terminals include an upper bridge drain lead-out terminal, an upper bridge gate lead-out terminal, and an upper bridge Kelvin source lead-out terminal disposed on one side of the AC terminals, and a lower bridge gate lead-out terminal, a lower bridge Kelvin source lead-out terminal, a first temperature sensing pin, and a second temperature sensing pin disposed on the other side of the AC terminals.

[0013] Specifically, the upper bridge drain terminal is connected to the drain of the upper bridge chip, the upper bridge gate terminal is connected to the gate of the upper bridge chip, and the upper bridge Kelvin source terminal is connected to the source of the upper bridge chip; the lower bridge gate terminal is connected to the gate of the lower bridge chip, and the lower bridge Kelvin source terminal is connected to the source of the lower bridge chip; the first temperature sensing pin and the second temperature sensing pin are respectively connected to the temperature sensing resistor.

[0014] Furthermore, the semiconductor power module also includes an AC terminal busbar, a DC negative terminal busbar, a DC positive terminal busbar, a first gate drive signal busbar, and a second gate drive signal busbar.

[0015] The drain of the upper bridge chip is electrically connected to the first DC positive terminal, the second DC positive terminal, and the upper bridge drain lead-out terminal via a DC positive terminal busbar. The source of the upper bridge chip is electrically connected to the AC terminal and the upper bridge Kelvin source lead-out terminal via an AC terminal busbar. The gate of the upper bridge chip is electrically connected to the upper bridge gate lead-out terminal via a first gate drive signal busbar.

[0016] The drain of the lower bridge chip is electrically connected to the AC terminal via the AC terminal busbar. The source of the lower bridge chip is electrically connected to the DC negative terminal and the lower bridge Kelvin source lead-out terminal via the DC negative terminal busbar. The gate of the lower bridge chip is electrically connected to the lower bridge gate lead-out terminal via the second gate drive signal busbar.

[0017] The second gate drive signal bus is arranged in the middle area of ​​the AC terminal bus, so that the drive circuit is symmetrically arranged. The second gate drive signal bus is insulated from the AC terminal bus and is electrically connected to the gate of the lower bridge chip and the gate lead-out terminal of the lower bridge chip through bonding wires.

[0018] The first gate drive signal bus is arranged around the edge of the insulating substrate and is electrically connected to the gate of the upper bridge chip and the upper bridge gate lead-out terminal through bonding wires, wherein the connection with the upper bridge gate lead-out terminal is a non-bonding wire surface connection.

[0019] Furthermore, the semiconductor power module also includes heat dissipation fins mounted on the heat dissipation base plate to improve heat dissipation efficiency.

[0020] The beneficial effects of this invention are as follows: By setting the chip layout to an axisymmetric distribution and setting the current direction between the upper and lower bridge chips to be opposite, the current magnitude of the upper and lower bridge arms of the power circuit is equal and the direction is opposite. This can be achieved by utilizing the principle of magnetic field cancellation, which can significantly reduce the parasitic inductance of the power module circuit, effectively reduce the power module loss, reduce the power chip turn-off voltage spike, and improve the reliability of the power module.

[0021] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0022] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0023] Figure 1 This is a schematic diagram of the structure of a power module provided in an embodiment of the present invention;

[0024] Figure 2 This is a schematic diagram of a power module heat sink provided in an embodiment of the present invention;

[0025] Figure 3 This is a schematic diagram of the power circuit of a power module provided in an embodiment of the present invention.

[0026] Reference numerals: 1-First DC positive terminal; 2-DC negative terminal; 3-Second DC positive terminal; 4-Insulating substrate; 5-Chip; 6-Upper bridge drain terminal; 7-Upper bridge gate terminal; 8-Upper bridge Kelvin source terminal; 9-AC terminal; 10-Lower bridge Kelvin source terminal; 11-Lower bridge gate terminal; 12-First temperature sensing pin; 13-Second temperature sensing pin; 14-AC terminal busbar; 15-First gate drive signal busbar; 16-DC negative terminal busbar; 17-Second gate drive signal busbar; 18-Temperature sensing resistor; 19-DC positive terminal busbar; 20-Heat dissipation base plate; 21-Pin fin. Detailed Implementation

[0027] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0028] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0029] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0030] This invention proposes a semiconductor power module, comprising a heat sink, an insulating substrate, multiple chips, and metal terminals. The insulating substrate is located above the heat sink, and a metal layer is disposed on its surface. The metal terminals are electrically connected to the metal layer. Multiple chips are located on the insulating substrate and electrically connected to the metal layer. A portion of the chips are connected in parallel to form the lower bridge of the power module, and another portion of the chips are connected in parallel to form the upper bridge of the power module. The number of chips in the upper and lower bridges is the same. Furthermore, the chips in both the upper and lower bridges are arranged in an array, with the upper bridge chips symmetrically distributed on both sides of the lower bridge chips.

[0031] This configuration, with both the upper and lower bridges arranged in an array within the multiple chip layout, reduces current imbalance and prevents individual chips from experiencing excessive current and localized overheating. Furthermore, the heatsink base of the power module, with its finned plates underneath, increases the heat dissipation area, enabling rapid heat dissipation and preventing chip damage due to overheating.

[0032] It should be noted that the power chip can be a switching transistor chip, and chip 5 can be a MOSFET, transistor, etc., and multiple chips form a single-phase half-bridge structure. Furthermore, this invention does not limit the material or number of chips. For example, the switching transistor chip can be a silicon carbide chip, and the number of chips can be 10, 16, or 20.

[0033] like Figure 1 As shown, this is a semiconductor power module proposed in an embodiment of the present invention. In this embodiment, the power chip 5 is a MOSFET, with a total of 16 MOSFETs, 8 in the upper bridge and 8 in the lower bridge. The 8 MOSFETs of the lower bridge are arranged in an array in the middle region of the insulating substrate 4, while the 8 MOSFETs of the upper bridge are symmetrically distributed on both sides of the lower bridge, with 4 MOSFETs on each side. This symmetrical, mirrored arrangement of the parallel chips in the upper and lower bridges reduces current imbalance, prevents excessive current in individual chips, and facilitates the routing of the chip bonding wires for easier installation.

[0034] In this embodiment, the power module has a rectangular external structure. The metal terminals include power terminals and signal terminals. The power terminals include a DC negative terminal 2, an AC terminal 9, and two DC positive terminals, designated as a first DC positive terminal 1 and a second DC positive terminal 3. The DC negative terminal 2 and the two DC positive terminals are located on the same side of the power module, with parallel leads to the module's positive and negative terminals. The two DC positive terminals are located on opposite sides of the DC negative terminal 2 and are symmetrically arranged. This symmetrical arrangement of the two DC positive terminals reduces the parasitic inductance of the entire power circuit, further reducing turn-off voltage spikes and switching oscillations, thus improving the power module's performance. The AC terminal 9 and signal terminals are located on the other side of the power module. For ease of wiring and miniaturization of the power module, the signal terminal is divided into two parts, located on opposite sides of the AC terminal 9.

[0035] Specifically, the signal terminals include an upper bridge drain lead-out terminal 6, an upper bridge gate lead-out terminal 7, an upper bridge Kelvin source lead-out terminal 8, a lower bridge Kelvin source lead-out terminal 10, a lower bridge gate lead-out terminal 11, a first temperature sensing pin 12, and a second temperature sensing pin 13. The upper bridge drain lead-out terminal 6, the upper bridge gate lead-out terminal 7, and the upper bridge Kelvin source lead-out terminal 8 are located on one side of the AC terminal 9, while the lower bridge Kelvin source lead-out terminal 10, the lower bridge gate lead-out terminal 11, the first temperature sensing pin 12, and the second temperature sensing pin 13 are located on the other side of the AC terminal 9.

[0036] In this embodiment, the selected chip 5 is a MOS transistor. The drain of the chip in the upper bridge is electrically connected to the DC positive terminal, and the drain of the chip in the lower bridge is electrically connected to the AC terminal. The source of the upper bridge chip is electrically connected to the AC terminal via a bonding wire, and the source of the lower bridge chip is connected to the DC negative terminal via a bonding wire. Specifically... Figure 3 As shown, the drain of one side of the upper bridge chip is connected to the first DC positive terminal 1, and the source is connected to the AC terminal 9. The drain of the other side of the upper bridge chip is connected to the second DC positive terminal, and the source is connected to the AC terminal 9, forming a symmetrical power loop from the DC positive terminal to the AC terminal. The drain of the lower bridge chip is connected to the AC terminal 9, and the source is connected to the DC negative terminal 2, forming a power loop from the AC terminal to the DC negative terminal. In this way, the chips 5 are connected to the metal layer on the insulating substrate 4 by bonding wires to form a power loop. The power loop is relatively short and symmetrically distributed, resulting in low parasitic inductance. Simultaneously, the 16 chips 5 are evenly distributed on the insulating substrate, which can dissipate the heat generated by the chips evenly, avoiding excessive thermal coupling between the chips and improving the reliability of the power module.

[0037] In this embodiment, in order to reduce the interference between the power circuit and the drive circuit and improve the switching efficiency of chip 5, Kelvin source connection is adopted when connecting chip 5.

[0038] The power module also includes an AC terminal busbar 14 and a DC negative terminal busbar 16. The upper bridge Kelvin source lead-out terminal 8 is located on the AC terminal busbar 14 to achieve electrical connection with the source of the upper bridge chip, and the lower bridge chip Kelvin source lead-out terminal 10 is located on the DC negative terminal busbar 16 to achieve electrical connection with the source of the lower bridge chip.

[0039] The power module also includes a first gate drive signal bus 15 and a second gate drive signal bus 17. The gates of the upper bridge chip are all led out to the first gate drive signal bus 15 by bonding wires to achieve electrical connection. The gates of the lower bridge chip are electrically connected to the second gate drive signal bus 17 by bonding wires. The second gate drive signal bus 17 is then electrically connected to the lower bridge gate lead-out terminal 11 by bonding wires.

[0040] In addition, to monitor the temperature of chip 5 in real time, the power module also includes a temperature-sensing resistor 18. This temperature-sensing resistor 18 can be a platinum resistance temperature sensor, and it is positioned on the side of the module to facilitate the overall module layout and bring it close to the chip for real-time monitoring of the module's operating temperature. A temperature measurement output terminal is correspondingly provided in the metal terminals. This temperature measurement output terminal includes a first temperature-sensing pin 12 and a second temperature-sensing pin 13. The temperature-sensing resistor 18 is electrically connected to both the first and second temperature-sensing pins, thereby accurately estimating the junction temperature of chip 5.

[0041] In this embodiment, in order to improve the heat dissipation effect, the surface of the heat dissipation base plate 20 is directly connected to the insulating substrate 4, thereby improving the heat dissipation efficiency. Furthermore, heat dissipation pins 21 are provided below the heat dissipation base plate 20 to further improve the heat dissipation efficiency.

[0042] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A semiconductor power module, characterized by include: Heat sink base plate, insulating substrate, metal layer, power terminals, signal terminals, chip and temperature sensing resistor; The insulating substrate is disposed on the surface of the heat dissipation base plate, the metal layer is disposed on the surface of the insulating substrate, and the power terminal, signal terminal, chip and temperature sensing resistor are all disposed on the insulating substrate and electrically connected to the metal layer; it also includes an AC terminal busbar, a DC negative terminal busbar, a DC positive terminal busbar, a first gate drive signal busbar and a second gate drive signal busbar. The chip includes an upper bridge chip and a lower bridge chip; the lower bridge chip is arranged in an array in the middle region of the insulating substrate, and the upper bridge chip is symmetrically distributed on both sides of the lower bridge chip. The power terminal includes a first DC positive terminal, a second DC positive terminal, a DC negative terminal, and an AC terminal, wherein the first DC positive terminal and the second DC positive terminal are located on both sides of the DC negative terminal; The first DC positive terminal is connected to the drain of the first part of the chips in the upper bridge chip via the DC positive terminal busbar. The second DC positive terminal is connected to the drain of the second part of the chips in the upper bridge chip via the DC positive terminal busbar. The sources of each chip in the upper bridge chip are connected to the AC terminals in sequence via bonding wires and AC terminal busbars, forming a power loop from the DC positive terminal to the AC terminals. The AC terminals are connected to the drains of all chips in the lower bridge chip. The sources of each chip in the lower bridge chip are connected to the DC negative terminal via bonding wires and DC negative terminal busbars, forming a power loop from the AC terminals to the DC negative terminals. The bonding wires of the upper and lower bridge chips are arranged in a staggered manner, thereby forming multiple commutation loops with adjacent paths and opposite current directions in the power module. The power terminals include an upper bridge drain terminal, an upper bridge gate terminal, and an upper bridge Kelvin source terminal disposed on one side of the AC terminal, and a lower bridge gate terminal, a lower bridge Kelvin source terminal, a first temperature sensing pin, and a second temperature sensing pin disposed on the other side of the AC terminal. The upper bridge drain terminal is connected to the drain of the upper bridge chip, the upper bridge gate terminal is connected to the gate of the upper bridge chip, and the upper bridge Kelvin source terminal is connected to the source of the upper bridge chip; the lower bridge gate terminal is connected to the gate of the lower bridge chip, and the lower bridge Kelvin source terminal is connected to the source of the lower bridge chip; the first temperature sensing pin and the second temperature sensing pin are respectively connected to the temperature sensing resistor; The drain of the upper bridge chip is electrically connected to the first DC positive terminal, the second DC positive terminal, and the upper bridge drain lead-out terminal through the DC positive terminal busbar. The source of the upper bridge chip is electrically connected to the AC terminal and the upper bridge Kelvin source lead-out terminal through the AC terminal busbar. The gate of the upper bridge chip is electrically connected to the upper bridge gate lead-out terminal through the first gate drive signal busbar. The drain of the lower bridge chip is electrically connected to the AC terminal via the AC terminal busbar. The source of the lower bridge chip is electrically connected to the DC negative terminal and the lower bridge Kelvin source lead-out terminal via the DC negative terminal busbar. The gate of the lower bridge chip is electrically connected to the lower bridge gate lead-out terminal via the second gate drive signal busbar.

2. The semiconductor power module according to claim 1, characterized in that The second gate drive signal bus is arranged in the middle area of ​​the AC terminal bus and is electrically connected to the gate of the lower bridge chip and the lower bridge gate lead-out terminal through bonding wires, respectively.

3. The semiconductor power module according to claim 1, characterized in that, The first gate drive signal bus is arranged around the edge of the insulating substrate and is electrically connected to the gate of the upper bridge chip and the upper bridge gate lead-out terminal through bonding wires, respectively.

4. The semiconductor power module according to any one of claims 1 to 3, characterized in that, The semiconductor power module also includes heat dissipation fins mounted on a heat dissipation base plate to improve heat dissipation efficiency.

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