Semiconductor structure and preparation method thereof, and electronic device

Abstract

The present application provides a semiconductor structure and a preparation method thereof, and an electronic device, and relates to the field of semiconductor technology. Among them, the semiconductor structure includes a substrate, a first electrode layer, a piezoelectric layer, and a second electrode layer. The first electrode layer and the second electrode layer can be used to connect to an external power source, so that the semiconductor structure of the present application can be powered on. The surface of the first side of the substrate is a concave-convex structure, so that the first side surface of the substrate has a concave and convex structure, so that when the crystals in the piezoelectric layer grow on the surface of the first side of the substrate, part of the crystals are located in the concave of the concave-convex structure, and the other part of the crystals are located on the convex of the concave-convex structure. The crystals located in the concave structure and the crystals located on the convex structure can interact and deform, thereby improving the dielectric properties of the crystals, and then improving the dielectric properties of the semiconductor structure of the present application.

Description

Technical Field

[0001] The present application relates to a semiconductor structure and a preparation method thereof, and electronic equipment, and belongs to the field of semiconductor technology. Background Art

[0002] The material of the piezoelectric film in non-volatile memory and MEMS sensors can be selected from lead zirconate titanate film or lead magnesium zirconate titanium, and the film structure is formed by magnetron sputtering. In order to promote the crystal growth of the film, it needs to be carried out in a high temperature environment, but the effect of such a promotion method is also relatively limited, resulting in poor crystal growth effect of the current piezoelectric film and high requirements for the preparation process. Summary of the invention

[0003] The present application provides a semiconductor structure and a preparation method thereof, and an electronic device, which solves the problem of poor crystal growth effect of piezoelectric films in related technologies.

[0004] In a first aspect, the present application provides a semiconductor structure, comprising:

[0005] The substrate has a first side and a second side opposite to each other, the surface of the first side is a concave-convex structure; the surface of the first side has a plurality of protrusions, and the plurality of protrusions are distributed on the surface of the first side at intervals;

[0006] a first electrode layer, stacked on the first side;

[0007] A piezoelectric layer, stacked on a side of the first electrode layer facing away from the substrate;

[0008] The second electrode layer is stacked on a side of the piezoelectric layer facing away from the first electrode layer.

[0009] In some embodiments, the roughness of the surface of the first side is 1 nm-2000 nm.

[0010] In some embodiments, the substrate includes a plate body and a protrusion, the first electrode layer is stacked on the surface of the plate body on the first side, and a plurality of the protrusions are distributed at intervals on the surface of the plate body on the first side.

[0011] In some embodiments, a surface of the plate body located on the first side is provided with a plurality of recessed grooves, and the plurality of protrusions are disposed in the plurality of recessed grooves.

[0012] In some embodiments, the distance between the side of the protrusion facing away from the plate body and the bottom wall of the recessed groove is 1 nm-3000 nm.

[0013] In some embodiments, the outer diameter of the protrusion is 1 μm-50 μm.

[0014] In some embodiments, the plurality of protrusions are spaced apart along the first direction and / or the second direction, the first direction intersects the second direction, and a spacing between adjacent protrusions is 1 μm-250 μm.

[0015] In some embodiments, the semiconductor structure further includes a first promotion layer, which is stacked on the first side and located between the substrate and the first electrode layer.

[0016] In some embodiments, the material of the first promotion layer includes at least one of zirconium dioxide and calcium titanate, and the thickness of the first promotion layer is 1 nm-1000 nm.

[0017] In some embodiments, the semiconductor structure further includes a second promotion layer stacked between the first electrode layer and the piezoelectric layer.

[0018] In some embodiments, the material of the second promotion layer includes at least one of barium titanate, strontium zirconate, strontium ferrite and strontium ruthenate, and the thickness of the second promotion layer is 1 nm-100 nm.

[0019] In some embodiments, the semiconductor structure further includes a diffusion prevention layer stacked between the piezoelectric layer and the second electrode layer.

[0020] In some embodiments, the material of the diffusion prevention layer includes at least one of barium titanate, strontium zirconate, strontium ferrite and strontium ruthenate, and the thickness of the diffusion prevention layer is 10 nm-1500 nm.

[0021] In some embodiments, the material of the piezoelectric layer is lead zirconate titanate film, and the thickness of the piezoelectric layer is 10nm-500nm.

[0022] In some embodiments, the semiconductor structure further includes a bonding layer, and the bonding layer is stacked between the first promotion layer and the first electrode layer.

[0023] In some embodiments, the material of the sealing layer includes at least one of titanium metal, iridium dioxide, zirconium dioxide and chromium metal, and the thickness of the sealing layer is 3nm-200nm.

[0024] In some embodiments, the material of the first electrode layer and the second electrode layer is at least one of platinum, iridium metal, rhenium metal and ruthenium metal;

[0025] The thickness of the first electrode layer and the second electrode layer is 10nm-1500nm.

[0026] In a second aspect, the present application also provides a method for preparing a semiconductor structure, comprising:

[0027] Providing a substrate, the substrate comprising a first side and a second side opposite to each other;

[0028] forming a concavo-convex structure on the surface of the first side;

[0029] forming a first electrode layer on the first side;

[0030] forming a piezoelectric layer on a side of the first electrode layer facing away from the substrate;

[0031] A second electrode layer is formed on a side of the piezoelectric layer facing away from the first electrode layer.

[0032] In some embodiments, forming a concave-convex structure on the surface of the first side includes:

[0033] A concavo-convex structure is formed on the surface of the first side by grinding and / or laser irradiation.

[0034] In some embodiments, before forming the first electrode layer on the first side, the method for preparing a semiconductor structure further includes:

[0035] A first promotion layer is formed on the first side.

[0036] In some embodiments, forming a first promotion layer on the first side includes:

[0037] The substrate is placed in a vacuum environment and heated to 200° C.-600° C., and the first promotion layer is formed on the first side by sputtering or evaporation.

[0038] In some embodiments, after forming the first electrode layer on the first side, the method for preparing a semiconductor structure further includes:

[0039] A second promotion layer is formed on a side of the first electrode layer facing away from the substrate.

[0040] In some embodiments, forming a second promotion layer on a side of the first electrode layer facing away from the substrate comprises:

[0041] The substrate is placed in a vacuum environment and heated to 200° C.-350° C., and the second promotion layer is formed on the first side by sputtering or evaporation.

[0042] In some embodiments, after forming the first promotion layer on the first side, the method for preparing a semiconductor structure further includes:

[0043] An adhesion layer is formed between the first promotion layer and the first electrode layer.

[0044] In some embodiments, forming a close contact layer between the first promotion layer and the first electrode layer comprises:

[0045] The substrate is placed in a vacuum environment and heated to 200° C.-350° C., and the adhesion layer is formed by sputtering or evaporation.

[0046] In some embodiments, during the process of forming the first electrode layer and the piezoelectric layer, a bias voltage is applied to the substrate.

[0047] In some embodiments, the bias voltage is a DC bias voltage of -500V-150V or an AC bias voltage of -500V-150V.

[0048] In a third aspect, based on the above semiconductor structure, the present application also proposes an electronic device, comprising the above semiconductor structure.

[0049] In the semiconductor structure provided by the present application, the first electrode layer is stacked on the first side of the substrate, the piezoelectric layer is stacked on the side of the first electrode layer facing away from the substrate, and the second electrode layer is stacked on the side of the piezoelectric layer facing away from the first electrode layer, so that the substrate, the first electrode layer, the piezoelectric layer and the second electrode layer can constitute a piezoelectric film structure. The first electrode layer and the second electrode layer can be used to connect to an external power source, so that the semiconductor structure of the present application can be powered. The surface of the first side of the substrate is a concave-convex structure, so that the first side surface of the substrate has a concave and convex structure, so that when the crystals in the piezoelectric layer grow on the surface of the first side of the substrate, part of the crystals are located in the concave of the concave-convex structure, and the other part of the crystals are located on the convex of the concave-convex structure. The crystals located in the concave structure and the crystals located on the convex structure can interact and deform, thereby improving the dielectric properties of the crystals, and further improving the dielectric properties of the semiconductor structure of the present application.

[0050] The semiconductor structure preparation method provided in the present application can prepare the above-mentioned semiconductor structure, and the dielectric properties of the semiconductor structure are better.

[0051] The electronic device proposed in the present application includes the above-mentioned semiconductor structure, thereby improving the dielectric performance of the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The above and other purposes, features and advantages of the embodiments of the present application will become more easily understood through the following detailed description with reference to the accompanying drawings. In the accompanying drawings, multiple embodiments of the present application will be described in an exemplary and non-limiting manner, wherein:

[0053] Figure 1 A schematic diagram of a semiconductor structure according to an embodiment of the present application;

[0054] Figure 2A schematic diagram of a substrate of a semiconductor structure according to an embodiment of the present application;

[0055] Figure 3 Flow chart of a method for preparing a semiconductor structure according to an embodiment of the present application.

[0056] Reference numerals:

[0057] 100 - substrate, 110 - first side, 120 - second side, 130 - plate body, 131 - recessed groove, 140 - raised portion,

[0058] 200- first electrode layer,

[0059] 300- piezoelectric layer,

[0060] 400- second electrode layer,

[0061] 500-first promotion layer,

[0062] 600-Second promotion layer,

[0063] 700-Diffusion prevention layer,

[0064] 800-Sealing layer. DETAILED DESCRIPTION

[0065] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0066] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0067] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0068] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or communication with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0069] In the present application, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being “above”, “above”, and “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0070] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0071] In non-volatile memory and micro-electromechanical system sensors, piezoelectric film is an important component structure. In order to improve the performance of piezoelectric film, the material of piezoelectric film can be selected from lead zirconate titanate film or lead magnesium zirconate titanium. The piezoelectric film includes a substrate and an electrode layer and a piezoelectric layer located on the substrate. The electrode layer and the piezoelectric layer can be formed on the substrate in sequence by magnetron sputtering. The growth effect of crystallization in the piezoelectric film is related to the performance of the piezoelectric film. The better the crystal growth, the better the performance of the piezoelectric film. In order to promote the crystal growth of the film, the current method is to form the film in a high temperature environment. Specifically, the substrate needs to be heated to a higher temperature, and then the electrode layer and the piezoelectric layer are generated on the substrate in sequence by a magnetron sputtering process, but the effect of such a promotion method is also relatively limited. However, blindly increasing the temperature of the substrate cannot bring a significant improvement in the growth effect of the crystallization, resulting in poor crystal growth effect of the current piezoelectric film and high requirements for the preparation process.

[0072] In the semiconductor structure proposed in the present application, the first electrode layer is stacked on the first side of the substrate, the piezoelectric layer is stacked on the side of the first electrode layer facing away from the substrate, and the second electrode layer is stacked on the side of the piezoelectric layer facing away from the first electrode layer, so that the substrate, the first electrode layer, the piezoelectric layer and the second electrode layer can constitute a piezoelectric film structure. The first electrode layer and the second electrode layer can be used to connect to an external power source, so that the semiconductor structure of the present application can be powered. The surface of the first side of the substrate is a concave-convex structure, so that the first side surface of the substrate has a concave and convex structure, so that when the crystals in the piezoelectric layer grow on the surface of the first side of the substrate, part of the crystals are located in the concave of the concave-convex structure, and the other part of the crystals are located on the convex of the concave-convex structure. The crystals located in the concave structure and the crystals located on the convex structure can interact and deform, thereby improving the dielectric properties of the crystals, and further improving the dielectric properties of the semiconductor structure of the present application.

[0073] The electronic device proposed in the present application includes the above-mentioned semiconductor structure, thereby improving the dielectric performance of the electronic device.

[0074] The semiconductor structure preparation method proposed in the present application can prepare the above-mentioned semiconductor structure, so that the dielectric properties of the semiconductor structure obtained by the semiconductor structure preparation method of the present application are better.

[0075] The semiconductor structure and its preparation method, and the electronic device provided by the present application are described in detail below in conjunction with specific embodiments.

[0076] This application proposes a semiconductor structure, referring to Figure 1 As shown, it includes a substrate 100, a first electrode layer 200, a piezoelectric layer 300 and a second electrode layer 400. The semiconductor structure can be applied to electronic devices.

[0077] The substrate 100 is a basic component of the semiconductor structure of the present application, and the substrate 100 can provide a mounting base for at least some of the other components of the semiconductor structure, so as to support at least some of the other components of the semiconductor structure. The material of the substrate 100 can be silicon material, so that the substrate 100 can match the characteristics of the semiconductor structure.

[0078] The substrate 100 has a first side 110 and a second side 120 opposite to each other. Specifically, the first side 110 and the second side 120 may be in the thickness direction of the substrate 100. Figure 1 The X direction in the diagram. It should be understood that the thickness direction of the substrate 100 is the direction in which the substrate 100 has the smallest size. The first electrode layer 200 is stacked on the first side 110 of the substrate 100, and the piezoelectric layer 300 is stacked on the side of the electrode layer facing away from the substrate 100, thereby making the substrate 100, the first electrode layer 200, the piezoelectric layer 300 and the second electrode layer 400 stacked in sequence from bottom to top. The first electrode layer 200 and the second electrode layer 400 are parts of the semiconductor structure of the present application that are used to connect to an external power source. After the first electrode layer 200 and the second electrode layer 400 are electrically connected to the external power source, the semiconductor structure of the present application can be energized. Specifically, the first electrode layer 200 can be used as a positive electrode, and the second electrode layer 400 can be used as a negative electrode. Of course, the first electrode layer 200 can also be set as a positive electrode, and correspondingly, the second electrode layer 400 is a negative electrode.

[0079] When the first electrode layer 200 and the second electrode layer 400 are energized, an electric field may be generated between the first electrode layer 200 and the second electrode layer 400 , so that the piezoelectric layer 300 may generate a piezoelectric effect.

[0080] The surface of the first side 110 of the substrate 100 is a concave-convex structure, so that the surface of the first side 110 of the substrate 100 has a concave and convex structure. In this way, when the crystals in the piezoelectric layer 300 grow on the surface of the first side 110 of the substrate 100, part of the crystals are located in the concave of the concave-convex structure, and the other part of the crystals are located on the convex of the concave-convex structure, so that the crystals can be deformed by force, thereby improving the dielectric properties of the crystals, and further improving the dielectric properties of the semiconductor structure of the present application.

[0081] Specifically, the convex structure on the surface of the substrate 100 is located inside or outside the concave structure. When part of a single crystal grows inside the concave structure on the surface of the first side 110 of the substrate 100, the other part of the single crystal grows outside the concave structure and can be attached to the convex structure located inside or outside the concave structure. In this way, the part of the single crystal located inside the concave structure and the part of the single crystal located on the convex structure can be relatively bent, thereby causing the crystal to deform. In this way, the dielectric properties of the crystal can be improved, and the dielectric properties of the semiconductor structure of the present application can be improved.

[0082] In addition, among the multiple crystals, when some crystals grow in the concave structure on the surface of the substrate 100 and another part of the crystals grow on the convex structure on the surface of the substrate 100, the crystals grown in the concave structure and the crystals grown on the convex structure will interact with each other, so that the crystals grown in the concave structure and the crystals grown on the convex structure interact with each other and produce deformation. In this way, the dielectric properties of the crystals can be improved, and then the dielectric properties of the semiconductor structure of the present application can be improved.

[0083] In some embodiments, the concavo-convex structure on the surface of the first side 110 of the substrate 100 of the present application can be formed by grinding, so that the concavo-convex structure can be distributed along the circumference of the substrate 100. Specifically, the substrate 100 can be placed on the table of a grinder, and the grinding disc can contact and rotate with the substrate 100, so as to form a texture structure on the substrate 100, and then form a concavo-convex structure. When the concavo-convex structure is formed on the surface of the first side 110 of the substrate 100 by grinding, the roughness of the surface of the first side 110 of the substrate 100 is 1nm-2000nm, so that the dielectric properties are better after the crystals grow on the substrate 100.

[0084] It should be understood that if the surface roughness of the first side 110 of the substrate 100 is less than 1 nm, the surface roughness of the first side 110 of the substrate 100 will be too small, so that the deformation degree of the crystals grown on the substrate 100 is too small, resulting in poor dielectric properties of the crystals.

[0085] If the surface roughness of the first side 110 of the substrate 100 is greater than 2000nm, the surface roughness of the first side 110 of the substrate 100 will be too large, so that the deformation degree of the crystals grown on the substrate 100 will be too large, thereby causing the structure of the crystals to be destroyed and making it difficult to grow on the surface of the substrate 100, which will also result in poor dielectric properties of the crystals.

[0086] In some embodiments, reference Figure 1 to Figure 2 As shown, in order to form a concavo-convex structure on the surface of the first side 110 of the substrate 100, it can also be achieved by laser irradiation. Specifically, the substrate 100 can be provided to include a plate body 130, and a pulsed laser can be emitted to the surface of the plate body 130 located on the first side 110 by laser irradiation, and the intensity of the pulsed laser can be controlled so that the irradiated position of the surface of the plate body 130 is melted, and then the melted part of the plate body 130 solidifies to form a protrusion 140 on the surface of the plate body 130 located on the first side 110. By emitting pulsed lasers to different parts of the surface of the plate body 130 located on the first side 110 multiple times, a plurality of protrusions 140 can be formed on the plate body 130.

[0087] A plurality of protrusions 140 may be distributed at intervals on the surface of the plate body 130 located on the first side 110, and accordingly, the portion located between adjacent protrusions 140 on the surface of the first side 110 of the plate body 130 is recessed relative to the protrusions 140. It should be understood that when the crystals in the piezoelectric layer 300 grow on the surface of the first side 110 of the substrate 100, part of the crystals grow in the region located between adjacent protrusions 140 on the plate body 130, and another part of the crystals may grow on the surface of the protrusions 140, so that the various parts of the crystals may interact with each other, thereby causing the crystals to deform. As a result, the dielectric properties of the crystals may be improved, and thus the dielectric properties of the semiconductor structure of the present application may be improved.

[0088] In some embodiments, reference Figure 1 to Figure 2 As shown, in order to further improve the degree of deformation of the crystal, a plurality of concave grooves 131 may be provided on the surface of the plate body 130 located on the first side 110, and a plurality of protrusions 140 may be disposed in the plurality of concave grooves 131. It should be understood that the plate body 130 has a plane portion located between adjacent concave grooves 131, and the spacing between the bottom wall of the concave groove 131 and the side of the protrusion 140 facing away from the plate body 130 is relatively large, so that the height difference between the protrusion 140 and the plate body 130 in the thickness direction of the plate body 130 can be increased, so that the concave-convex degree of the surface of the first side 110 of the substrate 100 can be strengthened, so that the degree of deformation of the crystal grown on the substrate 100 is greater.

[0089] Specifically, the number of the plurality of recessed grooves 131 may correspond to the number of the plurality of raised portions 140, so that each recessed groove 131 has a raised portion 140. Of course, the number of recessed grooves 131 may also be set to be greater than the number of raised portions 140, so that some recessed grooves 131 are provided with raised portions 140, while other recessed grooves 131 are not provided with raised portions 140. In addition, the number of recessed grooves 131 may also be set to be less than the number of raised portions 140, so that some recessed grooves 131 are provided with a plurality of raised portions 140, so that the concavo-convexity of the surface of the first side 110 of the substrate 100 can be increased.

[0090] In addition, it should be understood that the surface of the plate body 130 also has a planar portion located between adjacent recessed grooves 131, and the planar portion is a flat structure, and some crystals can also grow on the planar portion between adjacent recessed grooves 131. The crystals grown on the planar portion can interact with the crystals grown in the recessed grooves 131, so that the crystals grown on the planar portion and the crystals grown in the recessed grooves 131 are both deformed. The crystals grown on the planar portion can also interact with the crystals grown on the protruding portion 140, so that the crystals grown on the planar portion and the crystals grown on the protruding portion 140 are both deformed.

[0091] In some embodiments, in order to make the surface roughness of the first side 110 of the substrate 100 more conducive to crystal growth deformation, the distance between the side of the protrusion 140 of the present application facing away from the plate body 130 and the bottom wall of the recessed groove 131 can be set to 1nm-3000nm, so that the dielectric properties of the crystals are better after growing on the substrate 100.

[0092] It should be understood that if the distance between the side of the protrusion 140 facing away from the plate body 130 and the bottom wall of the recessed groove 131 is less than 1 nm, the surface unevenness of the first side 110 of the substrate 100 will be too small, so that the deformation degree of the crystals grown on the substrate 100 will be too small, resulting in poor dielectric properties of the crystals.

[0093] If the distance between the side of the protrusion 140 facing away from the plate body 130 and the bottom wall of the recessed groove 131 is greater than 3000nm, the surface of the first side 110 of the substrate 100 will be too uneven, so that the deformation degree of the crystals grown on the substrate 100 will be too large, thereby destroying the structure of the crystals and making it difficult for them to grow on the surface of the substrate 100, which will also result in poor dielectric properties of the crystals.

[0094] In some embodiments, in order to make the surface concavoconvexity of the first side 110 of the substrate 100 more conducive to crystal growth deformation, the outer diameter of the protrusion 140 of the present application can be set to 1μm-50μm, so that the dielectric properties of the crystals grown on the substrate 100 are better.

[0095] It should be understood that if the outer diameter of the protrusion 140 is less than 1 μm, the protrusion 140 will be too small, resulting in the surface unevenness of the first side 110 of the substrate 100 being too small, so that the deformation degree of the crystals grown on the substrate 100 is too small, resulting in poor dielectric properties of the crystals.

[0096] If the outer diameter of the protrusion 140 is greater than 50 μm, the protrusion 140 will be too large, resulting in the surface of the first side 110 of the substrate 100 being too uneven. In this way, the deformation degree of the crystals grown on the substrate 100 will be too large, which will cause the structure of the crystals to be destroyed and make it difficult for the crystals to grow on the surface of the substrate 100, which will also result in poor dielectric properties of the crystals.

[0097] In some embodiments, the plurality of protrusions 140 of the present application may be disposed on the plate 130 along a first direction and / or a second direction, wherein the first direction is Figure 2 The Y direction in the second direction is Figure 2In the Z direction, the first direction intersects the second direction. When the first direction is perpendicular to the second direction, and part of the protrusions 140 are arranged along the first direction, and another part of the protrusions 140 are arranged along the second direction, the plurality of protrusions 140 can be distributed on the plate body 130 in the form of a rectangular array. In this way, the plurality of protrusions 140 and the plurality of concave grooves 131 can be orderly distributed on the surface of the plate body 130, and the concave-convex effect of the substrate 100 is better, so that the dielectric properties of the crystals after growing on the substrate 100 are better.

[0098] In order to make the surface concavo-convexity of the first side 110 of the substrate 100 more conducive to crystal growth and deformation, the interval between adjacent protrusions 140 can be set to 1 μm-250 μm, so that the dielectric properties of the crystals grown on the substrate 100 are better.

[0099] It should be understood that if the spacing between adjacent protrusions 140 is less than 1 μm, the multiple protrusions 140 will be too dense, resulting in the surface concavity of the first side 110 of the substrate 100 being too small, so that the deformation degree of the crystals grown on the substrate 100 is too small, resulting in poor dielectric properties of the crystals.

[0100] If the spacing between adjacent protrusions 140 is greater than 250 μm, the multiple protrusions 140 will be too dispersed, resulting in the area of ​​the planar portion between the adjacent protrusions 140 on the plate body 130 being too large, which in turn causes the surface concavity of the first side 110 of the substrate 100 to be too small, so that the deformation degree of the crystals grown on the substrate 100 is too small, resulting in poor dielectric properties of the crystals.

[0101] In some embodiments, reference Figure 1 As shown, the semiconductor structure of the present application may also be provided with a first promotion layer 500, which may be stacked on the first side 110 of the substrate 100, so that the first promotion layer 500 is located between the substrate 100 and the first electrode layer 200. By providing the first promotion layer 500, alloying between the first electrode layer 200 and the substrate 100 may be prevented, so as to achieve the purpose of protecting the first electrode layer 200, so that the first electrode layer 200 can maintain its characteristics. In addition, the first promotion layer 500 may also promote the crystal growth in the first electrode layer 200, so that the electrical performance of the first electrode layer 200 is better.

[0102] In some embodiments, in order to prevent the first electrode layer 200 and the substrate 100 from alloying, and to promote the crystal growth in the first electrode layer 200, the first promotion layer 500 may be made of at least one of zirconium dioxide and calcium titanate. Specifically, the first promotion layer 500 may be made of zirconium dioxide or calcium titanate, or a mixture of zirconium dioxide and calcium titanate.

[0103] The thickness of the first promotion layer 500 can be set to 1nm-1000nm, so that the thickness of the first promotion layer 500 can be moderate. Accordingly, the first promotion layer 500 can better prevent alloying between the first electrode layer 200 and the substrate 100 and promote crystal growth in the first electrode layer 200.

[0104] It should be understood that if the thickness of the first promotion layer 500 is less than 1 nm, the thickness of the first promotion layer 500 will be too thin, so that the first promotion layer 500 will have a poor effect in preventing the first electrode layer 200 from alloying with the substrate 100, and the first promotion layer 500 will have a poor effect in promoting crystal growth in the first electrode layer 200.

[0105] If the thickness of the first promotion layer 500 is greater than 1000 nm, the distance between the first electrode layer 200 and the substrate 100 will be too large, so that the crystals in the first electrode layer 200 will be difficult to grow on the substrate 100, and the electrical performance of the first electrode layer 200 will be poor.

[0106] In some embodiments, reference Figure 1 As shown, the semiconductor structure of the present application may also be provided with a second promotion layer 600, which may be stacked on the side of the first electrode layer 200 facing away from the substrate 100, so that the second promotion layer 600 is located between the first electrode layer 200 and the piezoelectric layer 300. By providing the second promotion layer 600, alloying between the first electrode layer 200 and the piezoelectric layer 300 can be prevented, so as to achieve the purpose of protecting the first electrode layer 200 and the piezoelectric layer 300, so that the first electrode layer 200 and the piezoelectric layer 300 can maintain their characteristics. In addition, the second promotion layer 600 can also promote the crystal growth in the piezoelectric layer 300, so that the crystal growth in the piezoelectric layer 300 is better and the dielectric properties of the piezoelectric layer 300 are better.

[0107] In some embodiments, in order to prevent the second promotion layer 600 from alloying with the first electrode layer 200 and the piezoelectric layer 300 and to promote the crystal growth in the piezoelectric layer 300, the material of the second promotion layer 600 may be at least one of barium titanate, strontium zirconate, strontium ferrite and strontium ruthenate. Specifically, the second promotion layer 600 may be barium titanate, strontium zirconate, strontium ferrite and strontium ruthenate, or a mixture of any combination of the above three. In this way, the connection effect between the second promotion layer 600 and the first electrode layer 200 is more stable and reliable.

[0108] The thickness of the second promotion layer 600 can be set to 1 nm-100 nm, so that the thickness of the second promotion layer 600 can be moderate. Accordingly, the second promotion layer 600 can better promote the crystal growth in the first piezoelectric layer 300 .

[0109] It should be understood that if the thickness of the second promotion layer 600 is less than 1 nm, the thickness of the second promotion layer 600 will be too thin, so that the second promotion layer 600 will have a poor effect in promoting the crystal growth in the piezoelectric layer 300 .

[0110] If the thickness of the second promotion layer 600 is greater than 100 nm, the distance between the piezoelectric layer 300 and the substrate 100 will be too large, so that the crystals in the piezoelectric layer 300 will be difficult to grow on the substrate 100, thereby resulting in poor dielectric properties of the piezoelectric layer 300.

[0111] In some implementations, the thickness of the piezoelectric layer 300 can be set to 10 nm-500 nm, so that the thickness of the piezoelectric layer 300 can be moderate, and accordingly, the dielectric property of the piezoelectric layer 300 is better.

[0112] It should be understood that if the thickness of the piezoelectric layer 300 is less than 10 nm, the thickness of the piezoelectric layer 300 will be too thin, so that the dielectric property of the piezoelectric layer 300 is poor.

[0113] If the thickness of the piezoelectric layer 300 is greater than 500 nm, the piezoelectric layer 300 will be too thick, which will make it difficult to form the piezoelectric layer 300 on the second promotion layer 600 and will also cause the cost of the semiconductor structure of the present application to be too high.

[0114] In some embodiments, reference Figure 1 As shown, the semiconductor structure of the present application may also be provided with a diffusion prevention layer 700, which may be stacked on the side of the piezoelectric layer 300 facing away from the first electrode layer 200, so that the diffusion prevention layer 700 is located between the piezoelectric layer 300 and the second electrode layer 400. By providing the diffusion prevention layer 700, alloying between the second electrode layer 400 and the second electrode layer 400 can be prevented, thereby preventing the second electrode layer 400 and the piezoelectric layer 300 from corroding each other, so as to achieve the purpose of protecting the second electrode layer 400 and the piezoelectric layer 300, so that the second electrode layer 400 and the piezoelectric layer 300 can maintain their characteristics. In addition, the diffusion prevention layer 700 can also promote the crystal growth in the second electrode layer 400, so that the electrical performance of the second electrode layer 400 is better.

[0115] In some embodiments, in order to prevent the diffusion prevention layer 700 from diffusing the second electrode layer 400 into the piezoelectric layer 300 and causing the piezoelectric layer 300 to be metallized, and to promote the crystal growth in the second electrode layer 400, the diffusion prevention layer 700 may be made of at least one of barium titanate, strontium zirconate, strontium ferrite, and strontium ruthenate. Specifically, the diffusion prevention layer 700 may be made of barium titanate, strontium zirconate, strontium ferrite, and strontium ruthenate, or a mixture of any combination of the above three.

[0116] The thickness of the diffusion prevention layer 700 can be set to 10nm-1500nm, so that the thickness of the diffusion prevention layer 700 is moderate. Accordingly, the diffusion prevention layer 700 can better prevent alloying between the second electrode layer 400 and the piezoelectric layer 300 and promote crystal growth in the second electrode layer 400.

[0117] It should be understood that if the thickness of the diffusion prevention layer 700 is less than 10 nm, the thickness of the diffusion prevention layer 700 will be too thin. In this way, the diffusion prevention layer 700 will have a poor effect in preventing the second electrode layer 400 and the piezoelectric layer 300 from alloying. The second electrode layer 400 and the piezoelectric layer 300 will easily corrode each other, and the effect of promoting crystal growth in the second electrode layer 400 will be poor.

[0118] If the thickness of the diffusion prevention layer 700 is greater than 1500nm, the distance between the second electrode layer 400 and the piezoelectric layer 300 will be too large, and the distance between the second electrode layer 400 and the substrate 100 will be too large, resulting in the concave-convex structure on the surface of the first side 110 of the substrate 100 having a weaker effect on the growth effect of the crystals in the second electrode layer 400.

[0119] In some embodiments, it should be understood that the first promotion layer 500 and the second promotion layer 600 are located on opposite sides of the first electrode layer 200, and the connection between the first promotion layer 500 and the second promotion layer 600 and the first electrode layer 200 is poor due to the influence of the materials of the first promotion layer 500, the second promotion layer 600 and the first electrode layer 200. For this reason, refer to Figure 1 As shown, the semiconductor structure of the present application may also be provided with a sealing layer 800, which is stacked between the first promotion layer 500 and the first electrode layer 200. The sealing layer 800 can be reliably connected to both the first promotion layer 500 and the first electrode layer 200, so that the first promotion layer 500 can be reliably connected to the first electrode layer 200 through the sealing layer 800.

[0120] In some embodiments, in order to ensure that the adhesion layer 800 can be reliably connected to both the first promotion layer 500 and the first electrode layer 200 , the material of the adhesion layer 800 may include at least one of titanium metal, iridium dioxide, zirconium dioxide and chromium metal.

[0121] In some embodiments, the thickness of the sealing layer 800 can be set to 3nm-200nm so that the thickness of the sealing layer 800 is moderate, so that the sealing layer 800 can reliably connect the first promotion layer 500 and the first electrode layer 200 without affecting the first promotion layer 500's promoting effect on the crystal growth in the first electrode layer 200.

[0122] In some embodiments, the material of the first electrode layer 200 and the second electrode layer 400 is at least one of platinum, iridium metal, rhenium metal and ruthenium metal. The thickness of the first electrode layer 200 and the second electrode layer 400 is 10nm-1500nm. This can make the electrical performance of the first electrode layer 200 and the second electrode layer 400 better.

[0123] In some embodiments, the material of the piezoelectric layer 300 is a lead zirconate titanate film, and the thickness of the piezoelectric layer (300) is 10nm-500nm.

[0124] The present application also proposes an electronic device, comprising the above-mentioned semiconductor structure.

[0125] refer to Figure 3 As shown, the present application also proposes a method for preparing a semiconductor structure, which can be used to prepare the above-mentioned semiconductor structure. The method comprises:

[0126] S100, providing a substrate, wherein the substrate comprises a first side and a second side opposite to each other. The substrate may be made of silicon, so that the substrate is a silicon substrate.

[0127] S200, forming a concavo-convex structure on the surface of the first side of the substrate. After the concavo-convex structure is formed on the surface of the first side of the substrate, some areas of the surface of the first side of the substrate may be concave, and some areas may be convex.

[0128] S300, forming a first electrode layer on the first side of the substrate, wherein the first electrode layer may be stacked on the surface of the first side of the substrate.

[0129] S400, forming a piezoelectric layer on a side of the first electrode layer facing away from the substrate. The piezoelectric layer may be stacked on the first electrode layer.

[0130] S500, forming a second electrode layer on a side of the piezoelectric layer facing away from the first electrode layer. The second electrode layer may be stacked on a side of the piezoelectric layer facing away from the first electrode layer.

[0131] The surface of the first side of the substrate is a concave-convex structure, so that the first side surface of the substrate has a concave and convex structure. In this way, when the crystals in the piezoelectric layer grow on the surface of the first side of the substrate, part of the crystals are located in the concave of the concave-convex structure, and the other part of the crystals are located on the convex of the concave-convex structure, so that the crystals can be deformed by force, thereby improving the dielectric properties of the crystals, and further improving the dielectric properties of the semiconductor structure of the present application.

[0132] In some embodiments, in order to form a concavo-convex structure on the surface of the first side of the substrate, S200 may include:

[0133] S210, forming a concavo-convex structure on the surface of the first side of the substrate by grinding.

[0134] Specifically, the substrate can be placed on a grinding table of a grinding device, and a rotating grinding disc rubs against the surface of the first side of the substrate, thereby forming a concave-convex structure on the surface of the first side of the substrate. When grinding the surface of the first side of the substrate, the rotation speed of the grinding disc can be set to 20rpm-150rpm, the pressure of the grinding disc when grinding the substrate can be set to 30kpa-200kpa, and a non-woven fabric can be set on the surface of the grinding disc. After the substrate is ground to form the concave-convex structure, the substrate is cleaned and dried.

[0135] In some embodiments, in order to form a concavo-convex structure on the surface of the first side of the substrate, S200 may further include:

[0136] S220, forming a concavo-convex structure on the surface of the first side of the substrate by laser irradiation.

[0137] Specifically, by emitting a pulsed laser to the surface of the first side of the substrate, a local area of ​​the substrate surface can be dissolved instantly and then solidified immediately, so that a structure in which a protrusion is located in a concave groove can be formed on the surface of the substrate. By emitting a pulsed laser to the surface of the first side of the substrate multiple times, a plurality of protrusions and concave grooves can be formed, and the position of each protrusion and concave groove can be adjusted according to the irradiation position of the pulsed laser.

[0138] In some embodiments, before forming the first electrode layer on the first side of the substrate, that is, before S300, the method of the present application further includes:

[0139] S310, forming a first promotion layer on a first side of the substrate.

[0140] In some embodiments, to form a first promotion layer on a first side of a substrate, the method of the present application may include:

[0141] S311, placing the substrate in a vacuum environment and heating it to 200°C-600°C, forming a first promotion layer on the first side by sputtering or evaporation, wherein the material of the first promotion layer is at least one of zirconium dioxide and calcium titanate, and the thickness of the first promotion layer is 1nm-1000nm.

[0142] In some embodiments, after forming the first electrode layer on the first side of the substrate, the method of the present application further includes:

[0143] S320, forming a second promotion layer on a side of the first electrode layer facing away from the substrate.

[0144] In some embodiments, in order to form a second promotion layer on the first side of the first electrode layer facing away from the substrate, the method of the present application further includes:

[0145] S321, placing the substrate in a vacuum environment and heating it to 200°C-350°C, and forming a second promotion layer on the first side of the substrate by sputtering or evaporation. The material of the second promotion layer includes at least one of barium titanate, strontium zirconate, strontium ferrite and strontium ruthenate.

[0146] In some embodiments, after forming the first promotion layer on the first side of the substrate, the method of the present application further comprises:

[0147] S330, forming a close contact layer between the first promotion layer and the first electrode layer.

[0148] The adhesion layer can be reliably connected to both the first promotion layer and the first electrode layer, so that the first promotion layer can be reliably connected to the first electrode layer through the adhesion layer.

[0149] In some embodiments, in order to form a close contact layer between the first promotion layer and the first electrode layer, the method of the present application further includes:

[0150] S331, placing the substrate in a vacuum environment and heating it to 200°C-350°C, and forming a sealing layer by sputtering or evaporation. The material of the sealing layer includes at least one of titanium metal, iridium dioxide, zirconium dioxide and chromium metal, and the thickness of the sealing layer is 3nm-200nm.

[0151] In some embodiments, in order to achieve a better effect of forming the first electrode layer, the first promotion layer, the second promotion layer and the piezoelectric layer on the substrate, a bias voltage is applied to the substrate during the process of forming the first electrode layer, the first promotion layer, the second promotion layer and the piezoelectric layer. This can improve the electrical properties of the first electrode layer, improve the effect of the first promotion layer and the second promotion layer on promoting the growth of crystals, and improve the dielectric properties of the piezoelectric layer.

[0152] Specifically, the bias voltage may be a DC bias voltage of -500V-150V or an AC bias voltage of -500V-150V, and this application does not impose any limitation on this.

[0153] Finally, it should be noted that the above implementation modes are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned implementation modes, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned implementation modes can still be modified, or some or all of the technical features therein can be replaced by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the implementation modes of the present application.

Claims

1. A semiconductor structure, characterized in that: include A substrate (100) having a first side (110) and a second side (120) opposite to each other, the surface of the first side (110) being a concave-convex structure; the surface of the first side (110) having a plurality of protrusions (140) and a plurality of concave grooves (131), the plurality of protrusions (140) being arranged in the plurality of concave grooves (131), and the plurality of protrusions (140) being distributed at intervals on the surface of the first side (110); A first electrode layer (200), stacked on the first side (110); A piezoelectric layer (300) is stacked on a side of the first electrode layer (200) facing away from the substrate (100), wherein a portion of crystals in the piezoelectric layer (300) grow on the concave groove (131) and the convex portion (140); A second electrode layer (400) is stacked on a side of the piezoelectric layer (300) that faces away from the first electrode layer (200).

2. The semiconductor structure according to claim 1, characterized in that: The roughness of the surface of the first side (110) is 1 nm-2000 nm.

3. The semiconductor structure according to claim 1, characterized in that: The substrate (100) comprises a plate body (130) and a protruding portion (140); the first electrode layer (200) is stacked on a surface of the plate body (130) located on the first side (110); and a plurality of protruding portions (140) are distributed at intervals on the surface of the plate body (130) located on the first side (110).

4. The semiconductor structure according to claim 3, characterized in that: The distance between the side of the protrusion (140) facing away from the plate body (130) and the bottom wall of the recessed groove (131) is 1 nm-3000 nm.

5. The semiconductor structure according to claim 4, characterized in that: The outer diameter of the protrusion (140) is 1 μm-50 μm.

6. The semiconductor structure according to any one of claims 3 to 5, characterized in that: The plurality of protrusions (140) are spaced apart along a first direction and / or a second direction, the first direction intersects with the second direction, and a spacing between adjacent protrusions (140) is 1 μm-250 μm.

7. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises a first promotion layer (500), wherein the first promotion layer (500) is stacked on the first side (110) and is located between the substrate (100) and the first electrode layer (200).

8. The semiconductor structure according to claim 7, characterized in that: The material of the first promotion layer (500) includes at least one of zirconium dioxide and calcium titanate, and the thickness of the first promotion layer (500) is 1 nm-1000 nm.

9. The semiconductor structure according to claim 8, characterized in that: The semiconductor structure further comprises a second promotion layer (600), wherein the second promotion layer (600) is stacked between the first electrode layer (200) and the piezoelectric layer (300).

10. The semiconductor structure according to claim 9, characterized in that: The material of the second promotion layer (600) includes at least one of barium titanate, strontium zirconate, strontium ferrite and strontium ruthenate, and the thickness of the second promotion layer (600) is 1nm-100nm.

11. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises a diffusion prevention layer (700), wherein the diffusion prevention layer (700) is stacked between the piezoelectric layer (300) and the second electrode layer (400).

12. The semiconductor structure according to claim 11, characterized in that: The material of the diffusion prevention layer (700) includes at least one of barium titanate, strontium zirconate, strontium ferrite and strontium ruthenate, and the thickness of the diffusion prevention layer (700) is 10nm-1500nm.

13. The semiconductor structure according to claim 1, characterized in that The material of the piezoelectric layer (300) is a lead zirconate titanate film, and the thickness of the piezoelectric layer (300) is 10 nm-500 nm.

14. The semiconductor structure according to claim 9, characterized in that: The semiconductor structure further comprises a bonding layer (800), wherein the bonding layer (800) is stacked between the first promotion layer (500) and the first electrode layer (200).

15. The semiconductor structure according to claim 14, characterized in that: The material of the sealing layer (800) includes at least one of titanium metal, iridium dioxide, zirconium dioxide and chromium metal, and the thickness of the sealing layer (800) is 3nm-200nm.

16. The semiconductor structure according to claim 1, characterized in that The material of the first electrode layer (200) and the second electrode layer (400) is at least one of platinum, iridium metal, rhenium metal and ruthenium metal; The thickness of the first electrode layer (200) and the second electrode layer (400) is 10 nm-1500 nm.

17. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate (100), the substrate (100) comprising a first side (110) and a second side (120) opposite to each other; A plurality of protrusions (140) and a plurality of recessed grooves (131) are formed on the surface of the first side (110), the plurality of protrusions (140) are arranged in the plurality of recessed grooves (131), and the plurality of protrusions (140) are distributed at intervals on the surface of the first side (110); forming a first electrode layer (200) on the first side (110); forming a piezoelectric layer (300) on a side of the first electrode layer (200) facing away from the substrate (100), wherein a portion of crystals in the piezoelectric layer (300) grow on the concave groove (131) and the convex portion (140); A second electrode layer (400) is formed on a side of the piezoelectric layer (300) facing away from the first electrode layer (200).

18. The method for preparing a semiconductor structure according to claim 17, characterized in that: The forming of the concavo-convex structure on the surface of the first side (110) comprises: A concave-convex structure is formed on the surface of the first side (110) by grinding and / or laser irradiation.

19. The method for preparing a semiconductor structure according to claim 17, characterized in that: Before forming the first electrode layer (200) on the first side (110), the semiconductor structure preparation method further comprises: A first promotion layer (500) is formed on the first side (110).

20. The method for preparing a semiconductor structure according to claim 19, characterized in that: The forming of the first promotion layer (500) on the first side (110) comprises: The substrate (100) is placed in a vacuum environment and heated to 200°C-600°C, and the first promotion layer (500) is formed on the first side (110) by sputtering or evaporation.

21. The method for preparing a semiconductor structure according to claim 19, characterized in that: After forming a first electrode layer (200) on the first side (110), the semiconductor structure preparation method further comprises: A second promotion layer (600) is formed on a side of the first electrode layer (200) that is away from the substrate (100).

22. The method for preparing a semiconductor structure according to claim 21, characterized in that: The forming of a second promotion layer (600) on a side of the first electrode layer (200) facing away from the substrate (100) comprises: The substrate (100) is placed in a vacuum environment and heated to 200°C-350°C, and the second promotion layer (600) is formed on the first side (110) by sputtering or evaporation.

23. The method for preparing a semiconductor structure according to claim 19, characterized in that: After forming the first promotion layer (500) on the first side (110), the semiconductor structure preparation method further comprises: A close-fitting layer (800) is formed between the first promotion layer (500) and the first electrode layer (200).

24. The method for preparing a semiconductor structure according to claim 23, characterized in that: The step of forming a close-fitting layer (800) between the first promoting layer (500) and the first electrode layer (200) comprises: The substrate (100) is placed in a vacuum environment and heated to 200° C.-350° C., and the adhesion layer (800) is formed by sputtering or evaporation.

25. The method for preparing a semiconductor structure according to claim 21, characterized in that: During the process of forming the first electrode layer (200) and the piezoelectric layer (300), a bias voltage is applied to the substrate (100).

26. The method for preparing a semiconductor structure according to claim 25, characterized in that: The bias voltage is a DC bias voltage of -500V-150V or an AC bias voltage of -500V-150V.

27. An electronic device, characterized in that: Comprising the semiconductor structure according to any one of claims 1 to 16.

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