Display substrate and its preparation method, display device

Abstract

A display substrate includes a substrate (101) and a driving circuit layer (102) disposed on the substrate (101). The driving circuit layer (102) includes at least a plurality of circuit units, at least one of which includes a pixel circuit. The pixel circuit includes at least a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), and a first capacitor (C1). The gate electrode of the first transistor (T1) is electrically connected to a first scan signal line (GL1, 61), and its first electrode is electrically connected to a first initial signal line (INIT1, 81). The gate electrode of the second transistor (T2) is electrically connected to a second scan signal line (GL2, 62). The first initial signal line (INIT1, 81), the first scan signal line (GL1, 61), and the second scan signal line (GL2, 62) extend in at least partially the same direction and are located on the same side of the first transistor (T1). The first initial signal line (INIT1, 81) is located between the first scan signal line (GL1, 61) and the second scan signal line (GL2, 62).

Description

Technical Field

[0001] This article relates to, but is not limited to, display technology, particularly a display substrate and its preparation method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices, possessing advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate, a method for preparing the same, and a display device.

[0005] On one hand, this disclosure provides a display substrate, including: a substrate and a driving circuit layer disposed on the substrate, the driving circuit layer including at least a plurality of circuit units, at least one circuit unit including a pixel circuit; the pixel circuit including at least: a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor. The gate electrode of the first transistor is electrically connected to a first scan signal line, the first terminal of the first transistor is electrically connected to a first initial signal line, and the second terminal of the first transistor is electrically connected to the gate electrode of the third transistor; the gate electrode of the second transistor is electrically connected to a second scan signal line, the first terminal of the second transistor is electrically connected to the gate electrode of the third transistor, and the second terminal of the second transistor is electrically connected to the second terminal of the third transistor. The gate electrode of the fourth transistor is electrically connected to a third scan signal line, the first terminal of the fourth transistor is electrically connected to a data signal line, and the second terminal of the fourth transistor is electrically connected to the second terminal of the first capacitor; the first terminal of the first capacitor is electrically connected to the gate electrode of the third transistor. The first initial signal line, the first scan signal line, and the second scan signal line extend in at least partially the same direction and are located on the same side of the first transistor, the first initial signal line being located between the first scan signal line and the second scan signal line.

[0006] In some exemplary embodiments, the first initial signal line, the first scan signal line, and the second scan signal line are in the same layer.

[0007] In some exemplary embodiments, the active layer of the first transistor includes a first region, a second region, and a channel region located between the first and second regions, wherein the first region of the active layer of the first transistor is connected to the first initial signal line. The driving circuit layer further includes at least one first power line; the orthographic projection of the first power line onto the substrate covers the orthographic projection of the first region of the active layer of the first transistor onto the substrate.

[0008] In some exemplary embodiments, the pixel circuit further includes: a second capacitor; the second capacitor includes at least: a second plate as a second terminal of the second capacitor and a fourth plate as a first terminal of the second capacitor, wherein the orthographic projection of the second plate on the substrate at least partially overlaps with the orthographic projection of the fourth plate on the substrate. The first capacitor includes at least a first plate as a first terminal of the first capacitor and a third plate as a second terminal of the first capacitor, wherein the orthographic projection of the first plate on the substrate at least partially overlaps with the orthographic projection of the third plate on the substrate. The second capacitor includes at least a second plate and a fourth plate, wherein the orthographic projection of the second plate on the substrate at least partially overlaps with the orthographic projection of the fourth plate on the substrate. The fourth plate is connected to a first power line, the second plate is connected to the third plate, and the first plate serves as the gate electrode of the third transistor.

[0009] In some exemplary embodiments, the first electrode plate and the second electrode plate are of the same layer, and the third electrode plate and the fourth electrode plate are of the same layer.

[0010] In some exemplary embodiments, a second electrode connecting line extending toward the fourth electrode is provided on the third electrode plate, and a second groove recessed toward the direction away from the third electrode plate is provided on the fourth electrode plate; the second electrode connecting line is disposed in the second groove, and the end of the second electrode connecting line away from the third electrode plate is connected to the second electrode plate through a through hole and a connecting electrode.

[0011] In some exemplary embodiments, the driving circuit layer further includes: at least one first power connection line extending along a first direction and at least one first power line extending along a second direction, wherein the first direction and the second direction intersect; the first power line and the first power connection line are connected to form a mesh structure for transmitting a first power signal.

[0012] In some exemplary embodiments, the driving circuit layer further includes: at least one second power connection line extending along a first direction, and at least one second power line extending along a second direction, wherein the first direction intersects the second direction; the second power line and the second power connection line are connected to form a mesh structure for transmitting a second power signal; the second power connection line is located on the side of the first power connection line away from the second capacitor.

[0013] In some exemplary embodiments, the first power connection line and the second power connection line are in the same layer, the first power line and the second power line are in the same layer, and the first power line is located on the side of the first power connection line away from the substrate.

[0014] In some exemplary embodiments, the first capacitor and the second capacitor are located on the same side of the first transistor and the second transistor, the second capacitor is located on the side of the first capacitor away from the first transistor and the second transistor, and the orthographic projection of the third transistor on the substrate at least partially overlaps with the orthographic projection of the first capacitor on the substrate.

[0015] In some exemplary embodiments, the fourth plates of the second capacitors of the pixel circuits of adjacent circuit units along the first direction are interconnected as a single structure.

[0016] In some exemplary embodiments, the at least one circuit unit further includes: a first shielding electrode, the orthographic projection of the first shielding electrode on the substrate at least partially overlapping the orthographic projection of the first active layer on the substrate between the two gate electrodes of the first transistor in the circuit unit, and at least partially overlapping the orthographic projection of the second active layer on the substrate between the two gate electrodes of the second transistor in an adjacent circuit unit.

[0017] In some exemplary embodiments, the first shielding electrode includes: a first shielding terminal and a second shielding terminal; the orthographic projection of the first shielding terminal onto the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes of the first transistor in the circuit unit onto the substrate, and the first shielding terminal is electrically connected to a first power line. The orthographic projection of the second shielding terminal onto the substrate at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes of the second transistor in an adjacent circuit unit onto the substrate, and the second shielding terminal is electrically connected to the first power line.

[0018] In some exemplary embodiments, the first shielding electrode and the fourth plate of the second capacitor are an integral structure that is interconnected.

[0019] In some exemplary embodiments, the pixel circuit further includes: a fifth transistor, the gate electrode of which is electrically connected to a first light-emitting signal line, the first electrode of which is electrically connected to a first power supply line, and the second electrode of which is electrically connected to the first electrode of a third transistor; the first light-emitting signal line is located on the side of the second scan signal line away from the first initial signal line.

[0020] In some exemplary embodiments, the film layer containing the first light-emitting signal line is located on the side of the film layer containing the first initial signal line closer to the substrate; or, the first light-emitting signal line and the first initial signal line are in the same layer.

[0021] In some exemplary embodiments, the pixel circuit further includes a sixth transistor, the gate electrode of which is electrically connected to the second light-emitting signal line, the first electrode of which is electrically connected to the second electrode of the third transistor, and the second electrode of which is electrically connected to the light-emitting device. The second light-emitting signal line is located on the side of the first light-emitting signal line away from the first initial signal line. The second light-emitting signal line and the first light-emitting signal line are in the same layer.

[0022] In some exemplary embodiments, the pixel circuit further includes a ninth transistor. The gate electrode of the ninth transistor is electrically connected to a fifth scan signal line, the first electrode of the ninth transistor is electrically connected to a first reference signal line, and the second electrode of the ninth transistor is electrically connected to the second plate of the second capacitor and the third plate of the first capacitor; the fifth scan signal line and the second scan signal line output the same scan signal. The fourth transistor and the ninth transistor are located on the side of the second capacitor away from the first capacitor. The active layers of the fourth transistor and the ninth transistor are an integral structure interconnected.

[0023] In some exemplary embodiments, the active layers of at least two adjacent ninth transistors along a first direction are connected as a single structure via a first active interconnect line.

[0024] In some exemplary embodiments, the pixel circuit further includes a seventh transistor and an eighth transistor; the gate electrode of the seventh transistor is electrically connected to a fourth scan signal line, the first electrode of the seventh transistor is electrically connected to a second initial signal line, and the second electrode of the seventh transistor is electrically connected to a light-emitting device. The gate electrode of the eighth transistor is electrically connected to the fourth scan signal line, the first electrode of the eighth transistor is electrically connected to a second reference signal line, and the second electrode of the eighth transistor is electrically connected to the first electrode of the third transistor.

[0025] In some exemplary embodiments, in a direction perpendicular to the display substrate, the driving circuit layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the substrate. The active layers of the first transistor, the second transistor, and the third transistor are located on the semiconductor layer. The gate electrodes, the first electrode plate, and the second electrode plate of the first transistor, the second transistor, and the third transistor are located on the first conductive layer. The third electrode plate and the fourth electrode plate are located on the second conductive layer. The first initial signal line, the first scan signal line, and the second scan signal line are located on the third conductive layer.

[0026] On the other hand, embodiments of this disclosure provide a display device including a display substrate as described above.

[0027] On the other hand, this disclosure provides a method for fabricating a display substrate, comprising: forming a driving circuit layer on a substrate, the driving circuit layer including at least a plurality of circuit units, at least one circuit unit including a pixel circuit; the pixel circuit including at least: a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor. The gate electrode of the first transistor is electrically connected to a first scan signal line, the first terminal of the first transistor is electrically connected to a first initial signal line, and the second terminal of the first transistor is electrically connected to the gate electrode of the third transistor; the gate electrode of the second transistor is electrically connected to a second scan signal line, the first terminal of the second transistor is electrically connected to the gate electrode of the third transistor, and the second terminal of the second transistor is electrically connected to the second terminal of the third transistor. The gate electrode of the fourth transistor is electrically connected to a third scan signal line, the first terminal of the fourth transistor is electrically connected to a data signal line, and the second terminal of the fourth transistor is electrically connected to the second terminal of the first capacitor; the first terminal of the first capacitor is electrically connected to the gate electrode of the third transistor. The first initial signal line, the first scan signal line, and the second scan signal line extend in at least partially the same direction and are located on the same side of the first transistor, with the first initial signal line located between the first scan signal line and the second scan signal line.

[0028] On the other hand, embodiments of this disclosure provide a display substrate, including: a substrate and a driving circuit layer disposed on the substrate. The driving circuit layer includes at least a plurality of circuit units, at least one of which includes a pixel circuit. The pixel circuit includes at least: a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor. The gate electrode of the first transistor is electrically connected to a first scan signal line, the first terminal of the first transistor is electrically connected to a first initial signal line, and the second terminal of the first transistor is electrically connected to the gate electrode of the third transistor. The gate electrode of the second transistor is electrically connected to a second scan signal line, the first terminal of the second transistor is electrically connected to the gate electrode of the third transistor, and the second terminal of the second transistor is electrically connected to the second terminal of the third transistor. The gate electrode of the fourth transistor is electrically connected to a third scan signal line, the first terminal of the fourth transistor is electrically connected to a data signal line, and the second terminal of the fourth transistor is electrically connected to the second terminal of the first capacitor. The first terminal of the first capacitor is electrically connected to the gate electrode of the third transistor. The second transistor is located on one side of the first transistor in a first direction, and the third transistor and the fourth transistor are located on the same side of the first transistor and the second transistor in a second direction, wherein the first direction and the second direction intersect. The first initial signal line, the first scan signal line, and the second scan signal line all extend along the first direction and are located on the side of the first transistor away from the third transistor in the second direction. The first initial signal line is located between the first scan signal line and the second scan signal line.

[0029] In some exemplary embodiments, the orthographic projection of the first scan signal line onto the substrate overlaps with the orthographic projection portions of the gate electrode of the first transistor and the gate electrode of the second transistor onto the substrate.

[0030] In some exemplary embodiments, the pixel circuit further includes a second capacitor; the second capacitor includes at least a second plate as a second terminal of the second capacitor and a fourth plate as a first terminal of the second capacitor, wherein the orthographic projection of the second plate on the substrate at least partially overlaps with the orthographic projection of the fourth plate on the substrate. The first capacitor includes at least a first plate as a first terminal of the first capacitor and a third plate as a second terminal of the first capacitor, wherein the orthographic projection of the first plate on the substrate at least partially overlaps with the orthographic projection of the third plate on the substrate. The fourth plate is connected to a first power line, the second plate is connected to the third plate, and the first plate serves as the gate electrode of the third transistor.

[0031] In some exemplary embodiments, a second electrode connecting line extending toward the fourth electrode is provided on the third electrode plate, and a second groove recessed toward the direction away from the third electrode plate is provided on the fourth electrode plate; the second electrode connecting line is disposed in the second groove, and the end of the second electrode connecting line away from the third electrode plate is connected to the second electrode plate through a through hole and a connecting electrode.

[0032] In some exemplary embodiments, the at least one circuit unit further includes: a first shielding electrode; the first shielding electrode includes: a first shielding terminal and a second shielding terminal; the orthographic projection of the first shielding terminal onto the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes of the first transistor in the circuit unit onto the substrate, and the first shielding terminal is electrically connected to a first power line. The orthographic projection of the second shielding terminal onto the substrate at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes of the second transistor in an adjacent circuit unit onto the substrate, and the second shielding terminal is electrically connected to the first power line.

[0033] In some exemplary embodiments, the pixel circuit further includes a fifth transistor and a sixth transistor. The gate electrode of the fifth transistor is electrically connected to a first light-emitting signal line, the first electrode of the fifth transistor is electrically connected to a first power supply line, and the second electrode of the fifth transistor is electrically connected to the first electrode of the third transistor. The gate electrode of the sixth transistor is electrically connected to a second light-emitting signal line, the first electrode of the sixth transistor is electrically connected to the second electrode of the third transistor, and the second electrode of the sixth transistor is electrically connected to a light-emitting device. The first light-emitting signal line is located on one side of the second scan signal line in a second direction, and the second light-emitting signal line is located on one side of the first light-emitting signal line in a second direction.

[0034] In some exemplary embodiments, the first light-emitting signal line, the second light-emitting signal line, and the first initial signal line are in the same layer.

[0035] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0036] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of one or more components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0037] Figure 1 This is a schematic diagram of the structure of a display device;

[0038] Figure 2This is a schematic diagram of a planar structure of a display substrate;

[0039] Figure 3 This is a schematic diagram of a partial cross-sectional structure of a display substrate;

[0040] Figure 4 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0041] Figure 5 for Figure 4 An example diagram of the timing sequence of the pixel circuit shown;

[0042] Figure 6 This is a schematic diagram of the planar structure of a display substrate according to at least one embodiment of the present disclosure;

[0043] Figure 7 for Figure 6 A partial cross-sectional view along the Q-Q' direction;

[0044] Figure 8 for Figure 6 A schematic diagram of a display substrate after the semiconductor layer has been formed;

[0045] Figure 9A for Figure 6 A schematic diagram of the display substrate after the first conductive layer has been formed;

[0046] Figure 9B for Figure 9A A schematic diagram of the first conductive layer in the middle;

[0047] Figure 10A This is a schematic diagram of the display substrate after the second conductive layer has been formed, as shown in Figure 10.

[0048] Figure 10B for Figure 10A A schematic diagram of the second conductive layer in the middle;

[0049] Figure 11 for Figure 6 A schematic diagram of the display substrate after the third insulating layer has been formed;

[0050] Figure 12A for Figure 6 A schematic diagram of the display substrate after the third conductive layer has been formed;

[0051] Figure 12B for Figure 12A A schematic diagram of the third conductive layer in the middle;

[0052] Figure 13 for Figure 6 A schematic diagram of the display substrate after the fourth insulating layer has been formed;

[0053] Figure 14 for Figure 6 A schematic diagram of the fourth conductive layer in the middle;

[0054] Figure 15 This is a schematic diagram of the planar structure of another display substrate according to at least one embodiment of the present disclosure;

[0055] Figure 16A for Figure 15 A schematic diagram of the display substrate after the first conductive layer has been formed;

[0056] Figure 16B for Figure 16A A schematic diagram of the first conductive layer in the middle;

[0057] Figure 17A for Figure 15 A schematic diagram of the display substrate after the second conductive layer has been formed;

[0058] Figure 17B for Figure 17A A schematic diagram of the second conductive layer in the middle;

[0059] Figure 18 for Figure 15 A schematic diagram of the display substrate after the third insulating layer has been formed;

[0060] Figure 19A for Figure 15 A schematic diagram of the display substrate after the third conductive layer has been formed;

[0061] Figure 19B for Figure 19A A schematic diagram of the third conductive layer in the middle;

[0062] Figure 20 for Figure 15 A schematic diagram of the display substrate after the fourth insulating layer has been formed;

[0063] Figure 21 for Figure 15 A schematic diagram of the fourth conductive layer in the middle;

[0064] Figure 22 This is a schematic diagram of the planar structure of another display substrate according to at least one embodiment of the present disclosure;

[0065] Figure 23 for Figure 22 A schematic diagram of the display substrate after the first conductive layer has been formed;

[0066] Figure 24A for Figure 22 A schematic diagram of the display substrate after the second conductive layer has been formed;

[0067] Figure 24B for Figure 24A A schematic diagram of the second conductive layer in the middle;

[0068] Figure 25 for Figure 22 A schematic diagram of the display substrate after the third insulating layer has been formed;

[0069] Figure 26A for Figure 22 A schematic diagram of the display substrate after the third conductive layer has been formed;

[0070] Figure 26B for Figure 26A A schematic diagram of the third conductive layer in the middle;

[0071] Figure 27 for Figure 22 A schematic diagram of the display substrate after the fourth insulating layer has been formed;

[0072] Figure 28 for Figure 22 A schematic diagram of the fourth conductive layer in the middle;

[0073] Figure 29 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0074] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0075] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0076] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0077] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0078] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "coupling" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or link; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate. "Electrical connection" includes situations where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the term "component having some electrical function," as long as it allows for the transmission of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with one or more functions.

[0079] In this specification, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0080] In this specification, to distinguish the two terminals of a transistor other than the gate, one electrode is referred to as the first terminal and the other as the second terminal. The first terminal can be either the source or the drain, and the second terminal can be either the drain or the source. The gate of the transistor is referred to as the control terminal. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0081] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0082] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0083] In this disclosure, "approximately" and "roughly" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this disclosure, "roughly the same" means that the values ​​differ by no more than 10%.

[0084] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the following description, "A extends along direction B" refers to "the main part of A extends along direction B".

[0085] Figure 1 This is a schematic diagram of the structure of a display device. In some examples, such as... Figure 1 As shown, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller may be connected to the data driver, scan driver, and light-emitting driver respectively. The data driver is connected to multiple data signal lines (e.g., D1 to Dr), the scan driver is connected to multiple scan signal lines (e.g., S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (e.g., E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least pixel circuitry, which may be connected to the scan signal lines, light-emitting signal lines, and data signal lines respectively. The light-emitting unit may include a light-emitting device, which may be electrically connected to the pixel circuitry of the circuit unit.

[0086] In some examples, the timing controller can provide grayscale values ​​and control signals suitable for the data driver, clock signals, scan start signals, etc. suitable for the scan driver, and clock signals, transmit stop signals, etc. suitable for the light-emitting driver. The data driver can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dr. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 through Dr, in pixel rows, where r can be a natural number. The scan driver can use clock signals, scan start signals, etc., received from the timing controller to generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm. For example, the scan driver can sequentially provide scan signals with conduction level pulses to scan signal lines S1 through Sm, where m can be a natural number. For example, a scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of turn-on level pulses, to the next stage circuit under the control of a clock signal, where m can be a natural number. An LED driver can generate transmit signals to be provided to LED signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, the LED driver can sequentially provide transmit signals with cutoff level pulses to LED signal lines E1 to Eo. For example, the LED driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals, provided in the form of cutoff level pulses, to the next stage circuit under the control of a clock signal, where o can be a natural number. In some examples, a pixel array can be disposed on a display substrate.

[0087] Figure 2 This is a schematic diagram of a planar structure of a display substrate. In some examples, the display substrate may include a display area and a border area surrounding the display area. Figure 2As shown, the display area of ​​the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel circuit, which may be electrically connected to a scan signal line, a data signal line, and a light-emitting signal line, respectively. The pixel circuit may be configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting unit under the control of the scan signal line and the light-emitting signal line. The light-emitting unit may include at least a light-emitting device, which may be electrically connected to the pixel circuit of the sub-pixel. The light-emitting device may be configured to emit light of a corresponding brightness in response to the current output by the pixel circuit of the sub-pixel.

[0088] In some examples, a pixel circuit may include multiple transistors and at least one capacitor. For example, a pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In these circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0089] In some examples, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 can be a green sub-pixel (G) emitting green light. In some examples, the shape of the light-emitting device can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the light-emitting devices of the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement. When a pixel unit includes four sub-pixels, the light-emitting devices of the four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0090] Figure 3 This is a schematic diagram of a partial cross-sectional structure of a display substrate. Figure 3 The diagram illustrates the structure of three sub-pixels on a display substrate. In some examples, such as... Figure 3 As shown, in a direction perpendicular to the display substrate, the display area of ​​the display substrate may include: a substrate 101, a driving circuit layer 102 disposed on the substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer. This disclosure is not limited thereto.

[0091] In some examples, substrate 101 can be a flexible substrate or a rigid substrate. Driving circuit layer 101 can include multiple circuit units, each of which can include at least a pixel circuit, and the pixel circuit can include multiple transistors and at least one capacitor. Light-emitting structure layer 103 can include multiple light-emitting units, each of which can include at least a light-emitting device. Encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers can be made of inorganic materials, and the second encapsulation layer can be made of organic materials. The second encapsulation layer can be disposed between the first and third encapsulation layers, forming a stacked structure of inorganic / organic / inorganic materials, which can prevent external moisture from entering the light-emitting structure layer 103.

[0092] In some examples, the light-emitting device can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting device can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting device can be determined as needed. In some examples, the light-emitting device can include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting device can be electrically connected to the corresponding pixel circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer can emit light of the corresponding color under the drive of the anode and the cathode. However, this embodiment is not limited in this respect.

[0093] In some examples, the organic light-emitting layer may include an emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0094] This embodiment provides a display substrate, including: a substrate and a driving circuit layer disposed on the substrate, the driving circuit layer including at least a plurality of circuit units. At least one circuit unit includes a pixel circuit. The pixel circuit includes at least: a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor. The gate electrode of the first transistor is electrically connected to a first scan signal line, the first terminal of the first transistor is electrically connected to a first initial signal line, and the second terminal of the first transistor is electrically connected to the gate electrode of the third transistor. The gate electrode of the second transistor is electrically connected to a second scan signal line, the first terminal of the second transistor is electrically connected to the gate electrode of the third transistor, and the second terminal of the second transistor is electrically connected to the second terminal of the third transistor. The gate electrode of the fourth transistor is electrically connected to a third scan signal line, the first terminal of the fourth transistor is electrically connected to a data signal line, and the second terminal of the fourth transistor is electrically connected to the second terminal of the first capacitor; the first terminal of the first capacitor is electrically connected to the gate electrode of the third transistor. The first initial signal line, the first scan signal line, and the second scan signal line extend in at least partially the same direction and are located on the same side of the first transistor, with the first initial signal line located between the first scan signal line and the second scan signal line.

[0095] In the display substrate provided in this embodiment, the first transistor is configured to initialize the gate electrode of the third transistor (i.e., the first terminal of the first capacitor) using a first initial signal provided by a first initial signal line under the control of the first scan signal line. By placing the first initial signal line between the first scan signal line and the second scan signal line, the layout wiring can be optimized, the initialization path length of the first initial signal can be reduced, and the initialization effect can be improved.

[0096] In some exemplary embodiments, the active layer of the first transistor may include a first region, a second region, and a channel region located between the first and second regions. The first region of the active layer of the first transistor is connected to a first initial signal line. The driving circuit layer further includes at least one first power line. The orthographic projection of the first power line onto the substrate covers the orthographic projection of the first region of the active layer of the first transistor onto the substrate. Specifically, the orthographic projection of the first power line onto the substrate may cover the orthographic projection of the connection point between the first region of the active layer of the first transistor and the first initial signal line onto the substrate. This example, by setting the first power line to shield the first region of the active layer of the first transistor connected to the first initial signal line, can prevent other signals from affecting the reception of the first initial signal by the first region of the active layer of the first transistor, thereby ensuring the accuracy of the transmission of the first initial signal and ensuring the initialization effect.

[0097] In some exemplary embodiments, the pixel circuit may further include a second capacitor. The second capacitor includes at least a second plate serving as a second terminal and a fourth plate serving as a first terminal, wherein the orthographic projections of the second plate onto the substrate and the fourth plate onto the substrate at least partially overlap. The first capacitor includes at least a first plate serving as a first terminal and a third plate serving as a second terminal, wherein the orthographic projections of the first plate onto the substrate and the third plate onto the substrate at least partially overlap. The fourth plate is connected to a first power line, the second plate is connected to the third plate, and the first plate serves as the gate electrode of the third transistor.

[0098] In some exemplary embodiments, a second electrode connecting line extending toward the fourth electrode is provided on the third electrode plate, and a second groove recessed away from the third electrode plate is provided on the fourth electrode plate. The second electrode connecting line can be disposed within the second groove, and the end of the second electrode connecting line away from the third electrode plate can be connected to the second electrode plate through a via and a connecting electrode. The design structure of the third and fourth electrode plates in this example can increase the distance between the first and fifth nodes of the pixel circuit and is beneficial for increasing the arrangement space of the lateral traces.

[0099] In some exemplary embodiments, at least one circuit unit may further include a first shielding electrode. The orthographic projection of the first shielding electrode onto the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes of the first transistor in this circuit unit onto the substrate, and also at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes of the second transistor in an adjacent circuit unit onto the substrate. In some examples, the first shielding electrode may include a first shielding terminal and a second shielding terminal. The orthographic projection of the first shielding terminal onto the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes of the first transistor in this circuit unit onto the substrate, and the first shielding terminal is electrically connected to a first power line. The orthographic projection of the second shielding terminal onto the substrate at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes of the second transistor in an adjacent circuit unit onto the substrate, and the second shielding terminal is electrically connected to the first power line. The structural design of the first shielding electrode in this example can improve signal crosstalk.

[0100] The following examples illustrate the display substrate of this embodiment.

[0101] Figure 4This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. The pixel circuit of this example can be a 9T2C structure, which may include nine transistors (e.g., first transistor T1 to ninth transistor T9) and two capacitors (e.g., first capacitor C1 and second capacitor C2). The pixel circuit can be electrically connected to 12 signal lines (e.g., including first scan signal line GL1, second scan signal line GL2, third scan signal line GL3, fourth scan signal line GL4, first light emission signal line EM1, second light emission signal line EM2, first initial signal line INIT1, second initial signal line INIT2, first reference signal line REF1, second reference signal line REF2, data signal line DL, and first power supply line VDD).

[0102] In some examples, such as Figure 4 As shown, the pixel circuit may include: a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5. The first node N1 can be connected to the second terminal of the first transistor T1, the first terminal of the second transistor T2, the gate electrode of the third transistor T3, and the first terminal of the first capacitor C1. The second node N2 can be connected to the first terminal of the third transistor T3, the second terminal of the eighth transistor T8, and the second terminal of the fifth transistor T5. The third node N3 can be connected to the second terminals of the second transistor T2, the second terminals of the third transistor T3, and the first terminal of the sixth transistor T6. The fourth node N4 can be connected to the second terminal of the sixth transistor T6 and the second terminal of the seventh transistor T7. The fifth node N5 can be connected to the second terminal of the fourth transistor T4, the second terminal of the ninth transistor T9, the second terminal of the first capacitor C1, and the second terminal of the second capacitor C2. The fourth node N4 can also be connected to the anode of the light-emitting device EL.

[0103] In some examples, the first terminal (lower plate) of the first capacitor C1 is connected to the first node N1, and the second terminal (upper plate) of the first capacitor C1 is connected to the fifth node N5. The first terminal (upper plate) of the second capacitor C2 is connected to the first power line VDD, and the second terminal (lower plate) of the second capacitor C2 is connected to the fifth node N5.

[0104] In some examples, the gate electrode of the first transistor T1 is connected to the first scan signal line GL1, the first terminal of the first transistor T1 is connected to the first initial signal line INIT1, and the second terminal of the first transistor is connected to the first node N1. When a conduction signal is applied to the first scan signal line GL1, the first transistor T1 transmits the first initial voltage to the gate electrode of the third transistor T3 and the first terminal of the first capacitor C1, releasing the charge accumulated in the first capacitor C1 and achieving initialization.

[0105] In some examples, the gate electrode of the second transistor T2 is connected to the second scan signal line GL2, the first terminal of the second transistor T2 is connected to the first node N1, and the second terminal of the second transistor T2 is connected to the third node N3. When a conduction signal is applied to the second scan signal line GL2, the second transistor T2 causes the gate electrode of the third transistor T3 to connect to the second terminal.

[0106] In some examples, the gate electrode of the third transistor T3 is connected to the first node N1, meaning the gate electrode of the third transistor T3 is connected to the first terminal of the first capacitor C1. The first terminal of the third transistor T3 is connected to the second node N2, and the second terminal of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called the driving transistor, and the magnitude of the driving current is determined by the potential difference between its gate electrode and its first terminal.

[0107] In some examples, the gate electrode of the fourth transistor T4 is connected to the third scan signal line GL3, the first electrode of the fourth transistor T4 is connected to the data signal line DL, and the second electrode of the fourth transistor T4 is connected to the fifth node N5. When a conduction signal is applied to the third scan signal line GL3, the fourth transistor T4 causes the data voltage of the data signal line DL to be input to the fifth node N5 (i.e., the second terminal of the first capacitor C1 and the second terminal of the second capacitor C2).

[0108] In some examples, the gate electrode of the fifth transistor T5 is connected to the first light-emitting signal line EM1, the first terminal of the fifth transistor T5 is connected to the first power supply line VDD, and the second terminal of the fifth transistor T5 is connected to the second node N2. The gate electrode of the sixth transistor T6 is connected to the second light-emitting signal line EM2, the first terminal of the sixth transistor T6 is connected to the third node N3, and the second terminal of the sixth transistor T6 is connected to the fourth node N4. When a conduction signal is applied to the first light-emitting signal line EM1 and the second light-emitting signal line EM2, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power supply line VDD and the second power supply line VSS, causing the light-emitting device EL to emit light.

[0109] In some examples, the gate electrode of the seventh transistor T7 is connected to the fourth scan signal line GL4, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4. When a conduction signal is applied to the fourth scan signal line GL4, the seventh transistor T7 transmits the second initial voltage to the first electrode of the light-emitting device EL, releasing the charge accumulated in the first electrode of the light-emitting device EL and achieving initialization.

[0110] In some examples, the gate electrode of the eighth transistor T8 is connected to the fourth scan signal line GL4, the first electrode of the eighth transistor T8 is connected to the second reference signal line REF2, and the second electrode of the eighth transistor T8 is connected to the second node N2. When a conduction signal is applied to the fourth scan signal line GL4, the eighth transistor T8 transmits the second reference signal to the second node N2.

[0111] In some examples, the gate electrode of the ninth transistor T9 is connected to the second scan signal line GL2, the first electrode of the ninth transistor T9 is connected to the first reference signal line REF1, and the second electrode of the ninth transistor T9 is connected to the fifth node N5. When a conduction signal is applied to the second scan signal line GL2, the ninth transistor T9 transmits the first reference signal to the fifth node N5.

[0112] In some examples, the light-emitting device (EL) can be an OLED, comprising a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it can be a QLED, comprising a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode). The first electrode of the EL is connected to a fourth node N4, and the second electrode of the EL is connected to a second power line VSS. In some examples, the signal on the second power line VSS can be a continuously supplied low-level signal, and the signal on the first power line VDD can be a continuously supplied high-level signal.

[0113] In some examples, the first transistor T1 through the ninth transistor T9 of the pixel circuit can be either P-type or N-type transistors. Using the same type of transistor in the pixel circuit simplifies the manufacturing process, reduces the manufacturing difficulty of the display panel, and improves product yield. In some possible implementations, the first transistor T1 through the ninth transistor T9 may include both P-type and N-type transistors.

[0114] In some examples, the first transistor T1 to the ninth transistor T9 of the pixel circuit can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both. The active layer of the LTPS thin-film transistor is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the oxide thin-film transistor is made of oxide. LTPS thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0115] Figure 5 for Figure 4 The diagram shows an example of the timing sequence of the pixel circuitry. In some examples, using... Figure 4 Taking the pixel circuit shown as an example where the first transistor T1 to the ninth transistor T9 are all P-type transistors, the operation of the pixel circuit can include the following stages.

[0116] In the first stage S1, the signal of the first light-emitting signal line EM1 is a low-level signal, while the signals of the second light-emitting signal line EM2, the third scan signal line GL3, and the fourth scan signal line GL4 are high-level signals. The low-level signal of the first light-emitting signal line EM1 enables the fifth transistor T5 to conduct, allowing the first power signal of the first power line VDD to be supplied to the second node N2. The high-level signals of the second light-emitting signal line EM2, the third scan signal line GL3, and the fourth scan signal line GL4 cause the sixth transistor T6, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 to all turn off.

[0117] The first stage S1 may include at least: a first sub-stage S11, a second sub-stage S12, a third sub-stage S13, a fourth sub-stage S14, a fifth sub-stage S15, and a sixth sub-stage S16. In the first sub-stage S11, the signal on the first scan signal line GL1 is low, causing the first transistor T1 to turn on; the signal on the second scan signal line GL2 is high, causing the second transistor T2 and the ninth transistor T9 to turn off. With the first transistor T1 on, the first initial signal on the first initial signal line INIT1 can be provided to the first node N1 to initialize it. In the second sub-stage S12, the signal on the first scan signal line GL1 is high, causing the first transistor T1 to turn off; the signal on the second scan signal line GL2 is low, causing the second transistor T2 and the ninth transistor T9 to turn on. With the second transistor T2 on, the first node N1 and the third node N3 can be connected, threshold compensation can be performed on the third transistor T3, and the threshold voltage of the third transistor T3 can be written into the first node N1. When the ninth transistor T9 is turned on, the first reference signal of the first reference signal line REF1 can be provided to the fifth node N5 to initialize the fifth node N5. The third sub-stage S13 and the fifth sub-stage S15 are roughly the same as the first sub-stage S11, and the fourth sub-stage S14 and the sixth sub-stage S16 are roughly the same as the second sub-stage S12, so they will not be described in detail here.

[0118] When the driving transistor (i.e., the third transistor) remains in one state for an extended period, electrons are trapped, causing hysteresis. Therefore, in this stage, performing the initialization and threshold voltage writing process for the first node N1 multiple times (e.g., three times) can reduce the hysteresis of the driving transistor and ensure the potential stability of the first node N1.

[0119] The second stage, S2, can be called the data writing stage. The signals on the first light-emitting signal line EM1, the second light-emitting signal line EM2, the first scan signal line GL1, the second scan signal line GL2, and the fourth scan signal line GL4 are all high-level signals, causing the fifth transistor T5, the sixth transistor T6, the first transistor T1, the ninth transistor T9, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 to all turn off. The signal on the third scan signal line GL3 is low-level, causing the fourth transistor T4 to turn on. The data voltage provided by the data signal line DL is written to the fifth node N5, and then written to the first node N1 through the first capacitor C1.

[0120] In the third stage S3, the signals of the first light-emitting signal line EM1, the second light-emitting signal line EM2, the first scan signal line GL1, the second scan signal line GL2, and the third scan signal line GL3 are high-level signals, causing the fifth transistor T5, the sixth transistor T6, the first transistor T1, the second transistor T2, the ninth transistor T9, and the fourth transistor T4 to all turn off.

[0121] The signal on the fourth scan signal line GL4 is at a low level, causing both the seventh transistor T7 and the eighth transistor T8 to conduct. With the seventh transistor T7 conducting, the second initial signal of the second initial signal line INIT2 can be written into the fourth node N4. By initializing the fourth node N4, residual signals from the previous frame can be prevented from affecting the display of the current frame. With the eighth transistor T8 conducting, the second reference signal of the second reference signal line REF2 can be written into the second node N2, which helps reduce the hysteresis of the driving transistors.

[0122] In the fourth stage (S4), the signals of the first light-emitting signal line EM1, the first scan signal line GL1, the second scan signal line GL2, the third scan signal line GL3, and the fourth scan signal line GL4 are all high-level signals, causing the fifth transistor T5, the first transistor T1, the second transistor T2, the ninth transistor T9, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 to all be turned off. The signal of the second light-emitting signal line EM2 is low-level, causing the sixth transistor T6 to conduct, connecting the third node N3 and the fourth node N4, making the potentials of the fourth node N4 and the third node N3 the same. By connecting the fourth node N4 and the third node N3, the potential of the fourth node N4 is increased, thereby reducing the time required to reach the turn-on voltage of the light-emitting device.

[0123] In the fifth stage S5, the signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are low-level signals, causing the fifth transistor T5 and the sixth transistor T6 to conduct. The first power supply signal of the first power supply line VDD can provide a driving signal to the light-emitting device EL through the conducting fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting device EL to emit light. The signals of the first scan signal line GL1, the second scan signal line GL2, the third scan signal line GL3, and the fourth scan signal line GL4 are high-level signals, causing the first transistor T1, the second transistor T2, the ninth transistor T9, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 to all turn off.

[0124] The pixel circuit in this example can improve the hysteresis of the driving transistor, which is beneficial to improving the display effect.

[0125] Figure 6 This is a schematic diagram of the planar structure of a display substrate according to at least one embodiment of the present disclosure. Figure 6 The diagram illustrates the structure of the pixel circuits in the three circuit units (i.e., the first circuit unit, the second circuit unit, and the third circuit unit) of the display substrate. Figure 7 for Figure 6 A partial cross-sectional view along the Q-Q' direction.

[0126] In some examples, the display substrate may include: a driving circuit layer disposed on the substrate and a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate. The driving circuit layer may include at least a plurality of circuit units, and the light-emitting structure layer may include at least a plurality of light-emitting units. At least one circuit unit may include a pixel circuit, and at least one light-emitting unit may include a light-emitting device. The light-emitting device may include at least an anode, an organic light-emitting layer, and a cathode, and the anode of the light-emitting device may be connected to the pixel circuit in the corresponding circuit unit.

[0127] In this disclosure, a circuit unit refers to a region divided according to pixel circuits; a light-emitting unit refers to a region divided according to light-emitting devices. In some examples, the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0128] In some examples, multiple circuit units arranged sequentially along a first direction X can be called a cell row, and multiple circuit units arranged sequentially along a second direction Y can be called a cell column. Multiple cell rows and multiple cell columns can constitute an array of circuit units. The first direction X and the second direction Y can intersect; for example, the first direction X can be perpendicular to the second direction Y.

[0129] In some examples, such as Figure 6 and Figure 7 As shown, in a direction perpendicular to the display substrate, the driving circuit layer may include: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the substrate 101. A first insulating layer 201 may be disposed between the semiconductor layer and the first conductive layer; a second insulating layer 202 may be disposed between the first and second conductive layers; a third insulating layer 203 may be disposed between the second and third conductive layers; and a fourth insulating layer 204 may be disposed between the third and fourth conductive layers. In some examples, the first insulating layer 201, the second insulating layer 202, and the third insulating layer 203 may be inorganic insulating layers, and the fourth insulating layer 204 may be an organic insulating layer. However, this embodiment is not limited to this. In other examples, a buffer layer may be disposed between the substrate and the semiconductor layer. In other examples, a passivation layer located on the side of the fourth insulating layer closer to the substrate may also be disposed between the third conductive layer and the fourth conductive layer.

[0130] In some examples, such as Figure 6 As shown, at least one pixel circuit may include a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light-emitting control transistor, a sixth transistor T6 as a second light-emitting control transistor, a seventh transistor T7 as a second initialization transistor, an eighth transistor T8 as a second reference transistor, a ninth transistor T9 as a first reference transistor, a first capacitor, and a second capacitor.

[0131] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern."

[0132] The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0133] In some examples, taking three circuit units (i.e., the first circuit unit, the second circuit unit, and the third circuit unit) in the nth unit row as an example, the fabrication process of the display substrate in this embodiment may include the following operations.

[0134] (1-1) Forming a semiconductor layer. In some examples, a semiconductor thin film is deposited on a substrate, and the semiconductor thin film is patterned using a patterning process to form a semiconductor layer, such as... Figure 8 As shown. Figure 8 for Figure 6 A schematic diagram of a display substrate after the semiconductor layer has been formed.

[0135] In some examples, the semiconductor layer of each circuit unit in the display substrate may include at least: a first active layer 11 of a first transistor T1, a second active layer 12 of a second transistor T2, a third active layer 13 of a third transistor T3, a fourth active layer 14 of a fourth transistor T4, a fifth active layer 15 of a fifth transistor T5, a sixth active layer 16 of a sixth transistor T6, a seventh active layer 17 of a seventh transistor T7, an eighth active layer 18 of an eighth transistor T8, and a ninth active layer 19 of a ninth transistor T9. The first active layers 11 to 13 and the fifth active layers 15 to 18 can be interconnected as a single structure, and the fourth active layer 14 and the ninth active layer 19 can also be interconnected as a single structure.

[0136] In some examples, the fourth active layer 14 and the ninth active layer 19 of the nth cell row can be located on the side of the third active layer 13 near the (n-1)th cell row, that is, the fourth active layer 14 and the ninth active layer 19 can be located on the side of the third active layer 13 of this circuit cell opposite to the second direction Y. The first active layer 11, the second active layer 12, and the fifth active layer 15 to the eighth active layer 18 of the nth cell row can be located on the side of the third active layer 13 near the (n+1)th cell row, that is, the first active layer 11, the second active layer 12, and the fifth active layer 15 to the eighth active layer 18 can be located on the side of the third active layer 13 of this circuit cell in the second direction Y.

[0137] In some examples, the first active layer 11 may be located on one side of the third active layer 13 of this circuit unit in the second direction Y; the fifth active layer 15 may be located on one side of the first active layer 11 of this circuit unit in the second direction Y; and the eighth active layer 18 may be located on one side of the fifth active layer 15 of this circuit unit in the second direction Y. The second active layer 12 may be located on one side of the third active layer 13 of this circuit unit in the second direction Y; the sixth active layer 16 may be located on one side of the second active layer 12 of this circuit unit in the second direction Y; and the seventh active layer 17 may be located on one side of the sixth active layer 16 of this circuit unit in the second direction Y.

[0138] In some examples, the first active layer 11, the fourth active layer 14, the fifth active layer 15 and the eighth active layer 18 may be located on one side of the circuit unit in the first direction X (e.g., the opposite side of the first direction X), and the second active layer 12, the sixth active layer 16, the seventh active layer 17 and the ninth active layer 19 may be located on the other side of the circuit unit in the first direction X (e.g., one side of the first direction X).

[0139] In some examples, the first active layer 11 and the second active layer 12 can be roughly L-shaped, the third active layer 13 can be roughly C-shaped, the fourth active layer 14 and the ninth active layer 19 can be roughly n-shaped, and the fifth active layer 15, the sixth active layer 16, the seventh active layer 17 and the eighth active layer 18 can be roughly I-shaped.

[0140] In some examples, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In some examples, the second region 112 of the first active layer 11 and the first region 121 of the second active layer 12 may be interconnected, and the second region 112 of the first active layer 11 may serve as the first region 121 of the second active layer 12. The first region 131 of the third active layer 13, the second region 152 of the fifth active layer 15, and the second region 182 of the eighth active layer 18 may be interconnected, and the first region 131 of the third active layer 13 may simultaneously serve as the second region 152 of the fifth active layer 15 and the second region 182 of the eighth active layer 18, constituting the second node N2 of the pixel circuit. The second region 122 of the second active layer 12, the second region 132 of the third active layer 13, and the first region 161 of the sixth active layer 16 can be interconnected. The second region 132 of the third active layer 13 can simultaneously serve as the second region 122 of the second active layer 12 and the first region 161 of the sixth active layer 16, forming the third node N3 of the pixel circuit. The second region 142 of the fourth active layer 14 and the second region 192 of the ninth active layer 19 can be interconnected. The second region 142 of the fourth active layer 14 can serve as the second region 192 of the ninth active layer 19. The second region 162 of the sixth active layer 16 and the second region 172 of the seventh active layer 17 can be interconnected. The second region 162 of the sixth active layer 16 can serve as the second region 172 of the seventh active layer 17, forming the fourth node N4 of the pixel circuit. The first region 111 of the first active layer 11, the first region 141 of the fourth active layer 14, the first region 151 of the fifth active layer 15, and the first region 181 of the eighth active layer 18 can be set independently. The first region 141 of the fourth active layer 14 can be located on the side of the channel region of the fourth active layer 14 near the third active layer 13, and the first region 191 of the ninth active layer 19 can be located on the side of the channel region of the ninth active layer 19 near the third active layer 13.

[0141] In some examples, in at least one cell row, the semiconductor layers in adjacent circuit cells in the first direction X can be interconnected. For example, the semiconductor layer of the first circuit cell in the nth cell row can be connected to the semiconductor layer of the second circuit cell in the nth cell row, and the semiconductor layer of the second circuit cell in the nth cell row can be connected to the semiconductor layer of the third circuit cell in the nth cell row. In the nth cell row, the semiconductor layers of adjacent circuit cells in the first direction X can be connected via a first active connection line 10 and a second active connection line 20. For example, the first region 191 of the ninth active layer 19 of the ninth transistor T9 in adjacent circuit cells in the first direction X can be interconnected via the first active connection line 10, and the first region 171 of the seventh active layer 17 of the seventh transistor T7 can be interconnected via the second active connection line 20. The first active connection line 10 and the second active connection line 20 can extend at least along the first direction X. The first active connection line 10 can be located on the side of the fourth active layer 14 near the third active layer 13, and the second active connection line 20 can be located on the side of the eighth active layer 18 away from the fifth active layer 15.

[0142] In some examples, the shape of the first active connection line 10 can be a zigzag line extending along the first direction X of the main body. The first active connection line 10 and the ninth active layer 19 of the plurality of circuit units can be an integral structure interconnected. Since the first region 191 of the ninth active layer 19 is connected to the subsequently formed first reference signal line, the first active connection line 10 can be multiplexed as a first reference signal line extending along the first direction X. This not only ensures that the first regions 191 of the plurality of ninth active layers 19 in a unit row have the same potential, but also reduces the voltage drop of the first reference signal, which is beneficial to improving the uniformity of the substrate, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0143] In some examples, the shape of the second active connection line 20 can be a straight line extending along the first direction X of the main body. The second active connection line 20 and the seventh active layer 17 of multiple circuit units can be an integral structure interconnected. Since the first region 171 of the seventh active layer 17 is connected to the subsequently formed second initial signal line, the second active connection line 20 can be multiplexed as a second initial signal line extending along the first direction X. This not only ensures that the first regions 171 of multiple seventh active layers 17 in a unit row have the same potential, but also reduces the voltage drop of the second initial signal, which is beneficial to improving the uniformity of the substrate, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0144] In some examples, a first groove K1 can be formed between the edges of two adjacent first active connection lines 10 in the first direction X and the edge of the first region 191 of the ninth active layer 19. The first groove K1 can be configured as a first protrusion to accommodate the second plate of the second capacitor, which helps to increase the installation space of the second capacitor.

[0145] In some examples, in at least one cell column, the semiconductor layers in adjacent circuit cells in the second direction Y can be spaced apart from each other. For example, the semiconductor layer of the first circuit cell in the (n-1)th cell row may not be connected to the semiconductor layer of the first circuit cell in the nth cell row, and the semiconductor layer of the first circuit cell in the nth cell row may not be connected to the semiconductor layer of the first circuit cell in the (n+1)th cell row.

[0146] (1-2) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate on which the aforementioned pattern is formed. The first conductive film is patterned using a patterning process to form a first insulating layer covering the semiconductor layer, and a first conductive layer disposed on the first insulating layer, such as... Figure 9A and Figure 9B As shown. Figure 9A for Figure 6 A schematic diagram of the display substrate after the first conductive layer has been formed. Figure 9B for Figure 9A A schematic diagram of the first conductive layer. In some examples, the first conductive layer may also be referred to as the first gate metal (GATE1) layer.

[0147] In some examples, the first conductive layer of each circuit unit in the display substrate may include at least: a first gate electrode 21 of a first transistor T1, a second gate electrode 22 of a second transistor T2, a fourth gate electrode 24 of a fourth transistor T4, a fifth gate electrode 25 of a fifth transistor T5, a sixth gate electrode 26 of a sixth transistor T6, a ninth gate electrode 29 of a ninth transistor T9, a fourth scan signal line 64, a first electrode 71 of a first capacitor, and a second electrode 72 of a second capacitor.

[0148] In some examples, the shape of the first gate electrode 21 can be approximately "L" shaped. The first gate electrode 21 can be located on one side of the first plate 71 of the first capacitor in the second direction Y. The area where the first gate electrode 21 overlaps with the first active layer can serve as the gate electrode of the first transistor T1 in the dual-gate structure.

[0149] In some examples, the second gate electrode 22 can be roughly T-shaped, and the second gate electrode 22 can be located on one side of the first plate 71 of the first capacitor in the second direction Y. The area where the second gate electrode 22 overlaps with the second active layer can serve as the gate electrode of the second transistor T2 in the dual-gate structure.

[0150] In some examples, the fourth gate electrode 24 can be roughly L-shaped. The fourth gate electrode 24 can be located on the side opposite to the second direction Y of the second plate 72 of the second capacitor. The region where the fourth gate electrode 24 overlaps with the fourth active layer can serve as the gate electrode of the fourth transistor T4 in the dual-gate structure.

[0151] In some examples, the fifth gate electrode 25 may be in the shape of a strip extending along the second direction Y. The fifth gate electrode 25 may be located on one side of the first gate electrode 21 in the second direction Y. The region where the fifth gate electrode 25 overlaps with the fifth active layer may serve as the gate electrode of the fifth transistor T5.

[0152] In some examples, the sixth gate electrode 26 may be in the shape of a strip extending along the first direction X. The sixth gate electrode 26 may be located on one side of the second gate electrode 22 in the second direction Y. The region where the sixth gate electrode 26 overlaps with the sixth active layer may serve as the gate electrode of the sixth transistor T6.

[0153] In some examples, the ninth gate electrode 29 can be roughly in the shape of a strip extending along the first direction X. The ninth gate electrode 29 can be located on the side of the second plate 72 of the second capacitor opposite to the second direction Y. The region where the ninth gate electrode 29 overlaps with the ninth active layer can serve as the gate electrode of the ninth transistor T9 of the dual-gate structure.

[0154] In some examples, the fourth scan signal line 64 can be a straight line extending along the first direction X of the main body, and the fourth scan signal line 64 can be located on one side of the fifth gate electrode 25 and the sixth gate electrode 26 in the second direction Y. The region where the fourth scan signal line 64 overlaps with the seventh active layer can serve as the gate electrode of the seventh transistor T7, and the region where the fourth scan signal line 64 overlaps with the eighth active layer can serve as the gate electrode of the eighth transistor T8.

[0155] In some examples, the first plate 71 of the first capacitor can be rectangular in shape, and the corners of the rectangle can be chamfered. The orthographic projection of the first plate 71 on the substrate and the orthographic projection of the third active layer of the third transistor T3 on the substrate can at least partially overlap. The first plate 71 can simultaneously serve as the lower plate of the first capacitor and the gate electrode of the third transistor T3.

[0156] In some examples, the second electrode 72 of the second capacitor can be rectangular in shape, with chamfered corners. The second electrode 72 can be located on the side opposite to the first electrode 71 in the second direction Y, and on the side of the fourth gate electrode 24 and the ninth gate electrode 29 in the second direction Y. That is, in the second direction Y, the second electrode 72 can be located between the first electrode 71 and the fourth gate electrode 24 (or the ninth gate electrode 29). The orthographic projection of the second electrode 72 onto the substrate and the orthographic projection of the semiconductor layer onto the substrate may not overlap. The second electrode 72 can serve as the lower electrode of the second capacitor. A first protrusion 72-1 is provided on the side of the second electrode 72 closest to the ninth gate electrode 29. The first protrusion 72-1 can be approximately rectangular in shape. The first end of the first protrusion 72-1 is connected to the second electrode 72, and the second end extends towards the ninth gate electrode 29 and into the first groove K1. The second electrode 72 and the first protrusion 72-1 can be an integrally connected structure.

[0157] In some examples, the first electrode 71 and the second electrode 72, located at their first side edges (e.g., the right edge) in the first direction X, can be approximately aligned in the second direction Y. Similarly, the first electrode 71 and the second electrode 72, located at their second side edges (e.g., the left edge) in the first direction X, can be approximately aligned in the second direction X. The first protrusion 72-1 and the second electrode 72, located at their first side edges (e.g., the right edge) in the first direction X, can be flush in the second direction Y. The integral structure formed by the interconnection of the second electrode 72 and the first protrusion 72-1 can be approximately L-shaped.

[0158] In some examples, the areas of the first electrode 71 and the second electrode 72 projected onto the substrate may be the same or different. For example, the area of ​​the second electrode 72 projected onto the substrate may be smaller than the area of ​​the first electrode 71 projected onto the substrate.

[0159] In some examples, after the first conductive layer pattern is formed, the first conductive layer can be used as a shield to conduct the semiconductor layer. The semiconductor layer in the region shielded by the first conductive layer forms the channel region of the first transistor T1 to the ninth transistor T9. The semiconductor layer in the region not shielded by the first conductive layer is conducted, that is, the first and second regions of the first active layer 11 to the ninth active layer 19, the first active connection line 10 and the second active connection line 20 can all be conducted.

[0160] (1-3) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate on which the aforementioned pattern is formed. The second conductive film is patterned using a patterning process to form a second insulating layer covering the first conductive layer, and a second conductive layer disposed on the second insulating layer, such as... Figure 10A and Figure 10B As shown. Figure 10A This is a schematic diagram of the display substrate after the second conductive layer has been formed, as shown in Figure 10. Figure 10B for Figure 10A A schematic diagram of the second conductive layer. In some examples, the second conductive layer may be referred to as the second gate metal (GATE2) layer.

[0161] In some examples, the second conductive layer of each circuit unit in the display substrate may include at least: a first light-emitting signal line 31, a second light-emitting signal line 32, a repair line 33, a second reference signal line 35, a first shielding electrode 36, a second shielding electrode 37, a third shielding electrode 38, a third electrode plate 73 of a first capacitor, and a fourth electrode plate 74 of a second capacitor.

[0162] In some examples, the shapes of the first light-emitting signal line 31, the second light-emitting signal line 32, the repair line 33, and the second reference signal line 35 can be straight lines extending along the first direction X of the main body. The first light-emitting signal line 31, the second light-emitting signal line 32, and the repair line 33 can be located between the first gate electrode 21 and the fourth scan signal line 64, and the second reference signal line 35 can be located on the side of the fourth gate electrode 24 opposite to the second direction Y.

[0163] In some examples, the first light-emitting signal line 31 may be located on one side of the first gate electrode 21 of the circuit unit in the second direction Y, the second light-emitting signal line 32 may be located on one side of the first light-emitting signal line 31 in the second direction Y, and the repair line 33 may be located on one side of the second light-emitting signal line 32 in the second direction Y, that is, the second light-emitting signal line 32 may be located between the first light-emitting signal line 31 and the repair line 33.

[0164] In some examples, a first light-emitting connector block 31-1 may be provided on the side of the first light-emitting signal line 31 near the second light-emitting signal line 32. The first light-emitting connector block 31-1 may be provided in each circuit unit. The first end of the first light-emitting connector block 31-1 is connected to the first light-emitting signal line 31, and the second end of the first light-emitting connector block 31-1 extends toward the second light-emitting signal line 32. The first light-emitting connector block 31-1 may be configured to be connected to the fifth gate electrode 25 through a subsequently formed seventh connection electrode. In some examples, the first light-emitting signal line 31 and the plurality of first light-emitting connector blocks 31-1 may be an integral structure interconnected with each other.

[0165] In some examples, a second light-emitting connector 32-1 may be provided on the side of the second light-emitting signal line 32 near the first light-emitting signal line 31. The second light-emitting connector 32-1 may be provided in each circuit unit. The first end of the second light-emitting connector 32-1 is connected to the second light-emitting signal line 32, and the second end of the second light-emitting connector 32-1 extends toward the first light-emitting signal line 31. The second light-emitting connector 32-1 may be configured to be connected to the sixth gate electrode 26 through a subsequently formed eighth connection electrode. In some examples, the second light-emitting signal line 32 and the plurality of second light-emitting connectors 32-1 may be an integral structure interconnected with each other.

[0166] In some examples, a second reference connection block 35-1 may be provided on the side of the second reference signal line 35 in the nth cell row away from the second electrode plate 72 of the nth cell row. The second reference connection block 35-1 may be provided in each circuit cell. The first end of the second reference connection block 35-1 is connected to the second reference signal line 35, and the second end of the second reference connection block 35-1 may extend away from the second electrode plate 72, that is, extend towards the (n-1)th cell row. In some examples, the second reference connection block 35-1 of the second reference signal line 35 in the nth cell row is configured to be connected to the first region of the eighth active layer in the (n-1)th cell row through a subsequently formed sixth connection electrode, providing a second reference signal to the first electrode of the eighth transistor T8 in the (n-1)th cell row. In some examples, the second reference signal line 35 and the plurality of second reference connection blocks 35-1 may be an integral structure interconnected with each other.

[0167] In some examples, the outline shape of the third plate 73 of the first capacitor can be rectangular, and the corners of the rectangle can be chamfered. The third plate 73 can be located between the first light-emitting signal line 31 and the second reference signal line 35 of this circuit unit. The orthographic projection of the third plate 73 on the substrate can at least partially overlap with the orthographic projection of the first plate 71 on the substrate. The third plate 73 can serve as the upper plate of the first capacitor (i.e., the second end of the first capacitor C1). The first plate 71 and the third plate 73 can constitute the first capacitor C1 of the pixel circuit.

[0168] In some examples, the outline shape of the fourth plate 74 of the second capacitor can be rectangular, and the corners of the rectangle can be chamfered. The fourth plate 74 can be located between the second reference signal line 35 and the third plate 73 of this circuit unit. The orthographic projection of the fourth plate 74 on the substrate can at least partially overlap with the orthographic projection of the second plate 72 on the substrate. The fourth plate 74 can serve as the upper plate of the second capacitor (i.e., the first end of the second capacitor C2). The second plate 72 and the fourth plate 74 can constitute the second capacitor C2 of the pixel circuit.

[0169] In some examples, the areas of the third electrode 73 and the fourth electrode 74 projected onto the substrate may be the same or different. For example, the area of ​​the fourth electrode 74 projected onto the substrate may be smaller than the area of ​​the third electrode 73 projected onto the substrate.

[0170] In some examples, the fourth electrode plate 74 may have a first electrode plate connecting line 74-1 on one side of the first direction X or on the opposite side of the first direction X. The first end of the first electrode plate connecting line 74-1 is connected to the fourth electrode plate 74 of this circuit unit, and the second end of the first electrode plate connecting line 74-1 extends along the first direction X or the opposite direction of the first direction X and connects to the fourth electrode plate 74 of an adjacent circuit unit, allowing the fourth electrode plates 74 of adjacent circuit units in a unit row to be interconnected. In some examples, multiple fourth electrode plates 74 and multiple first electrode plate connecting lines 74-1 can be an integrated structure interconnected. For example, the length of the first electrode plate connecting line 74-1 along the second direction Y can be approximately the same as the length of the fourth electrode plate 74 along the second direction Y. Since the fourth electrode plate 74 is connected to the first power line formed subsequently, the fourth electrode plate 74 of the integrated structure of multiple circuit units can be reused as a transverse power line extending along the first direction X. This not only ensures that multiple fourth electrode plates 74 in a unit row have the same potential, but also reduces the voltage drop of the first power signal, which is beneficial to improving the uniformity of the display substrate, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0171] In some examples, a first opening 730 may be provided on the third electrode plate 73 of each circuit unit. The first opening 730 may be located in the middle of the third electrode plate 73 and may be rectangular, so that the third electrode plate 73 forms a ring structure. The first opening 730 may expose a second insulating layer covering the first electrode plate 71, and the orthographic projection of the first electrode plate 71 on the substrate may include the orthographic projection of the first opening 730 on the substrate. In some examples, the first opening 730 may be configured to accommodate a subsequently formed tenth via. The tenth via may be located within the first opening 730 and expose a portion of the surface of the first electrode plate 71, so that a subsequently formed first connection electrode is connected to the first electrode plate 71.

[0172] In some examples, a second opening 740 may be provided on the fourth electrode plate 74 of each circuit unit. The second opening 740 may be located in the middle of the fourth electrode plate 74 and may be rectangular, forming a ring structure with the fourth electrode plate 74. The second opening 740 may expose a second insulating layer covering the second electrode plate 72, and the orthographic projection of the second electrode plate 72 onto the substrate may include the orthographic projection of the second opening 740 onto the substrate. In some examples, the second opening 740 may be configured to accommodate a subsequently formed eleventh via. The eleventh via may be located within the second opening 740 and expose a portion of the surface of the second electrode plate 72, allowing a subsequently formed third connection electrode to be connected to the second electrode plate 72. In some examples, the second opening 740 and the first opening 730 are not aligned in the second direction Y.

[0173] In some examples, a second protrusion 74-2 may be provided on the side of the fourth electrode plate 74 near the second reference signal line 35, and the second protrusion 74-2 may be provided in each circuit unit. The second protrusion 74-2 may be located on the side of the second opening 740 opposite to the second direction Y. The first end of the second protrusion 74-2 is connected to the fourth electrode plate 74, and the second end of the second protrusion 74-2 extends toward the direction of the second reference signal line 35. The orthographic projection of the second protrusion 74-2 onto the substrate may be located between the first region and the second region of the fourth active layer of this circuit unit. In this example, the second protrusion 74-2 may be configured to shield the influence of data voltage transitions on the fifth node, thereby preventing data voltage transitions from affecting the normal operation of the pixel circuit and improving the display effect. In some examples, the fourth electrode plate 74 and the second protrusion 74-2 may be an integral structure interconnected.

[0174] In some examples, a third protrusion 74-3 may be provided on the side of the fourth electrode plate 74 near the second reference signal line 35. The third protrusion 74-3 may be provided in each circuit unit. The second protrusion 74-2 and the third protrusion 74-3 may be adjacent in the first direction X. For example, the third protrusion 74-3 may be located on the side of the second protrusion 74-2 in the first direction X. The first end of the third protrusion 74-3 is connected to the fourth electrode plate 74, and the second end of the third protrusion 74-3 extends toward the second reference signal line 35 and extends into the first groove K1. The orthographic projection of the third protrusion 74-3 onto the substrate and the orthographic projection of the first protrusion 72-1 of the second electrode plate 72 onto the substrate may at least partially overlap, for example, they may coincide with each other. For example, the length of the second protrusion 74-2 along the second direction Y can be greater than the length of the third protrusion 74-3 along the second direction Y, and the length of the second protrusion 74-2 along the first direction X can be less than the length of the third protrusion 74-3 along the first direction X. In this example, by setting the third protrusion 74-3 to at least partially overlap with the first protrusion 74-1, the area of ​​the second capacitor can be increased, effectively increasing the total capacitance of the second capacitor, thereby improving the working performance of the pixel circuit and enhancing the display effect. In some examples, the fourth electrode plate 74 and the third protrusion 74-3 can be an integrally connected structure.

[0175] In some examples, the first shielding electrode 36 may be approximately T-shaped. The first shielding electrode 36 may be located on the side of the fourth electrode plate 74 near the first light-emitting signal line 31, and the first shielding electrode 36 may be disposed in each circuit unit. The T-shaped first shielding electrode 36 may include a first extension 36-1 and a first shielding section 36-2; the first end of the first extension 36-1 is connected to the fourth electrode plate 74, and the second end of the first extension 36-1 extends towards the first light-emitting signal line 31 and connects to the first shielding section 36-2. The first shielding section 36-2 may be a strip shape extending along the first direction X. The first shielding section 36-2 may include: a first shielding end located on the first extension 36-1 on the first direction X side and a second shielding end located on the first extension 36-1 on the opposite side of the first direction X. The orthographic projection of the first shielding terminal on the substrate at least partially overlaps with the orthographic projection of the first active layer on the substrate between the two gate electrodes of the first transistor T1 in this circuit unit. Similarly, the orthographic projection of the second shielding terminal on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate between the two gate electrodes of the second transistor T2 in the adjacent circuit unit. In some examples, the first shielding electrode 36 can be configured to shield the effects of data voltage transitions on the first transistor T1 and the second transistor T2, preventing data voltage transitions from affecting the normal operation of the pixel circuit and improving the display effect. In some examples, the fourth electrode plate 74 and the first shielding electrode 36 can be an integrally connected structure.

[0176] In some examples, the orthographic projection of the first shielding end of the first shielding segment 36-2 onto the substrate overlaps with the orthographic projection of the first region of the third active layer 13 of the third transistor in this circuit unit (which is also the second region of the fifth active layer and the second region of the eighth active layer) onto the substrate. Since the first region of the third active layer 13 (which is also the second region of the fifth active layer and the second region of the eighth active layer) is a conductive layer that has undergone conductor treatment, and the first shielding segment 36-2 is also a conductive layer, the first region of the third active layer 13 (which is also the second region of the fifth active layer and the second region of the eighth active layer) and the first shielding end of the first shielding segment 36-2 of the first shielding electrode 36 of this circuit unit can form a first voltage-stabilizing capacitor. Since the first shielding electrode 36 can subsequently be connected to the first power supply connection line to receive a constant voltage and stable first power supply signal, the first voltage-stabilizing capacitor can be configured to stabilize the potential of the second node N2, which can prevent signal crosstalk and avoid the influence of data voltage jumps on the second node N2, thereby ensuring the normal operation of the pixel circuit and improving the display effect.

[0177] In some examples, the orthographic projection of the second shielding end of the first shielding segment 36-2 onto the substrate overlaps with the orthographic projection of the second region of the third active layer 13 of the third transistor in the adjacent circuit unit (which is also the first region of the sixth active layer and the second region of the second active layer) onto the substrate. Since the second region of the third active layer 13 (which is also the first region of the sixth active layer and the second region of the second active layer) is a conductive layer that has undergone conductor treatment, and the first shielding segment 36-2 is also a conductive layer, the second region of the third active layer 13 (which is also the first region of the sixth active layer and the second region of the second active layer) within a circuit unit and the second shielding end of the first shielding segment 36-2 of the first shielding electrode 36 in the adjacent circuit unit can form a second voltage-stabilizing capacitor. Since the first shielding electrode 36 can subsequently be connected to the first power supply connection line to receive a constant-voltage, stable first power supply signal, the second voltage-stabilizing capacitor can be configured to stabilize the potential of the third node N3, preventing signal crosstalk and avoiding the impact of data voltage jumps on the third node N3, thereby ensuring the normal operation of the pixel circuit and improving the display effect.

[0178] In some examples, the second shielding electrode 37 and the third shielding electrode 38 may be rectangular in shape and located on the side of the second reference signal line 35 near the fourth electrode plate 74. The second shielding electrode 37 and the third shielding electrode 38 may be disposed in each circuit unit. The first ends of the second shielding electrode 37 and the third shielding electrode 38 are connected to the second reference signal line 35, and the second ends of the second shielding electrode 37 and the third shielding electrode 38 may extend towards the fourth electrode plate 74. The orthographic projection of the second shielding electrode 37 on the substrate may at least partially overlap with the orthographic projection of the fourth active layer between the two gate electrodes of the fourth transistor T4 in this circuit unit on the substrate. Similarly, the orthographic projection of the third shielding electrode 38 on the substrate may at least partially overlap with the orthographic projection of the ninth active layer between the two gate electrodes of the ninth transistor T9 in this circuit unit on the substrate. In some examples, the second shielding electrode 37 may be configured to shield the effect of data voltage transitions on the fourth transistor T4, and the third shielding electrode 38 may be configured to shield the effect of data voltage transitions on the ninth transistor T9, thereby preventing data voltage transitions from affecting the normal operation of the pixel circuit and improving the display effect.

[0179] In some examples, the repair line 33 may be located on the side of the second light-emitting control line 32 away from the first light-emitting control line 31. For example, the repair line 33 may be configured to input a signal to the anode of the sub-pixel with the bright spot defect when a bright spot defect occurs on the display substrate, thereby repairing it into a dark spot.

[0180] (1-4) Forming a third insulating layer. In some examples, a third insulating film is deposited on the substrate where the aforementioned pattern is formed. The third insulating film is patterned using a patterning process to form a third insulating layer. Each circuit unit has multiple vias in its third insulating layer, such as... Figure 11 As shown. Figure 11 for Figure 6 A schematic diagram of the display substrate after the third insulating layer has been formed.

[0181] In some examples, the plurality of vias in each circuit unit of the display substrate may include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, a nineteenth via V19, a twentieth via V20, a twenty-first via V21, and a twenty-second via V22.

[0182] In some examples, the orthographic projection of the first via V1 onto the substrate may be within the range of the orthographic projection of the first region of the first active layer onto the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the first via V1 may be etched away to expose a portion of the surface of the first region of the first active layer. The first via V1 may be configured to allow a subsequently formed first initial signal line to be connected to the first region of the first active layer through the via.

[0183] In some examples, the orthographic projection of the second via V2 onto the substrate may be within the range of the orthographic projection of the second region of the first active layer (which is also the first region of the second active layer) onto the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the second via V2 may be etched away to expose a portion of the surface of the second region of the first active layer (which is also the first region of the second active layer). The second via V2 may be configured to allow a subsequently formed first connection electrode to be connected to the second region of the first active layer (which is also the first region of the second active layer) through the via.

[0184] In some examples, the orthographic projection of the third via V3 onto the substrate may be within the range of the orthographic projection of the first region of the fourth active layer onto the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the third via V3 may be etched away to expose a portion of the surface of the first region of the fourth active layer. The third via V3 may be configured to allow a subsequently formed second connection electrode to be connected to the first region of the fourth active layer through the via.

[0185] In some examples, the orthographic projection of the fourth via V4 onto the substrate may lie within the orthographic projection of the second region of the fourth active layer (which is also the second region of the ninth active layer) onto the substrate. The third, second, and first insulating layers within the fourth via V4 may be etched away to expose a portion of the surface of the second region of the fourth active layer (which is also the second region of the ninth active layer). The fourth via V4 may be configured to allow a subsequently formed third connection electrode to be connected to the second region of the fourth active layer (which is also the second region of the ninth active layer) through the via.

[0186] In some examples, the orthographic projection of the fifth via V5 onto the substrate may be within the range of the orthographic projection of the first region of the fifth active layer onto the substrate. The third, second, and first insulating layers within the fifth via V5 may be etched away to expose a portion of the surface of the first region of the fifth active layer. The fifth via V5 may be configured to allow a subsequently formed fourth connection electrode to be connected to the first region of the fifth active layer through the via.

[0187] In some examples, the orthographic projection of the sixth via V6 onto the substrate may lie within the orthographic projection of the second region of the sixth active layer (which is also the second region of the seventh active layer) onto the substrate. The third, second, and first insulating layers within the sixth via V6 may be etched away to expose a portion of the surface of the second region of the sixth active layer (which is also the second region of the seventh active layer). The sixth via V6 may be configured to allow a subsequently formed fifth connection electrode to be connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the via.

[0188] In some examples, the orthographic projection of the seventh via V7 onto the substrate may be within the range of the orthographic projection of the first region of the seventh active layer onto the substrate. The third, second, and first insulating layers within the seventh via V7 may be etched away to expose a portion of the surface of the first region of the seventh active layer. The seventh via V7 may be configured to allow a subsequently formed second initial signal line to be connected to the first region of the seventh active layer through the via.

[0189] In some examples, the orthographic projection of the eighth via V8 onto the substrate may be within the range of the orthographic projection of the first region of the eighth active layer onto the substrate. The third, second, and first insulating layers within the eighth via V8 may be etched away to expose a portion of the surface of the first region of the eighth active layer. The eighth via V8 may be configured to allow a subsequently formed sixth connection electrode to be connected to the first region of the eighth active layer through the via.

[0190] In some examples, the orthographic projection of the ninth via V9 onto the substrate may be within the orthographic projection of the first region of the ninth active layer onto the substrate. The third, second, and first insulating layers within the ninth via V9 may be etched away to expose a portion of the surface of the first region of the ninth active layer. The ninth via V9 may be configured to allow a subsequently formed first reference signal line to be connected to the first region of the ninth active layer through the via.

[0191] In some examples, the orthographic projection of the tenth via V10 onto the substrate may be within the range of the orthographic projection of the first opening 730 of the third electrode plate 73 onto the substrate. The third and second insulating layers within the tenth via V10 may be etched away to expose a portion of the surface of the first electrode plate 71. The tenth via V10 may be configured to allow a subsequently formed first connection electrode to be connected to the first electrode plate 71 through the via.

[0192] In some examples, the orthographic projection of the eleventh via V11 onto the substrate may be within the range of the orthographic projection of the second opening 740 of the fourth electrode 74 onto the substrate. The third and second insulating layers within the eleventh via V11 may be etched away to expose a portion of the surface of the second electrode 72. The eleventh via V11 is configured to allow a subsequently formed third connection electrode to be connected to the second electrode 72 through the via.

[0193] In some examples, the orthographic projection of the twelfth via V12 onto the substrate may be within the range of the orthographic projection of the third electrode 73 onto the substrate. The third insulating layer within the twelfth via V12 may be etched away to expose a portion of the surface of the third electrode 73. The twelfth via V12 may be configured to allow a subsequently formed third connection electrode to be connected to the third electrode 73 through the via.

[0194] In some examples, the orthographic projection of the thirteenth via V13 onto the substrate may be within the range of the orthographic projection of the fourth electrode plate 74 onto the substrate. The third insulating layer within the thirteenth via V13 may be etched away to expose a portion of the surface of the fourth electrode plate 74. The thirteenth via V13 may be configured to allow a subsequently formed first power connection line to be connected to the fourth electrode plate 74 through the via.

[0195] In some examples, the orthographic projection of the fourteenth via V14 on the substrate may be within the range of the orthographic projection of the first gate electrode 21 on the substrate. The third and second insulating layers within the fourteenth via V14 may be etched away to expose a portion of the surface of the first gate electrode 21. The fourteenth via V14 may be configured to allow the subsequently formed first scan signal line to be connected to the first gate electrode 21 through the via.

[0196] In some examples, the orthographic projection of the fifteenth via V15 onto the substrate may be within the range of the orthographic projection of the second gate electrode 22 onto the substrate. The third and second insulating layers within the fifteenth via V15 may be etched away to expose a portion of the surface of the second gate electrode 22. The fifteenth via V15 may be configured to allow a subsequently formed second scan signal line to be connected to the second gate electrode 22 through the via.

[0197] In some examples, the orthographic projection of the sixteenth via V16 onto the substrate may be within the range of the orthographic projection of the fourth gate electrode 24 onto the substrate. The third and second insulating layers within the sixteenth via V16 may be etched away to expose a portion of the surface of the fourth gate electrode 24. The sixteenth via V16 may be configured to allow a subsequently formed third scan signal line to be connected to the fourth gate electrode 24 through the via.

[0198] In some examples, the orthographic projection of the seventeenth via V17 onto the substrate may be within the range of the orthographic projection of the fifth gate electrode 25 onto the substrate. The third and second insulating layers within the seventeenth via V17 may be etched away to expose a portion of the surface of the fifth gate electrode 25. The seventeenth via V17 may be configured to allow a subsequently formed seventh connection electrode to be connected to the fifth gate electrode 25 through the via.

[0199] In some examples, the orthographic projection of the eighteenth via V18 onto the substrate may be within the range of the orthographic projection of the sixth gate electrode 26 onto the substrate. The third and second insulating layers within the eighteenth via V18 may be etched away to expose a portion of the surface of the sixth gate electrode 26. The eighteenth via V18 may be configured to allow the subsequently formed eighth connection electrode to be connected to the sixth gate electrode 26 through the via.

[0200] In some examples, the orthographic projection of the nineteenth via V19 onto the substrate may be within the range of the orthographic projection of the ninth gate electrode 29 onto the substrate. The third and second insulating layers within the nineteenth via V19 may be etched away to expose a portion of the surface of the ninth gate electrode 29. The nineteenth via V19 may be configured to allow the subsequently formed fifth scan signal line to be connected to the ninth gate electrode 29 through the via.

[0201] In some examples, the orthographic projection of the twentieth via V20 onto the substrate may be within the range of the orthographic projection of the first light-emitting connector 31-1 onto the substrate of the first light-emitting signal line 31. The third insulating layer within the twentieth via V20 may be etched away, exposing at least a portion of the surface of the first light-emitting connector 31-1. The twentieth via V20 may be configured to allow a subsequently formed seventh connection electrode to be connected to the first light-emitting connector 31-1 through the via.

[0202] In some examples, the orthographic projection of the 21st via V21 onto the substrate may be within the range of the orthographic projection of the second light-emitting connector 32-1 onto the substrate of the second light-emitting signal line 32. The third insulating layer within the 21st via V21 may be etched away, exposing at least a portion of the surface of the second light-emitting connector 32-1. The 21st via V21 may be configured to allow the subsequently formed eighth connection electrode to be connected to the second light-emitting connector 32-1 through the via.

[0203] In some examples, the orthographic projection of the 22nd via V22 onto the substrate may be within the range of the orthographic projection of the second reference connection block 35-1 of the second reference signal line 35 onto the substrate. The third insulating layer within the 22nd via V22 is etched away, exposing the surface of the second reference connection block 35-1. The 22nd via V22 may be configured to allow the subsequently formed sixth connection electrode to be connected to the second reference connection block 35-1 through the via.

[0204] (1-5) Forming a third conductive layer. In some examples, a third conductive film is deposited on the substrate with the aforementioned pattern, and a patterning process is used to pattern the third conductive film to form a third conductive layer disposed on the third insulating layer, such as... Figure 12A and Figure 12B As shown. Figure 12A for Figure 6 A schematic diagram of the display substrate after the third conductive layer has been formed.

[0205] Figure 12B for Figure 12A A schematic diagram of the third conductive layer. In some examples, the third conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0206] In some examples, the third conductive layer of multiple circuit units in the display substrate may include: a first connecting electrode 41, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a fifth connecting electrode 45, a sixth connecting electrode 46, a seventh connecting electrode 47, an eighth connecting electrode 48, a first scan signal line 61, a second scan signal line 62, a third scan signal line 63, a fifth scan signal line 65, a first power connection line 66, a first initial signal line 81, a second initial signal line 82, and a first reference signal line 34.

[0207] In some examples, the shapes of the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, the fifth scan signal line 65, the first initial signal line 81, the second initial signal line 82, and the first reference signal line 34 can be straight lines extending along the first direction X of the main body. The shape of the first power connection line 66 can be a broken line extending along the first direction X of the main body. The third scan signal line 63, the fifth scan signal line 65, and the first reference signal line 34 can be located on the side of the fourth electrode plate 74 opposite to the second direction Y. The first scan signal line 61, the second scan signal line 62, the first initial signal line 81, and the second initial signal line 82 can be located on the side of the third electrode plate 73 in the second direction Y. The first power connection line 66 can be located in the area where the third electrode plate 73 is located.

[0208] In some examples, the first reference signal line 34 may be located on the side of the fourth electrode 74 opposite to the second direction Y, the fifth scan signal line 65 may be located on the side of the first reference signal line 34 opposite to the second direction Y, and the third scan signal line 63 may be located on the side of the fifth scan signal line 65 opposite to the second direction Y.

[0209] In some examples, the first scan signal line 61 may be located on one side of the third electrode plate 73 in the second direction Y, the first initial signal line 81 may be located on one side of the first scan signal line 61 in the second direction Y, the second scan signal line 62 may be located on one side of the first initial signal line 81 in the second direction Y, and the second initial signal line 82 may be located on one side of the second scan signal line 62 in the second direction Y. The first initial signal line 81 may be located between the first scan signal line 61 and the second scan signal line 62.

[0210] This example demonstrates how setting the first initial signal line 81 to be located in the third conductive layer can reduce its resistance and ensure effective transmission of the first initial signal. By positioning the first initial signal line 81 between the first scan signal line 61 and the second scan signal line 62, the distance between the first initial signal line 81 and the channel region of the first active layer of the first transistor T1 can be reduced. The first initial signal line 81 can then provide the first initial signal for initialization processing to the first transistor T1 via the shortest path, thereby reducing the length of the first region of the first active layer, decreasing the load on the first initial signal line, and optimizing the initialization effect.

[0211] This example sets the second scan signal line 62 and the first initial signal line 81 to be on the same layer, and the second scan signal line 62 is located on the side of the first initial signal line 81 away from the first scan signal line 61. This reduces the overlap capacitance between the second scan signal line 62 and the first initial signal line 81, reduces the load on the second scan signal line 62, and thus reduces the drive load on the scan driver connected to the second scan signal line 62.

[0212] In this example, the first light-emitting signal line 31 can be located on one side of the second scan signal line 62 and the first initial signal line 81 in the second direction Y, and the orthographic projection of the second light-emitting signal line 31, the second scan signal line 62 and the first initial signal line 81 on the substrate can not overlap, which can reduce the overlap capacitance between the first light-emitting signal line 31 and the first initial signal line 81, reduce the load of the first light-emitting signal line 31, and thus reduce the driving load of the light-emitting driver connected to the first light-emitting signal line 31.

[0213] In some examples, the first power connection line 66 may be located on the side of the fourth electrode plate 74 close to the third electrode plate 73. The orthographic projection of the first power connection line 66 on the substrate and the orthographic projection of the third electrode plate 73 on the substrate may partially overlap. The first power connection line 66 may be configured to connect with the first power line formed subsequently, forming a high-voltage power grid structure with a mesh-like interconnection structure on the display substrate.

[0214] In some examples, the fifth scan signal line 65 can be connected to the ninth gate electrode 29 in each circuit unit through the nineteenth via V19, thus enabling the fifth scan signal line 65 to connect to the ninth gate electrode 29 of the ninth transistor T9, and the fifth scan signal line 65 can control the conduction and disconnection of the ninth transistor T9.

[0215] In some examples, the second scan signal line 62 can be connected to the second gate electrode 22 in each circuit unit through the fifteenth via V15, thus realizing that the second scan signal line 62 is connected to the second gate electrode 22 of the second transistor T2, and the second scan signal line 62 can control the conduction and disconnection of the second transistor T2.

[0216] In some examples, the second scan signal line 62 and the fifth scan signal line 65 can extend to the bezel area and be connected to the same gate drive circuit to achieve the same scan signal output, that is, the second scan signal line 62 and the fifth scan signal line 65 output the same second scan signal.

[0217] In some examples, the first scan signal line 61 can be connected to the first gate electrode 21 in each circuit unit through the fourteenth via V14, thus realizing that the first scan signal line 61 is connected to the first gate electrode 21 of the first transistor T1, and the first scan signal line 61 can control the conduction and disconnection of the first transistor T1.

[0218] In some examples, the third scan signal line 63 can be connected to the fourth gate electrode 24 in each circuit unit through the sixteenth via V16, thus enabling the third scan signal line 63 to be connected to the fourth gate electrode 24 of the fourth transistor T4, and the third scan signal line 63 can control the conduction and disconnection of the fourth transistor T4.

[0219] In some examples, the first initial signal line 81 can be connected to the first region of the first active layer in each circuit unit through the first via V1, thereby enabling the first initial signal line 81 to be connected to the first pole of the first transistor T1, and the first initial signal line 81 can write the first initial signal into the first pole of the first transistor T1.

[0220] In some examples, the second initial signal line 82 can be connected to the first region of the seventh active layer in each circuit unit through the seventh via V7, thus enabling the second initial signal line 82 to connect to the first terminal of the seventh transistor T7, and the second initial signal line 82 can write the second initial signal to the first terminal of the seventh transistor T7.

[0221] In some examples, a second initial connection block 82-1 may be provided on the side of the second initial signal line 82 near the second scan signal line 62. The second initial connection block 82-1 may be located between two adjacent circuit units within at least one cell row. The first end of the second initial connection block 82-1 is connected to the second initial signal line 82, and the second end of the second initial connection block 82-1 extends toward the second scan signal line 62. The second initial connection block 82-1 may be configured to connect to subsequently formed initial signal connection lines.

[0222] In some examples, the first reference signal line 34 can be connected to the first region of the ninth active layer in each circuit unit through the ninth via V9, thus enabling the first reference signal line 34 to be connected to the first terminal of the ninth transistor T9, and the first reference signal line 34 can write the first reference signal into the first terminal of the ninth transistor T9.

[0223] In some examples, a first reference connection block 34-1 may be provided on the side of the first reference signal line 34 near the first power connection line 66. The first end of the first reference connection block 34-1 is connected to the first reference signal line 34, and the second end of the first reference connection block 34-1 extends toward the first power connection line 66. The first reference connection block 34-1 may be configured to connect to a reference signal connection line that is subsequently formed.

[0224] In some examples, the first power connection line 66 can be connected to the fourth plate 74 in each circuit unit through the thirteenth via V13, thus realizing the connection of the first power connection line 66 to the fourth plate 74. Since the first power connection line 66 is connected to the subsequently formed first power line, the first power connection line 66 can write the first power signal to the upper plate of the second capacitor (i.e., the first end of the second capacitor).

[0225] In some examples, a first power connection block 66-1 may be provided on the side of the first power connection line 66 away from the first scan signal line 61. The first end of the first power connection block 66-1 is connected to the first power connection line 66, and the second end of the first power connection block 66-1 extends away from the first scan signal line 61. In some examples, the first power connection block 66-1 may be configured to connect to the fourth electrode plate 74 through the thirteenth via V13, or it may be configured to connect to the subsequently formed first power line.

[0226] In some examples, the first connecting electrode 41 can be a strip shape extending along the second direction Y of the main body. The first connecting electrode 41 can be located between the first scan signal line 61 and the first power connection line 66. The first end of the first connecting electrode 41 can be connected to the second region of the first active layer (which is also the first region of the second active layer) through the second via V2, and the second end of the first connecting electrode 41 can be connected to the first electrode plate 71 through the tenth via V10. In some examples, the first connecting electrode 41 can make the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 71 of the first capacitor (i.e., the first end of the first capacitor) have the same potential. The first connecting electrode 41 can serve as the first node N1 of the pixel circuit.

[0227] In some examples, the second connection electrode 42 may be generally rectangular in shape and may be located between the first reference signal line 34 and the first power connection line 66. The second connection electrode 42 may be connected to the first region of the fourth active layer through the third via V3. In some examples, the second connection electrode 42 may serve as the first electrode of the fourth transistor T4 and may be configured to connect to subsequently formed data signal lines.

[0228] In some examples, the third connecting electrode 43 can be shaped like a broken line extending along the second direction Y of the main body. The third connecting electrode 43 can be located between the first reference signal line 34 and the first power connection line 66. The first end of the third connecting electrode 43 can be connected to the second region of the fourth active layer (also the second region of the ninth active layer) through the fourth via V4. The second end of the third connecting electrode 43 can be connected to the third electrode plate 73 through the twelfth via V12. The third end between the first and second ends can be connected to the second electrode plate 72 through the eleventh via V11. In some examples, the third connecting electrode 43 can make the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the third electrode plate 73 of the first capacitor (i.e., the second end of the first capacitor), and the second electrode plate 72 of the second capacitor (i.e., the second end of the second capacitor) have the same potential. The third connecting electrode 43 can serve as the fifth node N5 of the pixel circuit.

[0229] In some examples, the fourth connection electrode 44 may be generally rectangular in shape and may be located between the second scan signal line 62 and the second initial signal line 82. The fourth connection electrode 44 may be connected to the first region of the fifth active layer through the fifth via V5. In some examples, the fourth connection electrode 44 may serve as the first electrode of the fifth transistor T5 and may be configured to connect to the subsequently formed first power line.

[0230] In some examples, the fifth connection electrode 45 may be approximately L-shaped and may be located between the second scan signal line 62 and the second initial signal line 82. The fifth connection electrode 45 may be connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) via the sixth via V6. In some examples, the fifth connection electrode 45 may serve as the second electrode of both the sixth transistor T6 and the seventh transistor T7, configured to connect to the subsequently formed anode connection electrode.

[0231] In some examples, the sixth connection electrode 46 can be a strip shape extending along the first direction X of the main body. The sixth connection electrode 46 can be located between the second scan signal line 62 and the second initial signal line 82. The first end of the sixth connection electrode 46 can be connected to the first region of the eighth active layer through the eighth via V8, and the second end of the sixth connection electrode 46 can be connected to the second reference connection block 35-1 through the twenty-second via V22. In some examples, the sixth connection electrode 46 can serve as the first electrode of the eighth transistor T8. Since the second reference connection block 35-1 is connected to the second reference signal line 35, the second reference signal line 35 is connected to the first electrode of the eighth transistor T8. The second reference signal line 35 in the nth cell row can write the second reference signal to the first electrode of the eighth transistor T8 in the (n-1)th cell row.

[0232] In some examples, the seventh connecting electrode 47 can be a strip shape extending along the first direction X of the main body. The seventh connecting electrode 47 can be located between the second scan signal line 62 and the second initial signal line 82. The first end of the seventh connecting electrode 47 can be connected to the fifth gate electrode 25 through the seventeenth via V17, and the second end of the seventh connecting electrode 47 can be connected to the first light-emitting connecting block 31-1 through the twentieth via V20. Since the first light-emitting connecting block 31-1 is connected to the first light-emitting signal line 31, the first light-emitting signal line 31 is connected to the fifth gate electrode 25 of the fifth transistor T5, and the first light-emitting signal line 31 can control the conduction and disconnection of the fifth transistor T5.

[0233] In some examples, the eighth connecting electrode 48 can be a strip shape extending along the first direction X of the main body. The eighth connecting electrode 48 can be located between the second scan signal line 62 and the second initial signal line 82. The first end of the eighth connecting electrode 48 can be connected to the sixth gate electrode 26 through the eighteenth via V18, and the second end of the eighth connecting electrode 48 can be connected to the second light-emitting connecting block 32-1 through the twenty-first via V21. Since the second light-emitting connecting block 32-1 is connected to the second light-emitting signal line 32, the second light-emitting signal line 32 is connected to the sixth gate electrode 26 of the sixth transistor T6, and the second light-emitting signal line 32 can control the conduction and disconnection of the sixth transistor T6.

[0234] (1-6) Forming a fourth insulating layer. In some examples, a fourth insulating film is coated on the substrate with the aforementioned pattern, and a patterning process is used to pattern the fourth insulating film to form a fourth insulating layer covering the third conductive layer. The fourth insulating layer in each circuit unit may have multiple vias, such as... Figure 13 As shown. Figure 13 for Figure 6 A schematic diagram of the display substrate after the fourth insulating layer has been formed. In some examples, the fourth insulating layer may also be referred to as the first planarization layer.

[0235] In some examples, the plurality of vias for each circuit unit in the display substrate may include at least: via V31, via V32, via V33, via V34, and via V35.

[0236] In some examples, the orthographic projection of the 31st via V31 onto the substrate may be within the range of the orthographic projection of the second connection electrode 42 onto the substrate. The fourth insulating layer within the 31st via V31 may be removed, exposing a portion of the surface of the second connection electrode 42. The 31st via V31 may be configured to allow subsequently formed data signal lines to be connected to the second connection electrode 42 through the via.

[0237] In some examples, the orthographic projection of the 32nd via V32 onto the substrate may be within the range of the orthographic projection of the fourth connecting electrode 44 onto the substrate. The fourth insulating layer within the 32nd via V32 may be removed, exposing a portion of the surface of the fourth connecting electrode 44. The 32nd via V32 may be configured to allow a subsequently formed first power line to be connected to the fourth connecting electrode 44 through the via.

[0238] In some examples, the orthographic projection of the 33rd via V33 onto the substrate may be within the range of the orthographic projection of the fifth connecting electrode 45 onto the substrate. The fourth insulating layer within the 33rd via V33 may be removed, exposing a portion of the surface of the fifth connecting electrode 45. The 33rd via V33 may be configured to allow a subsequently formed anode connecting electrode to be connected to the fifth connecting electrode 45 through the via.

[0239] In some examples, the orthographic projection of the 34th via V34 onto the substrate may be within the range of the orthographic projection of the first reference connection block 34-1 onto the substrate. The fourth insulating layer within the 34th via V34 may be removed, exposing a portion of the surface of the first reference connection block 34-1. The 34th via V34 may be configured to allow subsequently formed reference signal connection lines to be connected to the first reference connection block 34-1 through the via.

[0240] In some examples, the orthographic projection of the 35th via V35 onto the substrate may be within the range of the orthographic projection of the first power connection block 66-1 onto the substrate. The fourth insulating layer within the 35th via V35 may be removed, exposing a portion of the surface of the first power connection block 66-1. The 35th via V35 may be configured to allow the subsequently formed first power line to be connected to the first power connection block 66-1 through the via.

[0241] In some examples, at least one circuit unit may also include a thirty-sixth via V36. The orthographic projection of the thirty-sixth via V36 onto the substrate may lie within the range of the orthographic projection of the second initial connection block 82-1 onto the substrate. The fourth insulating layer within the thirty-sixth via V36 is removed, exposing a portion of the surface of the second initial connection block 82-1. The thirty-sixth via V36 may be configured to allow subsequently formed initial signal connection lines to connect to the second initial connection block 82-1 through this via. In some examples, the thirty-sixth via V36 may be located between the first circuit unit and the second circuit unit.

[0242] (1-7) Forming the fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the fourth conductive film is patterned using a patterning process to form a fourth conductive layer disposed on the fourth insulating layer, such as... Figure 14 As shown. Figure 14 for Figure 6 A schematic diagram of the fourth conductive layer. In some examples, the fourth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0243] In some examples, the fourth conductive layer of multiple circuit units in the display substrate may include: a data signal line 51, a first power supply line 52, a reference signal connection line 53, and an anode connection electrode 55.

[0244] In some examples, the data signal line 51, the first power line 52, and the reference signal connection line 53 can be in the shape of a strip extending along the second direction Y. The first power line 52 can be located on one side of the data signal line 51 in the first direction X, and the reference signal connection line 53 can be located on one side of the first power line 52 in the first direction X, that is, the first power line 52 can be located between the data signal line 51 and the reference signal connection line 53.

[0245] In some examples, the data signal line 51 can be a straight line extending along the second direction Y, and the data signal line 51 can be connected to the second connection electrode 42 through the thirty-first via V31. Since the second connection electrode 42 can be connected to the first region of the fourth active layer through the via, the data signal line 51 writes the data signal to the first electrode of the fourth transistor T4.

[0246] In some examples, the first power line 52 can be shaped like a broken line extending along the second direction Y of the main body. The first power line 52 can be connected to the fourth connection electrode 44 via the thirty-second via V32, and to the first power connection block 66-1 via the thirty-fifth via V35. Since the fourth connection electrode 44 is connected to the first region of the fifth active layer via a via, the first power line 52 writes the first power signal to the first electrode of the fifth transistor T5. Since the first power connection block 66-1 is connected to the first power connection line 66, the first power connection line 66 extending along the first direction X of the main body and the first power line 52 extending along the second direction Y of the main body are interconnected. This forms a mesh structure on the display substrate for transmitting the first power signal, effectively reducing the resistance of the first power line 52 and decreasing the voltage drop of the first power signal. It also effectively improves the uniformity of the first power signal in the display substrate, thus improving display uniformity, display quality, and display performance.

[0247] In some examples, a power shielding block 52-1 is provided on the side of the first power line 52 near the reference signal connection line 53. The first end of the power shielding block 52-1 is connected to the first power line 52, and the second end extends towards the reference signal connection line 53. The power shielding block 52-1 can be approximately rectangular in shape, and its orthographic projection on the substrate can cover the orthographic projection of the first connecting electrode 41 on the substrate. Since the first connecting electrode 41 serves as the first node N1 in the pixel circuit, the constant-voltage power shielding block 52-1 can effectively shield the first node N1 from the influence of other signals in the pixel circuit, preventing other signals (such as data voltage jumps) from affecting the potential of the first node N1 in the pixel circuit, thus improving the display effect. In some examples, the first power line 52 and the power shielding block 52-1 can be an integrated structure interconnected.

[0248] In some examples, a second power connection block 52-2 is provided on the side of the first power line 52 near the reference signal connection 53. The second power connection block 52-2 may be located on the side of the power shield block 52-1 opposite to the second direction Y. The shape of the second power connection block 52-2 may be approximately rectangular, and the orthographic projection of the second power connection block 52-2 on the substrate may at least partially overlap with the orthographic projection of the fourth electrode plate 74 on the substrate. The second power connection block 52-2 may be connected to the first power connection block 66-1 through the thirty-fifth via V35, thereby connecting the first power line 52 and the first power connection line 66. The length of the second power connection block 52-2 along the second direction Y may be less than the length of the power shield block 52-1 along the second direction Y, and the length of the second power connection block 52-2 along the first direction Y may be approximately the same as the length of the power shield block 52-1 along the first direction X. This embodiment is not limited in this respect.

[0249] In some examples, the orthographic projection of the first power line 52 on the substrate and the orthographic projection of the third connecting electrode 43 on the substrate may at least partially overlap. For example, the orthographic projection of the first power line 52 on the substrate may cover the orthographic projection of the third connecting electrode 43 on the substrate. Since the third connecting electrode 43 serves as the fifth node N5 in the pixel circuit, the constant voltage of the first power line 52 can effectively shield the influence of other signals in the pixel circuit on the fifth node N5, preventing other signals from affecting the potential of the fifth node N5 of the pixel circuit and improving the display effect.

[0250] In some examples, the orthographic projection of the first power line 52 onto the substrate can cover the orthographic projection of the first region of the first active layer of the first transistor T1 onto the substrate. Specifically, the orthographic projection of the first power line 52 onto the substrate can cover the orthographic projection of the connection point between the first region of the first active layer of the first transistor T1 and the first initial signal line 81 onto the substrate. By setting the first power line 52 to shield the first region of the first active layer of the first transistor T1 connected to the first initial signal line 81, other signals can be prevented from affecting the reception of the first initial signal by the first region of the first active layer of the first transistor T1, thereby ensuring the accuracy of the first initial signal transmission and guaranteeing the initialization effect.

[0251] In some examples, the first power line 52 can be designed with non-uniform width. The non-uniform width design of the first power line 52 can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance between the first power line 52 and the data signal line 51.

[0252] In some examples, the reference signal connection line 53 can be a straight line extending along the second direction Y of the main body. The reference signal connection line 53 can be connected to the first reference connection block 34-1 through the thirty-fourth via V34. Since the first reference connection block 34-1 is connected to the first reference signal line 34, the first reference signal line 34 extending along the first direction X of the main body and the reference signal connection line 53 extending along the second direction Y of the main body are interconnected. This makes the first reference signal line 34 and the reference signal connection line 53 form a mesh structure on the display substrate for transmitting the first reference signal. This not only effectively reduces the resistance of the first reference signal line and reduces the voltage drop of the first reference signal, but also effectively improves the uniformity of the first reference signal in the display substrate, effectively improving display uniformity, display quality, and display performance.

[0253] In some examples, the anode connection electrode 55 can be generally rectangular in shape. The anode connection electrode 55 can be located between the first power line 52 and the reference signal connection line 53. The anode connection electrode 55 can be connected to the fifth connection electrode 45 via the thirty-third via V33. Since the fifth connection electrode 45 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) via the via, the anode connection electrode 55 is connected to the second terminals of the sixth transistor T6 and the seventh transistor T7. In some examples, the anode connection electrode 55 can be configured to connect to a subsequently formed anode, thus enabling pixel circuitry to drive the light-emitting device.

[0254] In some examples, the orthographic projection of the anode connection electrode 55 onto the substrate and the orthographic projection of the anode repair line 33 onto the substrate may at least partially overlap.

[0255] In some examples, at least one circuit unit may further include an initial signal connection line 54. The initial signal connection line 54 may be a straight line extending along the second direction Y of the main body portion. The initial signal connection line 54 can be connected to the second initial connection block 82-1 via the thirty-sixth via V36. Since the second initial connection block 82-1 is connected to the second initial signal line 82, the interconnection between the second initial signal line 82 extending along the first direction X of the main body portion and the initial signal connection line 54 extending along the second direction Y of the main body portion is achieved. This allows the initial signal connection line 54 and the second initial signal line 82 to form a mesh structure on the display substrate for transmitting the second initial signal. This not only effectively reduces the resistance of the second initial signal line 82 and decreases the voltage drop of the second initial signal, but also effectively improves the uniformity of the second initial signal in the display substrate, thereby improving display uniformity and display quality. In some examples, the initial signal connection line 54 may be located between the reference signal connection line 53 of the first circuit unit and the data signal line 51 of the second circuit unit.

[0256] In some examples, the first power connection line 66 of the third conductive layer can be arranged in each cell row, the first power line 52 of the fourth conductive layer can be arranged in each cell column, and multiple first power lines 52 can be connected to multiple first power connection lines 66 respectively to form a mesh structure for transmitting the first power signal.

[0257] In some examples, the first reference signal line 34 of the third conductive layer can be disposed in each cell row, and the reference signal connection line 53 of the fourth conductive layer can be disposed in each cell column. Multiple first reference signal lines 34 are respectively connected to multiple reference signal connection lines 53 to form a mesh structure for transmitting the first reference signal.

[0258] In some examples, the second initial signal line 82 of the third conductive layer can be set in each cell row, and the initial signal connection line 54 of the fourth conductive layer can be set every two cell columns. Multiple second initial signal lines 82 are connected to multiple initial signal connection lines 54 respectively to form a mesh structure for transmitting the second initial signal.

[0259] Subsequent fabrication processes may include forming a second planarization layer pattern, on which a plurality of anode vias are provided. The orthographic projection of the anode vias onto the substrate may be within the range of the orthographic projection of the anode connection electrode onto the substrate. The second planarization layer within the anode vias is removed to expose at least a portion of the surface of the anode connection electrode. The anode vias are configured to allow a subsequently formed anode to be connected to the anode connection electrode through the vias.

[0260] Thus, the driving circuit layer of this embodiment is fabricated on the substrate. In some exemplary embodiments, after the driving circuit layer is fabricated, a light-emitting structure layer and an encapsulation structure layer can be fabricated sequentially on the driving circuit layer, which will not be described in detail here.

[0261] In some examples, the substrate can be a flexible substrate or a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass and quartz, while the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In some examples, the flexible substrate can include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0262] In some examples, the first, second, third, and fourth conductive layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of these metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). These layers can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo or Ti / Al / Ti. For example, the first and second conductive layers can be made of a single layer of molybdenum metal, and the third and fourth conductive layers can be a three-layer Ti / Al / Ti stacked structure. The resistivity of the traces in the third and fourth conductive layers can be lower than the resistivity of the traces in the first and second conductive layers.

[0263] In some examples, the first insulating layer 201, the second insulating layer 202, and the third insulating layer 203 can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The first insulating layer 201 and the second insulating layer 202 can also be referred to as gate insulating (GI) layers, and the third insulating layer 203 can also be referred to as interlayer insulating (ILD) layers. The fourth insulating layer 204 can also be referred to as a first planarization layer. The fourth insulating layer 204 and the second planarization layer can be made of organic materials, such as polyimide, acrylic, or polyethylene terephthalate. The active layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, etc., meaning this disclosure applies to transistors manufactured based on oxide technology, silicon technology, or organic technology.

[0264] The structure and fabrication process of the display substrate in this embodiment are merely illustrative. In some examples, the structure can be modified and patterning processes can be added or reduced according to actual needs. The fabrication process in this example can be implemented using currently mature fabrication equipment, is well compatible with existing fabrication processes, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0265] Figure 15 This is a schematic diagram of the planar structure of another display substrate according to at least one embodiment of the present disclosure. Figure 15 The diagram illustrates the structure of the pixel circuits in three circuit units (i.e., the first circuit unit, the second circuit unit, and the third circuit unit) of the display substrate.

[0266] In some examples, a first power line 52 extending along the second direction Y is interconnected with a first power connection line 66 extending along the first direction X to form a mesh structure for transmitting a first power signal. A second power line 56 extending along the second direction Y is interconnected with a second power connection line 67 extending along the first direction X to form a mesh structure for transmitting a second power signal. A reference signal connection line 53 extending along the second direction Y is interconnected with a first reference signal line 34 extending along the first direction X to form a mesh structure for transmitting a first reference signal.

[0267] In some examples, a second plate connecting line 73-1 extending towards the fourth plate 74 of the second capacitor is provided on the third plate 73 of the first capacitor. A second groove K2 recessed away from the third plate 73 is provided on the fourth plate 74. The second plate connecting line 73-1 is disposed within the second groove K2, and the end of the second plate connecting line 73-1 away from the third plate 73 can be connected to the second plate 72 via a via and a connecting electrode. The plate structure design of the first and second capacitors in this example can increase the distance between the first node N1 and the fifth node N5, and also increase the space for lateral wiring.

[0268] In some examples, at least one circuit unit may further include a first shielding electrode 36. The first shielding electrode 36 may include a first shielding terminal and a second shielding terminal. The orthographic projection of the first shielding terminal onto the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes of the first transistor in this circuit unit onto the substrate, and the first shielding terminal is electrically connected to the first power line 52 connected to the pixel circuit of this circuit unit. The orthographic projection of the second shielding terminal onto the substrate at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes of the second transistor in an adjacent circuit unit onto the substrate, and the second shielding terminal is electrically connected to the first power line 52 connected to the pixel circuit of the adjacent circuit unit.

[0269] In some examples, the fabrication process of the display substrate in this example may include the following operations.

[0270] (2-1) Forming a semiconductor layer. In some examples, a semiconductor thin film is deposited on a substrate, and the semiconductor thin film is patterned using a patterning process to form a semiconductor layer, such as... Figure 16A As shown. Figure 16A for Figure 15 This is a schematic diagram of a display substrate after the first conductive layer has been formed. The semiconductor layer of the display substrate in this example has the same structure as the semiconductor layer of the display substrate in the aforementioned embodiment, and therefore will not be described again here.

[0271] (2-2) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate on which the aforementioned pattern is formed. The first conductive film is patterned using a patterning process to form a first insulating layer covering the semiconductor layer, and a first conductive layer disposed on the first insulating layer, such as... Figure 16A and Figure 16B As shown. Figure 16B for Figure 16A A schematic diagram of the first conductive layer.

[0272] In some examples, the first conductive layer of each circuit unit in the display substrate may include at least: a first gate electrode 21 of a first transistor T1, a second gate electrode 22 of a second transistor T2, a fourth gate electrode 24 of a fourth transistor T4, a fifth gate electrode 25 of a fifth transistor T5, a sixth gate electrode 26 of a sixth transistor T6, a ninth gate electrode 29 of a ninth transistor T9, a fourth scan signal line 64, a first electrode 71 of a first capacitor, and a second electrode 72 of a second capacitor.

[0273] In some examples, the second electrode 72 of the second capacitor 72 can be rectangular in shape, with chamfered corners. A first protrusion 72-1 can be provided on the side of the second electrode 72 near the ninth gate electrode 29. The first end of the first protrusion 72-1 is connected to the second electrode 72, and the second end extends towards the ninth gate electrode 29 and into the first groove formed in the semiconductor layer. The first electrode 71 and the second electrode 72 may be misaligned in the second direction Y at their first side edges (e.g., the right edge) in the first direction X. For example, the right edge of the second electrode 72 in the first direction X may be located on one side of the right edge of the first electrode 71 in the first direction X. Similarly, the first electrode 71 and the second electrode 72 may be misaligned at their second side edges (e.g., the left edge) in the first direction X. For example, the left edge of the second electrode 72 in the first direction X may be located on one side of the left edge of the first electrode 71 in the first direction X. The first protrusion 72-1 and the second electrode 72 may be misaligned in the second direction Y at the first side edge (e.g., the right side edge) in the first direction X. For example, the right side edge of the second electrode 72 in the first direction X may be located on the same side as the right side edge of the first protrusion 72-1 in the first direction X. The integral structure formed by the interconnection of the second electrode 72 and the first protrusion 72-1 can be approximately T-shaped.

[0274] The remaining structure of the first conductive layer of the display substrate in this example is substantially the same as that of the first conductive layer of the display substrate in the aforementioned embodiments, and therefore will not be described again here.

[0275] (2-3) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate on which the aforementioned pattern is formed. The second conductive film is patterned using a patterning process to form a second insulating layer covering the first conductive layer, and a second conductive layer disposed on the second insulating layer, such as... Figure 17A and Figure 17B As shown. Figure 17A for Figure 15 A schematic diagram of the display substrate after the second conductive layer has been formed. Figure 17B for Figure 17A A schematic diagram of the second conductive layer.

[0276] In some examples, the second conductive layer of each circuit unit in the display substrate may include at least: a first light-emitting signal line 31, a second light-emitting signal line 32, a repair line 33, a second reference signal line 35, a first shielding electrode 36, a second shielding electrode 37, a third shielding electrode 38, a third electrode plate 73 of a first capacitor, and a fourth electrode plate 74 of a second capacitor.

[0277] In some examples, the outline shape of the third plate 73 of the first capacitor can be rectangular, and the corners of the rectangle can be chamfered. The third plate 73 can be located between the second reference signal line 35 and the first shielding electrode 36 of this circuit unit. A second plate connection line 73-1 can be provided on the side of the third plate 73 near the fourth plate 74. The first end of the second plate connection line 73-1 is connected to the third plate 73, and the second end of the second plate connection line 73-1 extends in the direction of the second reference signal line 35. The second plate connection line 73-1 can be configured to be connected to the second region of the fourth active layer (which is also the second region of the ninth active layer) through a subsequently formed third connection electrode, so that the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, and the third plate 73 have the same potential.

[0278] In some examples, the fourth electrode plate 74 may have a first electrode plate connecting line 74-1 on one side of the first direction X or on the opposite side of the first direction X. The first end of the first electrode plate connecting line 74-1 is connected to the fourth electrode plate 74 of this circuit unit, and the second end of the first electrode plate connecting line 74-1 extends along the first direction X or the opposite direction of the first direction X and connects to the fourth electrode plate 74 of an adjacent circuit unit, thus connecting the fourth electrode plates 74 of adjacent circuit units in a unit row. In some examples, the length of the first electrode plate connecting line 74-1 along the second direction Y may be less than the length of the fourth electrode plate 74 along the second direction Y.

[0279] In some examples, a second groove K2 can be formed between the edges of two adjacent fourth plates 74 in the first direction X and the edge of the first plate connection line 74-1. The second groove K2 can be configured to accommodate the second plate connection line 73-1. The second plate connection line 73-1 on the third plate 73 extends in the second groove K2 toward the second reference signal line 35, which allows the subsequently formed twelfth via to be moved as high as possible and as close as possible to the second region of the fourth active layer (i.e., the second region of the ninth active layer). The twelfth via can be configured to allow the subsequently formed third connection electrode to be connected to the second plate connection line 73-1 through the via. The third connection electrode can be simultaneously connected to the second region of the fourth active layer (i.e., the second region of the ninth active layer) and the second plate 72 through the via, so that the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the second plate 72, and the third plate 73 have the same potential.

[0280] In some examples, the first shielding electrode 36 can be a strip extending along the first direction X, and the first shielding electrode 36 can be located on the side of the third electrode plate 73 near the first light-emitting signal line 31. The first shielding electrode 36 can be disposed in each circuit unit. The first shielding electrode 36 can include a first shielding end and a second shielding end. The orthographic projection of the first shielding end on the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes of the first transistor T1 in this circuit unit on the substrate, and the orthographic projection of the second shielding end on the substrate at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes of the second transistor T2 in the adjacent circuit unit on the substrate. In an exemplary embodiment, the first shielding electrode 36 can be configured to shield the influence of data voltage jumps on the first transistor T1 and the second transistor T2, avoiding data voltage jumps from affecting the normal operation of the pixel circuit and improving the display effect.

[0281] In some examples, the orthographic projection of the first shielding end of the first shielding electrode 36 onto the substrate overlaps with the orthographic projection of the first region of the third active layer 13 of the third transistor in this circuit unit (which is also the second region of the fifth active layer and the second region of the eighth active layer) onto the substrate. Since the first region of the third active layer 13 (which is also the second region of the fifth active layer and the second region of the eighth active layer) is a conductive layer that has undergone conductor treatment, and the first shielding electrode 36 is also a conductive layer, the first region of the third active layer 13 (which is also the second region of the fifth active layer and the second region of the eighth active layer) and the first shielding end of the first shielding electrode 36 in this circuit unit can form a first voltage-stabilizing capacitor. Since the first shielding electrode 36 can subsequently be connected to the first power supply connection line to receive a constant voltage and stable first power supply signal, the first voltage-stabilizing capacitor can be configured to stabilize the potential of the second node N2, which can prevent signal crosstalk and avoid the influence of data voltage jumps on the second node N2, thereby ensuring the normal operation of the pixel circuit and improving the display effect.

[0282] In some examples, the orthographic projection of the second shielding end of the first shielding electrode 36 onto the substrate overlaps with the orthographic projection of the second region of the third active layer 13 of the third transistor in the adjacent circuit unit (which is also the first region of the sixth active layer and the second region of the second active layer) onto the substrate. Since the second region of the third active layer 13 (which is also the first region of the sixth active layer and the second region of the second active layer) is a conductive layer that has undergone conductor treatment, and the first shielding electrode 36 is also a conductive layer, the second region of the third active layer 13 (which is also the first region of the sixth active layer and the second region of the second active layer) within a circuit unit and the second shielding end of the first shielding electrode 36 of the adjacent circuit unit can form a second voltage-stabilizing capacitor. Since the first shielding electrode 36 can subsequently be connected to the first power supply connection line to receive a constant-voltage, stable first power supply signal, the second voltage-stabilizing capacitor can be configured to stabilize the potential of the third node N3, preventing signal crosstalk and avoiding the impact of data voltage jumps on the third node N3, thereby ensuring the normal operation of the pixel circuit and improving the display effect.

[0283] In some examples, the fourth electrode 74 and the first shielding electrode 36 are spaced apart, meaning there may be no direct connection between them. Adjacent first shielding electrodes 36 may be spaced apart.

[0284] Compared to the previous embodiment, this example eliminates the integrated structure design where the fourth electrode plate 74 and the first shielding electrode 36 are interconnected. This reduces the parasitic capacitance between the second node N2 and the third node N3 and the first power signal, thus improving signal crosstalk. Furthermore, it allows for more flexible design of the shape of the fourth electrode plate 74 to increase the distance between the first node and the fifth node, thereby increasing the space available for lateral wiring.

[0285] The remaining structure of the second conductive layer of the display substrate in this example is substantially the same as that of the second conductive layer of the display substrate in the aforementioned embodiments, and therefore will not be described again here.

[0286] (2-4) Forming a third insulating layer. In some examples, a third insulating film is deposited on the substrate where the aforementioned pattern is formed. The third insulating film is patterned using a patterning process to form a third insulating layer. Each circuit unit has multiple vias in its third insulating layer, such as... Figure 18 As shown. Figure 18 for Figure 15 A schematic diagram of the display substrate after the third insulating layer has been formed.

[0287] In some examples, the plurality of vias in each circuit unit of the display substrate may include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, a nineteenth via V19, a twentieth via V20, a twenty-first via V21, a twenty-second via V22, a twenty-third via V23, a twenty-fourth via V24, and a twenty-fifth via V25.

[0288] In some examples, the orthographic projection of the 23rd via V23 onto the substrate may be within the range of the orthographic projection of the second electrode connection line 73-1 of the third electrode 73 onto the substrate. The third insulating layer within the 23rd via V23 may be etched away, exposing a portion of the surface of the second electrode connection line 73-1. The 23rd via V23 may be configured to allow the subsequently formed third connection electrode to be connected to the third electrode 73 through the via.

[0289] In some examples, the orthographic projection of the 24th via V24 onto the substrate may be within the range of the orthographic projection of the first shielding end of the first shielding electrode 36 of this circuit unit onto the substrate. The third insulating layer within the 24th via V24 may be etched away to expose a portion of the surface of the first shielding end of the first shielding electrode 36. The 24th via V24 may be configured to allow the subsequently formed ninth connection electrode to be connected to the first shielding electrode 36 of this circuit unit through the via.

[0290] In some examples, the orthographic projection of the 25th via V25 onto the substrate may be within the range of the orthographic projection of the second shielding end of the first shielding electrode 36 of the adjacent circuit unit onto the substrate. The third insulating layer within the 25th via V25 may be etched away to expose a portion of the surface of the second shielding end of the first shielding electrode 36 of the adjacent circuit unit. The 25th via V25 may be configured to allow the subsequently formed 10th connection electrode to be connected to the first shielding electrode 36 of the adjacent circuit unit through the via.

[0291] The remaining structure of the third insulating layer of the display substrate in this example is substantially the same as that of the third insulating layer of the display substrate in the aforementioned embodiments, and therefore will not be described again here.

[0292] (2-5) Forming a third conductive layer. In some examples, a third conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the third conductive film is patterned using a patterning process to form a third conductive layer disposed on the third insulating layer, such as... Figure 19A and Figure 19B As shown. Figure 19A for Figure 15 A schematic diagram of the display substrate after the third conductive layer has been formed. Figure 19B for Figure 19A A schematic diagram of the third conductive layer. In some examples, the third conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0293] In some examples, the third conductive layer of multiple circuit units in the display substrate may include: a first connecting electrode 41, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a fifth connecting electrode 45, a sixth connecting electrode 46, a seventh connecting electrode 47, an eighth connecting electrode 48, a ninth connecting electrode 49, a tenth connecting electrode 50, a first scan signal line 61, a second scan signal line 62, a third scan signal line 63, a fifth scan signal line 65, a first power connection line 66, a second power connection line 67, a first initial signal line 81, a second initial signal line 82, and a first reference signal line 34.

[0294] In some examples, the first power connection line 66 and the second power connection line 67 can be straight lines extending along a first direction X. The second power connection line 67 can be located on the side of the first power connection line 66 away from the fourth electrode plate 74. The first power connection line 66 can be located on the side of the fourth electrode plate 74 closer to the third electrode plate 73, and the orthographic projection of the first power connection line 66 on the substrate can partially overlap with the orthographic projection of the third electrode plate 73 on the substrate. The first power connection line 66 can be configured to connect with a subsequently formed first power line, forming a high-voltage power grid structure with a mesh-like interconnection structure on the display substrate. The orthographic projection of the second power connection line 67 on the substrate can partially overlap with the orthographic projection of the third electrode plate 73 on the substrate. The second power connection line 67 can be configured to connect with a subsequently formed second power line, forming a low-voltage power grid structure with a mesh-like interconnection structure on the display substrate. In this example, the fourth electrode plate 74 is connected to the first power connection line 66. By setting the second power connection line 67 to be located on the side of the first power connection line 66 away from the fourth electrode plate 74, it is not only beneficial to realize the connection wiring between the first power connection line 66 and the fourth electrode plate 74, but the first power connection line 66 can also shield the second power connection line 67 from interference to the second capacitor, so as to ensure the performance of the second capacitor.

[0295] In some examples, a first power connection block 66-1 can be provided on the side of the first power connection line 66 away from the second power connection line 67. The first end of the first power connection block 66-1 is connected to the first power connection line 66, and the second end of the first power connection block 66-1 extends away from the second power connection line 67. The extension direction of the first power connection block 66-1 can be approximately perpendicular to the extension direction of the first power connection line 66. The first power connection line 66 can be connected to the fourth electrode plate 74 in each circuit unit through the thirteenth via V13, thus realizing the connection of the first power connection line 66 to the fourth electrode plate 74.

[0296] In some examples, a third power connection block 67-1 may be provided on the side of the second power connection line 67 away from the first power connection line 66. The third power connection block 67-1 may be located between two adjacent circuit units within at least one cell row. A first end of the third power connection block 67-1 is connected to the second power connection line 67, and a second end of the second power connection block 67-1 extends away from the first power connection line 66. The second power connection block 67-1 may be configured to connect to a subsequently formed second power line.

[0297] In some examples, the third connection electrode 43 can be roughly V-shaped. The third connection electrode 43 can be located between the first reference signal line 34 and the first power connection line 66. The first end of the third connection electrode 43 can be connected to the second region of the fourth active layer (also the second region of the ninth active layer) through the fourth via V4, and the second end of the third connection electrode 43 can be connected to the second electrode connection line 73-1 of the third electrode 73 through the twenty-third via V23. The third end between the first and second ends can be connected to the second electrode 72 through the eleventh via V11. In some examples, the third connection electrode 43 can make the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the third electrode 73 of the first capacitor (i.e., the second terminal of the first capacitor), and the second electrode 72 of the second capacitor (i.e., the second terminal of the second capacitor) have the same potential. The third connection electrode 43 can serve as the fifth node N5 of the pixel circuit.

[0298] In some examples, the ninth connection electrode 49 may be generally rectangular in shape and may be located between the second power connection line 67 and the first scan signal line 61. The ninth connection electrode 49 may be connected to the first shielding electrode 36 of this circuit unit through the twenty-fourth via V24. The ninth connection electrode 49 may be configured to connect to the first power line of the pixel circuit of this circuit unit that is subsequently formed.

[0299] In some examples, the tenth connecting electrode 50 may be generally shaped as a strip extending along the second direction Y, and may be located between the second power connection line 67 and the first scan signal line 61. The tenth connecting electrode 50 may be connected to the first shielding electrode 36 of an adjacent circuit unit via a twenty-fifth via V25. The tenth connecting electrode 50 may be configured to connect to the first power line of the pixel circuitry of this circuit unit, which is subsequently formed.

[0300] The remaining structure of the third conductive layer of the display substrate in this example is substantially the same as that of the third conductive layer of the display substrate in the aforementioned embodiments, and therefore will not be described again here.

[0301] (2-6) Forming a fourth insulating layer. In some examples, a fourth insulating film is coated on the substrate with the aforementioned pattern, and a patterning process is used to pattern the fourth insulating film to form a fourth insulating layer covering the third conductive layer. The fourth insulating layer in each circuit unit may have multiple vias, such as... Figure 20 As shown. Figure 20 for Figure 15 A schematic diagram of the display substrate after the fourth insulating layer has been formed.

[0302] In some examples, the vias of each circuit unit in the display substrate may include at least: via V31 (thirty-first), via V32 (thirty-second), via V33 (thirty-third), via V34 (thirty-fourth), via V35 (thirty-fifth), via V38 (thirty-eighth), and via V39 (thirty-ninth).

[0303] In some examples, the orthographic projection of the 38th via V38 onto the substrate may be within the orthographic projection range of the 9th connecting electrode 49 onto the substrate. The fourth insulating layer within the 38th via V38 may be removed, exposing a portion of the surface of the 9th connecting electrode 49. The 38th via V38 may be configured to allow a subsequently formed first power line to be connected to the 9th connecting electrode 49 through the via.

[0304] In some examples, the orthographic projection of the 39th via V39 onto the substrate may be within the orthographic projection range of the 10th connecting electrode 50 onto the substrate. The fourth insulating layer within the 39th via V39 may be removed, exposing a portion of the surface of the 10th connecting electrode 50. The 39th via V39 may be configured to allow a subsequently formed first power line to be connected to the 10th connecting electrode 50 through the via.

[0305] In some examples, at least one circuit unit may also include a thirty-seventh via V37. The orthographic projection of the thirty-seventh via V37 onto the substrate may lie within the range of the orthographic projection of the third power connection block 67-1 of the second power connection line 67 onto the substrate. The fourth insulating layer within the thirty-seventh via V37 is removed, exposing a portion of the surface of the third power connection block 67-1. The thirty-seventh via V37 may be configured to allow a subsequently formed second power line to connect to the third power connection block 67-1 through this via. In some examples, the thirty-seventh via V37 may be located between the first circuit unit and the second circuit unit.

[0306] The remaining structure of the fourth insulating layer of the display substrate in this example is substantially the same as that of the fourth insulating layer of the display substrate in the aforementioned embodiment, and therefore will not be described again here.

[0307] (2-7) Forming the fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate with the aforementioned pattern, and a patterning process is used to pattern the fourth conductive film to form a fourth conductive layer disposed on the fourth insulating layer, such as... Figure 21 As shown. Figure 21 for Figure 15 A schematic diagram of the fourth conductive layer.

[0308] In some examples, the fourth conductive layer of multiple circuit units in the display substrate may include: a data signal line 51, a first power supply line 52, a reference signal connection line 53, and an anode connection electrode 55.

[0309] In some examples, the first power line 52 can be shaped like a broken line extending along the second direction Y. The first power line 52 can be connected to the fourth connecting electrode 44 via the thirty-second via V32, to the first power connection block 66-1 via the thirty-fifth via V35, to the ninth connecting electrode 49 via the thirty-eighth via V38, and to the tenth connecting electrode 50 via the thirty-ninth via V39. Since the fourth connecting electrode 44 is connected to the first region of the fifth active layer via a via, the first power line 52 writes the first power signal to the first electrode of the fifth transistor T5. Since the first power connection block 66-1 is connected to the first power connection line 66, the first power connection line 66 extending along the first direction X of the main body and the first power line 52 extending along the second direction Y of the main body are interconnected. This allows the first power line 52 and the first power connection line 66 to form a mesh structure on the display substrate for transmitting the first power signal. This not only effectively reduces the resistance of the first power line 52 and the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, thus improving display uniformity and display quality. Since the ninth connection electrode 49 is connected to the first shield electrode 36 of this circuit unit through a via, the first power line 52 provides the first power signal to the first shield electrode 36 of this circuit unit. Since the tenth connection electrode 50 is connected to the first shield electrode 36 of the adjacent circuit unit through a via, the first power line 52 connected to this circuit unit provides the first power signal to the first shield electrode 36 of the adjacent circuit unit.

[0310] In some examples, at least one circuit unit may further include a second power line 56. The second power line 56 may be a straight line extending along the second direction Y of the main body. The second power line 56 can be connected to the third power connection block 67-1 through the thirty-seventh via V37. Since the third power connection block 67-1 is connected to the second power connection line 67, the interconnection of the second power connection line 67 extending along the first direction X of the main body and the second power line 67 extending along the second direction Y of the main body is achieved. This allows the second power connection line 67 and the second power line 56 to form a mesh structure on the display substrate for transmitting the second power signal. This not only effectively reduces the resistance of the second power line 56 and decreases the voltage drop of the second power signal, but also effectively improves the uniformity of the second power signal in the display substrate, thereby improving display uniformity and display quality. In some examples, the second power line 56 may be located between the reference signal connection line 53 of the first circuit unit and the data signal line 51 of the second circuit unit.

[0311] In some examples, the second power connection line 67 of the third conductive layer can be set in each cell row, and the second power line 56 of the fourth conductive layer can be set every two cell columns. Multiple second power connection lines 67 can be connected to multiple second power lines 56 respectively to form a mesh structure for transmitting the second power signal.

[0312] The remaining structure of the fourth conductive layer of the display substrate in this example is substantially the same as that of the fourth conductive layer of the display substrate in the aforementioned embodiments, and therefore will not be described again here.

[0313] Thus, the driving circuit layer of this embodiment is fabricated on the substrate. In some exemplary embodiments, after the driving circuit layer is fabricated, a light-emitting structure layer and an encapsulation structure layer can be fabricated sequentially on the driving circuit layer, which will not be described in detail here.

[0314] This example, by positioning the first initial signal line between the first scan signal line and the second scan signal line, reduces the distance between the first initial signal line and the channel region of the first active layer of the first transistor. The first initial signal line can provide the first initial signal for initialization processing to the first transistor via the shortest path, which helps reduce the length of the first region of the first active layer, reduces the load on the first initial signal line, and optimizes the initialization effect. Furthermore, compared to the previous embodiment, this example's display substrate, by eliminating the integrated structure design of the fourth electrode plate 74 and the first shielding electrode 36, reduces the parasitic capacitance between the second node N2 and the third node N3 and the first power signal, improving signal crosstalk. Moreover, it allows for a more flexible design of the shape of the fourth electrode plate 74 to increase the distance between the first node and the fifth node, thereby increasing the space for lateral trace arrangement.

[0315] Figure 22 This is a schematic diagram of the planar structure of another display substrate according to at least one embodiment of the present disclosure. Figure 22 The diagram illustrates the structure of the pixel circuits in the three circuit units (i.e., the first circuit unit, the second circuit unit, and the third circuit unit) of the display substrate.

[0316] In some examples, the first light-emitting signal line 31 and the first initial signal line 81 can be on the same layer, for example, both located on the third conductive layer. This example not only reduces the resistance of the first light-emitting signal line 31, but also reduces the number of vias in the third insulating layer, optimizing wiring space.

[0317] In some examples, the second light-emitting signal line 32 and the first initial signal line 81 can be on the same layer, for example, both located on the third conductive layer. This example not only reduces the resistance of the second light-emitting signal line 32, but also reduces the number of vias in the third insulating layer, optimizing wiring space.

[0318] In some examples, the fabrication process of the display substrate in this example may include the following operations.

[0319] (3-1) Forming a semiconductor layer. In some examples, a semiconductor thin film is deposited on a substrate, and the semiconductor thin film is patterned using a patterning process to form a semiconductor layer, such as... Figure 23 As shown. Figure 23 for Figure 22 A schematic diagram of a display substrate after the formation of the first conductive layer. The semiconductor layer of this example display substrate is... Figure 6 The semiconductor layer structure of the display substrate in the illustrated embodiment is the same, so it will not be described again here.

[0320] (3-2) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate on which the aforementioned pattern is formed. The first conductive film is patterned using a patterning process to form a first insulating layer covering the semiconductor layer, and a first conductive layer disposed on the first insulating layer, such as... Figure 23 As shown. In this example, the first conductive layer of the display substrate is... Figure 6 The structure of the first conductive layer of the display substrate in the illustrated embodiment is the same, so it will not be described again here.

[0321] (3-3) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate on which the aforementioned pattern is formed. The second conductive film is patterned using a patterning process to form a second insulating layer covering the first conductive layer, and a second conductive layer disposed on the second insulating layer, such as... Figure 24A and Figure 24B As shown. Figure 24A for Figure 22 A schematic diagram of the display substrate after the second conductive layer has been formed. Figure 24B for Figure 24A A schematic diagram of the second conductive layer in the image.

[0322] In some examples, the second conductive layer of each circuit unit in the display substrate may include at least: a repair line 33, a second reference signal line 35, a first shielding electrode 36, a second shielding electrode 37, a third shielding electrode 38, a third electrode 73 of a first capacitor, and a fourth electrode 74 of a second capacitor.

[0323] The structural description of the second conductive layer of the display substrate in this example can be found in [reference needed]. Figure 6 The structure of the second conductive layer of the display substrate in the illustrated embodiment is described, and therefore will not be repeated here.

[0324] (3-4) Forming a third insulating layer. In some examples, a third insulating film is deposited on the substrate where the aforementioned pattern is formed. The third insulating film is patterned using a patterning process to form a third insulating layer. Each circuit unit has multiple vias in its third insulating layer, such as... Figure 25 As shown. Figure 25 for Figure 22 A schematic diagram of the display substrate after the third insulating layer has been formed.

[0325] In some examples, the plurality of vias in each circuit unit of the display substrate may include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, a nineteenth via V19, and a twenty-second via V22.

[0326] The structural description of the third insulating layer of the display substrate in this example can be found in [reference]. Figure 6 The structure of the third insulating layer of the display substrate in the illustrated embodiment is described, and therefore will not be repeated here.

[0327] (3-5) Forming a third conductive layer. In some examples, a third conductive film is deposited on the substrate with the aforementioned pattern, and a patterning process is used to pattern the third conductive film to form a third conductive layer disposed on the third insulating layer, such as... Figure 26A and Figure 26B As shown. Figure 26A for Figure 22 A schematic diagram of the display substrate after the third conductive layer has been formed. Figure 26B for Figure 26A A schematic diagram of the third conductive layer.

[0328] In some examples, the third conductive layer of multiple circuit units in the display substrate may include: a first connecting electrode 41, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a fifth connecting electrode 45, a sixth connecting electrode 46, a first scan signal line 61, a second scan signal line 62, a third scan signal line 63, a fifth scan signal line 65, a first power connection line 66, a first initial signal line 81, a second initial signal line 82, a first reference signal line 34, a first light emission signal line 31, and a second light emission signal line 32.

[0329] In some examples, the first light-emitting signal line 31 can be a straight line extending along the first direction X, and the second light-emitting signal line 32 can be a broken line extending along the first direction X. The first light-emitting signal line 31 can be located on one side of the second scan signal line 62 in the second direction Y, and the second light-emitting signal line 32 can be located on one side of the first light-emitting signal line 31 in the second direction Y. The first light-emitting signal line 31 can be located between the second scan signal line 62 and the second light-emitting signal line 32.

[0330] In some examples, the first light-emitting signal line 31 can be connected to the fifth gate electrode 25 in each circuit unit through the seventeenth via V17, thus realizing that the first light-emitting signal line 31 is connected to the fifth gate electrode 25 of the fifth transistor T5, and the first light-emitting signal line 31 can control the conduction and disconnection of the fifth transistor T5.

[0331] In some examples, the second light-emitting signal line 32 can be connected to the sixth gate electrode 26 in each circuit unit through the eighteenth via V18, thus realizing that the second light-emitting signal line 32 is connected to the sixth gate electrode 26 of the sixth transistor T6, and the second light-emitting signal line 32 can control the conduction and disconnection of the sixth transistor T6.

[0332] The remaining structural description of the third conductive layer of the display substrate in this example can be found in [reference]. Figure 6 The structure of the third conductive layer of the display substrate in the illustrated embodiment is described, and therefore will not be repeated here.

[0333] (3-6) Forming a fourth insulating layer. In some examples, a fourth insulating film is coated on the substrate with the aforementioned pattern, and a patterning process is used to pattern the fourth insulating film to form a fourth insulating layer covering the third conductive layer. The fourth insulating layer in each circuit unit may have multiple vias, such as... Figure 27 As shown. Figure 27 for Figure 22 A schematic diagram of the display substrate after the fourth insulating layer has been formed.

[0334] In some examples, the plurality of vias for each circuit unit in the display substrate may include at least: via V31, via V32, via V33, via V34, and via V35.

[0335] In some examples, at least one circuit unit may also include a thirty-sixth via V36. The orthographic projection of the thirty-sixth via V36 onto the substrate may lie within the range of the orthographic projection of the second initial connection block 82-1 onto the substrate. The fourth insulating layer within the thirty-sixth via V36 is removed, exposing a portion of the surface of the second initial connection block 82-1. The thirty-sixth via V36 may be configured to allow subsequently formed initial signal connection lines to connect to the second initial connection block 82-1 through this via. In some examples, the thirty-sixth via V36 may be located between the first circuit unit and the second circuit unit.

[0336] The remaining structural description of the fourth insulating layer of the display substrate in this example can be found in [reference]. Figure 6 The structure of the fourth insulating layer of the display substrate in the illustrated embodiment is described, and will not be repeated here.

[0337] (3-7) Forming the fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate with the aforementioned pattern, and a patterning process is used to pattern the fourth conductive film to form a fourth conductive layer disposed on the fourth insulating layer, such as... Figure 28 As shown. Figure 28 for Figure 22 A schematic diagram of the fourth conductive layer.

[0338] In some examples, the fourth conductive layer of multiple circuit units in the display substrate may include: a data signal line 51, a first power supply line 52, a reference signal connection line 53, and an anode connection electrode 55.

[0339] In some examples, at least one circuit unit may further include an initial signal connection line 54. The initial signal connection line 54 may be a straight line extending along the second direction Y of the main body portion. The initial signal connection line 54 can be connected to the second initial connection block 82-1 via the thirty-sixth via V36. Since the second initial connection block 82-1 is connected to the second initial signal line 82, the interconnection between the second initial signal line 82 extending along the first direction X of the main body portion and the initial signal connection line 54 extending along the second direction Y of the main body portion is achieved. This allows the initial signal connection line 54 and the second initial signal line 82 to form a mesh structure on the display substrate for transmitting the second initial signal. This not only effectively reduces the resistance of the second initial signal line 82 and decreases the voltage drop of the second initial signal, but also effectively improves the uniformity of the second initial signal in the display substrate, thereby improving display uniformity and display quality. In some examples, the initial signal connection line 54 may be located between the reference signal connection line 53 of the first circuit unit and the data signal line 51 of the second circuit unit.

[0340] The remaining structural description of the fourth conductive layer of the display substrate in this example can be found in [reference needed]. Figure 6 The structure of the fourth conductive layer of the display substrate in the illustrated embodiment is described, and therefore will not be repeated here.

[0341] Thus, the driving circuit layer of this embodiment is fabricated on the substrate. In some exemplary embodiments, after the driving circuit layer is fabricated, a light-emitting structure layer and an encapsulation structure layer can be fabricated sequentially on the driving circuit layer, which will not be described in detail here.

[0342] This example, by positioning the first initial signal line between the first scan signal line and the second scan signal line, reduces the distance between the first initial signal line and the channel region of the first active layer of the first transistor. The first initial signal line can then provide the first initial signal for initialization processing to the first transistor via the shortest path, which helps reduce the length of the first region of the first active layer, reduces the load on the first initial signal line, and optimizes the initialization effect. Furthermore, by placing the first light-emitting signal line 31 and the second light-emitting signal line 32 in the third conductive layer, this embodiment reduces the resistance of the first light-emitting signal line 31 and the second light-emitting signal line 32, and reduces the number of vias opened in the third insulating layer, thereby optimizing wiring space. In other examples, one of the first light-emitting signal line and the second light-emitting signal line can be placed in the third conductive layer.

[0343] In other examples, the structures of the display substrates in the above embodiments can be combined with each other, for example, Figure 15 In the display substrate shown, at least one of the first light-emitting signal line and the second light-emitting signal line may be disposed in the third conductive layer. This embodiment is not limited in this respect.

[0344] The display substrate provided in this embodiment optimizes the layout wiring and reduces the initialization path length of the first initial signal by setting the first initial signal line between the first scan signal line and the second scan signal line, which is beneficial to optimizing the initialization effect.

[0345] In this embodiment, the display substrate, by independently setting the fourth electrode plate of the second capacitor and the first shielding electrode, can reduce the parasitic capacitance between the second and third nodes and the first power signal, thereby improving signal crosstalk. Furthermore, it allows for flexible design of the fourth electrode plate shape to increase the distance between the first and fifth nodes, thus increasing the space available for lateral wiring.

[0346] The display substrate provided in this embodiment has a first power connection line extending along the first direction X and a first power line extending along the second direction Y in the main body. The first power line and the first power connection line are interconnected, so that the first power line and the first power connection line form a mesh structure on the display substrate to transmit the first power signal. This can not only effectively reduce the resistance of the first power line and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, thereby improving display uniformity and display quality.

[0347] The display substrate provided in this embodiment has a second power connection line extending along the first direction X and a second power line extending along the second direction Y in the main body. The second power line and the second power connection line are interconnected, so that the second power line and the second power connection line form a mesh structure on the display substrate for transmitting the second power signal. This can not only effectively reduce the resistance of the second power signal line and reduce the voltage drop of the second power signal, but also effectively improve the uniformity of the second power signal in the display substrate, thereby improving display uniformity, display quality and display performance.

[0348] The display substrate provided in this embodiment has a first reference signal line extending along the first direction X and a reference signal connection line extending along the second direction Y in the main body. The first reference signal line and the reference signal connection line are interconnected, so that the first reference signal line and the reference signal connection line form a mesh structure on the display substrate to transmit the first reference signal. This can not only effectively reduce the resistance of the first reference signal line and reduce the voltage drop of the first reference signal, but also effectively improve the uniformity of the first reference signal in the display substrate, thereby improving display uniformity, display quality and display performance.

[0349] The display substrate provided in this embodiment can shield the effects of data voltage jumps on the first transistor T1 and the second transistor T2 by setting a first shielding electrode, thereby avoiding the impact of data voltage jumps on the normal operation of the pixel circuit and improving the display effect.

[0350] The display substrate provided in this embodiment can shield the effects of data voltage jumps on the fourth transistor T4, the ninth transistor T9, and the fifth node N5 by setting a second shielding electrode and a third shielding electrode. Data voltage jumps affect the normal operation of the pixel circuit, thereby improving the display effect.

[0351] The display substrate provided in this embodiment can effectively shield the influence of other signals in the pixel circuit on the first node N1 by setting a power shielding block on the first power line, thereby avoiding other signals from affecting the potential of the first node N1 of the pixel circuit and improving the display effect.

[0352] The display substrate provided in this embodiment can prevent other signals from affecting the reception of the first initial signal by setting a first power line shield on the first region of the active layer of the first transistor connected to the first initial signal line, thereby ensuring the accuracy of the transmission of the first initial signal and ensuring the initialization effect.

[0353] The display substrate provided in this embodiment is configured such that the second power connection line is located on the side of the first power connection line away from the fourth electrode plate. This not only facilitates the connection and wiring between the first power connection line and the fourth electrode plate, but also allows the first power connection line to shield the second power connection line from interference with the second capacitor, thereby ensuring the performance of the second capacitor.

[0354] This embodiment also provides a method for preparing a display substrate to prepare the display substrate provided in the above embodiment.

[0355] In some exemplary embodiments, a method for fabricating a display substrate may include forming a driving circuit layer on a substrate. The driving circuit layer includes at least a plurality of circuit units, at least one of which includes a pixel circuit. The pixel circuit includes at least a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor. The gate electrode of the first transistor is electrically connected to a first scan signal line, the first terminal of the first transistor is electrically connected to a first initial signal line, and the second terminal of the first transistor is electrically connected to the gate electrode of the third transistor. The gate electrode of the second transistor is electrically connected to a second scan signal line, the first terminal of the second transistor is electrically connected to the gate electrode of the third transistor, and the second terminal of the second transistor is electrically connected to the second terminal of the third transistor. The gate electrode of the fourth transistor is electrically connected to a third scan signal line, the first terminal of the fourth transistor is electrically connected to a data signal line, and the second terminal of the fourth transistor is electrically connected to the second terminal of the first capacitor. The first terminal of the first capacitor is electrically connected to the gate electrode of the third transistor. The first initial signal line, the first scan signal line, and the second scan signal line extend in at least partially the same direction and are located on the same side of the first transistor. The first initial signal line is located between the first scan signal line and the second scan signal line.

[0356] The method for preparing the display substrate in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0357] This embodiment also provides a display substrate, including: a substrate and a driving circuit layer disposed on the substrate. The driving circuit layer includes at least a plurality of circuit units, at least one circuit unit including a pixel circuit, the pixel circuit including at least: a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor. The gate electrode of the first transistor is electrically connected to a first scan signal line, the first terminal of the first transistor is electrically connected to a first initial signal line, and the second terminal of the first transistor is electrically connected to the gate electrode of the third transistor; the gate electrode of the second transistor is electrically connected to a second scan signal line, the first terminal of the second transistor is electrically connected to the gate electrode of the third transistor, and the second terminal of the second transistor is electrically connected to the second terminal of the third transistor. The gate electrode of the fourth transistor is electrically connected to a third scan signal line, the first terminal of the fourth transistor is electrically connected to a data signal line, and the second terminal of the fourth transistor is electrically connected to the second terminal of the first capacitor; the first terminal of the first capacitor is electrically connected to the gate electrode of the third transistor. The second transistor is located on one side of the first transistor in a first direction, and the third and fourth transistors are located on the same side of the first and second transistors in a second direction, the first direction intersecting the second direction. The first initial signal line, the first scan signal line, and the second scan signal line all extend along the first direction and are located on the side of the first transistor away from the third transistor in the second direction. The first initial signal line is located between the first scan signal line and the second scan signal line.

[0358] In some exemplary embodiments, the orthographic projection of the first scan signal line onto the substrate overlaps with the orthographic projections of the gate electrode of the first transistor and the gate electrode of the second transistor onto the substrate.

[0359] In some exemplary embodiments, the pixel circuit further includes: a second capacitor; the second capacitor includes at least: a second electrode plate serving as a second terminal of the second capacitor and a fourth electrode plate serving as a first terminal of the second capacitor, wherein the orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate on the substrate. The first capacitor includes at least a first electrode plate serving as a first terminal of the first capacitor and a third electrode plate serving as a second terminal of the first capacitor, wherein the orthographic projection of the first electrode plate on the substrate at least partially overlaps with the orthographic projection of the third electrode plate on the substrate. The fourth electrode plate is connected to a first power line, the second electrode plate is connected to the third electrode plate, and the first electrode plate serves as the gate electrode of the third transistor.

[0360] In some exemplary embodiments, a second electrode connecting line extending toward the fourth electrode is provided on the third electrode plate, and a second groove recessed toward the direction away from the third electrode plate is provided on the fourth electrode plate; the second electrode connecting line is disposed in the second groove, and the end of the second electrode connecting line away from the third electrode plate is connected to the second electrode plate through a through hole and a connecting electrode.

[0361] In some exemplary embodiments, at least one circuit unit further includes: a first shielding electrode; the first shielding electrode includes: a first shielding terminal and a second shielding terminal; the orthographic projection of the first shielding terminal onto the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes of the first transistor in the circuit unit onto the substrate, and the first shielding terminal is electrically connected to a first power line. The orthographic projection of the second shielding terminal onto the substrate at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes of the second transistor in an adjacent circuit unit onto the substrate, and the second shielding terminal is electrically connected to the first power line.

[0362] In some exemplary embodiments, the pixel circuit further includes a fifth transistor and a sixth transistor. The gate electrode of the fifth transistor is electrically connected to a first light-emitting signal line, the first electrode of the fifth transistor is electrically connected to a first power supply line, and the second electrode of the fifth transistor is electrically connected to the first electrode of the third transistor. The gate electrode of the sixth transistor is electrically connected to a second light-emitting signal line, the first electrode of the sixth transistor is electrically connected to the second electrode of the third transistor, and the second electrode of the sixth transistor is electrically connected to a light-emitting device. The first light-emitting signal line is located on one side of the second scan signal line in a second direction, and the second light-emitting signal line is located on one side of the first light-emitting signal line in a second direction.

[0363] In some exemplary embodiments, the first light-emitting signal line, the second light-emitting signal line, and the first initial signal line are in the same layer.

[0364] The description of the display substrate in this example can be found in the description of the foregoing embodiments, and therefore will not be repeated here.

[0365] Figure 29 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some examples, such as... Figure 29 As shown, this embodiment provides a display device 91, including the display substrate 910 of the aforementioned embodiment. In some examples, the display substrate 910 may include an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device 91 can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. However, this embodiment is not limited thereto.

[0366] The accompanying drawings in this disclosure only illustrate the structures involved in this disclosure; other structures can be referred to with common design. Unless otherwise specified, the embodiments and features described in these embodiments can be combined to obtain new embodiments. Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this disclosure without departing from the spirit and scope of this disclosure, and all such modifications and substitutions should be covered within the scope of the claims of this disclosure.

Claims

1. A display substrate, comprising: The substrate and a driving circuit layer disposed on the substrate, the driving circuit layer comprising at least a plurality of circuit units, at least one of the plurality of circuit units comprising a pixel circuit, the pixel circuit comprising at least: a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor and a second capacitor; The gate electrode of the first transistor is electrically connected to the first scan signal line, the first terminal of the first transistor is electrically connected to the first initial signal line, and the second terminal of the first transistor is electrically connected to the gate electrode of the third transistor; the gate electrode of the second transistor is electrically connected to the second scan signal line, the first terminal of the second transistor is electrically connected to the gate electrode of the third transistor, and the second terminal of the second transistor is electrically connected to the second terminal of the third transistor; the gate electrode of the fourth transistor is electrically connected to the third scan signal line, the first terminal of the fourth transistor is electrically connected to the data signal line, and the second terminal of the fourth transistor is electrically connected to the second terminal of the first capacitor; the first terminal of the first capacitor is electrically connected to the gate electrode of the third transistor; the first capacitor includes at least a first plate as the first terminal of the first capacitor and a third plate as the second terminal of the first capacitor; the second capacitor includes at least a second plate as the second terminal of the second capacitor and a fourth plate as the first terminal of the second capacitor; the fourth plate is connected to the first power line, the second plate is connected to the third plate, and the first plate serves as the gate electrode of the third transistor; The third electrode plate is provided with a second electrode plate connecting line extending toward the fourth electrode plate, and the fourth electrode plate is provided with a second groove recessed away from the third electrode plate; the second electrode plate connecting line is disposed in the second groove, and the end of the second electrode plate connecting line away from the third electrode plate is connected to the second electrode plate through a through hole and a connecting electrode; The first initial signal line, the first scan signal line, and the second scan signal line extend in at least partially the same direction and are located on the same side of the first transistor, with the first initial signal line located between the first scan signal line and the second scan signal line.

2. The display substrate according to claim 1, wherein, The first initial signal line, the first scan signal line, and the second scan signal line are in the same layer.

3. The display substrate according to claim 1 or 2, wherein, The active layer of the first transistor includes a first region, a second region, and a channel region located between the first region and the second region. The first region of the active layer of the first transistor is connected to the first initial signal line. The driving circuit layer further includes: at least one first power line; the orthographic projection of the first power line onto the substrate covers the orthographic projection of the first region of the active layer of the first transistor onto the substrate.

4. The display substrate according to claim 1, wherein, The orthographic projection of the second electrode plate onto the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate onto the substrate; The orthographic projection of the first electrode plate onto the substrate at least partially overlaps with the orthographic projection of the third electrode plate onto the substrate.

5. The display substrate according to claim 4, wherein, The first electrode plate and the second electrode plate are of the same layer structure, and the third electrode plate and the fourth electrode plate are of the same layer structure.

6. The display substrate according to claim 1, wherein, The driving circuit layer further includes: at least one first power connection line extending along a first direction and at least one first power line extending along a second direction, wherein the first direction and the second direction intersect; the first power line and the first power connection line are connected to form a mesh structure for transmitting a first power signal.

7. The display substrate according to claim 6, wherein, The driving circuit layer further includes: at least one second power connection line extending along a first direction and at least one second power line extending along a second direction, wherein the first direction and the second direction intersect; the second power line and the second power connection line are connected to form a mesh structure for transmitting a second power signal; the second power connection line is located on the side of the first power connection line away from the second capacitor.

8. The display substrate according to claim 7, wherein, The first power connection line and the second power connection line are in the same layer, and the first power line and the second power line are in the same layer. The first power line is located on the side of the first power connection line away from the substrate.

9. The display substrate according to any one of claims 4 to 8, wherein, The first capacitor and the second capacitor are located on the same side of the first transistor and the second transistor, the second capacitor is located on the side of the first capacitor away from the first transistor and the second transistor, and the orthographic projection of the third transistor on the substrate at least partially overlaps with the orthographic projection of the first capacitor on the substrate.

10. The display substrate according to any one of claims 4 to 8, wherein, The fourth plate of the second capacitor of the pixel circuit of the adjacent circuit unit along the first direction is an integral structure that is interconnected.

11. The display substrate according to any one of claims 4 to 8, wherein, The at least one circuit unit further includes: a first shielding electrode, wherein the orthographic projection of the first shielding electrode on the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes of the first transistor in the circuit unit on the substrate, and also at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes of the second transistor in the adjacent circuit unit on the substrate.

12. The display substrate according to claim 11, wherein, The first shielding electrode includes: a first shielding end and a second shielding end; the orthographic projection of the first shielding end on the substrate and the orthographic projection of the first active layer between the two gate electrodes of the first transistor in this circuit unit on the substrate at least partially overlap; the first shielding end is electrically connected to the first power line. The second shielding terminal's orthographic projection on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate between the two gate electrodes of the second transistor in the adjacent circuit unit, and the second shielding terminal is electrically connected to the first power line.

13. The display substrate according to claim 11, wherein, The first shielding electrode and the fourth plate of the second capacitor are an integral structure that are interconnected.

14. The display substrate according to any one of claims 4 to 8, wherein, The pixel circuit further includes: a fifth transistor, the gate electrode of which is electrically connected to the first light-emitting signal line, the first electrode of which is electrically connected to the first power supply line, and the second electrode of which is electrically connected to the first electrode of the third transistor; the first light-emitting signal line is located on the side of the second scan signal line away from the first initial signal line.

15. The display substrate according to claim 14, wherein, The film layer containing the first light-emitting signal line is located on the side of the film layer containing the first initial signal line closer to the substrate; or, the first light-emitting signal line and the first initial signal line are in the same layer.

16. The display substrate according to claim 14, wherein, The pixel circuit further includes: a sixth transistor, the gate electrode of the sixth transistor being electrically connected to the second light-emitting signal line, the first electrode of the sixth transistor being electrically connected to the second electrode of the third transistor, and the second electrode of the sixth transistor being electrically connected to the light-emitting device; The second light-emitting signal line is located on the side of the first light-emitting signal line that is away from the first initial signal line; The second light-emitting signal line and the first light-emitting signal line are in the same layer.

17. The display substrate according to any one of claims 4 to 8, wherein, The pixel circuit further includes: a ninth transistor; the gate electrode of the ninth transistor is electrically connected to the fifth scan signal line, the first electrode of the ninth transistor is electrically connected to the first reference signal line, and the second electrode of the ninth transistor is electrically connected to the second plate of the second capacitor and the third plate of the first capacitor; the fifth scan signal line and the second scan signal line output the same scan signal; The fourth transistor and the ninth transistor are located on the side of the second capacitor away from the first capacitor; The active layer of the fourth transistor and the active layer of the ninth transistor are an integral structure that are interconnected.

18. The display substrate according to claim 17, wherein, The active layers of at least two adjacent ninth transistors along the first direction are connected into a single structure by a first active interconnect line.

19. The display substrate according to any one of claims 4 to 8, wherein, The pixel circuit further includes a seventh transistor and an eighth transistor; the gate electrode of the seventh transistor is electrically connected to the fourth scan signal line, the first electrode of the seventh transistor is electrically connected to the second initial signal line, and the second electrode of the seventh transistor is electrically connected to the light-emitting device. The gate electrode of the eighth transistor is electrically connected to the fourth scan signal line, the first electrode of the eighth transistor is electrically connected to the second reference signal line, and the second electrode of the eighth transistor is electrically connected to the first electrode of the third transistor.

20. The display substrate according to any one of claims 4 to 8, wherein, In a direction perpendicular to the display substrate, the driving circuit layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially disposed on the substrate; The active layers of the first transistor, the second transistor, and the third transistor are located in the semiconductor layer; The gate electrodes of the first transistor, the second transistor, and the third transistor, the first electrode plate, and the second electrode plate are located in the first conductive layer; The third electrode plate and the fourth electrode plate are located in the second conductive layer; The first initial signal line, the first scan signal line, and the second scan signal line are located in the third conductive layer.

21. A display device comprising a display substrate as claimed in any one of claims 1 to 20.

22. A method for preparing a display substrate, comprising: A driving circuit layer is formed on a substrate; wherein the driving circuit layer includes at least a plurality of circuit units, at least one of the plurality of circuit units including a pixel circuit; the pixel circuit includes at least: a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor; the gate electrode of the first transistor is electrically connected to a first scan signal line, the first terminal of the first transistor is electrically connected to a first initial signal line, and the second terminal of the first transistor is electrically connected to the gate electrode of the third transistor; the gate electrode of the second transistor is electrically connected to a second scan signal line, the first terminal of the second transistor is electrically connected to the gate electrode of the third transistor, and the second terminal of the second transistor is electrically connected to the second terminal of the third transistor; the gate electrode of the fourth transistor is electrically connected to a third scan signal line, the first terminal of the fourth transistor is electrically connected to a data signal line, and the second terminal of the fourth transistor is electrically connected to the second terminal of the first capacitor; the first terminal of the first capacitor is electrically connected to the gate electrode of the third transistor; The first capacitor includes at least a first plate as a first terminal of the first capacitor and a third plate as a second terminal of the first capacitor. The second capacitor includes at least a second plate as a second terminal of the second capacitor and a fourth plate as a first terminal of the second capacitor. The fourth plate is connected to a first power line, the second plate is connected to the third plate, and the first plate serves as the gate electrode of the third transistor. The third electrode plate is provided with a second electrode plate connecting line extending toward the fourth electrode plate, and the fourth electrode plate is provided with a second groove recessed away from the third electrode plate; the second electrode plate connecting line is disposed in the second groove, and the end of the second electrode plate connecting line away from the third electrode plate is connected to the second electrode plate through a through hole and a connecting electrode; The first initial signal line, the first scan signal line, and the second scan signal line extend in at least partially the same direction and are located on the same side of the first transistor, with the first initial signal line located between the first scan signal line and the second scan signal line.

23. A display substrate, comprising: The substrate and a driving circuit layer disposed on the substrate, the driving circuit layer comprising at least a plurality of circuit units, at least one of the plurality of circuit units comprising a pixel circuit, the pixel circuit comprising at least: a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor and a second capacitor; The gate electrode of the first transistor is electrically connected to the first scan signal line, the first terminal of the first transistor is electrically connected to the first initial signal line, and the second terminal of the first transistor is electrically connected to the gate electrode of the third transistor; the gate electrode of the second transistor is electrically connected to the second scan signal line, the first terminal of the second transistor is electrically connected to the gate electrode of the third transistor, and the second terminal of the second transistor is electrically connected to the second terminal of the third transistor; the gate electrode of the fourth transistor is electrically connected to the third scan signal line, the first terminal of the fourth transistor is electrically connected to the data signal line, and the second terminal of the fourth transistor is electrically connected to the second terminal of the first capacitor; the first terminal of the first capacitor is electrically connected to the gate electrode of the third transistor. The second transistor is located on one side of the first transistor in a first direction, and the third transistor and the fourth transistor are located on the same side of the first transistor and the second transistor in a second direction, with the first direction intersecting the second direction; The first capacitor includes at least a first plate as a first terminal of the first capacitor and a third plate as a second terminal of the first capacitor. The second capacitor includes at least a second plate as a second terminal of the second capacitor and a fourth plate as a first terminal of the second capacitor. The fourth plate is connected to a first power line, the second plate is connected to the third plate, and the first plate serves as the gate electrode of the third transistor. The third electrode plate is provided with a second electrode plate connecting line extending toward the fourth electrode plate, and the fourth electrode plate is provided with a second groove recessed away from the third electrode plate; the second electrode plate connecting line is disposed in the second groove, and the end of the second electrode plate connecting line away from the third electrode plate is connected to the second electrode plate through a through hole and a connecting electrode; The first initial signal line, the first scan signal line, and the second scan signal line all extend along the first direction and are located on the side of the first transistor away from the third transistor in the second direction; The first initial signal line is located between the first scan signal line and the second scan signal line.

24. The display substrate according to claim 23, wherein, The orthographic projection of the first scan signal line onto the substrate overlaps with the orthographic projection portions of the gate electrode of the first transistor and the gate electrode of the second transistor onto the substrate.

25. The display substrate according to claim 23, wherein, The orthographic projection of the second electrode plate onto the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate onto the substrate; The orthographic projection of the first electrode plate onto the substrate at least partially overlaps with the orthographic projection of the third electrode plate onto the substrate.

26. The display substrate according to any one of claims 23 to 25, wherein, The at least one circuit unit further includes: a first shielding electrode; the first shielding electrode includes: a first shielding end and a second shielding end; the orthographic projection of the first shielding end on the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes of the first transistor in the circuit unit on the substrate; The orthographic projection of the second shielding terminal on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate between the two gate electrodes of the second transistor in the adjacent circuit unit, and both the first shielding terminal and the second shielding terminal are electrically connected to the first power line.

27. The display substrate according to any one of claims 23 to 25, wherein, The pixel circuit also includes: a fifth transistor and a sixth transistor; The gate electrode of the fifth transistor is electrically connected to the first light-emitting signal line, the first electrode of the fifth transistor is electrically connected to the first power supply line, and the second electrode of the fifth transistor is electrically connected to the first electrode of the third transistor. The gate electrode of the sixth transistor is electrically connected to the second light-emitting signal line, the first electrode of the sixth transistor is electrically connected to the second electrode of the third transistor, and the second electrode of the sixth transistor is electrically connected to the light-emitting device. The first light-emitting signal line is located on one side of the second scanning signal line in the second direction, and the second light-emitting signal line is located on one side of the first light-emitting signal line in the second direction.

28. The display substrate according to claim 27, wherein, The first light-emitting signal line, the second light-emitting signal line, and the first initial signal line are in the same layer.

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