Memory computing integrated circuit and electronic device

Abstract

Embodiments of the present disclosure provide a memory-computing integrated circuit and an electronic device. The memory-computing integrated circuit includes a memristor array, a digital-to-analog conversion circuit, a bit line computing module, a source line computing module, and a control module. The control module is configured to control the operation of the memristor array, the digital-to-analog conversion circuit, the bit line computing module, and the source line computing module based on a computing mode of the memory-computing integrated circuit, the computing mode including a forward computing mode and a back propagation mode. The bit line computing module and the source line computing module in the memory-computing integrated circuit are used in both the forward computing mode and the back propagation mode, thereby avoiding circuit redundancy, improving the area utilization efficiency of the memory-computing integrated circuit, and enhancing the weight and computing power density.

Description

Technical Field

[0001] Embodiments of this disclosure relate to an in-memory computing circuit and electronic device. Background Technology

[0002] In-memory computing (IMC) technology integrates storage and computation at the underlying level, significantly reducing latency and power consumption caused by data migration. It also enables high-parallelism analog computation using memristor arrays. IMC technology focuses on accelerating forward inference in neural networks. However, due to some non-ideal characteristics, the on-chip inference accuracy based on IMC limits the deployment and implementation of neural networks. Updating the mapped weights through on-chip backpropagation training allows the weights to adapt to some hardware non-ideal characteristics, thereby improving the accuracy of on-chip forward inference. Therefore, IMC hardware used for forward inference operations in neural networks needs to also have backpropagation computation capabilities. Summary of the Invention

[0003] This disclosure provides at least one embodiment of an in-memory computing circuit, including: a memristor array, a digital-to-analog converter circuit, a bit-line computing module, a source-line computing module, and a control module. The control module is configured to control the operation of the memristor array, the digital-to-analog converter circuit, the bit-line computing module, and the source-line computing module based on a computing mode of the in-memory computing circuit. The computing mode includes a forward computing mode and a backward propagation mode. In the forward computing mode, the digital-to-analog converter circuit converts received first data to obtain a first input voltage provided to the bit-line computing module, and the bit-line computing module provides input voltage to the memristor array. The first input voltage is received, so that the memristor array generates a first load current after performing a first calculation using the first input voltage, and the source line calculation module quantizes the first load current; and in the back propagation mode, the digital-to-analog converter circuit converts the received second data to obtain a second input voltage provided to the source line calculation module, the source line calculation module provides the received second input voltage to the memristor array, so that the memristor array generates a second load current after performing a second calculation using the second input voltage, and the bit line calculation module quantizes the second load current.

[0004] For example, in at least one embodiment of the in-memory computing circuit provided in this disclosure, the memristor array includes multiple source lines, multiple bit lines, and multiple array-arranged weighted units. The bit line calculation module is coupled to the multiple bit lines of the memristor array and is further configured to clamp the voltage of the multiple bit lines to a first clamping reference voltage in the reverse propagation mode. The source line calculation module is coupled to the multiple source lines of the memristor array and is further configured to clamp the voltage of the multiple source lines to a second clamping reference voltage in the forward calculation mode.

[0005] For example, in at least one embodiment of the in-memory computing circuit provided in this disclosure, the bitline computing module includes: a plurality of bitline driving / clamping circuits and a first analog-to-digital converter, wherein the plurality of bitline driving / clamping circuits are respectively coupled to the plurality of bitlines, and each bitline driving / clamping circuit is configured to provide the first input voltage to the corresponding bitline in the forward computing mode, or, in the reverse propagation mode, clamp the voltage of the corresponding bitline to the first clamping reference voltage and generate a second load voltage based on the second load current on the corresponding bitline; the first analog-to-digital converter is coupled to the plurality of bitline driving / clamping circuits and is configured to sequentially quantize the second load voltage generated by the plurality of bitline driving / clamping circuits in the reverse propagation mode and output a second quantization result.

[0006] For example, in at least one embodiment of the in-memory computing circuit provided in this disclosure, the first analog-to-digital converter is a current-type or voltage-type converter.

[0007] For example, in at least one embodiment of the in-memory computing circuit provided in this disclosure, the bit line drive / clamp circuit is configured based on a gain amplifier or a flip voltage follower.

[0008] For example, in at least one embodiment of the in-memory computing circuit provided in this disclosure, the source line computing module includes multiple source line drive / clamping circuits and a second analog-to-digital converter. The multiple source line drive / clamping circuits are respectively coupled to the multiple source lines. Each source line drive / clamping circuit is configured to, in the forward computing mode, clamp the voltage of the corresponding source line to the second clamping reference voltage and generate a first load voltage based on the first load current on the corresponding source line, or, in the reverse propagation mode, provide the second input voltage to the corresponding source line. The second analog-to-digital converter is coupled to the multiple source line drive / clamping circuits and is configured to, in the forward computing mode, sequentially quantize the first load voltage generated by the multiple source line drive / clamping circuits and output a first quantization result.

[0009] For example, in at least one embodiment of the in-memory computing circuit provided in this disclosure, the source line drive / clamping circuit includes a differential amplifier and a transistor. The output terminal of the differential amplifier is coupled to the control terminal of the transistor. In the forward computing mode, the first input terminal of the differential amplifier is clamped to the second clamping reference voltage, and the second input terminal of the differential amplifier receives the first load current. Alternatively, in the reverse propagation mode, the first input terminal of the differential amplifier receives the second input voltage, and the second input terminal of the differential amplifier provides the second input voltage to the corresponding source line.

[0010] For example, in at least one embodiment of the in-memory computing circuit provided in this disclosure, the second analog-to-digital converter includes a comparator, a logic control circuit (SAR), and a current generation unit (IDAC). The comparator is configured to compare a first load voltage and a reference voltage (V_REF). The logic control circuit is coupled to the comparator and the current generation unit and is configured to control the current generation unit to generate a first current based on the comparison result of the comparator, so as to adjust the first load current on the corresponding source line.

[0011] For example, in at least one embodiment of the in-memory computing circuit provided in this disclosure, the logic control circuit is further configured to output the first quantization result based on the comparison result of the comparator.

[0012] At least one embodiment of this disclosure also provides an electronic device, the padding device including the in-memory computing circuit described in any embodiment of this disclosure. Attached Figure Description

[0013] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0014] Figure 1 A schematic diagram of an in-memory computing circuit for implementing forward computation and backward propagation is shown.

[0015] Figure 2 A schematic diagram of a memory computing circuit provided in at least one embodiment of the present disclosure is shown;

[0016] Figure 3A A schematic diagram of a memory computing circuit provided in at least one embodiment of the present disclosure in forward computing mode is shown;

[0017] Figure 3B A schematic diagram of a memory computing circuit provided in at least one embodiment of the present disclosure in backpropagation mode is shown;

[0018] Figure 4AThe connection relationship between the weight unit and the peripheral circuit of the 1T1R structure provided in at least one embodiment of the present disclosure in forward computation mode is shown;

[0019] Figure 4B The connection relationship between the weight unit of the 1T1R structure provided in at least one embodiment of this disclosure and the peripheral circuit is shown in backpropagation mode;

[0020] Figure 4C The connection relationship between the weight unit and the peripheral circuit of the 2T2R structure provided in at least one embodiment of the present disclosure in forward computation mode is shown;

[0021] Figure 4D The connection relationship between the weight unit of the 2T2R structure provided in at least one embodiment of this disclosure and the peripheral circuit is shown in backpropagation mode;

[0022] Figure 5 This diagram illustrates the structure of a time-bit line calculation module using 1T1R weighted units provided in at least one embodiment of the present disclosure.

[0023] Figure 6 This diagram illustrates the structure of a bitline calculation module employing 2T2R weight units, provided in at least one embodiment of this disclosure.

[0024] Figure 7A and Figure 7B A schematic diagram of the structure of a bitline calculation module based on a gain amplifier and a current-mode analog-to-digital converter provided in at least one embodiment of the present disclosure is shown.

[0025] Figure 7C It shows Figure 7A and Figure 7B The diagram shown illustrates an analog-to-digital converter multiplexed with multiple bit line drive / clamp circuits.

[0026] Figure 8A and Figure 8B This diagram illustrates the structure of a bitline calculation module based on a gain amplifier and a voltage-mode analog-to-digital converter, according to at least one embodiment of the present disclosure.

[0027] Figure 8C It shows Figure 8A and Figure 8B The diagram shown illustrates an analog-to-digital converter multiplexed with multiple bit line drive / clamp circuits.

[0028] Figure 9A and 9B A schematic diagram of a bit line drive / clamp circuit based on a source follower configuration provided in at least one embodiment of this disclosure is shown;

[0029] Figure 10A and Figure 10BA schematic diagram of a bit line drive / clamp circuit based on a common-gate follower configuration provided in at least one embodiment of this disclosure is shown;

[0030] Figure 11A and Figure 11B This diagram illustrates the structure of a bitline calculation module based on a common-gate follower configuration according to at least one embodiment of the present disclosure;

[0031] Figure 12A and Figure 12B This illustration shows a schematic diagram of the source-line computing module provided in at least one embodiment of the present disclosure in forward computing and backward propagation modes; and

[0032] Figure 13 A schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure is shown. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0034] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0035] In-memory computing (IMC) technology integrates storage and computation at the underlying level, significantly reducing latency and power consumption caused by data migration. It also enables high-parallelism analog computation using IMC arrays (hereinafter referred to as "memristor arrays"). IMC technology focuses on accelerating forward inference in neural networks. However, due to some non-ideal characteristics, the on-chip inference accuracy based on IMC limits the deployment and implementation of neural networks. Updating the mapped weights through on-chip backpropagation training allows the weights to adapt to some hardware non-ideal characteristics, thereby improving the accuracy of on-chip forward inference. Therefore, IMC hardware used for neural network forward inference needs to also have backpropagation computation capabilities.

[0036] Because in-memory computing arrays based on resistive switching memory can adapt to bidirectional computation, including forward and backward propagation, in-memory computing circuits supporting bidirectional computation can be designed based on these arrays. However, these in-memory computing circuits often require two independent sets of input and output circuits, one for forward computation and the other for backward propagation. In forward or backward propagation mode, only half of the circuit modules are operational, resulting in low area efficiency and impacting the weighting and computational density of the in-memory computing circuit.

[0037] For example, Figure 1 A schematic diagram of a memory computing circuit for implementing forward computation and backward propagation is shown.

[0038] like Figure 1 As shown, this in-memory computing circuit requires two independent input and readout circuits. In forward computation mode, the forward digital-to-analog converter (i.e., the "forward DAC") 110 applies a voltage representing the input data to the bit line BL of the memristor array 150, and the forward readout circuit 120 clamps the source line SL of the memristor array 150 and quantizes the current on the source line SL to obtain the calculation result. Simultaneously, the reverse digital-to-analog converter (i.e., the "reverse DAC") 130 and the reverse readout circuit 140 are disconnected from the memristor array 150. In reverse propagation mode, the reverse digital-to-analog converter 130 applies a voltage representing the input data to the source line SL of the memristor array 150, and the reverse readout circuit 140 clamps the bit line BL of the memristor array 150 and quantizes the current on the bit line BL to obtain the result. Simultaneously, the forward digital-to-analog converter 110 and the forward readout circuit 120 are disconnected from the memristor array 150.

[0039] The inventors of this disclosure have noted that both forward computation and backward propagation modes only use a portion of the circuitry in the aforementioned in-memory computing circuit, resulting in reduced chip area efficiency and making it difficult to achieve an in-memory computing hardware system with high computing power density and weight density.

[0040] To address the above shortcomings, one or more embodiments of this disclosure propose an in-memory computing circuit and electronic device. The in-memory computing circuit includes a memristor array, a digital-to-analog converter (DAC), a bit-line computing module, a source-line computing module, and a control module. The control module is configured to control the operation of the memristor array, DAC, bit-line computing module, and source-line computing module based on the computing modes of the in-memory computing circuit. The computing modes include a forward computing mode and a backward propagation mode. In the forward computing mode, the DAC converts received first data to obtain a first input voltage provided to the bit-line computing module. The bit-line computing module provides the received first input voltage to the memristor array so that the memristor array generates a first load current after performing a first calculation using the first input voltage. The source-line computing module quantizes the first load current. In the backward propagation mode, the DAC converts received second data to obtain a second input voltage provided to the source-line computing module. The source-line computing module provides the received second input voltage to the memristor array so that the memristor array generates a second load current after performing a second calculation using the second input voltage. The bit-line computing module quantizes the second load current.

[0041] The in-memory computing circuit proposed in one or more embodiments of this disclosure shares a set of input circuits and readout circuits in both forward computing and backward propagation modes. That is, the bit line computing module and source line computing module in the in-memory computing circuit are used in both forward computing and backward propagation modes, thereby avoiding circuit redundancy, improving the area utilization efficiency of the in-memory computing circuit, and enhancing weight and computing power density.

[0042] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and components may be omitted. When any component of the embodiments of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numerals in each drawing.

[0043] For example, Figure 2A schematic diagram of a memory computing circuit provided in at least one embodiment of the present disclosure is shown. In forward computing mode, bit line calculation module 210 can act as the input circuit (i.e., "forward DAC") of the memory computing circuit, applying a voltage representing input data to the bit line BL of the memristor array 230; source line calculation module 220 can act as the readout circuit (i.e., "forward readout circuit") of the memory computing circuit, clamping the source line SL of the memristor array 230 and quantizing the current on the source line SL to obtain the calculation result. In reverse propagation mode, bit line calculation module 210 can act as the readout circuit (i.e., "reverse readout circuit") of the memory computing circuit, clamping the bit line BL of the memristor array 230 and quantizing the current on the bit line BL to obtain the result; source line calculation module 220 can act as the input circuit (i.e., "reverse DAC") of the memory computing circuit, applying a voltage representing input data to the source line SL of the memristor array 230.

[0044] For example, Figure 3A A schematic diagram of a memory computing circuit provided in at least one embodiment of the present disclosure in forward computing mode is shown.

[0045] like Figure 3A As shown, the in-memory computing circuit includes a memristor array 330, a digital-to-analog converter circuit 340, a bit-line calculation module 310, a source-line calculation module 320, and a control module (not shown in the figure). The control module is configured to control the operation of the memristor array 330, the digital-to-analog converter circuit 340, the bit-line calculation module 310, and the source-line calculation module 320 based on the computing mode of the in-memory computing circuit. The computing mode includes forward computing mode and backward propagation mode.

[0046] like Figure 3A As shown, in forward computation mode, the control module controls the digital-to-analog converter circuit 340 to be coupled to the bit-line computation module 310 and disconnected from the source-line computation module 320. The digital-to-analog converter circuit 340 converts the received first data (i.e., the input data for forward computation) to obtain a first input voltage VDAC_1[m-1:0] provided to the bit-line computation module 310. The bit-line computation module 310 provides the received first input voltage VDAC_1[m-1:0] to the memristor array 330 (i.e., applies the first input voltage VDAC_1[m-1:0] to the bit line BL of the memristor array 330) so that the memristor array 330 generates a first load current after performing a first computation using the first input voltage VDAC_1[m-1:0]. The source-line computation module 320 quantizes the first load current. Here, the "first load current" is the current on the source line SL of the memristor array 330 in forward computation mode.

[0047] For example, Figure 3BA schematic diagram of a memory computing circuit provided in at least one embodiment of the present disclosure in backpropagation mode is shown.

[0048] like Figure 3B As shown, in reverse propagation mode, the control module controls the digital-to-analog converter circuit 340 to be coupled to the source line calculation module 320 and disconnected from the bit line calculation module 310. The digital-to-analog converter circuit 340 converts the received second data (i.e., the input data for reverse propagation) to obtain a second input voltage VDAC_2[m-1:0] provided to the source line calculation module 320. The source line calculation module provides the received second input voltage VDAC_2[m-1:0] to the memristor array 330 (i.e., applies the second input voltage VDAC_2[m-1:0] to the source line SL of the memristor array 330) so that the memristor array 330 generates a second load current after performing a second calculation using the second input voltage VDAC_2[m-1:0]. The bit line calculation module 310 quantizes the second load current. Here, the "second load current" is the current on the bit line BL of the memristor array 330 in reverse propagation mode.

[0049] In the in-memory computing circuit provided in one or more embodiments of this disclosure, the memristor array includes multiple source lines, multiple bit lines, and multiple array-arranged weighted units. A bit line calculation module is coupled to the multiple bit lines of the memristor array and is further configured to clamp the voltages of the multiple bit lines to a first clamping reference voltage in reverse propagation mode. A source line calculation module is coupled to the multiple source lines of the memristor array and is further configured to clamp the voltages of the multiple source lines to a second clamping reference voltage in forward calculation mode.

[0050] For example, a memristor is a non-volatile device whose conductance can be adjusted, and the conductance value of the memristor is used to characterize the weight values ​​involved in the calculation. For example, the weighting unit in the memristor array can be a single-ended single-transistor single-memristor (1T1R) structure or a differential-based two-transistor two-memristor (2T2R) structure. The memristor in the aforementioned weighting unit can be resistive random access memory (RRAM), phase-change memory (PCM), conductive bridge memory, etc., and this disclosure does not impose any limitations on this.

[0051] For example, Figure 4A The connection relationship between the weight unit and the peripheral circuit of the 1T1R structure provided in at least one embodiment of the present disclosure in forward computation mode is shown; Figure 4B The connection relationship between the weight unit of the 1T1R structure provided in at least one embodiment of this disclosure and the peripheral circuit is shown in backpropagation mode; Figure 4C The connection relationship between the weight unit and the peripheral circuit of the 2T2R structure provided in at least one embodiment of the present disclosure in forward computation mode is shown; Figure 4DThe connection relationship between the weight unit of the 2T2R structure provided in at least one embodiment of the present disclosure and the peripheral circuit is shown in the backpropagation mode.

[0052] like Figure 4A and Figure 4B As shown, the weighting unit of the 1T1R structure includes a transistor NM and a memristor R. The first terminal of the memristor R is coupled to the bit line BL, which is also coupled to the bit line calculation module 410. The second terminal of the memristor R is coupled to the drain of the transistor NM. The source of the transistor NM is coupled to the source line SL, which is also coupled to the source line calculation module 420. The gate of the transistor NM receives a control signal.

[0053] like Figure 4C and Figure 4D As shown, the weighting unit of the 2T2R structure includes two transistors NM1 and NM2, and two memristors R. P and R N Memristor R P The first terminal is coupled to the bit line BLP, and the memristor R P The second terminal is coupled to the drain of transistor NM1, and the memristor R N The second terminal is coupled to the bit line BLN, and the memristor R N The second terminal is coupled to the drain of transistor NM2, where bit lines BLP and BLN are also coupled to bit line calculation module 410. The sources of transistors NM1 and NM2 are both coupled to the same source line SL, which is also coupled to source line calculation module 420. The gates of transistors NM1 and NM2 respectively receive corresponding control signals.

[0054] like Figure 4A As shown, in forward calculation mode, source line calculation module 420 clamps the source line SL to a fixed voltage (e.g., clamping voltage), bit line calculation module 410 inputs voltage to bit line BL to drive bit line BL, and source line calculation module 420 receives the current on the source line SL and performs quantization operation on the current to obtain the quantization result.

[0055] like Figure 4B As shown, in the reverse propagation mode, the bit line calculation module 410 clamps the bit line BL to a fixed voltage (e.g., clamping voltage), the source line calculation module 420 inputs a voltage to the source line SL to drive the bit line SL, and the bit line calculation module 410 receives the current on the bit line BL and performs a quantization operation on the current to obtain the quantization result.

[0056] like Figure 4CAs shown, in forward calculation mode, source line calculation module 420 clamps source line SL to a fixed voltage (e.g., clamping voltage), bit line calculation module 410 inputs differential voltage to bit line BLP and bit line BLN to drive bit line BLP and bit line BLN, source line calculation module 420 receives the current on source line SL and performs quantization operation on the current to obtain quantization result.

[0057] like Figure 4D As shown, in the reverse propagation mode, the bit line calculation module 410 clamps the bit line BLP and the bit line BLN to a fixed voltage (e.g., clamping voltage), the source line calculation module 420 inputs a voltage to the source line SL to drive the bit line SL, and the bit line calculation module 410 sequentially receives the current on the bit line BLP and the bit line BLN and performs a quantization operation on the current to obtain the quantization result.

[0058] In at least one embodiment of the in-memory computing circuit provided in this disclosure, the bitline computing module includes multiple bitline driver / clamping circuits and a first analog-to-digital converter (ADC). The multiple bitline driver / clamping circuits are coupled to multiple bitlines. Each bitline driver / clamping circuit is configured to provide a first input voltage to the corresponding bitline in forward computing mode, or, in reverse propagation mode, clamp the voltage of the corresponding bitline to a first clamping reference voltage and generate a second load voltage based on a second load current on the corresponding bitline. The first ADC is coupled to the multiple bitline driver / clamping circuits and is configured to sequentially quantize the second load voltages generated by the multiple bitline driver / clamping circuits in reverse propagation mode and output a second quantization result.

[0059] For example, Figure 5 A schematic diagram of the structure of a time-bit line calculation module using 1T1R weighted units provided in at least one embodiment of the present disclosure is shown.

[0060] like Figure 5 As shown, the bitline calculation module includes n bitline driver / clamp circuits (511_0~511_(n-1)) and an analog-to-digital converter (ADC) 512. The n bitline driver / clamp circuits (511_0~511_(n-1)) are coupled to n bitlines (BL[0]~BL[n-1]). The bitline calculation module also includes n switches (SW[0]~SW[n-1]), which are used to control the conduction between the bitline driver / clamp circuits 511_0~511_(n-1) and the analog-to-digital converter 512.

[0061] The following section uses the bitline driver / clamping circuit 511_0 as an example to illustrate the process of forward calculation and backward propagation of the bitline calculation module.

[0062] In forward propagation mode, switch SW[0] is open, and bit line drive / clamp circuit 511_0 applies an analog input voltage (i.e., the first input voltage) representing input data (e.g., VIN[0]) to bit line BL[0]. At this time, analog-to-digital converter 512 does not participate in forward propagation. In reverse propagation mode, bit line drive / clamp circuit 511_0 clamps the voltage on bit line BL[0] to a fixed level (i.e., the first clamp reference voltage) and linearly converts the current on bit line BL[0] into voltage V. O [0]; At the same time, switch SW[0] is closed, and analog-to-digital converter 512 adjusts voltage V O [0] Perform sampling and quantization operations to obtain the backpropagation result. The process of forward calculation and backpropagation performed by the remaining bit line drive / clamp circuits 511_1~511_(n-1) can be referred to bit line drive / clamp circuit 511_0, and will not be described in detail here.

[0063] It should be noted that the above Figure 5 When the bitline calculation module shown is in reverse propagation mode, n switches (SW[0]~SW[n-1]) are closed sequentially so that the analog-to-digital converter 512 sequentially applies voltage V O [0]~Voltage V O [n-1] is used for sampling and quantization operations.

[0064] For example, Figure 6 A schematic diagram of the structure of a bitline calculation module using 2T2R weight units is shown in at least one embodiment of the present disclosure.

[0065] like Figure 6 As shown, the bitline calculation module includes n bitline driver / clamp circuits (611_0~611_(n-1)) and an analog-to-digital converter 612 (ADC). The n bitline driver / clamp circuits (611_0~611_(n-1)) are coupled to n groups of bitlines, each group including two bitlines. For example, the first group includes bitline BLN[0] and bitline BLP[0], and the nth group includes bitline BLN[n-1] and bitline BLP[n-1]. The bitline calculation module also includes n groups of switches, each group used to control the conduction between the corresponding bitline driver / clamp circuit and the analog-to-digital converter 612. Each group of switches includes two switches; for example, the first group includes switch SW. N [0] and switch SW P [0]), the nth group of switches includes switch SW N [n-1] and switch SW P [n-1]).

[0066] The following section uses the bitline driver / clamping circuit 611_0 as an example to illustrate the process of forward calculation and backward propagation of the bitline calculation module.

[0067] In forward computation mode, switch SW N [0] and switch SW P [0] Disconnected, the bit line drive / clamp circuit 611_0 applies analog input voltages representing input data (e.g., VIN[0] and VIP[0]) to bit lines BLN[n-1] and BLP[n-1], at which time the analog-to-digital converter 612 does not participate in the forward calculation. In reverse propagation mode, the bit line drive / clamp circuit 611_0 clamps the voltages on bit lines BLN[n-1] and BLP[n-1] to a fixed level (i.e., the first clamp reference voltage), and linearly converts the currents on bit lines BLN[n-1] and BLP[n-1] into voltages V, respectively. OP [0] and voltage V ON [0]; Simultaneously switch SW N [0] and switch SW P [0] Closed, analog-to-digital converter 512 sequentially processes voltage V OP [0] and voltage V ON [0] Perform sampling and quantization operations to obtain and output the backpropagation result. The process of forward calculation and backpropagation of the remaining bit line drive / clamp circuits 611_1~611_(n-1) can be referred to bit line drive / clamp circuit 111_0, and will not be described in detail here.

[0068] It should be noted that the above Figure 6 When the bitline calculation module shown is in backpropagation mode, n sets of switches (SW) N [0]、SW P [0]、SW N [1] SW P [1]、……、SW N [n-1] and SW P [n-1]) are closed sequentially so that the analog-to-digital converter 612 sequentially applies voltage V. OP [0]、V ON [0]、V OP [1], V ON [1]、……V OP [n-1] and V ON [n-1] is used for sampling and quantization operations.

[0069] For example, the analog-to-digital converter (ADC) in the bitline calculation module can be current-type or voltage-type, and this disclosure does not limit it.

[0070] For example, the bit line drive / clamp circuit in the bit line calculation module can be set based on a gain amplifier or a flip voltage follower, which is not limited in this disclosure.

[0071] For example, Figure 7A and Figure 7B A schematic diagram of the structure of a bitline calculation module based on a gain amplifier and a current-mode analog-to-digital converter provided in at least one embodiment of the present disclosure is shown.

[0072] like Figure 7A and Figure 7B As shown, taking the weighted cell of the memristor array coupled to the bitline calculation module as an example, which adopts a 2T2R structure, the bitline calculation module includes a bitline drive / clamp circuit 711 and an analog-to-digital converter 712 (ADC). The ADC 712 is a current-type converter. The bitline drive / clamp circuit 711 includes two high-gain differential amplifiers 7111 and 7112 connected with unity-gain negative feedback, and a resistor R. P Resistance R N Switches SW.1 and SW.2 are used, wherein the outputs of differential amplifiers 7111 and 7112 are connected to the ADC via switches SW.1 and SW.2, respectively. The negative input terminal of differential amplifier 7111 is coupled to the bit line BLP of the memristor array and the analog-to-digital converter 712, respectively, and the negative input terminal of differential amplifier 7112 is coupled to the bit line BLN of the memristor array and the analog-to-digital converter 712, respectively.

[0073] like Figure 7B As shown, the analog-to-digital converter 712 may include a comparator 7121, a logic control circuit 7122 (e.g., a SAR logic control circuit), and a current generation unit 7123 (IDAC). The first input terminal of the comparator 7121 is coupled to the output terminal of the differential amplifier 7111 via switch SW.1, and the second input terminal of the comparator 7121 is coupled to the output terminal of the differential amplifier 7112 via switch SW.2. The output terminal of the comparator 7121 is coupled to the logic control circuit 7122. The logic control circuit 7122 is also coupled to the current generation unit 7123 to control the current generation unit 7123 to generate a corresponding current to the negative input terminals of the differential amplifiers 7111 and 7112 based on the comparison result output by the comparator 7121.

[0074] The following is based on Figure 7B Taking the bitline calculation module shown as an example, the circuit working principle of this bitline calculation module is as follows.

[0075] In forward computation mode, the positive input terminals of differential amplifiers 7111 and 7112 receive the VIP and VIN signals from the digital-to-analog converter (not shown in the diagram), respectively, to provide differential input voltages (i.e., drive voltages) for the memristor array. A voltage relationship exists between the VIP and VIN signals: (VIP + VIN) / 2 = V. CM V CM This is the clamping voltage on the source line of the memristor array. Simultaneously, switches SW.1 and SW.2 are open, and the analog-to-digital converter 712 (ADC) does not participate in the forward calculation.

[0076] In reverse propagation mode, the positive input terminals of both differential amplifiers 7111 and 7112 receive voltage V. RD (Not shown in the diagram), the voltage difference between voltage VRD and the source line input voltage of the memristor array is the read voltage during reverse propagation calculation. Differential amplifiers 7111 and 7112 clamp the source lines BLP and BLN respectively, and the current I on the source line BLP is... BLP After passing through resistor R P Generate output voltage V OP =I BLP ×R P The current I on the source line BLN BLN After passing through resistor R N Generate output voltage V ON =I BLN ×R N Simultaneously, switches SW.1 and SW.2 are closed, and the analog-to-digital converter 712 adjusts according to voltage V. OP and V ON For the differential current (I) representing the calculation result BLP -I BLN Quantization is performed. Specifically, during the readout quantization process, comparator 7121 compares the voltage V. OP and V ON The logic control circuit 7122 controls the current generation unit 7123 to feed back current to the clamping points of the coupled bit lines BLP and BLN according to the comparison result, so that the current difference flowing into the two clamping points is 0. The logic control circuit 7122 outputs the quantization result, thereby completing the quantization process of the analog-to-digital converter ADC.

[0077] The above Figure 7A and Figure 7B The bitline calculation module shown includes multiple bitline drive / clamping circuits. Figure 7A and Figure 7B Only one bit line drive / clamp circuit 711 is shown schematically. Each bit line drive / clamp circuit may employ a separate analog-to-digital converter (ADC), and multiple bit line drive / clamp circuits may share the same ADC; this disclosure does not limit this.

[0078] For example, Figure 7C It shows Figure 7A and Figure 7B The diagram shown illustrates an analog-to-digital converter multiplexed by multiple bit line drive / clamping circuits.

[0079] like Figure 7C As shown, the bitline calculation module includes N sets of bitline drive / clamp circuits and N analog-to-digital converters. Figure 7COnly one set of bit line drive / clamp circuits and one analog-to-digital converter 712 are schematically shown. This set of bit line drive / clamp circuits includes n bit line drive / clamp circuits 711_1 to 711_n. The bit line drive / clamp circuits 711_1 to 711_n multiplex the same analog-to-digital converter 712, that is, the analog-to-digital converter 712 sequentially quantizes the n bit line drive / clamp circuits 711_1 to 711_n.

[0080] In the bitline calculation module provided in at least one embodiment of this disclosure, each group of bitline drive / clamp circuits can be multiplexed to the same analog-to-digital converter, thereby avoiding the problem of low area utilization caused by the area difference between the analog-to-digital converter and the bitline drive / clamp circuit.

[0081] For example, Figure 8A and Figure 8B A schematic diagram of the structure of a bitline calculation module based on a gain amplifier and a voltage-type analog-to-digital converter provided in at least one embodiment of the present disclosure is shown.

[0082] like Figure 8A and Figure 8B As shown, taking the weighted cell of the memristor array coupled to the bitline calculation module as an example, which adopts a 2T2R structure, the bitline calculation module includes a bitline drive / clamp circuit 811 and an analog-to-digital converter 812 (ADC), and the ADC 812 is a voltage-type converter. The bitline drive / clamp circuit 811 includes two high-gain differential amplifiers 8111 and 8112 connected with unity-gain negative feedback, and a resistor R. P Resistance R N Switches SW.1 and SW.2 are used, wherein the outputs of differential amplifiers 8111 and 8112 are connected to analog-to-digital converter 812 via switches SW.1 and SW.2, respectively. The negative input terminal of differential amplifier 8111 is coupled to the bit line BLP of the memristor array, and the negative input terminal of differential amplifier 8112 is coupled to the bit line BLN of the memristor array.

[0083] like Figure 8B As shown, the analog-to-digital converter 812 may include a comparator 8121, logic control circuitry 8122 (e.g., SAR logic control circuitry), and two current-to-digital converters (CDACs). P and CDAC N The first input of comparator 8121 is connected to the CDAC. P Coupled, the second input of comparator 8121 is connected to CDAC N The output of comparator 8121 is coupled to logic control circuit 8122. Logic control circuit 8122 is also coupled to CDAC. P and CDAC N Coupled.

[0084] The following is based on Figure 8B Taking the bitline calculation module shown as an example, the circuit working principle of this bitline calculation module is as follows.

[0085] Figure 8B The working principle of the bitline calculation module shown in the forward calculation mode is similar to that described above. Figure 7B The bitline calculation module shown is described in the same way in the forward calculation mode, so it will not be repeated here.

[0086] In the backpropagation computation mode, Figure 8B The positive input terminals of the differential amplifiers 8111 and 8112 in the bit line calculation module shown are both connected to voltage V. RD (Not shown in the diagram), differential amplifiers 8111 and 8112 clamp bit lines BLP and BLN. The current I on bit line BLP... BLP After passing through resistor R P Generate output voltage V OP =I BLP ×R P The current I on the bit line BLN BLN The resistor generates an output voltage V. ON =I BLN ×R N Simultaneously, switches SW.1 and SW.2 are closed, and CDAC... P and CDAC N The output voltage V was tested respectively. OP and V ON Sample and output voltage signal V CP and V CN Then, switches SW.1 and SW.2 are opened, ending the sampling process and entering the quantization stage. During the quantization stage, comparator 8121 compares the voltage signal V. CP and V CN The voltage magnitude, the SAR logic control circuit 8122 controls the CDAC based on the comparison result. P and CDAC N The capacitor is flipped so that the voltage signal V CP and V CN The differential voltage converges to 0, ending the quantization process. Here, the CDAC in the voltage-type analog-to-digital converter (ADC)... P and CDAC N The sampling method can be either top plate sampling or bottom plate sampling, and this disclosure does not restrict it.

[0087] Unlike the bitline calculation module that uses a current-mode analog-to-digital converter (such as...) Figure 7A and 7B As shown), in Figure 8A and 8BDuring the backpropagation calculation process of the bitline calculation module shown, switches SW.1 and SW.2 only need to be closed during the sampling phase. After the sampling is completed, switches SW.1 and SW.2 are opened. The bitline drive / clamp circuit 811 can simultaneously establish the voltage for the next round of backpropagation calculation and the analog-to-digital converter 812 can simultaneously perform the quantization process for the current round of backpropagation calculation.

[0088] The above Figure 8A and Figure 8B The bitline calculation module shown includes multiple bitline drive / clamping circuits. Figure 8A and Figure 8B Only one bit line drive / clamp circuit 811 is shown schematically. Each bit line drive / clamp circuit may employ a separate analog-to-digital converter (ADC), and multiple bit line drive / clamp circuits may share the same ADC; this disclosure does not limit this.

[0089] For example, Figure 8C It shows Figure 8A and Figure 8B The diagram shown illustrates an analog-to-digital converter multiplexed by multiple bit line drive / clamping circuits.

[0090] like Figure 8C As shown, the bitline calculation module includes N sets of bitline drive / clamp circuits and N analog-to-digital converters. Figure 8C Only one set of bit line drive / clamp circuits and one analog-to-digital converter 812 are schematically shown. This set of bit line drive / clamp circuits includes n bit line drive / clamp circuits 811_1 to 811_n. The bit line drive / clamp circuits 811_1 to 811_n multiplex the same analog-to-digital converter 812, that is, the analog-to-digital converter 812 sequentially quantizes the n bit line drive / clamp circuits 811_1 to 811_n. Figure 8C The bitline calculation module shown can avoid the problem of low area utilization caused by the area difference between the analog-to-digital converter and the bitline drive / clamping circuit.

[0091] In the in-memory computing circuit provided in at least one embodiment of this disclosure, in addition to setting up the bit line calculation module based on a differential high-gain amplifier to form a unity-gain buffer, the bit line calculation module can also be set up based on a flip voltage follower (FVF) to drive and clamp the bit lines of the memristor array.

[0092] For example, the bit line calculation module can be based on a source follower (hereinafter referred to as "SF-FVF") or a common gate follower (hereinafter referred to as "CG-FVF"). The following uses the weight cell of the memristor array with a 2T2R structure as an example to introduce the process of the bit line calculation module driving the bit line (i.e., the process of performing forward calculation).

[0093] For example, Figure 9A and 9B A schematic diagram of a bit line drive / clamp circuit based on a source follower configuration provided in at least one embodiment of this disclosure is shown; Figure 10A and Figure 10B A schematic diagram of a bit line drive / clamp circuit based on a common-gate follower configuration provided in at least one embodiment of this disclosure is shown.

[0094] In forward computation mode, the current directions on bit line BLP and bit line BLN are different, that is, the current I on bit line BLN is different. BLN The drive current flows from the bit line BLN of the memristor array, and the current I on the bit line BLP is... BLP The bit line BLP (from which the drive current flows into the memristor array) allows the output stage to be configured to output current externally (e.g., from the bit line BLP of the memristor array). Figure 9A and 10A (as shown) and the inflow of current (such as) Figure 9B and 10B (As shown) There are two modes, which correspond to transistor PM.F1 being connected to the output stage circuit and transistor NM.F3 being connected to the output stage circuit, respectively.

[0095] like Figure 9A As shown, the bit line drive / clamp circuit includes transistors NM.F1 and NM.F2, three current generation units IG1~IG3, and an output stage circuit. The output stage circuit includes transistors NM.F3 and PM.F1, and four switches SW.1~SW.4. The drain of transistor NM.F1 is coupled to the voltage source VDD, the source of transistor NM.F1 is coupled to the input of current generation unit IG2, and the gate of transistor NM.F1 is coupled to the output of current generation unit IG1. The source of transistor NM.F2 is coupled to the input of current generation unit IG3 and the bit line node (e.g., N). BLP The transistors NM.F2 and IG1 are respectively coupled. The drain of NM.F2 is coupled to the output of the current generating unit IG1, and the gate of NM.F2 receives the input voltage signal (e.g., V). IP The drain and bit line node of transistor NM.F3 (e.g., N BLP The drain of transistor PM.F1 is coupled to the source of transistor NM.F3, which is grounded. The gate of transistor NM.F3 is coupled to the second terminal of switch SW.3 and the first terminal of switch SW.4, respectively. The source of transistor PM.F1 is coupled to the voltage source VDD and the first terminal of switch SW.1, respectively. The drain of transistor PM.F1 is coupled to the bit line node (e.g., N). BLPThe gate of transistor PM.F1 is coupled to the second terminal of switch SW.1 and the first terminal of switch SW.2. Switch SW.1 is used to control the conduction between the source and gate of transistor PM.F1, switch SW.2 is used to control the conduction between the gate of transistor PM.F1 and the source of transistor NM.F1, and switch SW.4 is used to control the conduction between the source and gate of transistor NM.F3.

[0096] like Figure 9A As shown, in forward computation mode, when the bit line BLP is driven by the bit line drive / clamp circuit based on the source follower configuration, switches SW.1 and SW.3 are open, and switches SW.2 and SW.4 are closed. The gate of transistor NM.F2 receives the input voltage signal V for the bit line BLP. IP The bit line nodes coupled to the output stage circuit are N. BLP At this point, only transistor PM.F1 is connected in the output stage circuit; transistor NM.F3 is not involved in the forward calculation. The voltage change at node ND is propagated to node NG, and the bit line drive / clamp circuit passes through bit line node N. BLP Apply a voltage signal V to the bit line BLP of the memristor array BLP To drive the bit line BLP, where the input voltage signal V IP The voltage signal V output by the bit line drive / clamp circuit is determined. BLP Size.

[0097] like Figure 9B As shown, in forward computation mode, when the bit line BLN is driven by the bit line drive / clamp circuit based on the source follower configuration, switches SW.1 and SW.3 are closed, and switches SW.2 and SW.4 are open. The gate of transistor NM.F2 receives the input voltage signal V for the bit line BLN. IN The bit line nodes coupled to the output stage circuit are N. BLN At this point, only transistor PM.F3 is connected in the output stage circuit, while transistor PM.F1 is not involved in the forward calculation. The voltage change at node ND is propagated to node NG, and the bit line drive / clamp circuit passes through bit line node N. BLN Apply a voltage signal V to the bit line BLN of the memristor array BLN To drive the bit line BLN, where the input voltage signal V IN The voltage signal V output by the bit line drive / clamp circuit is determined. BLN Size.

[0098] like Figure 10AAs shown, the bit line drive / clamp circuit includes transistor NM.F1, transistor PM.F1, three current generation units IG1~IG3, and an output stage circuit. The output stage circuit includes transistor PM.F2, transistor NM.F2, and four switches SW.1~SW.4. The source of transistor PM.F1 is coupled to the voltage source VDD and the output of current generation unit IG1, respectively. The drain of transistor PM.F1 is coupled to the input of current generation unit IG2 and the second terminal of switch SW.2, respectively. The gate of transistor PM.F1 receives the control signal V. B The source of transistor NM.F1 is connected to the input terminal and bit line node of current generation unit IG3 (e.g., N...). BLP The transistor NM.F1 is coupled to the output of the current generating unit IG1 at node ND, and the gate of transistor NM.F1 receives the input voltage signal (e.g., V). IP The drain of transistor PM.F2 and the bit line node (e.g., N). BLP The drain of transistor NM.F2 is coupled to the input of current generation unit IG3, the source of transistor PM.F2 is coupled to voltage source VDD, and the gate of transistor PM.F2 is coupled to the second terminal of switch SW.1 and the first terminal of switch SW.2, respectively. The source of transistor NM.F2 is grounded, and the drain of transistor NM.F2 is coupled to bit line node (e.g., N...). BLP The drain of transistor PM.F2 and the input of current generation unit IG3 are coupled to each other. The gate of transistor NM.F2 is coupled to the second terminal of switch SW.3 and the first terminal of switch SW.4. Switch SW.1 is used to control the conduction between the source and gate of transistor PM.F2, switch SW.2 is used to control the conduction between the gate of transistor PM.F2 and the drain of transistor PM.F1, and switch SW.4 is used to control the conduction between the source and gate of transistor NM.F2.

[0099] like Figure 10A As shown, in forward computation mode, when the bit line BLP is driven by the bit line drive / clamp circuit based on the common-gate follower configuration, switches SW.1 and SW.3 are open, and switches SW.2 and SW.4 are closed. The gate of transistor NM.F1 receives the input voltage signal V for the bit line BLP. IP The bit line nodes coupled to the output stage circuit are N. BLP At this point, only transistor PM.F2 is connected in the output stage circuit. Transistor NM.F2 is not involved in the forward calculation. The voltage change at node ND is transmitted to node NG. The bit line drive / clamp circuit passes through bit line node N. BLP Apply a voltage signal V to the bit line BLP of the memristor array BLP To drive the bit line BLP, where the input voltage signal V IPThe voltage signal V output by the bit line drive / clamp circuit is determined. BLP Size.

[0100] like Figure 10B As shown, in forward computation mode, when the bit line BLN is driven by the bit line drive / clamp circuit based on the common-gate follower configuration, switches SW.2 and SW.3 are closed, and switches SW.1 and SW.4 are open. The gate of transistor NM.F1 receives the input voltage signal V for the bit line BLN. IN The bit line nodes coupled to the output stage circuit are N. BLN At this point, only transistor NM.F2 is connected in the output stage circuit, while transistor PM.F1 is not involved in the forward calculation. The voltage change at node ND is propagated to node NG, and the bit line drive / clamp circuit passes through bit line node N. BLN Apply a voltage signal V to the bit line BLN of the memristor array BLN To drive the bit line BLN, where the input voltage signal V IN The voltage signal V output by the bit line drive / clamp circuit is determined. BLN Size.

[0101] The bit line drive / clamp circuit described above uses a common-gate follower (CG-FVF) (such as...) Figure 10A and Figure 10B The output voltage signal V (as shown) BLP and V BLN It has a higher voltage signal V than the bit line drive / clamp circuit that uses a source follower (SF-FVF) than the output voltage signal V. BLP and V BLN Higher loop gain.

[0102] For example, Figure 11A and Figure 11B A schematic diagram of the structure of a bitline calculation module based on a common-gate follower configuration provided in at least one embodiment of the present disclosure is shown.

[0103] like Figure 11A and Figure 11B As shown, the bitline calculation module includes a bitline driver / clamp circuit 1110, an analog-to-digital converter 1120, and four switches (i.e., switches SW.CP, SW.CN, SW.IP, and SW.IN). Switches SW.CP, SW.CN, SW.IP, and SW.IN are used to couple the bitline driver / clamp circuit 1110 and the analog-to-digital converter 1120.

[0104] Bit line drive / clamp circuit 1110 includes, for example, Figure 9A and Figure 9B The bitline drive / clamp circuit shown is based on a source follower configuration for simultaneous transmission through node N. BLN and node N BLPSimultaneously drives bit line BLN and bit line BLP. For a description of the bit line drive / clamp circuit 1110, please refer to the above description. Figure 9A and Figure 9B The description of the bit line drive / clamp circuit shown above, the structure of the analog-to-digital converter 1120, and other related information can be found in the above description. Figure 7B The description of the analog-to-digital converter in the document will not be repeated here.

[0105] In the above Figure 11A and Figure 11B In the bit line calculation module shown, the closing or opening of switches SW.CP, SW.CN, SW.IP, and SW.IN is determined according to the specific calculation mode.

[0106] For example, in forward computation mode (such as...) Figure 11A As shown), switches SW.CP, SW.CN, SW.IP, and SW.IN are all open to prevent the analog-to-digital converter 1120 from participating in calculations. Switches SW.1_1 and SW.3_1 are open, switches SW.2_1 and SW.4_1 are closed, switches SW.1 and SW.3 are closed, and switches SW.2 and SW.4 are open. Different voltage signals V are input to the gates of transistors NM.F2 and NM.F2_1, respectively. IN and V IP This causes the voltage on bit line BLP and bit line BLN (i.e., node N) to be such that BLN and node N BLP The voltages at the points are the differential voltages representing the input data, and satisfy the relationship (V... BLP +V BLN ) / 2=V CM At this time, bit line BLP is driven by transistor PM.F1_1 in output stage circuit 1102, and bit line BLN is driven by transistor NM.F3 in output stage circuit 1101.

[0107] For example, in backpropagation calculation mode, if the input voltage on the source line SL is higher than the clamping voltages of the bit lines BLP and BLN, then node N BLP and node N BLN The current flows into bit lines BLP and BLN. Output stage circuits 1101 and 1102 are connected by transistors NM.F3 and NM.F3_1, respectively. If the input voltage on the source line SL is lower than the clamping voltage of bit lines BLP and BLN, then output stage circuits 1101 and 1102 are connected by transistors PM.F1 and PM.F1_1, respectively.

[0108] For example, in the backpropagation computing mode, when the output stage circuits 1101 and 1102 are connected by transistors NM.F3 and NM.F3_1 respectively (e.g. Figure 11BAs shown), the same voltage signal (V) is input to the gates of transistors NM.F2 and NM.F2_1 respectively. IN =V IP ), making node N BLN and node N BLP The voltages at each point are the same and equal to V. RD The difference between the voltage at node CN and the voltage at node CP represents the difference between the current on bit line BLP and the current on bit line BLN. Simultaneously, switches SW.CP, SW.CN, SW.IP, and SW.IN are all closed to couple the bit line drive / clamp circuit 1110 to the analog-to-digital converter 1120. The logic control circuit 1122 (e.g., SAR logic control circuit) in the analog-to-digital converter 1120 controls the current generation unit 1123 (IDAC) to generate a corresponding current feedback to node N based on the magnitude relationship between the voltages at node CP and node CN. BLN and node N BLP This compensates for the load current flowing into the bit line drive / clamp circuit 1110. Ultimately, the voltages of nodes CP and CN are made the same, meaning the current difference component flowing into bit lines BLP and BLN is zero, thus completing quantization.

[0109] Furthermore, based on the above Figure 11A and Figure 11B The bitline calculation module shown can also be used as follows: Figure 10A and Figure 10B The bitline driving / clamping circuit shown is used to configure the bitline calculation module, but this disclosure does not limit this.

[0110] In at least one embodiment of the in-memory computing circuit provided in this disclosure, the source line computing module includes multiple source line drive / clamp circuits and a second analog-to-digital converter (ADC). The multiple source line drive / clamp circuits are coupled to multiple source lines respectively. Each source line drive / clamp circuit is configured to, in forward computing mode, clamp the voltage of the corresponding source line to a second clamp reference voltage and generate a first load voltage based on a first load current on the corresponding source line; or, in reverse propagation mode, provide a second input voltage to the corresponding source line. The second ADC is coupled to the multiple source line drive / clamp circuits and is configured to, in forward computing mode, sequentially quantize the first load voltage generated by the multiple source line drive / clamp circuits and output a first quantization result.

[0111] For example, Figure 12A and Figure 12B A schematic diagram of the source line computing module provided in at least one embodiment of the present disclosure is shown in forward computing and backward propagation modes.

[0112] like Figure 12A (or Figure 12BAs shown in Figure 12, the source line computing module includes multiple source line drive / clamp circuits 1221 and an analog-to-digital converter 1270. Figure 12B Only one source line drive / clamp circuit 1221 is schematically shown. This source line drive / clamp circuit 1221 includes a differential amplifier 1260 and a transistor NM, with the output of the differential amplifier coupled to the control terminal (i.e., the gate) of the transistor NM. In forward computation mode, the first input terminal (i.e., the positive input terminal) of the differential amplifier 1260 is clamped to a second clamping reference voltage V. CM (A fixed voltage) The second input terminal (i.e., the negative input terminal) of the differential amplifier receives the first load current (i.e., the current on the source line SL coupled to the source line drive / clamp circuit 1221). In reverse propagation mode, the first input terminal of the differential amplifier 1260 receives the second input voltage, which is supplied to the source line SL coupled to the source line drive / clamp circuit 1221. Here, the "second input voltage" is the analog voltage obtained after the digital-to-analog converter converts the received input data.

[0113] For example, analog-to-digital converter 1270 includes comparator 1271, logic control circuitry 1272 (e.g., SAR logic control circuitry), and current generation unit 1273 (IDAC). Comparator 1271 is configured to compare a first load voltage with a reference voltage V. REF The logic control circuit 1272 is coupled to the output of the comparator 1271 and the input of the current generation unit 1273, and is configured to control the current generation unit 1273 to generate a first current based on the comparison result of the comparator 1271, so as to regulate the first load current on the source line SL.

[0114] For example, the logic control circuit 1272 is also configured to output a first quantization result based on the comparison result of the comparator 1271.

[0115] The following is based on Figure 12A and Figure 12B Taking the source line computing module shown as an example, the process of the source line computing module performing forward computing and backward propagation in at least one embodiment of this disclosure is further described.

[0116] like Figure 12A As shown, in forward computation mode, switch SW.S1 is open and switch SW.S2 is closed. The voltage at the positive input terminal of the differential amplifier is clamped to voltage V. CM Then, switch SW.S3 closes, clamping the voltage at the two inputs of comparator 1271 to voltage V. REF Clamped to voltage V REFAfterwards, switch SW.S3 is opened, and the load current accumulates (or integrates) at the top plate of capacitor CINT. Comparator 1271 compares the voltage at the top plate of capacitor CINT with the voltage VREF and outputs the comparison result. Here, "load current" refers to the array load current flowing into or out of analog-to-digital converter 1270. SAR logic circuit 1272 controls current generation unit 1273 (IDAC) based on the comparison result, for example, by controlling current generation unit 1273 to generate a first current to the clamping point of source line SL, thereby adjusting the load current on source line SL. SAR logic circuit 1272 controls the magnitude and polarity of the first current generated by current generation unit 1273 based on the comparison result. For example, if the voltage at the top plate of capacitor CINT is greater than the voltage VREF, current generation unit 1273 generates a negative current (i.e., current flows into current generation unit 1273), causing the voltage at the top plate of capacitor CINT to decrease in the next operating cycle. If the source line calculation module includes m source line drive / clamp circuits 1221, the SAR logic circuit 1272 will also output a 1-bit quantization result based on the comparison result. This 1-bit quantization result is the most significant bit of the final quantization result (including m bits). Then, switch SW.S3 is closed, and the above process is repeated until the SAR logic circuit 1272 obtains an m-bit quantization result based on the comparison result. At this time, the first current generated by the current generation unit 1273 cancels the load current flowing from the source line SL into the clamping point, and the integrated current of capacitor CINT approaches zero.

[0117] like Figure 12B As shown, in reverse propagation mode, switch SW.S1 is closed, and switches SW.S2 and SW.S3 are open. At this time, the analog-to-digital converter 1270 does not participate in the reverse propagation process executed by the source line calculation module. The source line drive / clamping circuit 1221 is an input drive circuit based on gain boosting technology. The first input terminal of the differential amplifier 1260 receives voltage V. IF (That is, the analog voltage obtained after the digital-to-analog converter converts the received input data), and then the voltage V after gain enhancement. IF Apply to the source line SL.

[0118] At least one embodiment of this disclosure also provides an electronic device, which includes the in-memory computing circuit provided in any embodiment of this disclosure.

[0119] For example, Figure 13 A schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure is shown.

[0120] The electronic devices in the embodiments of this disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle terminals (such as vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. They may also be any combination of data processing devices and hardware, and the embodiments of this disclosure do not limit this. Figure 13 The illustrated electronic device 1300 is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0121] For example, such as Figure 13 As shown, in some examples, electronic device 1300 includes a processing device (e.g., central processing unit, graphics processing unit, etc.) 1301, which may include the aforementioned in-memory computing device and the in-memory computing device includes the in-memory computing circuitry of any of the above embodiments. This processing device can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1302 or a program loaded from storage device 1308 into random access memory (RAM) 1303. RAM 1303 also stores various programs and data required for the operation of the computer system. Processor 1301, ROM 1302, and RAM 1303 are connected via bus 1304. Input / output (I / O) interface 1305 is also connected to bus 1304.

[0122] For example, the following components can be connected to I / O interface 1305: input devices 1306 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 1307 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1308 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1309, such as network interface cards like LAN cards and modems, etc. Communication device 1309 allows electronic device 1300 to communicate wirelessly or wiredly with other devices to exchange data and perform communication processing via networks such as the Internet. Drive 1310 is also connected to I / O interface 1305 as needed. Removable media 1311, such as disks, optical discs, magneto-optical discs, semiconductor memories, etc., are installed on drive 1310 as needed so that computer programs read from them can be installed into storage device 1308 as needed. Although Figure 13 An electronic device 1300 including various devices is shown; however, it should be understood that implementation or inclusion of all shown devices is not required. More or fewer devices may be implemented or included alternatively.

[0123] For example, the electronic device 1300 may further include a peripheral interface ( Figure 13(Not shown in the image). The peripheral interface can be of various types, such as USB, Lightning, etc. The communication device 1309 can communicate with networks and other devices wirelessly, such as the Internet, intranets and / or wireless networks such as cellular telephone networks, wireless local area networks (LANs) and / or metropolitan area networks (MANs). Wireless communication can use any of a variety of communication standards, protocols and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging and / or Short Message Service (SMS), or any other suitable communication protocol.

[0124] In addition to the illustrative examples described above, the following points also need to be noted:

[0125] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0126] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0127] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A memory computing circuit, comprising: The system comprises a memristor array, a digital-to-analog converter circuit, a bit line calculation module, a source line calculation module, and a control module. The control module is configured to operate the memristor array, the digital-to-analog converter circuit, the bit line computing module, and the source line computing module in a computing mode based on the in-memory computing circuit. The computing mode includes a forward computing mode and a backward propagation mode. In the forward computing mode, the control module controls the digital-to-analog converter circuit to be coupled to the bit-line computing module and disconnected from the source-line computing module. The digital-to-analog converter circuit converts the received first data to obtain a first input voltage provided to the bit-line computing module. The bit-line computing module provides the received first input voltage to the memristor array so that the memristor array generates a first load current after performing a first calculation using the first input voltage. The source-line computing module quantizes the first load current. In the backpropagation mode, the control module controls the digital-to-analog converter circuit to be coupled to the source line computing module and disconnected from the bit line computing module. The digital-to-analog converter circuit converts the received second data to obtain a second input voltage provided to the source line computing module. The source line computing module provides the received second input voltage to the memristor array so that the memristor array generates a second load current after performing a second calculation using the second input voltage. The bit line computing module quantizes the second load current. The memristor array includes multiple source lines, multiple bit lines, and multiple array-arranged weighted cells. The bitline calculation module includes: multiple bitline driver / clamping circuits and a first analog-to-digital converter, wherein the multiple bitline driver / clamping circuits are respectively coupled to the multiple bitlines. Each of the bit line drive / clamp circuits is configured to, in the forward calculation mode, provide the first input voltage to the corresponding bit line, or, in the reverse propagation mode, clamp the voltage of the corresponding bit line to a first clamp reference voltage and generate a second load voltage based on the second load current on the corresponding bit line. The first analog-to-digital converter is coupled to the plurality of bit line drive / clamp circuits and is configured to sequentially quantize the second load voltage generated by the plurality of bit line drive / clamp circuits in the back propagation mode and output the second quantization result. The source line calculation module includes multiple source line driver / clamping circuits and a second analog-to-digital converter, wherein the multiple source line driver / clamping circuits are respectively coupled to the multiple source lines. Each of the source line drive / clamp circuits is configured to, in the forward calculation mode, clamp the voltage of the corresponding source line to a second clamp reference voltage and generate a first load voltage based on a first load current on the corresponding source line, or, in the reverse propagation mode, provide the second input voltage to the corresponding source line. The second analog-to-digital converter is coupled to the plurality of source line drive / clamp circuits and is configured to sequentially quantize the first load voltage generated by the plurality of source line drive / clamp circuits in the forward computing mode and output the first quantization result.

2. The in-memory computing circuit as described in claim 1, wherein, The first analog-to-digital converter is either a current-type or a voltage-type converter.

3. The in-memory computing circuit as described in claim 1, wherein, The bit line drive / clamp circuit is configured based on a gain amplifier or a flip voltage follower.

4. The in-memory computing circuit as described in claim 1, wherein, The source line drive / clamping circuit includes a differential amplifier and a transistor, with the output terminal of the differential amplifier coupled to the control terminal of the transistor. In the forward computation mode, the first input terminal of the differential amplifier is clamped to the second clamping reference voltage, and the second input terminal of the differential amplifier receives the first load current; or, in the reverse propagation mode, the first input terminal of the differential amplifier receives the second input voltage, and the second input terminal of the differential amplifier provides the second input voltage to the corresponding source line.

5. The in-memory computing circuit as described in claim 1, wherein, The second analog-to-digital converter includes a comparator, logic control circuitry, and a current generation unit. The comparator is configured to compare the first load voltage with a reference voltage. The logic control circuit is coupled to the comparator and the current generating unit, and is configured to control the current generating unit to generate a first current based on the comparison result of the comparator, so as to adjust the first load current on the corresponding source line.

6. The in-memory computing circuit as described in claim 5, wherein, The logic control circuit is further configured to output the first quantization result based on the comparison result of the comparator.

7. An electronic device comprising a memory computing circuit as claimed in any one of claims 1-6.

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