Methods for fabricating memory, memory, devices and equipment

Abstract

This application provides a method for fabricating a memory, a memory, a device, and an apparatus. The method includes: sequentially stacking a first material layer and a second material layer along a first direction on a substrate, wherein the doping concentrations of the first material layer and the second material layer are different; etching the first material layer and the second material layer in a WL region to form a semiconductor structure and a BL structure; depositing an insulating dielectric on both sides of the BL structure in the WL region to form a dielectric layer; flipping and removing the substrate to expose the semiconductor structure; etching the semiconductor structure in the BL region to form an active structure; and forming a memory based on the active structure, wherein the BL structure serves as the source and drain structure of the transistors in the memory. By forming a dielectric layer on both sides of the BL structure in the WL region, this application can reduce the parasitic capacitance of the BL structure, which is beneficial for optimizing device performance.

Description

Technical Field

[0001] This application relates to the field of integrated semiconductors, and more particularly to a method for fabricating a memory, a memory, a device, and an apparatus. Background Technology

[0002] Dynamic random access memory (DRAM) typically uses a transistor and a capacitor (1T1C) structure as the memory cell of a chip. However, the bottom-up (BL) structure of DRAM has a large parasitic capacitance. Summary of the Invention

[0003] This application provides a method for fabricating a memory, a memory, a device, and an apparatus, which can reduce the parasitic capacitance of the BL structure and is beneficial to the optimization of device performance.

[0004] In a first aspect, embodiments of this application provide a method for fabricating a memory, the method comprising: sequentially stacking a first material layer and a second material layer on a substrate along a first direction, wherein the doping concentration of the first material layer and the doping concentration of the second material layer are different; etching the first material layer and the second material layer in a word line (WL) region to form a semiconductor structure and a bit line (BL) structure; depositing an insulating dielectric on both sides of the BL structure in the WL region to form a dielectric layer; flipping and removing the substrate to expose the semiconductor structure; etching the semiconductor structure in the BL region to form an active structure; and forming a memory based on the active structure, wherein the BL structure serves as the source and drain structure of the transistors in the memory.

[0005] In one possible implementation, etching a first material layer and a second material layer in the word line WL region to form a semiconductor structure and a bit line BL structure includes: forming a first mask on the second material layer, the first mask being used to locate the WL region; and etching the second material layer and the first material layer based on the first mask to form the BL structure and the semiconductor structure.

[0006] In one possible implementation, an insulating dielectric is deposited on both sides of the BL structure within the WL region to form a dielectric layer, comprising: forming an isolation structure on both sides of the semiconductor structure within the WL region; and depositing an insulating dielectric on the isolation structure to form a dielectric layer, the height of which is the same as the height of the BL structure.

[0007] In one possible implementation, forming a memory based on an active structure includes: forming a transistor based on the active structure; and forming a capacitor structure on the transistor.

[0008] In one possible implementation, forming a transistor based on an active structure includes: forming a gate structure based on the active structure; removing the gate structure in the BL region to form a first groove; depositing an insulating material on the gate structure in the WL region and in the first groove to form an insulating layer, the upper surface of the insulating layer being flush with the upper surface of a third mask located on the active structure; removing the third mask to form a second groove; and forming a source-drain structure in the second groove.

[0009] In one possible implementation, the gate structure includes a gate electrode layer and a gate dielectric layer surrounding the gate electrode layer, the height of the gate electrode layer being lower than the height of the gate dielectric layer; removing the gate structure within the BL region to form a first groove includes: forming a sacrificial layer on the gate electrode layer located within the BL region, the upper surface of the sacrificial layer being flush with the upper surface of the gate dielectric layer; anisotropically etching the bottom of the sacrificial layer and the gate electrode layer located below the sacrificial layer to form the first groove; and removing the sacrificial layer.

[0010] Secondly, embodiments of this application provide a method for fabricating a memory, the method comprising: forming an active structure on a substrate, the active structure including a first active structure and a second active structure, the first active structure being farther from the substrate than the second active structure; forming a memory based on the first active structure; performing a wafer flipping on the memory and removing the substrate to expose the second active structure; performing ion implantation on the second active structure to form a bit line (BL) structure, the BL structure serving as the source / drain structure of the transistor in the memory; and depositing an insulating dielectric on both sides of the BL structure within the word line (WL) region to form a dielectric layer.

[0011] In one possible implementation, forming an active structure on a substrate includes: sequentially stacking a first material layer and a second material layer on the substrate along a first direction; etching a portion of the second material layer and the first material layer in a BL region to form a first semiconductor structure and a second semiconductor structure; and etching the first semiconductor structure and the second semiconductor structure in a WL region to form a first active structure and a second active structure.

[0012] In one possible implementation, forming a memory based on an active structure includes: forming an isolation structure on both sides of a second active structure; forming a transistor on the isolation structure based on a first active structure; and forming a capacitor structure on the transistor.

[0013] In one possible implementation, a transistor is formed on the isolation structure based on a first active structure, including: forming a gate structure based on the first active structure; removing the gate structure in the BL region to form a third groove; depositing an insulating material on the gate structure in the WL region and in the third groove to form an insulating layer, the upper surface of the insulating layer being flush with the upper surface of a third mask located on the first active structure; removing the third mask to form a fourth groove; and forming a source-drain structure in the fourth groove.

[0014] In one possible implementation, the gate structure includes a gate electrode layer and a gate dielectric layer surrounding the gate electrode layer, the height of the gate electrode layer being lower than the height of the gate dielectric layer; removing the gate structure in the BL region to form a third groove includes: forming a sacrificial layer on the gate electrode layer located in the BL region, the upper surface of the sacrificial layer being flush with the upper surface of the gate dielectric layer; anisotropically etching the bottom of the sacrificial layer and the gate electrode layer located below the sacrificial layer to form the third groove; and removing the sacrificial layer.

[0015] In one possible implementation, ion implantation is performed on the second active structure to form a bit line (BL) structure, including: removing a substrate to expose a first material layer retained in the BL region, and an isolation structure and a second active structure in the WL region; forming a fourth mask on the isolation structure; and performing ion implantation on the first material layer retained in the BL region and the second active structure in the WL region based on the fourth mask to form the BL structure.

[0016] In one possible implementation, an insulating dielectric is deposited on both sides of the BL structure within the WL region to form a dielectric layer, comprising: thinning the isolation structure within the WL region so that the upper surface of the retained isolation structure is flush with the upper surface of the second active structure; and depositing an insulating dielectric on the retained isolation structure to form a dielectric layer, the height of which is the same as the height of the BL structure.

[0017] Thirdly, embodiments of this application provide a memory, which is fabricated using the fabrication method described in the first aspect and any of its embodiments, or using the fabrication method described in the second aspect and any of its embodiments, comprising: a BL structure and a memory, wherein the BL structure serves as the source / drain structure of the transistor in the memory; and a dielectric layer located on both sides of the BL structure within the WL region.

[0018] Fourthly, embodiments of this application provide a semiconductor device, which includes a memory as described in the third aspect above.

[0019] Fifthly, embodiments of this application provide an electronic device, which includes: a circuit board and a semiconductor device as described in the fourth aspect above, wherein the semiconductor device is disposed on the circuit board.

[0020] In this application, a first material layer and a second material layer with different doping concentrations are firstly stacked on a substrate along a first direction. The first and second material layers are then etched in the WL region to form a semiconductor structure and a BL structure. An insulating dielectric is deposited on both sides of the BL structure within the WL region to form a dielectric layer. The substrate is then flipped and removed to expose the semiconductor structure. The semiconductor structure is etched within the BL region to form an active structure, and a memory is formed based on the active structure. This application ensures self-alignment of the active region by integrally molding the BL portion. Furthermore, the insulating dielectric deposited on both sides of the BL structure within the WL region, with an air gap in the dielectric, reduces the parasitic capacitance of the BL structure, which is beneficial for optimizing device performance.

[0021] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. Attached Figure Description

[0022] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0023] Figure 1 This is a schematic diagram illustrating one implementation process of the memory fabrication method in this application.

[0024] Figure 2 This is a schematic diagram of another implementation process of the memory fabrication method in this application embodiment;

[0025] Figure 3 This is a top view of a memory in an embodiment of this application;

[0026] Figures 4 to 13 This is a schematic diagram of the memory structure in the first fabrication process according to an embodiment of this application;

[0027] Figure 14 This is a schematic diagram of the first structure of the memory in the embodiments of this application;

[0028] Figures 15 to 26 This is a schematic diagram of the memory structure in the second fabrication process according to an embodiment of this application;

[0029] Figure 27 This is a schematic diagram of a second structure of the memory in an embodiment of this application.

[0030] The above images:

[0031] 10. Memory; 11. Transistor; 111. Active structure (first active structure); 112. Source-drain structure; 113. Gate structure; 1131. Gate dielectric layer; 1132. Gate electrode layer; 12. First insulating layer; 13. Carrier wafer; 20. Substrate; 21. First material layer; 22. Second material layer; 23. First mask; 24. Semiconductor structure; 25. BL structure; 26. First isolation structure; 27. First dielectric layer; 28. Second mask; 29. ​​Second isolation structure; 30. Oxide layer; 31. Second insulating layer; 32. Second dielectric layer; 33. Capacitor structure; 34. First semiconductor structure; 35. Second semiconductor structure; 36. Third isolation structure; 37. Third mask; 38. Second active structure; 39. Fourth isolation structure; 40. Fourth mask. Detailed Implementation

[0032] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0033] With Moore's Law continuing to advance, further miniaturizing transistors is a hot research topic in the industry. Stacked transistors, through three-dimensional transistor stacking, can integrate two or more layers of transistors in a vertical space, helping to further increase transistor integration density.

[0034] In DRAM, ferroelectric random access memory (FeRAM), or other memories, a memory cell may include a transistor and a capacitor structure. The transistor is disposed on a substrate, and the capacitor structure is located at the end of the transistor furthest from the substrate; the transistor and the capacitor structure are electrically connected.

[0035] Taking DRAM as an example, the basic composition of DRAM is 1T1C. Currently, there are three main types of DRAM. The first type of DRAM has an area of ​​8F. 2 The first type is achieved by horizontally placing transistors and capacitors; the second type of DRAM has an area of ​​6F. 2 By tilting the transistor and capacitor structures, the density can be increased, thus achieving a smaller integration area; the third type of DRAM has an area of ​​4F. 2 By vertically placing transistors and capacitors, the vertical volume is fully utilized, enabling a smaller DRAM area. 4F 2Bottom-up DRAM, by fabricating vertical capacitors on vertical transistors, helps to further increase DRAM integration density and improve circuit performance, and is considered one of the important technologies for continuing the miniaturization of integrated circuits. However, the bottom-up BL structure of DRAM has large parasitic capacitance, which can affect device performance.

[0036] Based on this, embodiments of this application provide a method for fabricating a memory that can reduce the parasitic capacitance of the BL structure and is beneficial for optimizing device performance.

[0037] In some embodiments, the memory may include a plurality of memory cells, each memory cell may include a flip-chip stacked transistor and a capacitor structure (capacitor), wherein the capacitor structure is electrically connected to the transistor.

[0038] In some embodiments, a transistor may include a gate structure, a source structure, and a drain structure. The electrical connection between the capacitor structure and the transistor can be either between the source structure of the transistor and the capacitor structure, or between the drain structure of the transistor and the capacitor structure. The transistor controls the writing, modification, or reading of information in the capacitor structure. That is, the transistor acts as a selection device (or switching device) and can control the writing, modification, or reading of information in the capacitor structure.

[0039] In some embodiments, the capacitor structure may include a first electrode and a second electrode, and a dielectric layer located between the first electrode and the second electrode. Exemplarily, the first electrode may be electrically connected to the drain structure of a transistor, and the second electrode may be grounded.

[0040] In some embodiments, the memory cell may further include multiple word line (WL) structures and multiple bit line (BL) structures. The WL structure may be connected to the gate structure of a transistor to control the transistor's on and off states. The BL structure may be connected to the source or drain structure of a transistor to write data to a capacitor structure connected to the transistor when the transistor is on.

[0041] In the embodiments of this application, the transistor can be, for example, a vertical channel transistor (VCT), also known as a vertical gate ring transistor.

[0042] Figure 1 This is a schematic diagram illustrating one implementation process of the memory fabrication method in this application. Figure 1 As shown, the method for fabricating the memory in the embodiments of this application may include:

[0043] Step S110: A first material layer and a second material layer are sequentially stacked on the substrate along a first direction to form a first material layer.

[0044] In some embodiments, the doping concentration of the first material layer is different from that of the second material layer. The first direction is a direction perpendicular to the extension direction of the substrate.

[0045] For example, the substrate can be any semiconductor substrate such as a silicon substrate, germanium substrate, silicon-germanium substrate, or silicon carbide substrate.

[0046] Understandably, the doping concentration of the first material layer is different from that of the second material layer. In this way, the first material layer can be etched and used as the active structure of the transistor in the memory, while the second material layer, which is doped differently, can be used as the BL structure of the memory.

[0047] In some embodiments, the doping concentration of the second material layer can be higher than that of the first material layer. As a data transmission channel, the doping concentration of the BL structure primarily affects data transmission efficiency and noise performance. A higher doping concentration can improve the conductivity of the BL structure, reduce resistance, and thus accelerate data transmission speed.

[0048] Step S120: Etch the first material layer and the second material layer in the WL region to form a semiconductor structure and a BL structure.

[0049] In some embodiments, step S120 can be implemented as follows: forming a first mask on the second material layer, the first mask being used to locate the WL region; based on the first mask, etching the second material layer and the first material layer to form the BL structure and the semiconductor structure.

[0050] Since the memory cells include WL and BL regions, after the first and second material layers are sequentially stacked on the substrate, the WL and BL regions can be etched to form an active structure. First, the first and second material layers can be etched within the WL region to form the semiconductor structure and the BL structure. That is, after forming a mask through photolithography, etching is performed along the BL direction to form the semiconductor structure and the BL structure.

[0051] Understandably, when etching the WL region, a first mask can first be formed on the second material layer. This first mask is used to locate the WL region; therefore, the first mask covers a portion of the second material layer in the WL region and the entire second material layer in the BL region. By etching the second and first material layers based on the first mask, a BL structure and a semiconductor structure can be formed. The BL structure within the WL region is discontinuous, while the BL structure within the BL region is continuous. The semiconductor structure includes the active structure within the WL region and the first material layer within the BL region.

[0052] For example, the etching process can be at least one of dry etching, wet etching, reactive ion etching, etc.

[0053] In some embodiments, the first mask may be removed after the semiconductor structure and the BL structure are formed.

[0054] Step S130: Deposit insulating dielectric on both sides of the BL structure within the WL region to form a dielectric layer.

[0055] In some embodiments, step S130 can be implemented as follows: forming isolation structures on both sides of the semiconductor structure within the WL region; depositing an insulating dielectric on the isolation structures to form a dielectric layer, the height of which is the same as the height of the BL structure. For ease of distinction, this isolation structure is referred to as the first isolation structure.

[0056] In some embodiments, after etching the substrate, trenches can be formed at the etched locations, and these trenches can be filled with oxide to form a first isolation structure. For example, the first isolation structure may also be referred to as a shallow trench isolation (STI) structure. The oxide forming the first isolation structure may, for example, be silicon nitride (SiN, Si3N4), silicon dioxide (SiO2), or silicon oxycarbide (SiCO), etc.

[0057] In some embodiments, to facilitate subsequent processing, after the first isolation structure is formed, the first isolation structure can be polished or chemical-mechanical planarized (CMP) so that different regions of the first isolation structure have the same etching depth when the first isolation structure is subsequently etched, thereby making the top height of the exposed active structure the same.

[0058] In some embodiments, a portion of the first isolation structure may be etched first, such that the upper surface of the first isolation structure is lower than the lower surface of the BL structure, thereby exposing the BL structure and facilitating subsequent manipulation of the BL structure. The solvent used for etching the first isolation structure may, for example, be a dilute hydrofluoric acid (DHF) solution or a buffered oxide etch (BOE) solution.

[0059] Understandably, after forming the first isolation structure, an insulating dielectric can be deposited on both sides of the BL structure on the first isolation structure to form a first dielectric layer. Since the BL structure is discontinuous within the WL region, and the parasitic capacitance between the discontinuous BL structures is large, the deposition rate of the insulating dielectric can be controlled to create gaps in the first dielectric layer during the deposition process. These air gaps reduce the parasitic capacitance between the BL structures. For example, the insulating dielectric can be a dielectric material such as silicon nitride or silicon oxide.

[0060] Step S140: Wash and remove the substrate to expose the semiconductor structure.

[0061] Understandably, after forming the BL structure and dielectric layer, the BL structure and dielectric layer can be bonded to a carrier wafer, then flipped over to place the substrate on top. The substrate is then removed to expose the semiconductor structure, facilitating subsequent memory fabrication.

[0062] In some embodiments, an insulating material (such as silicon oxide) may be deposited on the BL structure and dielectric layer to form a first insulating layer, and the first insulating layer may be bonded to a carrier wafer, after which the wafer is flipped and the substrate is removed.

[0063] In one example, the substrate can be removed after wafer flipping using polishing or chemical mechanical planarization.

[0064] Step S150: Etch the semiconductor structure in the BL region to form an active structure.

[0065] Understandably, the aforementioned semiconductor structure includes the active structure within the WL region and the first material layer within the BL region. Therefore, after wafer fabrication, the back surface region needs to be etched, stopping at the BL structure, to form the active structure. That is, the first material layer is etched along the WL direction to form the active structure, which includes the active structure within the WL region and the active structure within the BL region.

[0066] In some embodiments, a second mask can be formed on the first material layer in the BL region and the active structure in the WL region. The second mask is used to locate the active structure in the BL region. Therefore, when etching downwards based on the second mask, the first material layer in the BL region can be etched, thus forming the active structure in the BL region, while the structure in the WL region remains unaffected.

[0067] In some embodiments, the second mask may be removed after the active structure is formed.

[0068] In some embodiments, after the active structure is formed, oxide material can be deposited on the BL structure within the BL region to form a second isolation structure.

[0069] Understandably, after the first and second isolation structures, the first and second isolation structures can be thinned to a predetermined height to expose the gate region of the back transistor, so as to facilitate the subsequent fabrication of the gate structure of the back transistor.

[0070] Step S160: Based on the active structure, form a memory.

[0071] In some embodiments, the implementation process of step S160 may include the following two steps: forming a transistor based on an active structure; and forming a capacitor structure on the transistor.

[0072] In some embodiments, the process of forming a transistor based on an active structure can be as follows: forming a gate structure based on the active structure; removing the gate structure in the BL region to form a first groove; depositing insulating material on the gate structure in the WL region and in the first groove to form an insulating layer, the upper surface of the insulating layer being flush with the upper surface of a third mask, the third mask being located on the active structure; removing the third mask to form a second groove; and forming a source / drain structure in the second groove. For ease of distinction, the insulating layer here is referred to as the second insulating layer.

[0073] In some embodiments, after the active structure is formed, a third mask can be formed on the active structure in the WL and BL regions, and the third mask exposes the gate region.

[0074] Understandably, after thinning the first and second isolation structures to a predetermined height, the gate region of the back-side transistor is exposed, forming a gate trench between the active structures. This allows for the deposition of insulating material at the gate trench to form a gate dielectric layer, and the deposition of metal material on the gate dielectric layer to form a gate electrode layer. The gate dielectric layer and the gate electrode layer together constitute the gate structure. The height of the gate electrode layer can be lower than the height of the gate dielectric layer.

[0075] For example, the gate dielectric layer can be composed of a silicon oxide layer plus a hafnium oxide layer with a high K value, and the thickness of the silicon oxide layer and the hafnium oxide layer can be determined according to the polarity and performance of the transistor.

[0076] For example, the gate electrode layer may be composed of multiple layers of electrode materials, each layer of which may include, but is not limited to, hafnium, zirconium, titanium, tantalum, aluminum, and alloys of these metals.

[0077] Since the WL structure in the WL region is connected to the gate structure of the transistor, the gate structure in the WL region is necessary, while the gate structure in the BL region should not exist. Therefore, the gate structure in the BL region can be selectively removed.

[0078] In some embodiments, the process of removing the gate structure in the BL region to form the first groove can be as follows: forming a sacrificial layer on the gate electrode layer located in the BL region, with the upper surface of the sacrificial layer flush with the upper surface of the gate dielectric layer; anisotropically etching the bottom of the sacrificial layer and the gate electrode layer located below the sacrificial layer to form the first groove.

[0079] Understandably, a sacrificial layer can be deposited on the gate electrode layer within the BL region, attaching to the bottom of the gate electrode layer, the sidewalls of the gate dielectric layer, and the sidewalls of the mask. The upper surface of the sacrificial layer is flush with the upper surface of the gate dielectric layer. Then, the bottom of the sacrificial layer and the gate electrode layer below the sacrificial layer are anisotropically etched to obtain the first groove. Since the anisotropic etching proceeds downwards from the bottom of the sacrificial layer, and a portion of the gate electrode layer remains below the sidewalls of the sacrificial layer, this portion of the gate electrode layer is preserved. The insulating material can, for example, be an oxide, nitride, or similar material. When depositing the sacrificial layer, a very thin film can be deposited on the surface of the substrate using atomic layer deposition (ALD).

[0080] In some embodiments, the sacrificial layer may be removed after the first groove is formed.

[0081] Understandably, after forming the first groove, insulating material can be deposited on the gate structure within the WL region and within the first groove to form a second insulating layer, the upper surface of which is flush with the upper surface of the third mask. The third mask can then be removed to form the second groove, and the source / drain structure of the transistor can be formed within the second groove. The second insulating layer serves to isolate the transistor from its source / drain structure. In the case of a VCT transistor formed in this embodiment, the source and drain structures of the VCT are approximately symmetrical. Therefore, for ease of explanation, the source / drain structure mentioned in this embodiment is abbreviated, specifically referring to the source structure and / or drain structure.

[0082] For example, ion implantation can be performed first in the second groove to deposit metal material, followed by annealing to form silicide. The silicide can then be used as the source / drain structure. This is only an illustrative example; the specific method can be determined based on actual needs. When using silicide as the source structure, the BL structure can be used as the drain structure. Conversely, when using silicide as the drain structure, the BL structure can be used as the source structure.

[0083] In some embodiments, an insulating material can be deposited on the gate structure within the WL region to form an isolation layer, so that only the BL region is processed. Thus, after removing the sacrificial layer, the isolation layer above the WL region can be removed to form a second insulating layer on both the WL and BL regions.

[0084] In some embodiments, after removing the sacrificial layer, an oxide material can be deposited within the groove in the BL region to form an oxide layer. Then, a second insulating layer is formed on the oxide layer in the BL region and the gate structure in the WL region. The oxide layer can also, for example, be formed by ALD deposition.

[0085] After the source-drain structure is formed, the capacitor structure of the memory can be formed on the transistor.

[0086] In some embodiments, the process of forming a capacitor structure on a transistor can be as follows: forming a dielectric layer on the source / drain structure; etching a portion of the dielectric layer to expose the source / drain structure; and forming a capacitor structure on the source / drain structure. For ease of distinction, the dielectric layer here is referred to as the second dielectric layer.

[0087] Understandably, an insulating dielectric can be deposited on the source / drain structure to form a second dielectric layer. Then, a portion of the second dielectric layer is etched to expose the underlying source / drain structure. A metal layer is first deposited on the source / drain structure, followed by a dielectric layer, and then another metal layer. This forms a capacitor structure including a first electrode, a second electrode, and a dielectric layer between the first and second electrodes, thus completing the memory fabrication. The dielectric layer between the capacitor structures serves as an isolation structure between them.

[0088] In this application, a first material layer and a second material layer with different doping concentrations are firstly stacked on a substrate along a first direction. The first and second material layers are then etched in the WL region to form a semiconductor structure and a BL structure. An insulating dielectric is deposited on both sides of the BL structure within the WL region to form a dielectric layer. The substrate is then flipped and removed to expose the semiconductor structure. The semiconductor structure is etched within the BL region to form an active structure, and a memory is formed based on the active structure. This application ensures self-alignment of the active region through integrated molding of the BL region. Furthermore, the insulating dielectric deposited on both sides of the BL structure within the WL region, with air gaps in the dielectric, reduces the parasitic capacitance of the BL structure, which is beneficial for optimizing device performance.

[0089] Figure 2 This is a schematic diagram illustrating another implementation of the memory fabrication method in this application. For example... Figure 2 As shown, the method for fabricating the memory in this application embodiment may include:

[0090] Step S210: Form an active structure on the substrate.

[0091] In some embodiments, the active structure includes a first active structure and a second active structure, wherein the first active structure is further away from the substrate than the second active structure.

[0092] In some embodiments, the implementation process of step S210 can be divided into the following three steps: Step 1: A first material layer and a second material layer are sequentially stacked on the substrate along a first direction; Step 2: A portion of the second material layer and the first material layer are etched in the BL region to form a first semiconductor structure and a second semiconductor structure; Step 3: The first semiconductor structure and the second semiconductor structure are etched in the WL region to form a first active structure and a second active structure.

[0093] In step one, the first material layer and the second material layer are doped in the same way.

[0094] For example, the substrate can be any semiconductor substrate such as a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, silicon-on-insulator substrate, etc.

[0095] Since the memory cells include WL and BL regions, after the first and second material layers are sequentially stacked on the substrate, the WL and BL regions can be etched to form an active structure. First, based on step two, the first and second material layers can be etched in the BL region to form a first semiconductor structure and a second semiconductor structure.

[0096] In some embodiments, step two can be implemented as follows: a second mask is formed on the second material layer, and the first mask is used to locate the BL region; based on the second mask, a portion of the second material layer and the first material layer is etched to form a first semiconductor structure and a second semiconductor structure. That is, after the mask is formed by photolithography, etching is performed along the WL direction to form the first semiconductor structure and the second semiconductor structure.

[0097] Understandably, a second mask can first be formed on the second material layer. This second mask is used to locate the BL region. Therefore, the second mask covers a portion of the second material layer in the BL region and the entire second material layer in the WL region. By etching the second material layer and a portion of the first material layer based on the second mask, a first semiconductor structure and a second semiconductor structure can be formed. The first semiconductor structure includes a first active structure in the BL region and a second material layer in the WL region. The second semiconductor structure includes a second active structure in the WL region, a portion of the first material layer, and the first material layer in the BL region.

[0098] For example, the etching process can be at least one of dry etching, wet etching, reactive ion etching, etc.

[0099] After forming the first semiconductor structure and the second semiconductor structure, the first semiconductor structure and the second semiconductor structure can be etched in the WL region based on step three to form the first active structure and the second active structure. That is, etching is performed along the BL direction, and the etching stops on the first material layer to form the first active structure and the second active structure.

[0100] In some embodiments, step three can be implemented as follows: forming a first mask on the second mask, the first mask being used to locate the region of BL; based on the first mask, etching the second mask, the first semiconductor structure, and the second semiconductor structure to form the first active structure and the second active structure.

[0101] Understandably, the BL region can be located using a first mask, and a second mask can be used to form the first mask. The first mask covers the entire second mask in the BL region and a portion of the second mask in the WL region. Thus, when etching downwards based on the first mask, the second mask, the second material layer, and the first material layer in the WL region can be etched to form the first active structure and the second active structure, while the structure in the BL region remains unaffected.

[0102] In some embodiments, after forming the first semiconductor structure and the second semiconductor in the etched BL region, an oxide material can be deposited on the first material layer retained in the BL region to form a third isolation structure.

[0103] Understandably, an oxide material can be deposited on the retained first material layer, such that the upper surface of the formed third isolation structure is flush with the upper surface of the second mask. For example, the third isolation structure can also be called a shallow trench isolation structure. The oxide forming the third isolation structure can, for example, be silicon nitride, silicon dioxide, or silicon oxycarbide, etc.

[0104] In some embodiments, the third isolation structure may also be polished or chemically mechanically planarized so that different regions of the third isolation structure have the same etching depth when the third isolation structure is subsequently etched, thereby making the top height of the exposed active structure the same.

[0105] Step S220: Based on the first active structure, form a memory.

[0106] In some embodiments, step S220 can be implemented as follows: forming an isolation structure on both sides of the second active structure; forming a transistor on the isolation structure based on the first active structure; and forming a capacitor structure on the transistor.

[0107] Understandably, after etching the WL region to form the first and second active structures, oxide material can be deposited on the substrate within the WL region to form the fourth isolation structure. After forming the third and fourth isolation structures, the third and fourth isolation structures can be thinned to a predetermined height to expose the first active structure so that transistors can be fabricated based on the first active structure.

[0108] In some embodiments, the process of forming a transistor based on the first active structure can be as follows: forming a gate structure based on the first active structure; removing the gate structure in the BL region to form a third groove; depositing insulating material on the gate structure in the WL region and in the third groove to form an insulating layer, the upper surface of the insulating layer being flush with the upper surface of the third mask, the third mask being located on the first active structure; removing the third mask to form a fourth groove; and forming a source / drain structure in the fourth groove. For ease of distinction, the insulating layer here is referred to as the second insulating layer.

[0109] Understandably, after thinning the first and second isolation structures to a predetermined height, the gate region of the back-side transistor is exposed, forming a gate trench between the first active structures. This allows for the deposition of insulating material at the gate trench to form a gate dielectric layer, and the deposition of metal material on the gate dielectric layer to form a gate electrode layer. The gate dielectric layer and the gate electrode layer together constitute the gate structure. The height of the gate electrode layer can be lower than the height of the gate dielectric layer.

[0110] For example, the gate dielectric layer can be composed of a silicon oxide layer plus a hafnium oxide layer with a high K value, and the thickness of the silicon oxide layer and the hafnium oxide layer can be determined according to the polarity and performance of the transistor.

[0111] For example, the gate electrode layer may be composed of multiple layers of electrode materials, each layer of which may include, but is not limited to, hafnium, zirconium, titanium, tantalum, aluminum, and alloys of these metals.

[0112] Since the WL structure in the WL region is connected to the gate structure of the transistor, the gate structure in the WL region is necessary, while the gate structure in the BL region may not exist. Therefore, the gate structure in the BL region can be selectively removed.

[0113] In some embodiments, the process of removing the gate structure in the BL region to form a third groove can be as follows: forming a sacrificial layer on the gate electrode layer located in the BL region, with the upper surface of the sacrificial layer flush with the upper surface of the gate dielectric layer; anisotropically etching the bottom of the sacrificial layer and the gate electrode layer located below the sacrificial layer to form a third groove.

[0114] Understandably, a sacrificial layer can be deposited on the gate electrode layer within the BL region, attaching to the bottom of the gate electrode layer, the sidewalls of the gate dielectric layer, and the sidewalls of the mask. The upper surface of the sacrificial layer is flush with the upper surface of the gate dielectric layer. Then, the bottom of the sacrificial layer and the gate electrode layer below the sacrificial layer are anisotropically etched to obtain a third groove. Since the anisotropic etching proceeds downwards from the bottom of the sacrificial layer, and a portion of the gate electrode layer remains below the sidewalls of the sacrificial layer, this portion of the gate electrode layer is preserved. The insulating material can, for example, be an oxide, nitride, or similar material. During the deposition of the sacrificial layer, a very thin film can be deposited on the surface of the substrate using an ALD (Alternating Deposition) method.

[0115] In some embodiments, the sacrificial layer may be removed after the third groove is formed.

[0116] Understandably, after forming the third groove, insulating material can be deposited on the gate structure within the WL region and within the third groove to form a second insulating layer, the upper surface of which is flush with the upper surface of the third mask. The third mask can then be removed to form a fourth groove, and the source / drain structure of the transistor can be formed within the fourth groove. The second insulating layer serves to isolate the transistor from its source / drain structure. In the case of a VCT transistor formed in this embodiment, the source and drain structures of the VCT are approximately symmetrical. Therefore, for ease of explanation, the source / drain structure mentioned in this embodiment is abbreviated, specifically referring to the source structure and / or drain structure.

[0117] For example, ion implantation can be performed first in the fourth groove to deposit metal material, followed by annealing to form silicide, which can then be used as the source / drain structure. This is only an example and can be determined as needed in actual operation.

[0118] In some embodiments, an insulating material can be deposited on the gate structure within the WL region to form an isolation layer, so that only the BL region is processed. Thus, after removing the sacrificial layer, the isolation layer above the WL region can be removed to form a second insulating layer on both the WL and BL regions.

[0119] In some embodiments, after removing the sacrificial layer, an oxide material can be deposited within the groove in the BL region to form an oxide layer. Then, a second insulating layer is formed on the oxide layer in the BL region and the gate structure in the WL region. The oxide layer can also, for example, be formed by ALD deposition.

[0120] After the source-drain structure is formed, the capacitor structure of the memory can be formed on the transistor.

[0121] In some embodiments, the process of forming a capacitor structure on a transistor can be as follows: forming a dielectric layer on the source / drain structure; etching a portion of the dielectric layer to expose the source / drain structure; and forming a capacitor structure on the source / drain structure. For ease of distinction, the dielectric layer here is referred to as the second dielectric layer.

[0122] Understandably, an insulating dielectric can be deposited on the source / drain structure to form a second dielectric layer. Then, a portion of the second dielectric layer is etched to expose the underlying source / drain structure. A metal layer is first deposited on the source / drain structure, followed by a dielectric layer, and then another metal layer. This forms a capacitor structure including a first electrode, a second electrode, and a dielectric layer between the first and second electrodes, thus completing the memory fabrication. The dielectric layer between the capacitor structures serves as an isolation structure between them.

[0123] Step S230: The memory is flipped and the substrate is removed to expose the second active structure.

[0124] Understandably, after the memory is formed, it can be bonded to a carrier wafer, then flipped over to place the substrate on top, and then the substrate is removed. Since the etching in step S210 involves etching the entire first material layer in the WL region and a portion of the first material layer in the BL region, after flipping the memory and removing the substrate, the first material layer remaining in the BL region, as well as the second active structure in the WL region and the fourth isolation structures on both sides, are exposed.

[0125] In some embodiments, an insulating material (such as silicon oxide) may be deposited on the flip chip to form a first insulating layer, and the first insulating layer may be bonded to a carrier wafer, after which the wafer may be flipped and the substrate removed.

[0126] In one example, the substrate can be removed after wafer flipping using polishing or chemical mechanical planarization.

[0127] Step S240: Ion implantation is performed on the second active structure to form a BL structure.

[0128] In some embodiments, step S240 can be implemented as follows: forming a fourth mask on the fourth isolation structure in the WL region; and performing ion implantation on the first material layer retained in the BL region and the second active structure in the WL region based on the fourth mask to form the BL structure.

[0129] Understandably, after removing the substrate, the first material layer remaining in the BL region, the second active structure in the WL region, and the fourth isolation structures on both sides are exposed. A fourth mask is formed on the fourth isolation structure, and ion implantation is performed based on the fourth mask. Thus, the areas covered by the fourth mask are not ion implanted. Therefore, after ion implantation, the first material layer in the BL region and a portion of the second active structure in the WL region can form the BL structure. When the silicide formed in step S220 is used as the source structure, the BL structure can be used as the drain structure. When the silicide is used as the drain structure, the BL structure can be used as the source structure.

[0130] Step S250: Deposit insulating dielectric on both sides of the BL structure within the WL region to form a dielectric layer.

[0131] In some embodiments, step S250 can be implemented by: thinning the fourth isolation structure in the WL region so that the upper surface of the retained fourth isolation structure is flush with the upper surface of the second active structure; depositing an insulating dielectric on the retained fourth isolation structure to form a first dielectric layer, the height of the first dielectric layer being the same as the height of the BL structure.

[0132] Understandably, after the BL structure is formed, the upper surface of the fourth isolation structure is flush with the upper surface of the BL structure. Therefore, the fourth isolation structure can be thinned down to below the BL structure, exposing the BL structure within the WL region. Then, an insulating dielectric is deposited on both sides of the BL structure on the fourth isolation structure to form the first dielectric layer. Since the BL structure is discontinuous within the WL region, and the parasitic capacitance between the discontinuous BL structures is large, the deposition rate of the insulating dielectric can be controlled to create gaps in the first dielectric layer during deposition. These air gaps reduce the parasitic capacitance between the BL structures. For example, the insulating dielectric can be a dielectric material such as silicon nitride or silicon oxide.

[0133] In this embodiment, an active structure is first formed on a substrate, and a memory is formed based on the first active structure away from the substrate. The memory is then flipped and the substrate is removed to expose the second active structure. An insulating dielectric is deposited on both sides of the BL structure within the WL region to form a dielectric layer. This application ensures self-alignment of the active region by integrally molding the WL portion. Moreover, the insulating dielectric deposited on both sides of the BL structure within the WL region, which contains air gaps, can reduce the parasitic capacitance of the BL structure, thus optimizing device performance.

[0134] Furthermore, the two solutions provided in this application correspond to the integrated molding of BL and WL, respectively, which enables self-alignment of the active regions before and after wafer fabrication. Moreover, the two solutions in this application separate the fabrication of BL and WL, which is beneficial for optimizing the key processes of the two fabrications separately, with minimal mutual impact, and is compatible with current DRAM fabrication processes.

[0135] The following describes the fabrication method of the memory provided in this application, taking the active structure in VCT as a nanowire structure as an example. First, the first fabrication process is introduced, which involves fabricating a BL structure on the front side and a transistor and capacitor structure on the back side. Figure 3 This is a top view of a memory in an embodiment of this application. It should be noted that, for ease of understanding, only the nanowire structure, the BL structure, and the WL structure are shown in the top view. The AA' direction is the direction of the memory along the tangent of the BL structure; the BB' direction is the direction of the memory along the tangent of the WL structure. Figures 4 to 13 This is a schematic diagram of the memory structure in the first fabrication process according to an embodiment of this application. Figure 14 This is a schematic diagram of a first structure of the memory in an embodiment of this application. Wherein, Figures 4 to 14 (a) is a cross-sectional view of the memory along the BL structure (i.e., the AA' direction). Figures 4 to 14 (b) is a cross-sectional view of the memory along the tangential direction of the WL structure (i.e., the BB' direction).

[0136] In one example, the fabrication process of memory 10 may include the following steps:

[0137] Step 1: Sequentially form a first material layer 21 and a second material layer 22 on the original substrate 20 to obtain the following: Figure 4 The structure shown.

[0138] In this embodiment, the doping concentration of the second material layer is higher than that of the first material layer.

[0139] For example, a highly doped silicon layer can be epitaxially grown on a silicon substrate as the BL structure of a memory.

[0140] In some embodiments, a highly doped BL layer can also be formed on the silicon substrate by ion implantation on the top layer.

[0141] Step 2: A first mask 23 is formed on the second material layer 22. The first mask 23 is used to define the active structure of the WL region. Then, based on the first mask 23, the second material layer 22 and the first material layer 21 of the WL region are etched sequentially until the substrate 20 is formed to form the semiconductor structure 24 and the BL structure 25 of the WL region, resulting in the following: Figure 5 The structure shown.

[0142] like Figure 5 As shown in (a) above, the BL structure is a connected structure within the BL region. Figure 5 As shown in (b) in the diagram, the BL structure is a disconnected structure in the WL region.

[0143] Step 3: Deposit oxide material on both sides of the semiconductor structure 24 to form the first isolation structure 26, resulting in... Figure 6 The structure shown.

[0144] Understandably, the upper surface of the first isolation structure 26 is lower than the lower surface of the BL structure 25.

[0145] Step 4: Remove the first mask 23 and deposit an insulating dielectric on both sides of the BL structure 25 within the WL region to form the first dielectric layer 27, resulting in... Figure 7 The structure shown.

[0146] Understandably, the parasitic capacitance of the BL structure can be reduced by controlling the deposition rate to form an air gap.

[0147] Step 5: Deposit insulating material on the BL structure 25 to form the first insulating layer 12, and bond the first insulating layer 12 to the carrier wafer 13. Then, flip the wafer to obtain the following: Figure 8 The structure shown.

[0148] Step 6: Remove substrate 20 to isolation structure 26 to obtain as shown. Figure 9 The structure shown.

[0149] Step 7: Form a second mask 28 on the first material layer in the BL region and the semiconductor structure and first isolation structure 26 in the WL region. The second mask 28 is used to define the active structure in the BL region, resulting in... Figure 10 The structure shown.

[0150] Step 8: Etch based on the second mask 28 to form the active structure 111, resulting in... Figure 11 The structure shown.

[0151] Step 9: Remove the second mask 28 to obtain the following result. Figure 12 The structure shown.

[0152] Step 10: Deposit oxide material on the BL structure 25 within the BL region to form a second isolation structure 29, resulting in... Figure 13 The structure shown.

[0153] Understandably, the height of the second isolation structure 29 is the same as the height of the first isolation structure 26.

[0154] Step 11: Fabricate transistor and capacitor structures to obtain... Figure 14The structure shown.

[0155] Understandably, a third mask can first be formed on the active structure 111. Then, an insulating material is selectively deposited on the surface of the active structure 111 to form a gate dielectric layer 1131. A metal material is then deposited on the gate dielectric layer 1131 and CMPed to a certain height to form a gate electrode layer 1132. This forms the gate structure 113. Next, an isolation layer is formed by photolithography and etching to cover the WL region, facilitating the processing of the BL region. Subsequently, a sacrificial layer can be deposited on the gate electrode layer 1132, attached to the bottom of the gate electrode layer 1132, the sidewalls of the gate dielectric layer 1131, and the sidewalls of the third mask. The bottom of the sacrificial layer and the gate electrode layer 1132 below the sacrificial layer are anisotropically etched. The sacrificial layer is then removed to form a groove, and an oxide material is deposited within the groove to form an oxide layer 30. The isolation layer above the WL region is removed, and an insulating material (such as SiN) is deposited in both regions to form a second insulating layer 31. The third mask is selectively etched to form a groove, and a source / drain structure 112 is formed within the groove. An insulating dielectric is deposited on the source / drain structure 112 to form a second dielectric layer 32. A portion of the second dielectric layer 32 is etched to expose the source / drain structure 112, and a capacitor structure 33 is formed on the source / drain structure 112. The capacitor structure may include the deposition of an upper metal plate, a dielectric layer, and a lower metal plate. Figure 14 This is a simplified representation. Here, the drain structure of the transistor is connected to the BL structure 25, and the source structure of the transistor is connected to the capacitor structure 33.

[0156] In this embodiment, a first material layer and a second material layer with different doping concentrations are firstly stacked sequentially on a substrate along a first direction. The first and second material layers are etched in the WL region to form a semiconductor structure and a BL structure. An insulating dielectric is deposited on both sides of the BL structure within the WL region to form a dielectric layer. Then, the substrate is flipped and removed to expose the semiconductor structure. The semiconductor structure is etched within the BL region to form an active structure, and a memory is formed based on the active structure. This application ensures self-alignment of the active region by integrally molding the BL portion. Furthermore, the insulating dielectric deposited on both sides of the BL structure within the WL region, with an air gap in the dielectric, reduces the parasitic capacitance of the BL structure, which is beneficial for optimizing device performance.

[0157] The second fabrication process is described below, which involves fabricating transistor and capacitor structures on the front side and BL structures on the back side. Figures 15 to 26 This is a schematic diagram of the memory structure in the second fabrication process according to an embodiment of this application. Figure 27 This is a schematic diagram of a second structure of the memory in an embodiment of this application. Figures 15 to 27(a) is a cross-sectional view of the memory along the BL structure (i.e., the AA' direction). Figures 15 to 27 (b) is a cross-sectional view of the memory along the tangential direction of the WL structure (i.e., the BB' direction).

[0158] In one example, the fabrication process of memory 10 may include the following steps:

[0159] Step 1: Sequentially form a first material layer 21 and a second material layer 22 on the substrate 20 to obtain the following... Figure 15 The structure shown.

[0160] The second step involves forming a second mask 28 on the second material layer 22. The second mask 28 defines the active structure of the BL region. Then, based on the second mask 28, a portion of the second material layer 22 and the first material layer 21 in the BL region are etched to form the first semiconductor structure 34 and the second semiconductor structure 35 in the BL region, resulting in... Figure 16 The structure shown.

[0161] Step 3: Deposit oxide material on the first material layer retained in the BL region to form the third isolation structure 36, resulting in... Figure 17 The structure shown.

[0162] Step 4: Form a first mask 23 on the second mask. The first mask 23 is used to locate the active structure in the WL region. Based on the first mask 23, etch the second mask 28, the second material layer, and the first material layer in the WL region to form a third mask 37, a first active structure 111, and a second active structure 38, resulting in... Figure 18 The structure shown.

[0163] Step 5: Remove the first mask 23 to obtain the following result. Figure 19 The structure shown.

[0164] Step 6: Deposit oxide material on the substrate within the WL region and perform CMP to form the fourth isolation structure 39, resulting in... Figure 20 The structure shown.

[0165] Understandably, the fourth isolation structure 39 is higher than the third isolation structure 36.

[0166] Step 7: Thin the third isolation structure 36 and the fourth isolation structure 39 to a preset height to expose the first active structure 111, resulting in the following: Figure 21 The structure shown.

[0167] Step 8: Based on the first active structure 111, form the transistor and capacitor structure 33 to obtain the following... Figure 22 The structure shown.

[0168] Understandably, an insulating material can be selectively deposited on the surface of the first active structure 111 to form a gate dielectric layer 1131. A metal material can then be deposited on the gate dielectric layer 1131 and CMPed to a certain height to form a gate electrode layer 1132, thus constituting the gate structure 113. Next, an isolation layer is formed by photolithography and etching to cover the WL region, facilitating the processing of the BL region. Subsequently, a sacrificial layer can be deposited on the gate electrode layer 1132, attached to the bottom of the gate electrode layer 1142, the sidewall of the gate dielectric layer 1131, and the sidewall of the third mask 37. The bottom of the sacrificial layer and the gate electrode layer 1132 located below the sacrificial layer are anisotropically etched. Then, the sacrificial layer is removed to form a groove, and an oxide material is deposited in the groove to form an oxide layer 30. The isolation layer above the WL region is removed, and an insulating material (such as SiN) is deposited in the two regions to form a second insulating layer 31. The third mask 37 is selectively etched to form a groove, and a source / drain structure 112 is formed in the groove. An insulating dielectric is deposited on the source / drain structure 112 to form a second dielectric layer 32. A portion of the second dielectric layer 32 is etched to expose the source / drain structure 112, and a capacitor structure 33 is formed on the source / drain structure 112.

[0169] Step 9: Deposit insulating material on the transistor to form a first insulating layer 12, and bond the first insulating layer 12 to the carrier wafer 13. Then, flip the wafer to obtain the desired result. Figure 23 The structure shown.

[0170] Step 10: Remove substrate 20 to expose the first material layer retained in the BL region, the second active structure in the WL region, and the fourth isolation structures 39 on both sides. Then, form a fourth mask 40 on the fourth isolation structure 39. Based on the fourth mask 40, perform ion implantation on the first material layer in the BL region and the second active structure in the WL region to form the BL structure 25, resulting in... Figure 24 The structure shown.

[0171] Step 11: Remove the fourth mask 40 to obtain the following result. Figure 25 The structure shown.

[0172] Step 12: Thin the lower surface of the fourth isolation structure 39 to the BL structure 25 so that the height of the thinned fourth isolation structure 39 is the same as the height of the third isolation structure 36, resulting in the following... Figure 26 The structure shown.

[0173] Step 13: Deposit insulating dielectric on both sides of the BL structure 25 within the WL region to form the first dielectric layer 27, resulting in... Figure 27 The structure shown.

[0174] In this embodiment, an active structure is first formed on a substrate, and a memory is formed based on the first active structure away from the substrate. The memory is then flipped and the substrate is removed to expose the second active structure. An insulating dielectric is deposited on both sides of the BL structure within the WL region to form a dielectric layer. This application ensures self-alignment of the active region by integrally molding the WL portion. Moreover, the insulating dielectric deposited on both sides of the BL structure within the WL region, which contains air gaps, can reduce the parasitic capacitance of the BL structure, thus optimizing device performance.

[0175] Furthermore, based on the active region self-alignment, this application can optimize the BL and WL sections separately. Apart from thermal budget considerations, the impact of WL fabrication on BL does not need to be considered. Therefore, the process optimization of BL and WL can be performed separately. For example, introducing an air gap in the isolation WL section can effectively reduce the parasitic capacitance of the BL section, which is beneficial to the optimization of device performance.

[0176] Furthermore, the memory provided in this application embodiment can be detected using detection and analysis instruments, such as scanning electron microscope (SEM), transmission electron microscope (TEM), and scanning transmission electron microscopy (STEM). Taking TEM as an example, this application embodiment can use TEM slicing to detect the structure of the above-mentioned memory. It can be observed that the cross-section contains the 1T1C structure in the basic structure of the memory, and that air gaps exist in the BL part.

[0177] This application provides a semiconductor device, including a memory as described in the above embodiments. Specific limitations of the memory can be found in the description of the memory described above, and will not be repeated here.

[0178] This application provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiments, wherein the semiconductor device is disposed on the circuit board. The semiconductor device includes the memory described above. Specific limitations of the memory can be found in the description of the memory described above, and will not be repeated here.

[0179] In the description of the embodiments in this application, the terms "an embodiment," "an example," "a specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this application. In this application, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine different embodiments or examples described in this application, as well as features of different embodiments or examples.

[0180] The above description is merely a preferred embodiment of this application and is not intended to limit the application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for fabricating a memory, characterized in that, The method includes: A first material layer and a second material layer are sequentially stacked on a substrate along a first direction, wherein the doping concentration of the first material layer and the doping concentration of the second material layer are different. The first material layer and the second material layer are etched in the word line WL region to form a semiconductor structure and a bit line BL structure; An isolation structure is formed on both sides of the semiconductor structure within the WL region; An insulating dielectric is deposited on the isolation structure to form a dielectric layer, the height of which is the same as the height of the BL structure; The substrate is flipped and removed to expose the semiconductor structure; The semiconductor structure is etched within the BL region to form an active structure; Based on the active structure, a memory is formed, wherein the BL structure serves as the source and drain structure of the transistors in the memory.

2. The method according to claim 1, characterized in that, The etching of the first material layer and the second material layer in the word line WL region to form a semiconductor structure and a bit line BL structure includes: A first mask is formed on the second material layer, and the first mask is used to locate the WL region; Based on the first mask, the second material layer and the first material layer are etched to form the BL structure and the semiconductor structure.

3. The method according to claim 1, characterized in that, The formation of a memory based on the active structure includes: Based on the aforementioned active structure, a transistor is formed; A capacitor structure is formed on the transistor.

4. The method according to claim 1, characterized in that, The process of forming a transistor based on the active structure includes: Based on the active structure, a gate structure is formed; Remove the gate structure within the BL region to form a first groove; An insulating material is deposited on the gate structure within the WL region and within the first groove to form an insulating layer, the upper surface of which is flush with the upper surface of a third mask located on the active structure. Remove the third mask to form the second groove; A source / drain structure is formed within the second groove.

5. The method according to claim 4, characterized in that, The gate structure includes a gate electrode layer and a gate dielectric layer surrounding the gate electrode layer, wherein the height of the gate electrode layer is lower than the height of the gate dielectric layer; The step of removing the gate structure within the BL region to form the first groove includes: A sacrificial layer is formed on the gate electrode layer located within the BL region, the upper surface of the sacrificial layer being flush with the upper surface of the gate dielectric layer; The bottom of the sacrificial layer and the gate electrode layer located below the sacrificial layer are anisotropically etched to form the first groove; Remove the sacrificial layer.

6. A method for fabricating a memory, characterized in that, The method includes: A first material layer and a second material layer are sequentially stacked on a substrate along a first direction; A portion of the second material layer and the first material layer are etched within the bit line BL region to form a first semiconductor structure and a second semiconductor structure; The first semiconductor structure and the second semiconductor structure are etched in the word line WL region to form a first active structure and a second active structure, wherein the first active structure is farther away from the substrate than the second active structure. A memory is formed based on the first active structure; The memory is flipped and the substrate is removed to expose the second active structure; Ion implantation is performed on the second active structure to form a BL structure, which serves as the source / drain structure of the transistor in the memory. An insulating dielectric is deposited on both sides of the BL structure within the WL region to form a dielectric layer.

7. The method according to claim 6, characterized in that, The formation of a memory based on the first active structure includes: An isolation structure is formed on both sides of the second active structure; A transistor is formed on the isolation structure based on the first active structure; A capacitor structure is formed on the transistor.

8. The method according to claim 7, characterized in that, The step of forming a transistor on the isolation structure based on the first active structure includes: A gate structure is formed based on the first active structure; Remove the gate structure within the BL region to form a third groove; An insulating material is deposited on the gate structure within the WL region and within the third groove to form an insulating layer, the upper surface of which is flush with the upper surface of the third mask, which is located on the first active structure. Remove the third mask to form the fourth groove; A source-drain structure is formed within the fourth groove.

9. The method according to claim 8, characterized in that, The gate structure includes a gate electrode layer and a gate dielectric layer surrounding the gate electrode layer, wherein the height of the gate electrode layer is lower than the height of the gate dielectric layer; The step of removing the gate structure within the BL region to form the third groove includes: A sacrificial layer is formed on the gate electrode layer located within the BL region, the upper surface of the sacrificial layer being flush with the upper surface of the gate dielectric layer; The bottom of the sacrificial layer and the gate electrode layer located below the sacrificial layer are anisotropically etched to form the third groove; Remove the sacrificial layer.

10. The method according to claim 7, characterized in that, The step of ion implantation on the second active structure to form a BL structure includes: A fourth mask is formed on the isolation structure within the WL region; Based on the fourth mask, ion implantation is performed on the first material layer retained in the BL region and the second active structure in the WL region to form the BL structure.

11. The method according to claim 7, characterized in that, The deposition of an insulating dielectric on both sides of the BL structure within the WL region to form a dielectric layer includes: The isolation structure is thinned within the WL region so that the upper surface of the retained isolation structure is flush with the upper surface of the second active structure; An insulating dielectric is deposited on the retained isolation structure to form the dielectric layer, the height of which is the same as the height of the BL structure.

12. A memory, manufactured using any one of the methods described in claims 1 to 5 or 6 to 11, characterized in that, include: Bit line BL structure, the BL structure serving as the source and drain structure of transistors in the memory; A dielectric layer located on both sides of the BL structure within the word line WL region.

13. A semiconductor device, characterized in that, include: The memory as described in claim 12.

14. An electronic device, characterized in that, include: The circuit board and the semiconductor device as claimed in claim 13, wherein the semiconductor device is disposed on the circuit board.

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