A method for preparing an LDMOS device, and an LDMOS device

Abstract

The present invention relates to a preparation method of an LDMOS device and an LDMOS device, and relates to the field of semiconductor technology. In the preparation method, a first etching machine is used for a self-aligned polysilicon material layer, and a second etching machine is used for a shielding material layer. A dedicated etching machine is used for different materials, so that the accuracy of etching can be improved, thereby avoiding the incomplete etching of the material to be etched or the material loss caused by over-etching during etching, and improving the yield of the product. In addition, the formed LDMOS device has a metal silicide covering the shielding layer as a supplementary gate of the LDMOS device gate, which increases the length of the conductive channel, so that the LDMOS device has better high-voltage resistance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing an LDMOS device and an LDMOS device. Background Art

[0002] In the existing power management integrated circuit (PMIC) series products, LDMOS devices are widely used due to their high gain, high breakdown voltage and good thermal stability.

[0003] When preparing LDMOS devices, over-etching is performed during the etching process to ensure that all materials that need to be removed are completely removed. If the over-etching amount is insufficient, the width of the metal silicide area will be too small; if the over-etching amount is too much, the sidewall and sidewall oxide layer of the gate structure will be seriously damaged, and some areas will suffer from severe silicon loss. Obviously, too much or too little over-etching will cause unexpected deviations in the prepared device and reduce the yield.

[0004] Based on this, how to achieve clean etching of the material to be etched without causing structural loss during etching has become a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0005] Based on this, it is necessary to provide a method for preparing an LDMOS device and an LDMOS device to address the problem that an excessive or insufficient amount of over-etching may cause unexpected deviations in the device.

[0006] In order to achieve the above object, on the one hand, the present invention provides a method for preparing an LDMOS device, comprising:

[0007] Providing a substrate, the substrate comprising a substrate and a gate structure, wherein the gate structure is located on a surface of the substrate;

[0008] Forming a shielding material layer, a self-aligned polysilicon material layer and a patterned photoresist in sequence on the substrate and the gate structure;

[0009] Based on the patterned photoresist, a first etching machine is used to at least etch the self-aligned polysilicon material layer to form a self-aligned polysilicon layer;

[0010] removing at least a portion of the patterned photoresist;

[0011] Using the self-aligned polysilicon layer as a mask layer, or using the self-aligned polysilicon layer and the remaining patterned photoresist as a mask layer, a second etching machine is used to etch the shielding material layer to form a shielding layer, wherein the shielding layer has first openings and second openings alternately arranged along a first direction, the first openings expose a portion of the upper surface of the gate structures adjacent along the first direction and the substrate therebetween, and the second openings expose the substrate between the gate structures adjacent along the first direction; the first direction is parallel to the substrate;

[0012] A metal silicide process is performed on the self-aligned polysilicon layer and the exposed upper surfaces of the substrate and the gate structure to form a metal silicide layer.

[0013] In one embodiment, the step of etching at least the self-aligned polysilicon material layer using a first etching machine based on the patterned photoresist to form a self-aligned polysilicon layer includes:

[0014] Using the first etching machine, dry-etching the self-aligned polysilicon material layer and the shielding material layer of a preset thickness;

[0015] The self-aligned polysilicon layer is used as a mask layer, or the self-aligned polysilicon layer and the remaining patterned photoresist are used as mask layers, and a second etching machine is used to etch the shielding material layer to form a shielding layer, comprising:

[0016] The second etching machine is used to perform dry etching on the remaining shielding material layer.

[0017] In one embodiment, the preset thickness is 1 / 4 to 1 / 2 of the thickness of the shielding material layer.

[0018] In one embodiment, the step of etching at least the self-aligned polysilicon material layer using a first etching machine based on the patterned photoresist to form a self-aligned polysilicon layer includes:

[0019] The first etching machine is used to perform dry etching on the self-aligned polysilicon material layer.

[0020] In one embodiment, the second etching machine includes a first sub-etching machine and a second sub-etching machine; the self-aligned polysilicon layer is used as a mask layer, or the self-aligned polysilicon layer and the remaining patterned photoresist are used as a mask layer, and the second etching machine is used to etch the shielding material layer to form a shielding layer, including:

[0021] Using the first sub-etching machine, dry-etching a portion of the shielding material layer to form a shielding intermediate layer, wherein the shielding intermediate layer includes a first shielding portion and a second shielding portion, the thickness of the second shielding portion is less than the thickness of the first shielding portion, and the orthographic projection area of ​​a side of the first shielding portion close to the base on the substrate is greater than the orthographic projection area of ​​a side of the first shielding portion close to the self-aligned polysilicon layer on the substrate;

[0022] The second sub-etching machine is used to perform wet etching on the shielding intermediate layer to remove the second shielding portion to form a shielding layer.

[0023] In one embodiment, in the first opening, a portion of the surface and sidewall of the gate structure is exposed between the second shielding portion and the first shielding portion.

[0024] In one of the embodiments, in the second direction, the orthographic projection areas of the side walls of the second shielding portion on the substrate increase sequentially, and the second direction is perpendicular to the substrate and points from the substrate to the gate structure.

[0025] In one embodiment, the thickness of the second shielding portion is 30 angstroms to 50 angstroms.

[0026] In one embodiment, the metal silicide layer includes a first conductive portion, a second conductive portion, a third conductive portion and a fourth conductive portion, the first conductive portion is located on one side of the second opening, the second conductive portion is located on one side of the shielding layer, the third conductive portion is located on one side of a portion of the upper surface of the gate structure, and the fourth conductive portion is located on one side of the substrate in the first opening; after the metal silicide process is performed on the self-aligned polysilicon layer and the exposed substrate and the portion of the upper surface of the gate structure to form the metal silicide layer, the method further includes:

[0027] Contact structures are formed on the first conductive portion, the second conductive portion, the third conductive portion, and the fourth conductive portion.

[0028] On the other hand, the present application further provides an LDMOS device, which is manufactured by any of the above-mentioned methods for manufacturing an LDMOS device, and the LDMOS device comprises:

[0029] A substrate, comprising a substrate and a gate structure, wherein the gate structure is located on a surface of the substrate;

[0030] a shielding layer, the shielding layer covering a portion of the gate structure and a portion of the substrate, the shielding layer having a first opening and a second opening alternately arranged along a first direction, the first opening exposing a portion of the upper surface of the gate structure adjacent to each other along the first direction and the substrate therebetween, the second opening exposing the substrate between the gate structures adjacent to each other along the first direction, and the first direction being parallel to the substrate;

[0031] A metal silicide layer covers the shielding layer and the exposed upper surfaces of the substrate and the gate structure.

[0032] In one embodiment, the metal silicide layer includes a first conductive portion, a second conductive portion, a third conductive portion and a fourth conductive portion, the first conductive portion is located on one side of the second opening, the second conductive portion is located on one side of the shielding layer, the third conductive portion is located on one side of a portion of the upper surface of the gate structure, and the fourth conductive portion is located on one side of the substrate in the first opening; the LDMOS device also includes: a plurality of contact structures, the plurality of contact structures are respectively in contact with the first conductive portion, the second conductive portion, the third conductive portion and the fourth conductive portion of the metal silicide layer.

[0033] Compared with the prior art, the above technical solution has the following unexpected technical effects:

[0034] In the preparation method of the LDMOS device, a first etching machine is used for the self-aligned polysilicon material layer. Since the first etching machine is targeted at the self-aligned polysilicon material layer, the etching rate during etching is relatively high. A second etching machine is used for the shielding material layer. The second etching machine is targeted at the shielding material layer. When the self-aligned polysilicon layer is used as the mask layer, the second etching machine has little effect on the self-aligned polysilicon layer when etching the shielding material layer. Using dedicated etching machines for different materials can improve the accuracy of etching, thereby avoiding incomplete etching of the material to be etched or material loss due to over-etching during etching, and improving the yield of the product.

[0035] In the LDMOS device, since the metal silicide covering the shielding layer serves as a supplementary gate of the LDMOS device gate, the length of the conductive channel is increased, so that the LDMOS device has better high-voltage resistance performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 A schematic diagram of an existing LDMOS device structure with insufficient etching;

[0038] Figure 2 A schematic diagram of an existing LDMOS device structure with excessive etching;

[0039] Figure 3 A schematic diagram of a preparation process of an LDMOS device provided in an embodiment of the present application;

[0040] Figure 4 A partial structural schematic diagram of an LDMOS device provided in an embodiment of the present application;

[0041] Figure 5 A partial structural schematic diagram of another LDMOS device provided in an embodiment of the present application;

[0042] Figure 6 A partial structural diagram of another LDMOS device provided in an embodiment of the present application;

[0043] Figure 7 A partial structural diagram of another LDMOS device provided in an embodiment of the present application;

[0044] Figure 8 A partial structural diagram of another LDMOS device provided in an embodiment of the present application;

[0045] Fig. 9 A partial structural diagram of another LDMOS device provided in an embodiment of the present application;

[0046] Fig.10 A partial structural diagram of another LDMOS device provided in an embodiment of the present application;

[0047] Fig.11 A partial structural diagram of another LDMOS device provided in an embodiment of the present application;

[0048] Fig.12 A partial structural diagram of another LDMOS device provided in an embodiment of the present application;

[0049] Fig.13A partial structural diagram of another LDMOS device provided in an embodiment of the present application;

[0050] Fig.14 A partial structural diagram of another LDMOS device provided in an embodiment of the present application.

[0051] Explanation of the reference numerals: 01-substrate; 02-gate structure; 02a polysilicon gate; 02b gate oxide layer; 02d silicon oxide layer; 02e-silicon nitride layer; 03-shielding material layer; 04-self-aligned polysilicon material layer; 05-patterned photoresist; 06-self-aligned polysilicon layer; 07-shielding layer; 08-shielding intermediate layer; 08a-first shielding portion; 08b second shielding portion; 09-metal silicide layer; 09a-first conductive portion; 09b-second conductive portion; 09c-third conductive portion; 09d-fourth conductive portion; 10-contact structure. DETAILED DESCRIPTION

[0052] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0054] It should be understood that when a layer is referred to as being "on," "adjacent to," or "connected to" another layer, it can be directly on, adjacent to, or connected to the other layer, or intervening layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," or "directly connected to" another layer, there are no intervening layers.

[0055] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0056] Based on the content in the background technology, a self-aligned polysilicon layer (SA-poly) and a self-aligned silicide shielding layer (SAB) are provided in an LDMOS device. Since the setting of the self-aligned silicide shielding layer shields the specific area where silicide does not need to be formed, the parasitic resistance of the LDMOS device finally formed is low, which further improves the performance of the LDMOS device. When forming the self-aligned polysilicon layer and the self-aligned silicide shielding layer, an etching process is required. In order to completely remove the unnecessary material structure, over-etching will be performed.

[0057] refer to Figure 1 , Figure 1 The schematic diagram of the structure of an existing LDMOS device with insufficient etching is shown in FIG. 1 . If the over-etching amount is insufficient, the self-aligned silicide shielding layer may have a bottom residue due to insufficient etching, thereby causing some metal silicide regions to be unable to be fully opened, resulting in the metal silicide region width being too small, especially at the metal silicide where a contact structure is required. Figure 1 The area encircled by the dotted line is the insufficiently etched area. Figure 2 , Figure 2 The schematic diagram of an existing LDMOS device structure with excessive etching is shown in the figure. If the etching amount is too much, the spacing of the gate structure with smaller spacing will just meet the requirements, and there will be no sufficient process window, so that any slight process deviation may cause short circuit or leakage. The silicon material loss in the larger spacing will be serious during etching, resulting in structural damage or functional failure, and the sidewall and oxide layer of the gate structure will also be lost. Figure 2 The portion encircled by the dotted line is the over-etched area, which further leads to unexpected deviations in the fabricated device and reduces the yield.

[0058] For LDMOS devices, the existing solution uses a one-step etching method. The etching equipment uses a polysilicon (Poly) etching machine. That is, after the Poly etching machine etches the self-aligned polysilicon layer, it continues to etch the self-aligned silicide shielding layer greater than 1000 angstroms. This method is the current etching solution. When the polysilicon etching machine etches the self-aligned silicide shielding layer, its uniformity is difficult to control, especially for large wafers. It is very easy for the self-aligned silicide shielding layer to remain in the center or edge of the wafer, making the LDMOS device unable to meet the production target, causing serious problems such as damage to the final product.

[0059] Based on this, the present application provides a method for preparing an LDMOS device. The preparation method first provides a substrate, which includes a substrate and a gate structure, wherein the gate structure is arranged on the surface of the substrate, and a shielding material layer, a self-aligned polysilicon material layer and a patterned photoresist are sequentially formed on the side of the substrate where the gate structure is arranged. Based on the patterned photoresist and using a first etching machine, at least the self-aligned polysilicon material layer is etched to form a self-aligned polysilicon layer, and the self-aligned polysilicon layer is used as a mask layer, or the self-aligned polysilicon layer and the remaining patterned photoresist are used as mask layers, and the shielding material layer is etched by a second etching machine to form a shielding layer, and the shielding layer has a first opening and a second opening, the first opening exposes a portion of the upper surface of the gate structure adjacent to each other along a first direction and the substrate therebetween, and the second opening exposes the substrate between the gate structures adjacent to each other along the first direction, and then a metal silicide process is performed on the exposed substrate of the self-aligned polysilicon layer and a portion of the upper surface of the gate structure to form a metal silicide layer.

[0060] In the preparation method of the LDMOS device, a first etching machine is used for the self-aligned polysilicon material layer. Since the first etching machine is targeted at the self-aligned polysilicon material layer, the etching rate during etching is relatively high. A second etching machine is used for the shielding material layer. The second etching machine is targeted at the shielding material layer. When the self-aligned polysilicon layer is used as the mask layer, the second etching machine has little effect on the self-aligned polysilicon layer when etching the shielding material layer. Using dedicated etching machines for different materials can improve the accuracy of etching, thereby avoiding incomplete etching of the material to be etched or material loss due to over-etching during etching, and improving the yield of the product.

[0061] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0062] Please refer to Figure 3 , Figure 3 A schematic diagram of a manufacturing process of an LDMOS device provided in an embodiment of the present application; Figure 4 , Figure 4 A partial structural diagram of an LDMOS device provided in an embodiment of the present application; Figure 5 , Figure 5 A partial structural diagram of another LDMOS device provided in an embodiment of the present application; a method for preparing the LDMOS device includes:

[0063] S101: providing a substrate.

[0064] The base includes a substrate 01 and a gate structure 02, and the gate structure 02 is located on the surface of the substrate 01. In this step, Figure 4 As shown, the base includes a substrate 01, which can be a silicon substrate, and a gate structure 02 includes a polysilicon gate 02a and a gate oxide layer 02b located between the polysilicon gate 02a and the substrate 01. Sidewalls are also provided on both sides of the polysilicon gate 02a, and the sidewalls include a silicon oxide layer 02d and a silicon nitride layer 02e. The base provides a basis for the subsequent preparation of LDMOS devices.

[0065] S102 : forming a shielding material layer 03 , a self-aligned polysilicon material layer 04 and a patterned photoresist 05 on the substrate 01 and the gate structure 02 in sequence.

[0066] In this step, if Figure 5 As shown, a shielding material layer 03, a self-aligned polysilicon material layer 04 and a patterned photoresist 05 are formed in sequence on one side of a substrate 01 and a gate structure 02. First, the shielding material layer 03 is deposited. The material of the shielding material layer 03 can be a silicon dioxide material, and the thickness of its deposition can be greater than 1000 angstroms. Then, the self-aligned polysilicon material layer 04 is grown on a polysilicon furnace tube. The material of the self-aligned polysilicon material layer 04 can be a polysilicon material, and the total thickness can be 330 angstroms-400 angstroms. A patterned photoresist 05 is formed on the self-aligned polysilicon material layer 04. The patterned photoresist 05 is opened based on the exposed area required by the LDMOS device. The orthographic projection of the opening of the patterned photoresist 05 overlaps with the orthographic projection of the source region, the drain region and a portion of the gate structure 02 of the LDMOS device.

[0067] It should be noted that, in the present embodiment, the self-aligned polysilicon material layer 04 may include two layers, a self-aligned polysilicon sub-material layer close to the shielding material layer 03, and a self-aligned polysilicon buffer material layer located in the self-aligned polysilicon sub-material layer away from the shielding material layer 03. Among them, the thickness of the self-aligned polysilicon sub-material layer may be 300 angstroms to 350 angstroms, and the thickness of the self-aligned polysilicon buffer material layer may be 30 angstroms to 50 angstroms. Compared with the existing addition of the self-aligned polysilicon buffer material layer of 30 angstroms to 50 angstroms, when the self-aligned polysilicon material layer 04 is used as a mask in the subsequent process, the thickness of the self-aligned polysilicon material layer 04 can be ensured to be within the required range.

[0068] S103 : Based on the patterned photoresist 05 , a first etching machine is used to at least etch the self-aligned polysilicon material layer 04 to form a self-aligned polysilicon layer 06 .

[0069] In this step, the first etching machine may be a polysilicon etching machine, which is more accurate in etching the self-aligned polysilicon material layer 04. Figure 6 , Figure 6A partial structural diagram of another LDMOS device provided in an embodiment of the present application; it should be noted that at least the self-aligned polysilicon material layer 04 is etched, which means that the first etching machine can also etch the shielding material layer 03 located below the self-aligned polysilicon material layer 04 based on the patterned photoresist 05. Different etching methods have different effects. In order to better illustrate the etching process, it will not be repeated here, and the overall steps will be explained later.

[0070] S104: removing at least a portion of the patterned photoresist 05.

[0071] In this step, there is no specific limitation on the method of removing at least part of the patterned photoresist 05. It should be noted that after removing at least part of the patterned photoresist 05 in this step, the overall structure will be cleaned. During the cleaning process, the polymer etched by the first etching machine can be cleaned off to ensure that there is no excess polymer on the structure at this time to affect subsequent processes.

[0072] It should be noted that the reference Figure 7 , Figure 7 A partial structural diagram of another LDMOS device provided in an embodiment of the present application; Figure 8 , Figure 8 A partial structural diagram of another LDMOS device provided in an embodiment of the present application; removing at least a portion of the patterned photoresist 05 includes completely removing the patterned photoresist 05 (such as Figure 7 As shown) and removing part of the patterned photoresist 05 (as shown Figure 8 There are two methods as shown in the figure. Different removal methods play different roles in different steps. In order to better illustrate the etching process, they will not be described here. The overall steps will be described later.

[0073] S105: using the self-aligned polysilicon layer 06 as a mask layer, or using the self-aligned polysilicon layer 06 and the remaining patterned photoresist 05 as mask layers, a second etching machine is used to etch the shielding material layer 03 to form a shielding layer.

[0074] Among them, reference Fig. 9 , Fig. 9 A partial structural diagram of another LDMOS device provided in an embodiment of the present application; the shielding layer has first openings A and second openings B alternately arranged along a first direction M, the first openings A expose a portion of the upper surface of the gate structures 02 adjacent along the first direction M and the substrate 01 therebetween, and the second openings B expose the substrate 01 between the gate structures 02 adjacent along the first direction M. The first direction M is a direction parallel to the substrate 01, and the first direction M is parallel to the substrate 01.

[0075] In this step, the second etching machine is a dedicated machine for etching the shielding material layer 03. Since the etching machine is more accurate when etching the shielding material layer 03, the etching accuracy can be improved, thereby avoiding the incomplete etching of the material to be etched or the loss of material due to over-etching, thereby improving the yield of the product. In addition, when the self-aligned polysilicon layer 06 is used as the mask layer, the second etching machine has little effect on the self-aligned polysilicon layer 06 when etching the shielding material layer 03.

[0076] It should be noted that when the second etching machine is used to etch the shielding material layer 03, different etching methods can also be used. Based on this, the overall steps are described for step S103 using the first etching machine to at least etch the self-aligned polysilicon material layer 04, step S104 removing at least a portion of the patterned photoresist 05, and step S105 using the second etching machine to etch the shielding material layer 03 in different etching methods.

[0077] Optional, such as Figure 6 As shown, in another embodiment of the present application, based on the patterned photoresist 05, a first etching machine is used to etch at least the self-aligned polysilicon material layer 04 to form a self-aligned polysilicon layer 06, including:

[0078] The first etching machine is used to perform dry etching on the self-aligned polysilicon material layer 04 and the shielding material layer 03 with a preset thickness.

[0079] Specifically, the first etching machine can be a polysilicon etching machine, which uses dry etching to perform etching. In this embodiment, etching is performed based on the opening of the patterned photoresist 05. Since the orthographic projection of the opening at least overlaps with the orthographic projection of the source region, the drain region and part of the gate structure 02 of the LDMOS device, the self-aligned polysilicon material layer 04 at these positions is etched away, and the remaining is the self-aligned polysilicon layer 06. During this etching, in order to reduce the uneven etching phenomenon when the shielding material layer 03 is specially etched in the next step, to promote better etching consistency, and to avoid the self-aligned polysilicon layer 06 not being etched cleanly and causing circuit short circuits, the first etching machine is also used to etch the shielding material layer 03 of a preset thickness, ensuring the foundation for subsequent processes.

[0080] Optionally, in another embodiment of the present application, the preset thickness is 1 / 4 to 1 / 2 of the thickness of the shielding material layer 03 .

[0081] Specifically, the preset thickness can range from 1 / 4 to 1 / 2 of the thickness of the shielding material layer 03, including endpoint values. For example, the preset thickness can be 1 / 3 of the thickness of the shielding material layer 03, or 1 / 4 of the thickness of the shielding material layer 03, or 1 / 2 of the thickness of the shielding material layer 03, etc. There is no specific limitation on this and it can be set as needed.

[0082] Then, at least a portion of the patterned photoresist 05 is removed, and the patterned photoresist 05 is removed in the same manner as described above. Figure 7 As shown, in one embodiment, the patterned photoresist 05 is completely removed. Figure 8 As shown, in another embodiment, a portion of the patterned photoresist 05 is left.

[0083] If all of it is removed, when the second etching machine performs etching, only the self-aligned polysilicon layer 06 is used as a mask layer. If a portion is left, when the second etching machine performs etching, the self-aligned polysilicon layer 06 and the remaining patterned photoresist 05 are used together as a mask layer.

[0084] It should be noted that when all the self-aligned polysilicon layer 06 is completely removed, since a 30-50 angstrom self-aligned polysilicon buffer material layer is pre-grown in step S102, even if part of the thickness is consumed as a mask, the thickness of the self-aligned polysilicon layer 06 will be within a preset range. Retaining a portion of the patterned photoresist 05 can consume the patterned photoresist 05 first during subsequent etching, reducing the consumption of the self-aligned polysilicon layer 06, thereby making the thickness of the self-aligned polysilicon layer 06 within a preset range.

[0085] Afterwards, if Fig. 9 As shown, the self-aligned polysilicon layer 06 is used as a mask layer, or the self-aligned polysilicon layer 06 and the remaining patterned photoresist 05 are used as mask layers, and a second etching machine is used to etch the shielding material layer 03 to form the shielding layer 07, including:

[0086] The second etching machine is used to perform dry etching on the remaining shielding material layer 03 .

[0087] When the masking material layer 03 is etched, a portion of the upper surface of the gate structure 02 in the first opening A and the substrate 01 therebetween, as well as the substrate 01 in the second opening B are exposed, providing a basis for subsequent processes.

[0088] Among them, the second etching machine can be a special etching machine for the shielding material layer 03. When the material of the shielding material layer 03 is silicon dioxide, the second etching machine is a special etching machine for etching silicon dioxide. At this time, since the first etching machine etches away the shielding material layer 03 of the preset thickness, the remaining shielding material layer 03 is etched.

[0089] In order to ensure that the etched structure has no excess structural material residue or structural loss, it is necessary to adjust the selection ratio of the second etching machine for etching the masking material layer 03, the self-aligned polysilicon layer 06, and the gate structure 02, so that the structural profile after etching can be ensured to be the same as the target, for example, the etching ratio can be increased to ensure that the etching amount of the masking material layer 03 is larger.

[0090] It should be noted that if there is still a masking material layer 03 remaining after etching, the SiCoNi technology can be further used to remove the remaining masking material layer 03. The SiCoNi technology removes the surface oxide in the form of a chemical reaction. At this time, in order to ensure that the silicon oxide layer 02d of the side wall of the gate structure 02 is not removed, it can be allowed to form a certain angle with the side wall of the gate structure 02 so that its plasma will not hit the silicon oxide layer 02d. In this way, the remaining masking material layer 03 can be further removed cleanly and thoroughly.

[0091] Then, a wet cleaning step is performed to remove the remaining polymer or particles or residual patterned photoresist 05 after etching, so as to ensure that there is no residue before the subsequent process.

[0092] In the above embodiment, etching is divided into two steps. First, a first etching machine is used to etch and form a self-aligned polysilicon layer 06. Second, a second etching machine is used to etch and form a shielding layer 07. Two layers of different material structures use a dedicated etching machine that matches them to improve the accuracy of etching, thereby avoiding incomplete etching of the material to be etched or material loss due to over-etching, thereby improving the yield of the product.

[0093] Compared with the prior art which uses one etching machine to directly etch a self-aligned polysilicon layer on a shielding layer, the present application uses two different etching machines to etch in two steps. Since the etching is more targeted, it is obviously less likely to have problems of insufficient or excessive etching.

[0094] Optional, reference Fig.10 , Fig.10 A partial structural diagram of another LDMOS device provided in an embodiment of the present application; based on the patterned photoresist 05, a first etching machine is used to etch at least the self-aligned polysilicon material layer 04 to form a self-aligned polysilicon layer 06, including:

[0095] The self-aligned polysilicon material layer 04 is dry-etched by using a first etching machine.

[0096] Specifically, the first etching machine can be a polysilicon etching machine, which uses dry etching to perform etching. In this embodiment, etching is performed based on the opening of the patterned photoresist 05. Since the orthographic projection of the opening at least overlaps with the orthographic projection of the source region, the drain region and part of the gate structure 02 of the LDMOS device, the self-aligned polysilicon material layer 04 at these positions is etched away, and the remaining is the self-aligned polysilicon layer 06. Since the first etching machine is targeted at the self-aligned polysilicon material layer 04, the etching rate during etching is relatively high.

[0097] Then, at least a portion of the patterned photoresist 05 is removed, and the patterned photoresist 05 is removed in the same manner. In one embodiment, the patterned photoresist 05 is completely removed, and in another embodiment, a portion of the patterned photoresist 05 is left. It should be noted that this step is the same as that in the above embodiment, and will not be described in detail here.

[0098] refer to Fig.11 , Fig.11 A partial structural diagram of another LDMOS device provided in an embodiment of the present application; the second etching machine includes a first sub-etching machine and a second sub-etching machine, and the self-aligned polysilicon layer 06 is used as a mask layer, or the self-aligned polysilicon layer 06 and the remaining patterned photoresist 05 are used as a mask layer. The second etching machine is used to etch the shielding material layer 03 to form a shielding layer 07, including:

[0099] A first sub-etching machine is used to dry-etch a portion of the shielding material layer 03 to form a shielding intermediate layer 08, wherein the shielding intermediate layer 08 includes a first shielding portion 08a and a second shielding portion 08b, wherein a thickness h of the second shielding portion 08b is smaller than a thickness H of the first shielding portion 08a, and an orthographic projection area L of a side of the first shielding portion 08a close to the base on the substrate 01 is larger than an orthographic projection area R of a side of the first shielding portion 08a close to the self-aligned polysilicon layer 06 on the substrate 01.

[0100] Specifically, when the shielding material layer 03 is etched, a portion of the upper surface of the gate structure 02 in the first opening A and the substrate 01 therebetween, as well as the substrate 01 in the second opening B are exposed, providing a basis for subsequent processes.

[0101] In this embodiment, the etching of the shielding material layer 03 is divided into two steps: dry etching and wet etching. First, the first sub-etching machine is used to perform dry etching, wherein the first sub-etching machine can be a dedicated etching machine for the shielding material layer 03. When the material of the shielding material layer 03 is silicon dioxide, the first sub-etching machine is a dedicated etching machine for etching silicon dioxide.

[0102] It should be noted that, in order to prevent the shielding material layer 03 from being over-etched during the subsequent wet etching, thereby causing pointed structures to be produced on both sides of the self-aligned polysilicon layer 06, the dry etching does not completely etch the shielding material layer 03, but forms a shielding intermediate layer 08. In order to form the shielding intermediate layer 08, it is necessary to adjust the selection ratio of the first sub-etching machine for etching the shielding material layer 03, the self-aligned polysilicon layer 06, and the gate structure 02. The adjustment implementation method may include adjusting the etching gas ratio and flow rate, as well as the direction angle of the etching gas entry, etc.

[0103] The shielding intermediate layer 08 includes a first shielding portion 08a and a second shielding portion 08b. It should be noted that, in order to form a shielding layer 07 of a target shape under the self-aligned polysilicon layer 06 during wet etching, when etching is performed using the first sub-etching machine, the orthographic projection area L of the side of the first shielding portion 08a close to the base on the substrate 01 is made larger than the orthographic projection area R of the side of the first shielding portion 08a close to the self-aligned polysilicon layer 06 on the substrate 01, so that the tip of the self-aligned polysilicon layer 06 will not be formed during wet etching, ensuring that the final device will not be affected. It should also be noted that, since the first shielding portion 08a is located below the self-aligned polysilicon layer 06 during etching, its thickness H is not lost, so the thickness h of the second shielding portion 08b is less than the thickness H of the first shielding portion 08a.

[0104] Optionally, in another embodiment of the present application, the thickness h of the second shielding portion 08b is 30 angstroms to 50 angstroms.

[0105] It should be noted that the thickness h of the second shielding portion 08b may range from 30 angstroms to 50 angstroms, including end points. For example, the thickness h of the second shielding portion 08b may be 30 angstroms, 42 angstroms, or 47 angstroms, etc., and is not specifically limited.

[0106] Optionally, in another embodiment of the present application, in the first opening A, a portion of the surface and sidewall of the gate structure 02 is exposed between the second shielding portion 08 b and the first shielding portion 08 a .

[0107] Specifically, the second shielding portion 08b and the first shielding portion 08a may not be continuous, that is, during etching by the first sub-etching machine, a portion of the surface and sidewall of the gate structure 02 may be directly exposed, thereby increasing the etching efficiency during wet etching.

[0108] Optionally, in another embodiment of the present application, in the second direction N, perpendicular to the substrate 01, the positive projection area of ​​the side wall of the second shielding portion 08b on the substrate 01 increases successively, and the second direction N is perpendicular to the substrate 01 and points from the substrate 01 to the gate structure 02.

[0109] It should be noted that the second shielding portion 08 b forms a concave trapezoidal structure, such a configuration ensures that no shielding layer 07 remains at the sidewall of the gate structure 02 after wet etching.

[0110] refer to Fig.12 , Fig.12 A partial structural diagram of another LDMOS device provided in an embodiment of the present application is provided. A second sub-etching machine is used to wet-etch the shielding intermediate layer 08 to remove the second shielding portion 08 b to form a shielding layer 07 .

[0111] Specifically, at this time, the second sub-etching machine is a wet etching machine, which performs wet etching on the shielding intermediate layer 08. At this time, based on the structure of the first shielding part 08a and the second shielding part 08b etched by the first sub-etching machine, the wet etching will not damage the side wall of the gate structure 02 and will not cause over-etching at the tip of the self-aligned polysilicon layer 06. At the same time, it can avoid the incomplete etching of the material to be etched or the material loss due to over-etching, thereby improving the yield of the product.

[0112] It should be noted that if there is still a masking material layer 03 remaining after etching, SiCoNi technology can be used to remove the residual oxide. SiCoNi technology removes the surface oxide by chemical reaction. At this time, in order to ensure that the silicon oxide layer 02d of the side wall of the gate structure 02 is not removed, it can form a certain angle with the side wall of the gate structure 02 so that the plasma will not hit the silicon oxide layer 02d. In this way, the residual masking material layer 03 can be further removed cleanly and thoroughly.

[0113] Then, a wet cleaning step is performed to remove the remaining polymer or particles or residual patterned photoresist 05 after etching, so as to ensure that there is no residue before the subsequent process.

[0114] In the above embodiment, etching is divided into three steps. First, the self-aligned polysilicon layer 06 is formed by etching using the first etching machine. Secondly, the shielding layer 07 is formed by etching using the first sub-etching machine and the second sub-etching machine. For two layers of different materials, the etching accuracy can be improved, thereby avoiding incomplete etching of the material to be etched or material loss due to over-etching, thereby improving the yield of the product.

[0115] Compared with the prior art which uses one etching machine to directly etch a self-aligned polysilicon layer on a shielding layer, the present application uses three different etching machines to etch in three steps. Since the etching is more targeted, it is obviously less likely to have problems of insufficient or excessive etching.

[0116] It should be noted that, in addition to the three-step etching method used in this embodiment, when etching the shielding material layer 03, a combination of dry etching and wet etching in more steps can also be used, for example, dry etching first, then wet etching, and then dry etching, that is, the entire etching process adopts a four-step etching method. There is no specific limitation on the number and method of etching, so that a contour and structure that better meets the requirements can be obtained.

[0117] like Fig.12 As shown, after the self-aligned polysilicon layer 06 and the shielding layer 07 are formed by etching, at least a portion of the gate structure 02 and the substrate 01 outside the gate structure 02 and the shielding layer 07 are exposed. Then, step S106 is performed. Fig.13 , Fig.13 A partial structural diagram of another LDMOS device provided in an embodiment of the present application.

[0118] S106 : performing a metal silicide process on the self-aligned polysilicon layer 06 and the exposed upper surfaces of the substrate 01 and the gate structure 02 to form a metal silicide layer 09 .

[0119] Specifically, the formation of the metal silicide layer 09 requires a metal silicide process for the silicide, and the silicide layer exposed by the etched structure, that is, the self-aligned polysilicon layer 06, the substrate 01, and the partial upper surface of the gate structure 02 are metallized to form the metal silicide layer 09. It should be noted that in the present application, the metal silicide formed by metallizing the self-aligned polysilicon layer 06 and the metal silicide layer 09 formed by metallizing the partial upper surface of the gate structure 02 are used together as the gate of the device, wherein the metal silicide formed by the self-aligned polysilicon layer 06 is used as a supplementary gate, which can increase the conductive channel between the source S and the drain D in the active region, thereby increasing the high-voltage resistance of the LDMOS device. Therefore, the LDMOS device prepared by the preparation method has both low parasitic resistance and high-voltage resistance, and its application is more extensive.

[0120] Specifically, refer to Fig.14 , Fig.14 A schematic diagram of a partial structure of another LDMOS device provided in an embodiment of the present application; in another embodiment of the present application, the metal silicide layer 09 includes a first conductive portion 09a, a second conductive portion 09b, a third conductive portion 09c and a fourth conductive portion 09d, the first conductive portion 09a is located on one side of the second opening, the second conductive portion 09b is located on one side of the shielding layer 07, the third conductive portion 09c is located on one side of a portion of the upper surface of the gate structure 02, and the fourth conductive portion 09d is located on one side of the substrate in the first opening; the steps after the self-aligned polysilicon layer 06 and the exposed substrate 01 and the portion of the upper surface of the gate structure 02 are subjected to a metal silicide process to form the metal silicide layer 09, further include:

[0121] The contact structure 10 is formed on the first conductive portion 09 a , the second conductive portion 09 b , the third conductive portion 09 c , and the fourth conductive portion 09 d .

[0122] Specifically, a contact structure is formed on the second conductive portion 09b and the third conductive portion 09c, and the second conductive portion 09b and the third conductive portion 09c are used together as a gate to control the on and off of the device, thereby extending the conductive channel of the device and increasing the high-voltage resistance of the device. The first conductive portion 09a is used as a source S, and the fourth conductive portion 09d is used as a drain D. A contact structure is formed on the first conductive portion 09a and the fourth conductive portion 09d, which can provide an inflow and outflow path for current to achieve electrical connection with an external circuit.

[0123] In the present application, the first etching machine is used for the self-aligned polysilicon material layer 04, and the second etching machine is used for the shielding material layer 03. Different etching machines are used for different material layers, which can improve the accuracy of etching, thereby avoiding the incomplete etching of the material to be etched or the material loss caused by over-etching, and improving the yield of the product. In addition, since the self-aligned polysilicon layer 06 in the formed LDMOS device finally forms a metal silicide as a supplementary gate of the gate, the conductive channel of the LDMOS device is extended, and a high-voltage resistant LDMOS device is obtained.

[0124] Based on the above-mentioned method for preparing the LDMOS device, the present application further provides an LDMOS device, which is prepared by the above-mentioned method, such as Fig.13 As shown, the LDMOS device includes:

[0125] The substrate includes a substrate 01 and a gate structure 02 . The gate structure 02 is located on the surface of the substrate 01 .

[0126] The shielding layer 07 covers a portion of the gate structure 02 and a portion of the substrate 01. The shielding layer 07 has a first opening and a second opening alternately arranged along a first direction M. The first opening exposes a portion of the upper surface of the gate structure 02 adjacent to each other along the first direction M and the substrate 01 therebetween. The second opening exposes the substrate 01 between the gate structures 02 adjacent to each other along the first direction M. The first direction M is parallel to the substrate 01.

[0127] The metal silicide layer 09 covers the shielding layer 07 and the exposed upper surfaces of the substrate 01 and the gate structure 02 .

[0128] Optionally, in another embodiment of the present application, the metal silicide layer 09 includes a first conductive portion 09a, a second conductive portion 09b, a third conductive portion 09c and a fourth conductive portion 09d, the first conductive portion 09a is located on one side of the second opening, the second conductive portion 09b is located on one side of the shielding layer 07, the third conductive portion 09c is located on one side of a portion of the upper surface of the gate structure 02, and the fourth conductive portion 09d is located on one side of the substrate in the first opening, and the LDMOS device also includes: a plurality of contact structures 10, which are respectively in contact with the first conductive portion 09a, the second conductive portion 09b, the third conductive portion 09c and the fourth conductive portion 09d of the metal silicide layer 09.

[0129] Specifically, the contact structure 10 contacts the first conductive part 09a to provide a path for current to flow in, contacts the second conductive part 09b and the third conductive part 09c to provide voltage to control the on and off of the LDMOS device, and contacts the fourth conductive part 09d to provide a path for current to flow out.

[0130] Since the second conductive portion 09b in the metal silicide layer 09 of the LDMOS device is formed by metallizing the self-aligned polysilicon layer 06, it and the metal silicide formed by metallizing the polysilicon gate in the gate structure 02 serve together as the gate of the device, extending the conductive channel of the LDMOS device, so that the LDMOS device has better high-voltage resistance and is more widely used.

[0131] In the description of this specification, the description with reference to the terms "some embodiments", "an embodiment", "another embodiment", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0132] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0133] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing an LDMOS device, characterized in that: include: Providing a substrate, the substrate comprising a substrate and a gate structure, wherein the gate structure is located on a surface of the substrate; Forming a shielding material layer, a self-aligned polysilicon material layer and a patterned photoresist in sequence on the substrate and the gate structure; Based on the patterned photoresist, using a first etching machine to dry-etch at least the self-aligned polysilicon material layer to form a self-aligned polysilicon layer; removing at least a portion of the patterned photoresist; Using the self-aligned polysilicon layer as a mask layer, or using the self-aligned polysilicon layer and the remaining patterned photoresist as a mask layer, a second etching machine is used to etch the shielding material layer to form a shielding layer; Performing a metal silicide process on the self-aligned polysilicon layer and the exposed upper surfaces of the substrate and the gate structure to form a metal silicide layer; The second etching machine includes a first sub-etching machine and a second sub-etching machine; the self-aligned polysilicon layer is used as a mask layer, or the self-aligned polysilicon layer and the remaining patterned photoresist are used as a mask layer, and the second etching machine is used to etch the shielding material layer to form a shielding layer, including: Using the first sub-etching machine, dry-etching a portion of the shielding material layer to form a shielding intermediate layer, wherein the shielding intermediate layer includes a first shielding portion and a second shielding portion, the thickness of the second shielding portion is less than the thickness of the first shielding portion, and the orthographic projection area of ​​a side of the first shielding portion close to the base on the substrate is greater than the orthographic projection area of ​​a side of the first shielding portion close to the self-aligned polysilicon layer on the substrate; The second sub-etching machine is used to wet-etch the shielding intermediate layer to remove the second shielding portion to form the shielding layer, wherein the shielding layer has first openings and second openings alternately arranged along a first direction, wherein the first openings expose a portion of the upper surface of the gate structures adjacent along the first direction and the substrate therebetween, and the second openings expose the substrate between the gate structures adjacent along the first direction, and the first direction is parallel to the substrate.

2. The method for preparing an LDMOS device according to claim 1, characterized in that: The step of dry etching at least the self-aligned polysilicon material layer using a first etching machine based on the patterned photoresist to form a self-aligned polysilicon layer includes: Using the first etching machine, dry-etching the self-aligned polysilicon material layer and the shielding material layer of a preset thickness; The self-aligned polysilicon layer is used as a mask layer, or the self-aligned polysilicon layer and the remaining patterned photoresist are used as mask layers, and a second etching machine is used to etch the shielding material layer to form a shielding layer, comprising: The second etching machine is used to perform dry etching on the remaining shielding material layer.

3. The method for preparing an LDMOS device according to claim 2, characterized in that: The preset thickness is 1 / 4 to 1 / 2 of the thickness of the shielding material layer.

4. The method for preparing an LDMOS device according to claim 1, characterized in that: In the first opening, a portion of the surface and sidewall of the gate structure is exposed between the second shielding portion and the first shielding portion.

5. The method for preparing an LDMOS device according to claim 1, characterized in that: In the second direction, the orthographic projection areas of the side walls of the second shielding portion on the substrate increase sequentially. The second direction is perpendicular to the substrate and points from the substrate to the gate structure.

6. The method for preparing an LDMOS device according to claim 1, characterized in that: The metal silicide layer comprises a first conductive portion, a second conductive portion, a third conductive portion and a fourth conductive portion, wherein the first conductive portion is located on one side of the second opening, the second conductive portion is located on one side of the shielding layer, the third conductive portion is located on one side of a portion of the upper surface of the gate structure, and the fourth conductive portion is located on one side of the substrate in the first opening; after the metal silicide process is performed on the self-aligned polysilicon layer and the exposed substrate and the portion of the upper surface of the gate structure to form the metal silicide layer, the method further comprises: Contact structures are formed on the first conductive portion, the second conductive portion, the third conductive portion, and the fourth conductive portion.

7. An LDMOS device, characterized in that: The LDMOS device is manufactured by the method for preparing the LDMOS device according to any one of claims 1 to 6, wherein the LDMOS device comprises: A substrate, comprising a substrate and a gate structure, wherein the gate structure is located on a surface of the substrate; a shielding layer, the shielding layer covering a portion of the gate structure and a portion of the substrate, the shielding layer having a first opening and a second opening alternately arranged along a first direction, the first opening exposing a portion of the upper surface of the gate structure adjacent along the first direction and the substrate therebetween, and the second opening exposing the substrate between the gate structures adjacent along the first direction; the first direction is parallel to the substrate; A metal silicide layer covers the shielding layer and the exposed upper surfaces of the substrate and the gate structure.

8. The LDMOS device according to claim 7, characterized in that: The metal silicide layer includes a first conductive portion, a second conductive portion, a third conductive portion and a fourth conductive portion, the first conductive portion is located on one side of the second opening, the second conductive portion is located on one side of the shielding layer, the third conductive portion is located on one side of a portion of the upper surface of the gate structure, and the fourth conductive portion is located on one side of the substrate in the first opening; The LDMOS device further comprises: A plurality of contact structures are provided, and the plurality of contact structures are respectively in contact with the first conductive portion, the second conductive portion, the third conductive portion, and the fourth conductive portion of the metal silicide layer.

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