Back-illuminated image sensor preparation method and back-illuminated image sensor

Abstract

The present invention relates to a method for preparing a back-illuminated image sensor and the back-illuminated image sensor, and relates to the technical field of integrated circuits. The method comprises: providing a substrate including a first top surface, wherein the first top surface includes an isolation layer and an initial semiconductor layer sequentially stacked along a first direction away from the first top surface; forming a plurality of isolation stacks spaced along a second direction on the top surface of the initial semiconductor layer, and sequentially forming a first semiconductor layer and a second semiconductor layer stacked between adjacent isolation stacks; diffusing a first pentavalent element of the first semiconductor layer into the initial semiconductor layer to obtain a first target semiconductor layer; diffusing a second pentavalent element of the second semiconductor layer into the first semiconductor layer to obtain a second target semiconductor layer; and forming a dielectric layer covering the top surface of the second semiconductor layer and the exposed outer surface of the isolation stack, thereby increasing the electron concentration of the photosensitive area and improving the photosensitivity of the BSI image sensor.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a method for preparing a back-illuminated image sensor and the back-illuminated image sensor. Background Art

[0002] Backside illumination (BSI) image sensor is a type of image sensor. In low light conditions, BSI image sensor has better performance than front-illuminated image sensor.

[0003] However, the photosensitivity of BSI image sensors manufactured by existing BSI image sensor preparation methods cannot meet actual needs. Therefore, how to improve the photosensitivity of BSI image sensors has become one of the technical problems that urgently need to be solved. Summary of the invention

[0004] Based on this, it is necessary to provide a back-illuminated image sensor preparation method and a back-illuminated image sensor to address the technical problem of insufficient photosensitivity of BSI image sensors in the prior art.

[0005] In a first aspect, the present disclosure provides a method for preparing a back-illuminated image sensor, comprising:

[0006] Providing a substrate including a first top surface, wherein the first top surface includes an isolation layer and an initial semiconductor layer stacked in sequence along a first direction away from the first top surface;

[0007] A plurality of isolation stacks are formed on the top surface of the initial semiconductor layer and are arranged in a second direction parallel to the first top surface, wherein the isolation stacks include an intermediate layer and a grid layer sequentially stacked along the first direction, and the intermediate layer includes at least two film layers sequentially stacked along the first direction and containing different trivalent elements;

[0008] A first semiconductor layer and a second semiconductor layer containing different pentavalent elements are sequentially formed between adjacent isolation stacks; the top surface of the second semiconductor layer is not higher than the bottom surface of the grid layer;

[0009] diffusing the first pentavalent element of the first semiconductor layer into the initial semiconductor layer to obtain a first target semiconductor layer containing the first pentavalent element;

[0010] diffusing the second pentavalent element of the second semiconductor layer into the first semiconductor layer to obtain a second target semiconductor layer containing the second pentavalent element;

[0011] A dielectric layer is formed to cover the top surface of the second semiconductor layer and the exposed outer surface of the isolation stack.

[0012] In the method for preparing a back-illuminated image sensor in the above-mentioned embodiment, an isolation layer and an initial semiconductor layer are sequentially stacked along a first direction away from the first top surface of the substrate, and a plurality of isolation stacks are formed on the top surface of the initial semiconductor layer and are arranged at intervals along a second direction parallel to the first top surface of the substrate, wherein the isolation stack comprises an intermediate layer and a grid layer sequentially stacked along the first direction, and the intermediate layer comprises at least two film layers sequentially stacked along the first direction and comprising different trivalent elements; thereby, a first semiconductor layer and a second semiconductor layer sequentially stacked and comprising different pentavalent elements are formed between adjacent isolation stacks using the isolation stack as an initial isolation sidewall, wherein the top surface of the second semiconductor layer is not higher than the bottom surface of the grid layer; a first ion diffusion process can be used to treat the first semiconductor layer. The first pentavalent element of the conductor layer is diffused into the initial semiconductor layer to obtain a first target semiconductor layer containing the first pentavalent element; then a second ion diffusion process is used to diffuse the second pentavalent element of the second semiconductor layer into the first semiconductor layer to obtain a second target semiconductor layer containing the second pentavalent element, and an isolation wall including a part of the initial semiconductor layer, an intermediate layer and a grid layer; since the intermediate layer containing different trivalent elements forms a PN junction with the adjacent first target semiconductor layer containing pentavalent elements, the first semiconductor layer, the second target semiconductor layer and the second semiconductor layer, the PN junction can effectively improve the isolation effect of the isolation wall, avoid signal crosstalk between photosensitive stacks separated by the isolation wall, and thus improve the display quality of the BSI image sensor. In addition, in the embodiment of the present disclosure, an ion diffusion process is used to diffuse the first pentavalent element of the first semiconductor layer into the initial semiconductor layer to obtain a first target semiconductor layer containing the first pentavalent element, and the second pentavalent element of the second semiconductor layer is diffused into the first semiconductor layer to obtain a second target semiconductor layer containing the second pentavalent element. Compared with the conventional technology of using an ion implantation process to obtain a first target semiconductor layer containing the first pentavalent element and a second target semiconductor layer containing the second pentavalent element, the embodiment of the present disclosure can effectively avoid unnecessary damage to the substrate caused by high-energy ions in the ion implantation process, and further improve the performance and reliability of the back-illuminated image sensor. Furthermore, in the embodiment of the present disclosure, after forming a photosensitive stack including a first target semiconductor layer, a first semiconductor layer, a second target semiconductor layer, and a second semiconductor layer stacked in sequence along a first direction, a dielectric layer is used to cover the top surface of the second semiconductor layer and the exposed outer surface of the isolation stack, so that the dielectric layer can bind electrons in the photosensitive stack, avoid signal crosstalk between different photosensitive stacks, and improve the performance and reliability of the image sensor.

[0013] In one of the embodiments, the initial semiconductor layer includes a SiB layer; the intermediate layer includes a SiGa layer and an Al layer stacked in sequence along a first direction; the first semiconductor layer includes a SiP layer; forming the first target semiconductor layer includes: using a first laser annealing process to treat the SiP layer so that P in the SiP layer vertically diffuses into the SiB layer to obtain a first target semiconductor layer containing the P element.

[0014] In one embodiment, the second semiconductor layer includes a SiAs layer; forming the second target semiconductor layer includes: processing the SiAs layer with a second laser annealing process so that As in the SiAs layer vertically diffuses into the SiP layer to obtain a second target semiconductor layer containing the As element.

[0015] In one embodiment, the dielectric constant of the dielectric layer is greater than a preset dielectric constant threshold; the top surface of the second semiconductor layer is flush with the top surface of the Al layer; and the dielectric layer covers the outer surface of the grid layer and the top surface of the second semiconductor layer.

[0016] In one embodiment, the substrate includes a plurality of first isolation structures extending into the substrate through a first top surface of the substrate and arranged at intervals along a second direction; the plurality of first isolation structures are located directly below the plurality of isolation stacks.

[0017] In one embodiment, the initial semiconductor layer includes a SiB layer; forming the initial semiconductor layer includes: forming the SiB layer on the top surface of the isolation layer using a selective epitaxial deposition process.

[0018] In one embodiment, after forming the dielectric layer, the method further includes: forming a filter between adjacent grid layers along the second direction.

[0019] In a second aspect, the present disclosure provides a back-illuminated image sensor, which is prepared by the back-illuminated image sensor preparation method in any of the aforementioned embodiments, wherein the back-illuminated image sensor includes a substrate, and an isolation layer and an initial semiconductor layer stacked in sequence along a first direction away from a first top surface of the substrate; the top surface of the initial semiconductor layer includes a plurality of isolation stacks arranged at intervals along a second direction parallel to the first top surface of the substrate, the isolation stack includes an intermediate layer and a grid layer stacked in sequence along the first direction, the intermediate layer includes at least two film layers stacked in sequence along the first direction and containing different trivalent elements; adjacent isolation stacks include a first target semiconductor layer, a first semiconductor layer, a second target semiconductor layer and a second semiconductor layer stacked in sequence along a direction away from the substrate; wherein the first semiconductor layer and the first target semiconductor layer both contain a first pentavalent element, and the second semiconductor layer and the second target semiconductor layer both contain a second pentavalent element; the top surface of the second semiconductor layer and the exposed outer surface of the isolation stack are covered with a dielectric layer.

[0020] In one embodiment, the initial semiconductor layer includes a SiB layer; the intermediate layer includes a SiGa layer and an Al layer sequentially stacked along a first direction; the first semiconductor layer includes a SiP layer; and the first target semiconductor layer contains a P element.

[0021] In one embodiment, the second semiconductor layer includes a SiAs layer; and the second target semiconductor layer includes an As element.

[0022] The method for preparing a back-illuminated image sensor and the back-illuminated image sensor in the embodiments of the present disclosure include the following unexpected technical effects:

[0023] An isolation stack is used as an initial isolation side wall, and a first semiconductor layer and a second semiconductor layer containing different pentavalent elements are sequentially stacked between adjacent isolation stacks, wherein the top surface of the second semiconductor layer is not higher than the bottom surface of the grid layer; a first ion diffusion process can be used to diffuse the first pentavalent element of the first semiconductor layer into the initial semiconductor layer to obtain a first target semiconductor layer containing the first pentavalent element; and then a second ion diffusion process is used to diffuse the second pentavalent element of the second semiconductor layer into the first semiconductor layer to obtain a second target semiconductor layer containing the second pentavalent element, and an isolation wall including part of the initial semiconductor layer, an intermediate layer and a grid layer; since a PN junction is formed between the intermediate layer containing different trivalent elements and the adjacent first target semiconductor layer, the first semiconductor layer, the second target semiconductor layer and the second semiconductor layer containing pentavalent elements, the PN junction can be used to effectively improve the isolation effect of the isolation wall, avoid signal crosstalk between photosensitive stacks separated by the isolation wall, and thus improve the display quality of the BSI image sensor. In addition, in the embodiment of the present disclosure, an ion diffusion process is used to diffuse the first pentavalent element of the first semiconductor layer into the initial semiconductor layer to obtain a first target semiconductor layer containing the first pentavalent element, and the second pentavalent element of the second semiconductor layer is diffused into the first semiconductor layer to obtain a second target semiconductor layer containing the second pentavalent element. Compared with the conventional technology of using an ion implantation process to obtain a first target semiconductor layer containing the first pentavalent element and a second target semiconductor layer containing the second pentavalent element, the embodiment of the present disclosure can effectively avoid unnecessary damage to the substrate caused by high-energy ions in the ion implantation process, and further improve the performance and reliability of the back-illuminated image sensor. Furthermore, in the embodiment of the present disclosure, after forming a photosensitive stack including a first target semiconductor layer, a first semiconductor layer, a second target semiconductor layer, and a second semiconductor layer stacked in sequence along a first direction, a dielectric layer is used to cover the top surface of the second semiconductor layer and the exposed outer surface of the isolation stack, so that the dielectric layer can bind electrons in the photosensitive stack, avoid signal crosstalk between different photosensitive stacks, and improve the performance and reliability of the image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 is a schematic flow chart of a method for preparing a back-illuminated image sensor provided in an embodiment;

[0026] Figure 2 Schematic diagram of the longitudinal cross-sectional structure of a substrate provided in step S10 in a method for preparing a back-illuminated image sensor provided in an embodiment;

[0027] Figure 3 Schematic diagram of the longitudinal cross-sectional structure of the semiconductor structure obtained after forming a stacked isolation layer, an initial semiconductor layer, a first semiconductor material layer, a metal material layer, a first grid material layer, a second grid material layer and a third grid material layer on a substrate in step S20 in a method for preparing a back-illuminated image sensor provided in an embodiment;

[0028] Figure 4 It is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor structure obtained after forming a plurality of isolation stacks spaced apart along a second direction on a substrate in step S20 in a method for preparing a back-illuminated image sensor provided in an embodiment;

[0029] Figure 5 It is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor structure obtained after forming a stacked first semiconductor layer and a second semiconductor layer between adjacent isolation stacks in step S30 in a method for preparing a back-illuminated image sensor provided in an embodiment;

[0030] Figure 6 It is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor structure obtained after forming a first target semiconductor layer in step S40 in a method for preparing a back-illuminated image sensor provided in an embodiment;

[0031] Figure 7 It is a schematic diagram of the longitudinal cross-section structure of the semiconductor structure obtained after the second target semiconductor layer is formed in step S50 in the method for preparing a back-illuminated image sensor provided in one embodiment;

[0032] Figure 8 It is a schematic diagram of the longitudinal cross-section structure of the semiconductor structure obtained after the dielectric layer is formed in step S60 in the method for preparing a back-illuminated image sensor provided in one embodiment;

[0033] Fig. 9 It is a schematic diagram of the longitudinal cross-section structure of a semiconductor structure obtained after forming a filter in a method for preparing a back-illuminated image sensor provided in an embodiment;

[0034] Description of reference numerals:

[0035] 10. Substrate; 10a. First top surface; 11. Isolation layer; 12. Initial semiconductor layer; 21. Intermediate layer; 22. Grid layer; 2111. First semiconductor material layer; 211. Semiconductor film layer; 2121. Metal material layer; 212. Metal layer; 2211. First grid material layer; 221. First grid layer; 2221. Second grid material layer; 222. Second grid layer; 2231. Third grid material layer; 223. Third grid layer; 14. Groove; 31. First semiconductor layer; 32. Second semiconductor layer; 41. First target semiconductor layer; 42. Second target semiconductor layer; 50. Dielectric layer; 101. First isolation structure; 102. Etch stop layer; 103. Interlayer dielectric layer; 60. Filter. DETAILED DESCRIPTION

[0036] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0038] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0039] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0040] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0041] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present disclosure should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present disclosure.

[0042] In the embodiment of the present disclosure, when the flatness of the substrate surface is ignored, the direction away from the substrate surface (the thickness direction of the substrate) is, for example, the first direction, and the direction parallel to the substrate surface is, for example, the second direction. For example, the arrangement direction of the isolation stack is the second direction. In the embodiment of the present disclosure, the first direction may be the Z-axis direction, and the second direction may be the X-axis direction.

[0043] Please refer to Figure 1 In some embodiments, a method for preparing a back-illuminated image sensor is provided, comprising:

[0044] Step S10: providing a substrate including a first top surface, wherein the first top surface includes an isolation layer and an initial semiconductor layer stacked in sequence along a first direction away from the first top surface;

[0045] Step S20: forming a plurality of isolation stacks arranged at intervals along a second direction parallel to the first top surface on the top surface of the initial semiconductor layer, wherein the isolation stacks include an intermediate layer and a grid layer sequentially stacked along the first direction, and the intermediate layer includes at least two film layers sequentially stacked along the first direction and containing different trivalent elements;

[0046] Step S30: sequentially forming a first semiconductor layer and a second semiconductor layer containing different pentavalent elements between adjacent isolation stacks; the top surface of the second semiconductor layer is not higher than the bottom surface of the grid layer;

[0047] Step S40: diffusing the first pentavalent element of the first semiconductor layer into the initial semiconductor layer to obtain a first target semiconductor layer containing the first pentavalent element;

[0048] Step S50: diffusing the second pentavalent element of the second semiconductor layer into the first semiconductor layer to obtain a second target semiconductor layer containing the second pentavalent element;

[0049] Step S60: forming a dielectric layer covering the top surface of the second semiconductor layer and the exposed outer surface of the isolation stack.

[0050] Please refer to Figure 2 In some embodiments, the provided substrate 10 includes a plurality of first isolation structures 101 arranged in a spaced relationship along a second direction, such as the ox direction. The material of the first isolation structure 101 may include, but is not limited to, silicon oxide (SiO 2 )、Silicon Nitride(Si 3 N 4 ), silicon oxynitride (Si 2 N 2 O), etc. or a combination thereof.

[0051] As an example, the first isolation structure 101 can be used to isolate electrons and light energy. The shape of the longitudinal section (the section parallel to the zox plane) of the first isolation structure 101 may include a regular trapezoid, an inverted trapezoid, a rectangle, etc., or may also be a combination of a regular trapezoid, an inverted trapezoid, a rectangle, etc. The present disclosure does not impose any specific restrictions on the shape, material, and size of the first isolation structure 101, as long as it can isolate electrons, light energy, and doped ions. In addition, this embodiment does not impose any specific restrictions on the spacing between adjacent first isolation structures 101, and it can be set according to actual needs.

[0052] As an example, the substrate 10 can be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. Therefore, the type of substrate should not limit the scope of protection of the present disclosure.

[0053] Please continue to refer to Figure 2 In some embodiments, a surface of the first isolation structure 101 facing away from the substrate 10 is covered with an etch stop layer 102 , and a side of the etch stop layer 102 facing away from the first isolation structure 101 includes an interlayer dielectric layer 103 .

[0054] For example, after forming the etch stop layer 102, metal is deposited to form a partial connection structure, and on this basis, an interlayer dielectric layer 103 is formed. When the etch stop layer 102 is multi-layer, other process problems and / or metal connection structure failure problems caused by cracks in a single layer can be avoided. The interlayer dielectric layer 103 can be a silicon oxide or other low-dielectric material layer. In addition, a metal interconnect structure can be formed on the interlayer dielectric layer 103 as a metal connection part of the device.

[0055] Of course, this embodiment only shows one of the methods, as long as the metal interconnection structure can be reasonably formed, and the thickness of the etch stop layer 102 and the interlayer dielectric layer 103 is not limited, and can be adjusted according to specific process requirements.

[0056] Please continue to refer to Figure 2 In some embodiments, after forming the first isolation structure 101, the etch stop layer 102, and the interlayer dielectric layer 103, the substrate 10 may be flipped over to form an isolation layer 11 in the substrate 10 on the side of the first isolation structure 101 facing away from the interlayer dielectric layer 103. For example, the isolation layer 11 may include a silicon oxide layer. The silicon oxide layer may be formed in the substrate 10 on the side of the first isolation structure 101 facing away from the interlayer dielectric layer 103 by an oxygen implantation isolation process.

[0057] For example, the thickness of the isolation layer 11 is 5 nanometers to 10 nanometers. For example, the thickness of the isolation layer 11 can be 5 nanometers, 7 nanometers, 9 nanometers, or 10 nanometers.

[0058] Please refer to Figure 3 In some embodiments, after forming the isolation layer 11, at least one of an etching process, a push-on process, and a chemical mechanical polishing process can be used to remove the portion of the substrate 10 located on the side of the isolation layer 11 away from the first isolation structure 101, exposing the top surface of the isolation layer 11, and obtaining the substrate 10 including the first top surface 10a, wherein the isolation layer 11 is located on the first top surface 10a of the substrate 10. The etching process may include, but is not limited to, a dry etching process and / or a wet etching process. The dry etching process may include, but is not limited to, one or more of RIE and ICP.

[0059] Please continue to refer to Figure 3 In some embodiments, in step S10, a selective epitaxial deposition process may be used to form an initial semiconductor layer 12 on the isolation layer 11. The initial semiconductor layer 12 may include a SiB layer.

[0060] Please continue to refer to Figure 3 In some embodiments, in step S20, a first semiconductor material layer 2111, a metal material layer 2121, a first grid material layer 2211, a second grid material layer 2221, and a third grid material layer 2231 may be formed on the initial semiconductor layer 12 in a first direction, such as the oz direction, in sequence. For example, the first semiconductor material layer 2111 may be sequentially formed by a selective epitaxial deposition process; the metal material layer 2121 may be formed by a plasma deposition process; the first grid material layer 2211 may be formed by a selective epitaxial deposition process; and the second grid material layer 2221 and the third grid material layer 2231 may be sequentially formed by a chemical vapor deposition process.

[0061] For example, the initial semiconductor layer 12 includes a SiB layer; the first semiconductor material layer 2111 includes a SiGa layer; the metal material layer 2121 includes an Al layer; the first grid material layer 2211 includes a SiIn layer; and the second grid material layer 2221 includes a Ta layer. 2 O 5 layer; the third grid material layer 2231 includes a TiN layer.

[0062] Please refer to Figure 4 In some embodiments, in step S20, a dry etching process can be used to etch the third grid material layer 2231, the second grid material layer 2221, the first grid material layer 2211, the metal material layer 2121, and the first semiconductor material layer 2111 to obtain a plurality of grooves 14 arranged at intervals along the second direction, thereby obtaining grooves 14 and an isolation stack (not shown) that are alternately distributed in sequence along the second direction; wherein the isolation stack includes an intermediate layer 21 and a grid layer 22 that are sequentially stacked along the first direction. The intermediate layer includes a semiconductor film layer 211 and a metal layer 212 that are sequentially stacked along the first direction and contain different trivalent elements. The grid layer 22 includes a first grid layer 221, a second grid layer 222, and a third grid layer 223 that are sequentially stacked along the first direction.

[0063] For example, the intermediate layer 21 includes a SiGa layer and an Al layer sequentially stacked along a first direction; the grid layer 22 includes a SiIn layer, a Ta layer sequentially stacked along a first direction. 2 O 5 layer and TiN layer.

[0064] Please refer to Figure 5 In some embodiments, a selective epitaxial deposition process may be used in step S30 to sequentially form a first semiconductor layer 31 and a second semiconductor layer 32 containing different pentavalent elements between adjacent isolation stacks; the top surface of the second semiconductor layer 32 is not higher than the bottom surface of the grid layer 22, for example, the top surface of the second semiconductor layer 32 is flush with the bottom surface of the grid layer 22.

[0065] Please refer to Figure 6 In some embodiments, the first semiconductor layer 31 includes a SiP layer; in step S40, a first laser annealing process may be used to treat the SiP layer so that P in the SiP layer vertically diffuses into the SiB layer to obtain a first target semiconductor layer 41 containing the P element.

[0066] For example, the first laser annealing process includes: using a laser pulse with a pulse energy of 115 mJ to 125 mJ (e.g., a pulse width of 9 ms to 11 ms) to process the SiP layer. For example, a laser pulse with a pulse energy of 120 mJ and a pulse width of 10 ms may be used to process the SiP layer, so that P in the SiP layer vertically diffuses into the SiB layer, thereby obtaining a first target semiconductor layer 41 containing the P element.

[0067] Please refer to Figure 7 In some embodiments, the second semiconductor layer 32 includes a SiAs layer; in step S50, a second laser annealing process may be used to treat the SiAs layer so that As in the SiAs layer vertically diffuses into the SiP layer to obtain a second target semiconductor layer 42 containing the As element.

[0068] For example, the second laser annealing process includes: using a laser pulse with a pulse energy of 95 mJ to 105 mJ (e.g., a pulse width of 4.5 ms to 5.5 ms) to process the SiAs layer. For example, a laser pulse with a pulse energy of 100 mJ and a pulse width of 5 ms may be used to process the SiAs layer, so that As in the SiAs layer diffuses vertically into the SiP layer, thereby obtaining a second target semiconductor layer 42 containing the As element.

[0069] The laser annealing process can better activate and fix the ions in the device, reduce the impact of external environmental factors on device performance, enable ions to better participate in charge transfer and photoelectric conversion processes, and improve device performance.

[0070] Please continue to refer to Figure 7 In the above-mentioned embodiment of the present disclosure, an ion diffusion treatment process is adopted to diffuse the first pentavalent element of the first semiconductor layer 31 into the initial semiconductor layer 12 to obtain a first target semiconductor layer 41 containing the first pentavalent element, and to diffuse the second pentavalent element of the second semiconductor layer 32 into the first semiconductor layer 31 to obtain a second target semiconductor layer 42 containing the second pentavalent element. Compared with the conventional technology of adopting an ion implantation process to obtain the first target semiconductor layer 41 containing the first pentavalent element and the second target semiconductor layer 42 containing the second pentavalent element, it can effectively avoid unnecessary damage to the substrate 10 caused by high-energy ions in the ion implantation process, and further improve the performance and reliability of the back-illuminated image sensor.

[0071] Please refer to Figure 8 In some embodiments, an atomic layer deposition process may be used in step S60 to form a dielectric layer 50 covering the top surface of the second semiconductor layer 32 and the exposed outer surface of the isolation stack.

[0072] Since the first target semiconductor layer 41, the first semiconductor layer 31, the second target semiconductor layer 42 and the second semiconductor layer 32 can together constitute the photosensitive stack of the photodiode, and the photosensitive stack doped with different pentavalent elements will also generate a concentration gradient inside after light excitation, the difference is used to optimize the transmission path of the photogenerated carriers, and the recombination rate in the diffusion process is reduced. Under the joint action of the two, the quantum efficiency of the photodiode based on this structure is effectively improved. In addition, since the atomic mass of pentavalent elements is higher than that of silicon, the mobility is low in epitaxial growth, resulting in uneven doping concentration in a single doping layer. Growing pentavalent elements with different doping in multiple times can improve the uniformity of doping concentration in the pixel area.

[0073] Please continue to refer to Figure 8 The dielectric layer 50 is used to cover the top surface of the second semiconductor layer 32 and the exposed outer surface of the isolation stack, so that the dielectric layer 50 can bind electrons in the photosensitive stack, avoid signal crosstalk between different photosensitive stacks, and improve the performance and reliability of the image sensor.

[0074] For example, the dielectric constant of the dielectric layer 50 may be set to be greater than a preset dielectric constant threshold; the top surface of the second semiconductor layer 32 is flush with the top surface of the Al layer; and the dielectric layer 50 covers the outer surface of the grid layer 22 and the top surface of the second semiconductor layer 32. For example, the dielectric layer 50 may include HfO 2 layer.

[0075] Furthermore, multiple epitaxial growths are used to prepare the photodiodes in the BSI image sensor, thus avoiding substrate damage introduced by the photodiode preparation method using high-energy ion implantation in the traditional process.

[0076] By forming an isolation stack arranged at intervals in the pixel area, the internal structure of the pixel area is improved, the mutual penetration of photogenerated carriers between adjacent pixel areas is blocked, the probability of light diffusion to adjacent pixels is reduced, and the adverse effects of light and / or charge crosstalk on imaging quality are suppressed.

[0077] Please continue to refer to Figure 1-Figure 8, after forming an isolation layer 11 and an initial semiconductor layer 12 stacked in sequence along a first direction away from the first top surface 10a of the substrate 10 on the first top surface 10a of the substrate 10; forming a plurality of isolation stacks arranged in a second direction parallel to the first top surface 10a of the substrate 10 on the top surface of the initial semiconductor layer 12, the isolation stack includes an intermediate layer 21 and a grid layer 22 stacked in sequence along the first direction, and the intermediate layer 21 includes at least two film layers stacked in sequence along the first direction and containing different trivalent elements; thereby using the isolation stack as the initial isolation sidewall, after forming a first semiconductor layer 31 and a second semiconductor layer 32 stacked in sequence containing different pentavalent elements between adjacent isolation stacks, wherein the top surface of the second semiconductor layer 32 is not higher than the bottom surface of the grid layer 22; a first ion diffusion process can be used to treat the first semiconductor layer 31 The first pentavalent element is diffused into the initial semiconductor layer 12 to obtain a first target semiconductor layer 41 containing the first pentavalent element; and then a second ion diffusion process is used to diffuse the second pentavalent element of the second semiconductor layer 32 into the first semiconductor layer 31 to obtain a second target semiconductor layer 42 containing the second pentavalent element, and an isolation wall including a portion of the initial semiconductor layer 12, an intermediate layer 21 and a grid layer 22; since the intermediate layer 21 containing different trivalent elements forms a PN junction with the adjacent first target semiconductor layer 41 containing pentavalent elements, the first semiconductor layer 31, the second target semiconductor layer 42 and the second semiconductor layer 32, the PN junction can effectively improve the isolation effect of the isolation wall, avoid signal crosstalk between the photosensitive stacks separated by the isolation wall, and thus improve the display quality of the BSI image sensor. Furthermore, in the embodiment of the present disclosure, an ion diffusion treatment process is adopted, so that the first pentavalent element of the first semiconductor layer 31 is diffused into the initial semiconductor layer 12 to obtain a first target semiconductor layer 41 containing the first pentavalent element, and the second pentavalent element of the second semiconductor layer 32 is diffused into the first semiconductor layer 31 to obtain a second target semiconductor layer 42 containing the second pentavalent element. Compared with the conventional technology of adopting an ion implantation process to obtain the first target semiconductor layer 41 containing the first pentavalent element and the second target semiconductor layer 42 containing the second pentavalent element, the embodiment of the present disclosure can effectively avoid unnecessary damage to the substrate 10 caused by high-energy ions in the ion implantation process, thereby further improving the performance and reliability of the back-illuminated image sensor. Furthermore, in the embodiment of the present disclosure, after forming a photosensitive stack including a first target semiconductor layer 41, a first semiconductor layer 31, a second target semiconductor layer 42 and a second semiconductor layer 32 stacked in sequence along a first direction, a dielectric layer 50 is used to cover the top surface of the second semiconductor layer 32 and the exposed outer surface of the isolation stack, so that the dielectric layer 50 can bind electrons in the photosensitive stack, thereby avoiding signal crosstalk between different photosensitive stacks and improving the performance and reliability of the image sensor.

[0078] Please refer to Fig. 9In some embodiments, after forming the dielectric layer 50, it further includes: forming a filter 60 between the grid layers 22 adjacent along the second direction, such as the ox direction. The filter 60 includes but is not limited to a red filter, a yellow filter, a blue filter, etc., and the three filters are arranged adjacently to form a pixel group. Among them, the red filter transmits red light waves, the yellow filter transmits yellow light waves, and the blue filter transmits blue light waves.

[0079] Please refer to Fig. 9 In some embodiments, a back-illuminated image sensor is provided, which is prepared by the back-illuminated image sensor preparation method in any of the above embodiments. The back-illuminated image sensor includes a substrate 10, and an isolation layer 11 and an initial semiconductor layer 12 are sequentially stacked along a first direction away from a first top surface 10a of the substrate 10, such as the oz direction; the top surface of the initial semiconductor layer 12 includes a plurality of isolation stacks (not shown) arranged at intervals along a second direction parallel to the first top surface 10a of the substrate 10, such as the ox direction, and the isolation stack includes an intermediate layer 21, a grid layer 22, and a plurality of isolation stacks (not shown) sequentially stacked along the first direction. Layer 22, the middle layer 21 includes at least two film layers stacked in sequence along a first direction and containing different trivalent elements; adjacent isolation stacks include a first target semiconductor layer 41, a first semiconductor layer 31, a second target semiconductor layer 42 and a second semiconductor layer 32 stacked in sequence along a direction away from the substrate 10; wherein the first semiconductor layer 31 and the first target semiconductor layer 41 both contain a first pentavalent element, and the second semiconductor layer 32 and the second target semiconductor layer 42 both contain a second pentavalent element; the top surface of the second semiconductor layer 32 and the exposed outer surface of the isolation stack are covered with a dielectric layer 50.

[0080] Please refer to Fig. 9 In some embodiments, the initial semiconductor layer 12 may include a SiB layer. The intermediate layer 21 includes a SiGa layer and an Al layer sequentially stacked along the first direction; the grid layer 22 includes a SiIn layer, a Ta layer sequentially stacked along the first direction. 2 O 5 The first semiconductor layer 31 includes a SiP layer; and the first target semiconductor layer 41 includes a P element.

[0081] Please refer to Fig. 9 In some embodiments, the second semiconductor layer 32 includes a SiAs layer; and the second target semiconductor layer 42 includes an As element.

[0082] For example, the dielectric constant of the dielectric layer 50 may be set to be greater than a preset dielectric constant threshold; the top surface of the second semiconductor layer 32 is flush with the top surface of the Al layer; and the dielectric layer 50 covers the outer surface of the grid layer 22 and the top surface of the second semiconductor layer 32. For example, the dielectric layer 50 may include HfO 2 layer.

[0083] Furthermore, multiple epitaxial growths are used to prepare the photodiodes in the BSI image sensor, thus avoiding substrate damage introduced by the photodiode preparation method using high-energy ion implantation in the traditional process.

[0084] By forming an isolation stack arranged at intervals in the pixel area, the internal structure of the pixel area is improved, the mutual penetration of photogenerated carriers between adjacent pixel areas is blocked, the probability of light diffusion to adjacent pixels is reduced, and the adverse effects of light and / or charge crosstalk on imaging quality are suppressed.

[0085] Please continue to refer to Fig. 9 In some embodiments, after forming the dielectric layer 50, it further includes: forming a filter 60 between the grid layers 22 adjacent along the second direction, such as the ox direction. The filter 60 includes but is not limited to a red filter, a yellow filter, a blue filter, etc., and the three filters are arranged adjacently to form a pixel group. Among them, the red filter transmits red light waves, the yellow filter transmits yellow light waves, and the blue filter transmits blue light waves.

[0086] Please continue to refer to Fig. 9 The method for preparing a back-illuminated image sensor and the back-illuminated image sensor in the embodiments of the present disclosure include the following unexpected technical effects:

[0087] By using the isolation stack as the initial isolation side wall, a first semiconductor layer 31 and a second semiconductor layer 32 containing different pentavalent elements are sequentially stacked between adjacent isolation stacks, wherein the top surface of the second semiconductor layer 32 is not higher than the bottom surface of the grid layer 22; a first ion diffusion process can be used to diffuse the first pentavalent element of the first semiconductor layer 31 into the initial semiconductor layer 12 to obtain a first target semiconductor layer 41 containing the first pentavalent element; and then a second ion diffusion process is used to diffuse the second pentavalent element of the second semiconductor layer 32 into the first semiconductor layer 31 to obtain a second target semiconductor layer 42 containing the second pentavalent element, and an isolation wall including a portion of the initial semiconductor layer 12, an intermediate layer 21 and a grid layer 22; since a PN junction is formed between the intermediate layer 21 containing different trivalent elements and the adjacent first target semiconductor layer 41 containing pentavalent elements, the first semiconductor layer 31, the second target semiconductor layer 42 and the second semiconductor layer 32, the PN junction can be used to effectively improve the isolation effect of the isolation wall, avoid signal crosstalk between the photosensitive stacks separated by the isolation wall, and thus improve the display quality of the BSI image sensor. Furthermore, in the embodiment of the present disclosure, an ion diffusion treatment process is adopted, so that the first pentavalent element of the first semiconductor layer 31 is diffused into the initial semiconductor layer 12 to obtain a first target semiconductor layer 41 containing the first pentavalent element, and the second pentavalent element of the second semiconductor layer 32 is diffused into the first semiconductor layer 31 to obtain a second target semiconductor layer 42 containing the second pentavalent element. Compared with the conventional technology of adopting an ion implantation process to obtain the first target semiconductor layer 41 containing the first pentavalent element and the second target semiconductor layer 42 containing the second pentavalent element, the embodiment of the present disclosure can effectively avoid unnecessary damage to the substrate 10 caused by high-energy ions in the ion implantation process, thereby further improving the performance and reliability of the back-illuminated image sensor. Furthermore, in the embodiment of the present disclosure, after forming a photosensitive stack including a first target semiconductor layer 41, a first semiconductor layer 31, a second target semiconductor layer 42 and a second semiconductor layer 32 stacked in sequence along a first direction, a dielectric layer 50 is used to cover the top surface of the second semiconductor layer 32 and the exposed outer surface of the isolation stack, so that the dielectric layer 50 can bind electrons in the photosensitive stack, thereby avoiding signal crosstalk between different photosensitive stacks and improving the performance and reliability of the image sensor.

[0088] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0089] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0090] The above-mentioned embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure.

Claims

1. A method for preparing a back-illuminated image sensor, characterized in that: include: Providing a substrate including a first top surface, wherein the first top surface includes an isolation layer and an initial semiconductor layer sequentially stacked along a first direction away from the first top surface; Forming a plurality of isolation stacks on the top surface of the initial semiconductor layer and arranged in a second direction parallel to the first top surface, wherein the isolation stacks include an intermediate layer and a grid layer sequentially stacked along the first direction, and the intermediate layer includes at least two film layers sequentially stacked along the first direction and containing different trivalent elements; A first semiconductor layer and a second semiconductor layer containing different pentavalent elements are sequentially formed between adjacent isolation stacks; the top surface of the second semiconductor layer is not higher than the bottom surface of the grid layer; diffusing the first pentavalent element of the first semiconductor layer into the initial semiconductor layer to obtain a first target semiconductor layer containing the first pentavalent element; diffusing the second pentavalent element of the second semiconductor layer into the first semiconductor layer to obtain a second target semiconductor layer containing the second pentavalent element; forming a dielectric layer covering the top surface of the second semiconductor layer and the exposed outer surface of the isolation stack; The intermediate layer including different trivalent elements is used to form a PN junction with the adjacent first target semiconductor layer, the first semiconductor layer, the second target semiconductor layer and the second semiconductor layer.

2. The method for preparing a back-illuminated image sensor according to claim 1, characterized in that: The initial semiconductor layer includes a SiB layer; The intermediate layer includes a SiGa layer and an Al layer sequentially stacked along the first direction; The first semiconductor layer includes a SiP layer; Forming the first target semiconductor layer includes: The SiP layer is processed by a first laser annealing process, so that P in the SiP layer diffuses into the SiB layer, thereby obtaining a first target semiconductor layer containing P elements.

3. The method for preparing a back-illuminated image sensor according to claim 2, characterized in that: The second semiconductor layer includes a SiAs layer; Forming the second target semiconductor layer includes: The SiAs layer is processed by a second laser annealing process, so that As in the SiAs layer diffuses into the SiP layer, thereby obtaining a second target semiconductor layer containing the As element.

4. The method for preparing a back-illuminated image sensor according to claim 2, characterized in that: The dielectric constant of the dielectric layer is greater than a preset dielectric constant threshold; the top surface of the second semiconductor layer is flush with the top surface of the Al layer; The dielectric layer covers the outer surface of the grid layer and the top surface of the second semiconductor layer.

5. The method for preparing a back-illuminated image sensor according to any one of claims 1 to 4, characterized in that: The substrate includes a plurality of first isolation structures extending into the substrate through the first top surface of the substrate and arranged at intervals along the second direction; The plurality of first isolation structures are located directly below the plurality of isolation stacks.

6. The method for preparing a back-illuminated image sensor according to any one of claims 1 to 4, characterized in that: The initial semiconductor layer includes a SiB layer; and forming the initial semiconductor layer includes: A SiB layer is formed on the top surface of the isolation layer by adopting a selective epitaxial deposition process.

7. The method for preparing a back-illuminated image sensor according to any one of claims 1 to 4, characterized in that: After forming the dielectric layer, the method further comprises: A filter is formed between adjacent grid layers along the second direction.

8. A back-illuminated image sensor, characterized in that: The back-illuminated image sensor is prepared by the method for preparing a back-illuminated image sensor according to any one of claims 1 to 7; the back-illuminated image sensor comprises a substrate, and an isolation layer and an initial semiconductor layer stacked in sequence along a first direction away from a first top surface of the substrate; The top surface of the initial semiconductor layer includes a plurality of isolation stacks arranged at intervals along a second direction parallel to the first top surface, the isolation stacks include an intermediate layer and a grid layer sequentially stacked along the first direction, the intermediate layer includes at least two film layers sequentially stacked along the first direction and containing different trivalent elements; Adjacent isolation stacks include a first target semiconductor layer, a first semiconductor layer, a second target semiconductor layer and a second semiconductor layer stacked in sequence in a direction away from the substrate; wherein the first semiconductor layer and the first target semiconductor layer both contain a first pentavalent element, and the second semiconductor layer and the second target semiconductor layer both contain a second pentavalent element; The top surface of the second semiconductor layer and the exposed outer surface of the isolation stack are covered with a dielectric layer.

9. The back-illuminated image sensor according to claim 8, characterized in that: The initial semiconductor layer includes a SiB layer; The intermediate layer includes a SiGa layer and an Al layer sequentially stacked along the first direction; The first semiconductor layer includes a SiP layer; The first target semiconductor layer contains a P element.

10. The back-illuminated image sensor according to claim 9, characterized in that: The second semiconductor layer includes a SiAs layer; The second target semiconductor layer contains As element.

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