A pixel driving circuit with Vth self-compensation

Abstract

The application discloses a pixel driving circuit with Vth self-compensation, comprising a first transistor, a second transistor, a third transistor and a fourth transistor, wherein the first source-drain electrode of the first transistor is coupled to a data signal line, the second source-drain electrode is coupled to a pre-storage node, and the gate electrode is coupled to a control signal line; the first source-drain electrode of the third transistor is coupled to the pre-storage node, the second source-drain electrode is coupled to a pixel node, and the gate electrode is coupled to a transfer signal line; the first source-drain electrode of the second transistor is coupled to a reference signal line, the second source-drain electrode is coupled to the pixel node, and the gate electrode is coupled to a self-compensation node; the first source-drain electrode of the fourth transistor is coupled to the data signal line, the second source-drain electrode is coupled to the self-compensation node, and the gate electrode is coupled to a reset signal line; one end of a self-compensation capacitor is coupled to the pre-storage node, and the other end is coupled to the self-compensation node; one end of a pre-storage capacitor is coupled to a coupling signal line, and the other end is coupled to the pre-storage node.

Description

Technical Field

[0001] This invention relates to the field of pixel driving technology, and more specifically to a pixel driving circuit with Vth self-compensation. Background Technology

[0002] In traditional field-sequential or color-sequential display driving technologies, the backlight can only be turned on after all screen data has been written and the liquid crystal has reached a stable state. Otherwise, image distortion will occur. Therefore, the data writing and liquid crystal deflection time greatly compresses the backlight turn-on time, leading to difficulties in increasing display brightness, refresh rate, and resolution, as well as increased power consumption and backlight material costs. Therefore, how to accelerate the liquid crystal driving time and increase the backlight turn-on time is a crucial issue.

[0003] Canon, in its US Patent No. 6,181,311, discloses a pixel driving circuit. This circuit differs from the conventional 1T2C pixel design in that, in addition to the pixel signal write switch TFT T1, it includes a data storage capacitor Cs1, a signal transfer TFT T2, and a reset TFT T3. The signal storage capacitor Cs1 is used to pre-store the pixel data voltage required for the next frame. The signal transfer TFT T2 transfers the pixel data voltage pre-stored in the signal storage capacitor Cs1 to the corresponding pixel voltage storage capacitor Cs2. The reset TFT T3 eliminates residual charge on the pixel capacitors to prevent color shift and brightness differences caused by residual charge. This circuit design allows the pixel data voltage of the next frame to be pre-stored in the signal storage capacitor Cs1 during backlight illumination, and all pixels synchronously read the pixel data voltage in the corresponding Cs1 during frame switching. This pixel data voltage register design saves pixel write time and correspondingly increases backlight illumination time.

[0004] However, this pixel circuit design faces the problem of voltage drop associated with charge sharing. Assuming the pre-charge capacitor Cs1 = Cs2 + Clc, and Vcom = 0V (i.e., the pixel electrode is reset to 0V before charging), then according to the principle of charge conservation, Cs1 needs to be pre-charged to 10V to charge Clc to 5V. Therefore, this driving method requires increasing the Data voltage supply range to meet the operating voltage range of the liquid crystal, placing higher demands on the output voltage range of the Source IC and significantly increasing power consumption. When the Source IC does not meet the requirements, a larger Cs1 capacitor is needed. Only when Cs1 is much larger than Cs2 + Clc will the voltage drop during charge sharing be smaller, but this will reduce the aperture ratio and increase the difficulty of pre-charging Cs1, which is not conducive to achieving high refresh rates and high resolutions.

[0005] In summary, traditional pixel driving circuits cannot simultaneously achieve high refresh rates, long illumination times, and high aperture ratios. Summary of the Invention

[0006] In view of this, the present invention provides a pixel driving circuit with Vth self-compensation. By improving the circuit structure and driving timing, it solves the problem that traditional pixel driving circuits cannot simultaneously achieve high refresh rate, long lamp brightness time and high aperture ratio.

[0007] To solve the above problems, the technical solution of the present invention is to employ a pixel driving circuit with Vth self-compensation, comprising: a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the first transistor's first source-drain is coupled to a data signal line, its second source-drain is coupled to a pre-storage node, and its gate is coupled to a control signal line; the third transistor's first source-drain is coupled to the pre-storage node, its second source-drain is coupled to a pixel node, and its gate is coupled to a transfer signal line; the second transistor's first source-drain is coupled to a reference signal line, its second source-drain is coupled to the pixel node, and its gate is coupled to a self-compensation node; the fourth transistor's first source-drain is coupled to a data signal line, its second source-drain is coupled to a self-compensation node, and its gate is coupled to a reset signal line; one end of the self-compensation capacitor is coupled to the pre-storage node, and the other end is coupled to the self-compensation node; one end of the pre-storage capacitor is coupled to a coupling signal line, and the other end is coupled to the pre-storage node.

[0008] Optionally, the driving timing of the pixel driving circuit is configured as follows: In the first frame, the backlight is kept off throughout. The reset signal first jumps to a high potential, the fourth transistor turns on, and the data signal is written to the self-compensation node. The reset signal first jumps back to a low potential, and the fourth transistor turns off. The potential change of the pre-stored node is V2, and the potential of the self-compensation node is expressed as V1, where V1 > V2. The reference signal line jumps to a high potential, the second transistor turns on, and until the second transistor operates in the saturation region, the potential of the pixel node becomes V1 - Vth, where Vth is the threshold voltage of the second transistor, and V1 - Vth > V2. When the transfer signal jumps to a high potential, the third transistor turns on, and the pixel node shares charge with the pre-storage node. As the potential of the pre-storage node increases, the potential of the self-compensation node is simultaneously affected and increases, further affecting the potential of the pixel node, until the potential difference between the self-compensation node and the pixel node is Vth and the potentials of the pre-storage node and the pixel node are the same. At this time, the voltage on the self-compensation capacitor is Vth, completing the threshold voltage extraction of the second transistor.

[0009] Optionally, the driving timing of the pixel driving circuit is configured as follows: during the backlight-on stage of the Nth frame, the control signal jumps to a high potential, the first transistor turns on, and the data signal is written to the pre-storage node. The control signal then jumps back to a low potential, and the first transistor turns off. The potential change of the pre-storage node is Vdata-VH. Affected by the potential change of the pre-storage node, when the voltage difference across the self-compensation capacitor is Vth, the potential change of the self-compensation node is Vdata-VH+Vth. When the coupling signal jumps to a high potential, the potential change of the pre-storage node is Vdata, and the potential change of the self-compensation node is Vdata-+Vth. When the reference signal jumps to a low potential, the second transistor turns on. After the potential of the pixel node is reset to a low potential, the reference signal jumps to a high potential until the second transistor operates in the saturation region, and the potential of the pixel node becomes Vdata, completing the writing of the data signal.

[0010] Optionally, when the threshold voltage of the second transistor decreases, the potential of the pixel node is Vdata', where Vdata' is greater than Vdata. After the pixel node completes the writing of the data signal, the transfer signal jumps to a high potential, and the third transistor turns on. At this time, the potential of the pixel node decreases, while the potentials of the pre-store node and the self-compensation node increase. Consequently, the voltage difference between the self-compensation node and the pixel node is greater than Vth, and the operating state of the second transistor becomes the linear region. This continues until the operating state of the second transistor returns to the saturation region. At this point, the voltage difference across the self-compensation capacitor is the threshold voltage of the second transistor in the current frame, thus enabling the pixel driving circuit to perform self-compensation based on the change in Vth.

[0011] Optionally, the pixel driving circuit further includes a holding capacitor and a pixel capacitor, one end of which is coupled to the pixel node and the other end of which is coupled to a common signal.

[0012] Optionally, the pixel driving circuit further includes a fifth transistor, a holding capacitor, and a pixel capacitor. The first source-drain of the fifth transistor is coupled to the pixel node, and the gate is coupled to the second transfer signal line. One end of the holding capacitor and the pixel capacitor are coupled to the second source-drain of the fifth transistor, and the other end is coupled to a common signal.

[0013] Optionally, when the pixel driving circuit is equipped with the fifth transistor, when the reference signal jumps to a high potential, the second transfer signal simultaneously jumps to a high potential, causing both the fifth transistor and the second transistor to turn on until the second transistor operates in the saturation region, at which point the potential of the pixel node and the upper plate of the pixel capacitor both become Vdata, completing the writing of the data signal; and before the transfer signal jumps to a high potential, the second transfer signal jumps back to a low potential, causing the potential of the upper plate of the pixel capacitor to be locked and not participating in the subsequent self-compensation process of the circuit.

[0014] Optionally, in a negative polarity frame, the low potential of the reference signal is configured as: Vcom-Vop_max; the high potential of the reference signal is configured as: higher than Vcom; where Vcom is the common signal and Vop_max is the driving voltage of the highest gray level of the pixel.

[0015] Optionally, in a positive polarity frame, the low potential of the reference signal is configured to be lower than Vcom; the high potential of the reference signal is configured to be Vcom + Vop_max; where Vcom is the common signal and Vop_max is the driving voltage of the highest gray level of the pixel. The primary improvement of this invention is the pixel driving circuit with Vth self-compensation provided. By setting a pre-storage capacitor in conjunction with the transistor, the grayscale voltage of the next frame is stored in the pre-storage capacitor during the backlight illumination time of the current frame. This enables all pixels to synchronously achieve grayscale voltage when the backlight is off, greatly reducing the pixel voltage writing time and relatively increasing the backlight illumination time.

[0016] Meanwhile, this invention, through the cooperation of the fourth transistor, the second transistor, the third transistor, and a capacitor, achieves the extraction of the threshold voltage of the second transistor in the first frame, ensuring that the interference caused by the threshold voltage is eliminated when writing the gate-controlled grayscale voltage, effectively ensuring the accuracy of grayscale voltage writing, and avoiding the problem of requiring a large capacitor for the pre-storage capacitor in the charge sharing scheme, effectively improving the aperture ratio and reducing the difficulty of pre-charging.

[0017] Furthermore, during subsequent circuit operation, the first, second, and third transistors, along with the capacitor, work together to dynamically update the voltage difference across the self-compensating capacitor based on the threshold voltage change of the second transistor. This solves a key problem in the gate control technology route, namely, the threshold voltage drift problem that occurs when the second transistor operates for a long time, further ensuring the accuracy of the grayscale voltage. Attached Figure Description

[0018] Figure 1 This is a simplified circuit diagram of the pixel driving circuit of Embodiment 1 of the present invention; Figure 2This is a simplified driving timing diagram of the first frame of the pixel driving circuit in Embodiment 1 of the present invention; Figure 3 This is a simplified driving timing diagram of the Nth frame of the pixel driving circuit in Embodiment 1 of the present invention; Figure 4 This is a simplified circuit diagram of the pixel driving circuit of Embodiment 2 of the present invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0022] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0024] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0025] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0026] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship. Example 1

[0027] Specifically, such as Figure 1 As shown, a pixel driving circuit with Vth self-compensation includes: a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. The first transistor T1 has its first source-drain coupled to the data signal line Data, its second source-drain coupled to the pre-storage node VA, and its gate coupled to the control signal line scan. The third transistor T3 has its first source-drain coupled to the pre-storage node VA, its second source-drain coupled to the pixel node VQ, and its gate coupled to the transfer signal line Tran. The second transistor T2 has its first source-drain coupled to the data signal line Data, its second source-drain coupled to the pixel node VQ, and its gate coupled to the transfer signal line Tran. The source and drain of the first transistor T4 are coupled to the reference signal line Vref, the second source and drain are coupled to the pixel node VQ, and the gate is coupled to the self-compensation node VP. The first source and drain of the fourth transistor T4 are coupled to the data signal line Data, the second source and drain are coupled to the self-compensation node VP, and the gate is coupled to the reset signal line Reset. One end of the self-compensation capacitor Cs1 is coupled to the pre-storage node VA, and the other end is coupled to the self-compensation node VP. One end of the pre-storage capacitor Cs3 is coupled to the coupling signal line Couple, and the other end is coupled to the pre-storage node VA.

[0028] Furthermore, the pixel driving circuit also includes a holding capacitor Cs2 and a pixel capacitor Clc, one end of which is coupled to the pixel node VQ and the other end is coupled to the common signal Vcom.

[0029] Specifically, the driving timing of the pixel driving circuit is configured as follows: In the first frame, as Figure 2As shown, the backlight remains off throughout the process. The reset signal first jumps to a high potential, turning on the fourth transistor T4, and the data signal is written to the self-compensation node VP. The reset signal first jumps back to a low potential, turning off the fourth transistor T4. Affected by the potential change of the self-compensation node VP, the potential change of the pre-storage node VA is V2, and the potential of the self-compensation node VP is expressed as V1, where V1 > V2. The reference signal line Vref jumps to a high potential, turning on the second transistor T2. Until the second transistor T2 operates in the saturation region, the potential of the pixel node VQ becomes V1 - Vth, where Vth is the threshold voltage of the second transistor T2, and V1 - Vth > V2. When the transfer signal jumps to a high potential, the third transistor T3 turns on, and the pixel node VQ shares charge with the pre-storage node VA. As the potential of the pre-storage node VA increases, the potential of the self-compensation node VP is simultaneously affected and increases, further affecting the potential of the pixel node VQ, until the potential difference between the self-compensation node VP and the pixel node VQ is Vth and the potentials of the pre-storage node VA and the pixel node VQ are the same. At this time, the voltage on the self-compensation capacitor Cs1 is Vth, completing the threshold voltage extraction of the second transistor T2.

[0030] like Figure 3 As shown, during the backlight-on phase of the Nth frame (N > 2), the control signal jumps to a high potential, the first transistor T1 turns on, and the data signal is written to the pre-storage node VA. The control signal then jumps back to a low potential, and the first transistor T1 turns off. The potential change of the pre-storage node VA is Vdata - VH. Affected by the potential change of the pre-storage node VA, when the voltage difference across the self-compensating capacitor Cs1 is Vth, the potential change of the self-compensating node VP is Vdata - VH + Vth. During the backlight-off phase of the Nth frame, the coupling signal jumps to a high potential, the potential change of the pre-storage node VA is Vdata, and the potential change of the self-compensating node VP is Vdata - + Vth. The reference signal jumps to a low potential, the second transistor T2 turns on, and after the potential of the pixel node VQ is reset to a low potential, the reference signal jumps to a high potential until the second transistor T2 operates in the saturation region, and the potential of the pixel node VQ becomes Vdata, completing the data signal writing. The driving timing of the second frame is similar to that of the Nth frame (N is greater than 2), except that the backlight is kept off throughout, so it will not be described in detail.

[0031] When the threshold voltage of the second transistor T2 decreases, the potential of the pixel node VQ is Vdata', which is greater than Vdata. After the pixel node VQ completes the writing of the data signal, the transfer signal jumps to a high potential, and the third transistor T3 turns on. At this time, the potential of the pixel node VQ decreases, and the potentials of the pre-storage node VA and the self-compensation node VP increase. Consequently, the voltage difference between the self-compensation node VP and the pixel node VQ is greater than Vth, and the operating state of the second transistor T2 becomes the linear region. Until the operating state of the second transistor T2 returns to the saturation region, the voltage difference across the self-compensation capacitor Cs1 is the threshold voltage of the second transistor T2 in the current frame, realizing self-compensation of the pixel driving circuit according to the change of Vth. The transfer signal, reference signal, and coupling signal jump to a low potential, entering the backlight on stage of the next frame.

[0032] Furthermore, the low potential of the coupling signal is -VH+Vcom, the high potential is Vcom, and VH>Vcom+Vop_max-(Vcom-Vop_max)=2Vop_max, so as to satisfy that T2 is in the off state regardless of whether the backlight is on in a positive or negative frame.

[0033] To facilitate understanding of the potential linkage principle between VA and VP in this case, the three working conditions involved are explained below: ① When the coupling voltage is upward and coupled with VH voltage, since transistors T1, T2, T3, and T4 are off, VA and VP are in a floating state, and are therefore coupled with VH voltage in the same direction. ② When transistor T1 is on and transistors T3 and T4 are off, Vdata voltage is written, the voltage Vth on Cs1 is fixed, and Vp is rewritten as Vdata + Vth. ③ When transistor T4 is on and transistors T1 and T3 are off, VD is written, and VA is coupled and divided to VD*Cs1 / (Cs1 + Cs3).

[0034] Furthermore, in negative polarity frames, the low potential of the reference signal is configured as: Vcom - Vop_max; the high potential of the reference signal is configured as: higher than Vcom; where Vcom is the common signal and Vop_max is the driving voltage of the highest gray level of the pixel.

[0035] Furthermore, in positive polarity frames, the low potential of the reference signal is configured to be lower than Vcom; the high potential of the reference signal is configured to be Vcom + Vop_max; where Vcom is the common signal and Vop_max is the driving voltage of the highest gray level of the pixel.

[0036] This invention, by setting a pre-storage capacitor in conjunction with a transistor, enables the storage of the grayscale voltage of the next frame during the backlight illumination time of the current frame. This allows all pixels to synchronously achieve grayscale voltage when the backlight is off, greatly reducing the pixel voltage writing time and relatively increasing the backlight illumination time.

[0037] Meanwhile, this invention, through the cooperation of the fourth transistor, the second transistor, the third transistor, and a capacitor, achieves the extraction of the threshold voltage of the second transistor in the first frame, ensuring that the interference caused by the threshold voltage is eliminated when writing the gate-controlled grayscale voltage, effectively ensuring the accuracy of grayscale voltage writing, and avoiding the problem of requiring a large capacitor for the pre-storage capacitor in the charge sharing scheme, effectively improving the aperture ratio and reducing the difficulty of pre-charging.

[0038] Furthermore, during subsequent circuit operation, the first, second, and third transistors, along with the capacitor, work together to dynamically update the voltage difference across the self-compensating capacitor based on the threshold voltage change of the second transistor. This solves a key problem in the gate control technology route, namely, the threshold voltage drift problem that occurs when the second transistor operates for a long time, further ensuring the accuracy of the grayscale voltage. Example 2

[0039] like Figure 4 As shown, the pixel driving circuit in this embodiment differs from the pixel driving circuit in Embodiment 1 in that: the pixel driving circuit further includes a fifth transistor T5, a holding capacitor Cs2, and a pixel capacitor Clc. The first source-drain of the fifth transistor T5 is coupled to the pixel node VQ, and the gate is coupled to the second transfer signal line Tran2. One end of the holding capacitor Cs2 and the pixel capacitor Clc are coupled to the second source-drain of the fifth transistor T5, and the other end is coupled to the common signal Vcom.

[0040] Furthermore, the difference between the driving timing of the pixel driving circuit in this embodiment and the driving timing of the pixel driving circuit in Embodiment 1 is that: when the pixel driving circuit is equipped with the fifth transistor T5, when the reference signal jumps to a high potential, the second transfer signal simultaneously jumps to a high potential, so that both the fifth transistor T5 and the second transistor T2 are turned on until the second transistor T2 is working in the saturation region, and the potential of the pixel node VQ and the upper plate of the pixel capacitor Clc both become Vdata, completing the writing of the data signal; and before the transfer signal jumps to a high potential, the second transfer signal jumps back to a low potential, so that the potential of the upper plate of the pixel capacitor Clc is locked and does not participate in the subsequent circuit self-compensation process.

[0041] Meanwhile, since the potential of the upper plate of the pixel capacitor Clc is locked, it does not participate in the subsequent circuit self-compensation process. Therefore, in this embodiment, the coupling signal does not need to jump, that is, one end of the pre-storage capacitor Cs3 does not need to be connected to the coupling signal line Couple, and can be directly connected to the common signal line (Vcom), saving the coupling signal line Couple compared to Embodiment 1. The above describes a pixel driving circuit with Vth self-compensation provided by embodiments of the present invention. The various embodiments are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

[0042] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can implement the described functions using different methods for each specific application, but such implementation should not be considered beyond the scope of the invention. The steps of the methods or algorithms described in connection with the embodiments disclosed herein can be implemented directly in hardware, software modules executed by a processor, or a combination of both. Software modules can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

Claims

1. A pixel driving circuit with Vth self-compensation, characterized in that, include: The first transistor (T1), the second transistor (T2), the third transistor (T3), and the fourth transistor (T4), wherein, The first transistor (T1) has its first source and drain coupled to the data signal line (Data), its second source and drain coupled to the pre-storage node (VA), and its gate coupled to the control signal line (scan); the third transistor (T3) has its first source and drain coupled to the pre-storage node (VA), its second source and drain coupled to the pixel node (VQ), and its gate coupled to the transfer signal line (Tran); the second transistor (T2) has its first source and drain coupled to the reference signal line (Vref), its second source and drain coupled to the pixel node (VQ), and its gate coupled to the self-compensation node (VP); the fourth transistor (T4) has its first source and drain coupled to the data signal line (Data), its second source and drain coupled to the self-compensation node (VP), and its gate coupled to the reset signal line (Reset). One end of the self-compensating capacitor (Cs1) is coupled to the pre-compensating node (VA), and the other end is coupled to the self-compensating node (VP); one end of the pre-compensating capacitor (Cs3) is coupled to the coupling signal line (Couple), and the other end is coupled to the pre-compensating node (VA). The driving timing of the pixel driving circuit is configured as follows: In the first frame, the backlight remains off throughout. The reset signal first jumps to a high potential, the fourth transistor (T4) turns on, and the data signal is written to the self-compensation node (VP). The reset signal first jumps back to a low potential, and the fourth transistor (T4) turns off. The potential change of the pre-store node (VA) is V2 due to the potential change of the self-compensation node (VP), and the potential of the self-compensation node (VP) is V1, where V1 > V2. When the reference signal line (Vref) jumps to a high potential, the second transistor (T2) turns on until the second transistor (T2) operates in the saturation region, and the potential of the pixel node (VQ) becomes V1-Vth, where Vth is the threshold voltage of the second transistor (T2), and V1-Vth > V2. When the transfer signal jumps to a high potential, the third transistor (T3) turns on, and the pixel node (VQ) shares charge with the pre-storage node (VA). As the potential of the pre-storage node (VA) increases, the potential of the self-compensation node (VP) is simultaneously affected and increases, further affecting the potential of the pixel node (VQ) until the potential difference between the self-compensation node (VP) and the pixel node (VQ) is Vth and the potentials of the pre-storage node (VA) and the pixel node (VQ) are the same. At this time, the voltage on the self-compensation capacitor (Cs1) is Vth, and the threshold voltage extraction of the second transistor (T2) is completed. During the backlight-on phase of the Nth (N > 2) frame, the control signal jumps to a high potential, the first transistor (T1) turns on, and the data signal is written to the pre-storage node (VA). The control signal then jumps back to a low potential, and the first transistor (T1) turns off. The potential change of the pre-storage node (VA) is Vdata - VH. Affected by the potential change of the pre-storage node (VA), when the voltage difference across the self-compensating capacitor (Cs1) is Vth, the potential change of the self-compensating node (VP) is Vdata - VH + Vth. Where VH is the voltage jump amplitude of the coupled signal line; During the backlight-off phase of the Nth frame, the coupling signal jumps to a high potential, the potential change of the pre-store node (VA) is Vdata, and the potential change of the self-compensation node (VP) is Vdata-+Vth. When the reference signal jumps to a low potential, the second transistor (T2) turns on, and the potential of the pixel node (VQ) is reset to a low potential. Then, the reference signal jumps to a high potential until the second transistor (T2) operates in the saturation region, and the potential of the pixel node (VQ) becomes Vdata, completing the writing of the data signal. When the threshold voltage of the second transistor (T2) drops, the potential of the pixel node (VQ) is Vdata', where Vdata' is greater than Vdata. After the pixel node (VQ) completes the writing of the data signal, the transfer signal jumps to a high potential, the third transistor (T3) turns on, at this time the potential of the pixel node (VQ) decreases, the potential of the pre-storage node (VA) and the self-compensation node (VP) increases, and then the voltage difference between the self-compensation node (VP) and the pixel node (VQ) is greater than Vth, and the working state of the second transistor (T2) becomes the linear region; Until the second transistor (T2) returns to the saturation region, the voltage difference across the self-compensating capacitor (Cs1) is the threshold voltage of the second transistor (T2) in the current frame, enabling the pixel driving circuit to perform self-compensation according to the change of Vth. The driving timing of the second frame is similar to that of the Nth (N is greater than 2) frame, and the backlight is kept off throughout.

2. The pixel driving circuit according to claim 1, characterized in that, The pixel driving circuit also includes a holding capacitor (Cs2) and a pixel capacitor (Clc). One end of the holding capacitor (Cs2) and the pixel capacitor (Clc) is coupled to the pixel node (VQ), and the other end is coupled to the common signal (Vcom).

3. The pixel driving circuit according to claim 1, characterized in that, The pixel driving circuit also includes a fifth transistor (T5), a holding capacitor (Cs2), and a pixel capacitor (Clc). The first source and drain of the fifth transistor (T5) are coupled to the pixel node (VQ), and the gate is coupled to the second transfer signal line (Tran2). One end of the holding capacitor (Cs2) and the pixel capacitor (Clc) is coupled to the second source and drain of the fifth transistor (T5), and the other end is coupled to the common signal (Vcom).

4. The pixel driving circuit according to claim 3, characterized in that, When the pixel driving circuit is equipped with the fifth transistor (T5), At the same time the reference signal jumps to a high potential, the second transfer signal also jumps to a high potential, causing both the fifth transistor (T5) and the second transistor (T2) to turn on until the second transistor (T2) is operating in the saturation region, at which point the potential of the pixel node (VQ) and the upper plate of the pixel capacitor (Clc) both become Vdata, completing the writing of the data signal; Furthermore, before the transfer signal jumps to a high potential, the second transfer signal jumps back to a low potential, causing the potential of the upper plate of the pixel capacitor (Clc) to be locked and not participate in the subsequent circuit self-compensation process.

5. The pixel driving circuit according to claim 1, characterized in that, In negative polarity frames, the low potential of the reference signal is configured as: Vcom - Vop_max; the high potential of the reference signal is configured as: higher than Vcom; where Vcom is the common signal and Vop_max is the driving voltage of the highest gray level of the pixel.

6. The pixel driving circuit according to claim 1, characterized in that, In a positive polarity frame, the low potential of the reference signal is configured to be lower than Vcom; the high potential of the reference signal is configured to be Vcom + Vop_max; where Vcom is the common signal and Vop_max is the driving voltage of the highest gray level of the pixel.

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