Gate control circuit and method capable of realizing Vth self-compensation

Abstract

The invention discloses a gate control circuit and method capable of realizing Vth self-compensation. The gate control circuit comprises a pre-storage unit, a compensation unit and a driving unit, the compensation unit comprises a second transistor and a fourth transistor; a grid electrode of the second transistor is coupled to a pre-storage unit, a first source drain electrode of the second transistor is coupled to a reference signal line, and a second source drain electrode of the second transistor is coupled to a second source drain electrode of the fourth transistor and a driving unit; a first source drain electrode of the fourth transistor is coupled to the pre-storage unit, and a grid electrode of the fourth transistor is coupled to a setting signal line. The beneficial effects of the invention are that the influence of the threshold voltage on the write-in pixel voltage is eliminated by using the conduction characteristic of the transistor, so that the image abnormity phenomenon caused by the drift of the threshold voltage is avoided.

Description

Technical Field

[0001] The present invention relates to the field of pixel display technology, and in particular to a gate control circuit and method capable of realizing Vth self-compensation. Background Art

[0002] Field sequential or color sequential display driving technology directly utilizes the RGB three-color light source to mix colors through the residual effect of human visual pause to achieve full-color display effect. No color filter is required, which improves the utilization rate of the light source on the one hand and reduces the power consumption of the light source on the other hand. The backlight can be turned on only after all the screen data is written and the liquid crystal is deflected to a stable state, otherwise there will be a chaotic picture, so a lot of time needs to be reserved for the liquid crystal to deflect before the backlight is turned on. This makes it difficult to achieve high brightness and high frequency display within the average time, and at the same time, the requirements for backlight brightness specifications and life are increased, which increases the cost.

[0003] Due to the influence of the transistor process, the threshold voltage of the driving transistors at different spatial positions is likely to be different. For a-Si, the threshold voltage of the hydrogenated amorphous silicon transistor changes over time. The change or inconsistency of the threshold voltage of the driving transistor will cause the LCD display to display unevenly. When displaying an image, the brightness of the image is determined by the current. If the current is related to the threshold voltage of the driving tube, the difference in the threshold voltage of each driving tube in each pixel will cause the brightness of the displayed image to be not the desired brightness. In fact, due to the deviation of the transistor manufacturing process, it is inevitable that the threshold voltage of each driving transistor is different and there is a certain deviation. Therefore, it is necessary to obtain a driving current that is independent of the threshold voltage to eliminate the adverse effects of the threshold voltage deviation on the brightness of the screen display.

[0004] Therefore, the present invention proposes a gate control circuit and method that can realize Vth self-compensation to eliminate the influence of threshold voltage, thereby avoiding the influence of abnormal screen display. Summary of the invention

[0005] The purpose of the present invention is to provide a gate control circuit and method capable of realizing Vth self-compensation, thereby eliminating the influence of threshold voltage.

[0006] The object of the present invention is to realize a gate control circuit capable of realizing Vth self-compensation through the following technical scheme, including a pre-storage unit, a compensation unit and a driving unit; The compensation unit includes a second transistor and a fourth transistor; the gate of the second transistor is coupled to the pre-storage unit, the first source and drain of the second transistor are coupled to the reference signal line, the second source and drain of the second transistor are coupled to the second source and drain of the fourth transistor and the driving unit; the first source and drain of the fourth transistor are coupled to the pre-storage unit, and the gate of the fourth transistor is coupled to the setting signal line.

[0007] Further, the pre-storage unit includes a first transistor and a pre-storage capacitor; the gate of the first transistor is coupled to the row gate signal line, and the first source and drain of the first transistor are coupled to the data signal line; the second source and drain of the first transistor are coupled to one end of the pre-storage capacitor, and the other end of the pre-storage capacitor is coupled to the gate of the second transistor and the first source and drain of the fourth transistor.

[0008] Furthermore, the pre-storage unit further includes a holding capacitor, one end of the holding capacitor is coupled to one end of the pre-storage capacitor, and the other end of the holding capacitor is coupled to the common signal line.

[0009] Furthermore, the driving unit includes a third transistor and a pixel electrode; the gate of the third transistor is coupled to the transfer signal line, the first source and drain of the third transistor are coupled to the second source and drain of the second transistor, the second source and drain of the third transistor are coupled to the pixel electrode, and the other end of the pixel electrode is coupled to the common signal line.

[0010] Furthermore, the driving unit further includes a holding capacitor, one end of the holding capacitor is coupled to the second source and drain of the third transistor, and the other end of the holding capacitor is coupled to the common signal line.

[0011] The present invention also provides a method for controlling a gate control circuit capable of realizing Vth self-compensation, comprising: During the backlight on phase: The row gate signal line jumps to a high level, the first transistor is turned on, and the data signal line pre-writes a data signal voltage into the pre-storage capacitor, so that the potential of the first node is the data signal voltage, and the potential of the second node is the first potential; After the pre-writing is completed, the row gate signal line jumps to a low level, and the fifth transistor is turned off; During the backlight off phase: The transfer signal line jumps to a high level, and the third transistor is turned on; the reference signal line jumps to a first low potential, so that the reference signal line is reset to the pixel electrode through the third transistor and the second transistor; After the reset is completed, the reference signal line jumps to the first high potential, and the second transistor is turned on, so that the reference signal line writes the pixel voltage to the pixel electrode through the second transistor and the third transistor; After writing is completed, the transfer signal line jumps to a low level, and the third transistor is turned off; the row gate signal line jumps to a high level, and the first transistor is turned on; the setting signal line jumps to a high level, and the fourth transistor is turned on; the reference signal line jumps to a common level; the data signal line passes through the first transistor to make the potential of the first node a high potential; the data signal line continues to discharge to the reference signal line through the second transistor and the fourth transistor until it reaches the cut-off region of the second transistor, at which time the potential of the second node and the potential of the third node are both the sum of the threshold voltage of the second transistor and the current voltage of the reference signal line.

[0012] Furthermore, before the backlight-on stage of the first frame, a pre-extraction stage is also included; the pre-extraction stage includes: The row gate signal line jumps to a high level, and the first transistor is turned on; the setting signal line jumps to a high level, and the fourth transistor is turned on; the data signal line writes a high potential signal to the pre-storage capacitor, and the first node, the second node, and the third node are all at high potential; The row gate signal line jumps to a low level, and the first transistor is turned off; the setting signal line jumps to a low level, and the fourth transistor is turned off; The level of the reference signal line jumps to a first high potential, and the second transistor is turned on; the transfer signal line jumps to a high level, the third transistor is turned on, and the reference signal line writes a high potential to the pixel electrode; The transfer signal line jumps to a low level, and the third transistor is turned off; The reference signal line jumps to a common level, the second node is at a high potential, the third node is at a high potential, and the third node discharges to the reference signal line until the second transistor reaches the cut-off region. At this time, the potential of the second node is the sum of the threshold voltage of the second transistor and the current voltage of the reference signal line.

[0013] The present invention has the following advantages: The present invention sets a fourth transistor and a second transistor, and the source and drain of the second transistor are coupled to a reference signal line; the second transistor cooperates with the on-off of the fourth transistor and the level jump of the reference signal line, so that the gate (i.e., the second node) of the second transistor is pre-written with the threshold voltage of the second transistor; thus, when writing the pixel voltage to the pixel electrode in the backlight off stage, the pre-compensated threshold voltage is used, so that the pixel voltage written to the pixel electrode is a voltage not affected by the threshold voltage, thereby avoiding the difference in the threshold voltage of each driving transistor due to uneven process and the existence of a certain deviation; therefore, it is necessary to obtain a voltage that is independent of the threshold voltage to eliminate the adverse effect of the threshold voltage deviation on the screen display brightness; Furthermore, the present invention only has a pre-extraction stage before the first frame, which is used to extract the threshold voltage of the second transistor before working; and after the nth frame starts, the threshold voltage of the second transistor is extracted again at the end of the nth frame and pre-written into the second node for writing the pixel voltage of the n+1th frame, thereby pre-extracting the transistor threshold voltage in each frame of the cycle, thereby extracting the threshold voltage from time to time and making corrections from time to time, thereby avoiding abnormal screen display caused by the drift of the transistor threshold voltage over time. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a circuit diagram of Embodiment 1 of the present invention; Figure 2 It is a timing diagram of the first embodiment of the present invention / a timing diagram of the third embodiment of the present invention; Figure 3 This is a circuit diagram of Embodiment 2 of the present invention. DETAILED DESCRIPTION

[0015] The present invention is further described below in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following description.

[0016] It should be noted that the directions or positional relationships indicated by "left", "right", etc. are based on the directions or positional relationships shown in the accompanying drawings, or are the directions or positional relationships in which the inventive product is usually placed when in use, or are the directions or positional relationships commonly understood by those skilled in the art. Such terms are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0017] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features and technical solutions in the embodiments may be combined with each other. Example

[0018] See also Figure 1 , the present invention provides embodiment 1, which is a gate control circuit capable of realizing Vth self-compensation, including a pre-storage unit, a compensation unit and a driving unit; The compensation unit includes a second transistor T2 and a fourth transistor T4; the gate of the second transistor T2 is coupled to one end of the pre-storage capacitor Cs1, the first source and drain of the second transistor T2 are coupled to the reference signal line Vref, and the second source and drain of the second transistor T2 are coupled to the second source and drain of the fourth transistor T4; the first source and drain of the fourth transistor T4 are coupled to one end of the pre-storage capacitor Cs1, and the gate of the fourth transistor T4 is coupled to the setting signal line Set.

[0019] The pre-storage unit includes a first transistor T1 and a pre-storage capacitor Cs1; the gate of the first transistor T1 is coupled to the row gate signal line Scan, and the first source and drain of the first transistor T1 are coupled to the data signal line Data; the second source and drain of the first transistor T1 are coupled to one end of the pre-storage capacitor Cs1, and the other end of the pre-storage capacitor Cs1 is coupled to the gate of the second transistor T2 and the first source and drain of the fourth transistor T4.

[0020] The driving unit includes a third transistor T3, a pixel electrode Clc and a holding capacitor Cs2; the gate of the third transistor T3 is coupled to the transfer signal line Tran, the first source and drain of the third transistor T3 are coupled to the second source and drain of the second transistor T2, the second source and drain of the third transistor T3 are coupled to the pixel electrode Clc, and the other end of the pixel electrode Clc is coupled to the common signal line Com; one end of the holding capacitor Cs2 is coupled to the second source and drain of the third transistor T3, and the other end of the holding capacitor Cs2 is coupled to the common signal line Com.

[0021] Before the circuit works in the first frame backlight-on phase, it also includes a pre-extraction phase; The row gate signal line Scan jumps to a high level, and the first transistor T1 is turned on; the set signal line Set jumps to a high level, and the fourth transistor T4 is turned on; the data signal line Data writes a high potential signal to the pre-storage capacitor Cs1, and the first node A, the second node B and the third node Q are all at high potential; The row gate signal line Scan jumps to a low level, and the first transistor T1 is turned off; the set signal line Set jumps to a low level, and the fourth transistor T4 is turned off; The level of the reference signal line Vref jumps to a first high potential, and the second transistor T2 is turned on; the transfer signal line Tran jumps to a high level, and the third transistor T3 is turned on, and the reference signal line Vref writes a high potential to the pixel electrode; The transfer signal line Tran jumps to a low level, and the third transistor T3 is turned off; The reference signal line Vref jumps to a common level, that is, Vref=Vcom, the second node B is at a high potential, the third node Q is at a high potential, and the third node Q discharges to the reference signal line Vref until the second transistor T2 reaches the cut-off region. At this time, the potential of the second node B is the sum of the threshold voltage of the second transistor T2 and the current voltage of the reference signal line Vref, that is, the current VB=Vth+Vref.

[0022] The pre-extraction stage is used to write a positive threshold voltage Vth of the second transistor T2 into the second node B in advance, so as to obtain the first potential of the second node B during the capacitive coupling in the backlight-on stage of the first frame.

[0023] In the pre-extraction stage, the on and off states of the second transistor T2 are changed by the on and off of the fourth transistor T4 and the level jump of the reference signal line Vref, so that the threshold voltage Vth of the second transistor T2 is pre-written into the second node B. At this time, the second transistor T2 is used to pre-extract the threshold voltage Vth of the transistor.

[0024] In operation, the timing diagram of the pixel circuit is configured as follows Figure 2 As shown, During the backlight on phase: The row gate signal line Scan jumps to a high level, the first transistor T1 is turned on, and the data signal line Data pre-writes a data signal voltage into the pre-storage capacitor Cs1; At this time, the potential of the first node A across the pre-storage capacitor Cs1 is the data signal voltage Vdata; The potential of the second node B is the first potential, which is obtained by coupling the pre-storage capacitor Cs1 through the two-terminal capacitors. VB=Vdata-Vop_max+Vcom+Vth; Where: Vdata: data signal voltage; Vop_max: maximum grayscale corresponding voltage; Vcom=Vref: common level; Vth: threshold voltage of the second transistor T2; Set Vdata-Vop_max+Vcom as VD, then VB=VD+Vth; wherein VD is the pixel voltage that actually needs to be written into the pixel electrode Clc in the Nth frame; After pre-writing is completed, the row gate signal line Scan jumps to a low level, and the fifth transistor T5 is turned off. In the backlight on stage, the potential of the second node B can reach the required first potential VD+Vth through the charge conservation law of the capacitor and the pre-written voltage.

[0025] During the backlight off phase: The transfer signal line Tran jumps to a high level, and the third transistor T3 is turned on; the reference signal line Vref jumps to a first low potential, and the first low potential is Vcom-Vop_max, so that the reference signal line Vref resets the pixel electrode Clc through the third transistor T3 and the second transistor T2; By turning on the third transistor T3, turning on the second transistor T2 and the reference signal line Vref jumping to the first low potential, the pixel electrode Clc can release the residual charge of the previous frame through the third transistor T3 and the second transistor T2 to avoid affecting the display of the pixel voltage that currently needs to be written. The second transistor T2 assists the pixel electrode Clc in completing the resetting.

[0026] After the reset is completed, the reference signal line Vref jumps to the first high potential, which is Vcom+Vop_max. At this time, the second transistor T2 is fully turned on, so that the reference signal line Vref writes the pixel voltage VD to the pixel electrode Clc through the second transistor T3 and the third transistor T4. The potential of the second node B is VB=VD+Vth. When the second transistor T2 reaches the cut-off region, the potential of the third node Q is VQ=VB-Vth. Therefore, the potential of the input pixel electrode Clc is VQ, that is, VQ=VB-Vth=VD+Vth-Vth=VD. Therefore, VD is written into the pixel electrode Clc. This embodiment pre-compensates the threshold voltage Vth of the second transistor T2 by turning on and off the first transistor T1 , the second transistor T2 and the third transistor T3 in the circuit structure, thereby removing the influence of the threshold voltage Vth when writing the pixel voltage.

[0027] After the pixel voltage is written, the transfer signal line Tran jumps to a low level, and the third transistor T3 is turned off; the row gate signal line Scan jumps to a high level, and the first transistor T1 is turned on; the setting signal line Set jumps to a high level, and the fourth transistor T4 is turned on; the reference signal line Vref jumps to a common level Vcom; The level of the data signal line Data is Vop_max at this time, and the data signal line Data makes the potential of the first node A Vop_max through the first transistor T1; The data signal line Data continues to discharge to the reference signal line Vref through the second transistor T2 and the fourth transistor T4 until reaching the cut-off region of the second transistor T2. At this time, the potentials of the second node B and the third node Q are both Vcom+Vth.

[0028] After the pixel voltage of the nth frame is written, the threshold voltage Vth of the current second transistor T2 is extracted through the state changes of the second transistor T2, the fourth transistor T4 and the reference signal line Vref, and the threshold voltage Vth at this time is written into the second node B for writing the pixel voltage of the n+1th frame. By constantly extracting and correcting the threshold voltage Vth, the abnormal screen display caused by the drift of the threshold voltage Vth of the transistor during the display working time can be avoided.

[0029] The present invention sets a fourth transistor T4 and a second transistor T2, wherein the gate of the second transistor T2 is coupled to one end of a pre-storage capacitor Cs1, the first source and drain of the second transistor T2 is coupled to a reference signal line Vref, and the second source and drain of the second transistor T2 is coupled to the second source and drain of the fourth transistor T4; in the pre-extraction stage, the fourth transistor T4 and the reference signal line Vref cooperate to extract the threshold voltage Vth of the second transistor T2; in the backlight off stage, the second transistor T2 and the third transistor T3 are turned on and off, so that the pixel electrode Clc is reset; after the reset is completed, the pre-written threshold voltage Vth is used when writing the pixel voltage to the pixel electrode Clc, so that the written pixel voltage can subtract the influence of the threshold voltage Vth, thereby avoiding the abnormal display of the screen caused by the uneven process in the surface and the drift of the threshold voltage of the transistor over time. Example

[0030] like Figure 3 As shown, in some specific embodiments, such as the second embodiment, the pre-storage unit further includes a holding capacitor Cs3, one end of the holding capacitor Cs3 is coupled to one end of the pre-storage capacitor Cs3, and the other end of the holding capacitor Cs3 is coupled to the common signal line Com; The capacitor Cs3 stores the data signal voltage inputted by the data signal line Data and is used to maintain the potential of the second node B. At this time, the potential of the second node B is: VB=(Vdata-Vop)*C3 / (C1+C3)+Vcom+Vth; Let (Vdata-Vop)*C3 / (C1+C3)+Vcom be VD.

[0031] When writing the pixel voltage in the backlight off stage, the reference signal line Vref jumps to the first high potential, which is Vcom+Vop_max. At this time, the second transistor T2 is fully turned on, so that the reference signal line Vref writes the pixel voltage VD to the pixel electrode Clc through the second transistor T3 and the third transistor T4. The potential of the second node B is VB=VD+Vth. When the second transistor T2 reaches the cut-off region, the potential of the third node Q is VQ=VB-Vth. Therefore, the potential of the input pixel electrode Clc is VQ, that is, VQ=VB-Vth=VD+Vth-Vth=VD. Therefore, VD is written into the pixel electrode Clc.

[0032] Compared with the first embodiment, the present embodiment has a better voltage holding rate, and can maintain the potential of the second node B in each stage of the circuit. The threshold voltage Vth is stored in the stable potential of the second node B, so that the potential of the second node B can continue to stabilize the first potential until the pixel voltage is written into the pixel electrode Clc, and leakage due to the on-off of the transistor will not cause potential instability; however, due to the addition of the maintenance capacitor Cs3, the aperture ratio of the present embodiment is reduced compared with the first embodiment. Example

[0033] like Figure 2 As shown, the third embodiment is a control method for a gate control circuit that can realize Vth self-compensation.

[0034] Before the circuit works in the first frame backlight-on phase, it also includes a pre-extraction phase; The row gate signal line Scan jumps to a high level, and the first transistor T1 is turned on; the set signal line Set jumps to a high level, and the fourth transistor T4 is turned on; the data signal line Data writes a high potential signal to the pre-storage capacitor Cs1, and the first node A, the second node B and the third node Q are all at high potential; The row gate signal line Scan jumps to a low level, and the first transistor (T1) is turned off; the set signal line (Set) jumps to a low level, and the fourth transistor T4 is turned off; The level of the reference signal line Vref jumps to the first high potential, and the second transistor T2 is turned on; the transfer signal line (Tran) jumps to a high level, and the third transistor T3 is turned on, and the reference signal line Vref writes a high potential to the pixel electrode; The transfer signal line Tran jumps to a low level, and the third transistor T3 is turned off; The reference signal line Vref jumps to a common level, that is, Vref=Vcom, the second node B is at a high potential, the third node Q is at a high potential, and the third node Q discharges to the reference signal line Vref until the second transistor T2 reaches the cut-off region. At this time, the potential of the second node B is the sum of the threshold voltage of the second transistor T2 and the current voltage of the reference signal line Vref, that is, the current VB=Vth+Vref.

[0035] The pre-extraction stage is used to write a positive threshold voltage Vth of the second transistor T2 into the second node B in advance, so as to obtain the first potential of the second node B during the capacitive coupling in the backlight-on stage of the first frame.

[0036] During the backlight on phase: The row gate signal line Scan jumps to a high level, the first transistor T1 is turned on, and the data signal line Data pre-writes a data signal voltage into the pre-storage capacitor Cs1; At this time, the potential of the first node A across the pre-storage capacitor Cs1 is the data signal voltage Vdata; The potential of the second node B is the first potential, which is obtained by coupling the pre-storage capacitor Cs1 through the two-terminal capacitors. VB=Vdata-Vop_max+Vcom+Vth; Set Vdata-Vop_max+Vcom as VD, then VB=VD+Vth; wherein VD is the pixel voltage that actually needs to be written into the pixel electrode Clc in the Nth frame; After the pre-writing is completed, the row gate signal line Scan jumps to a low level, and the fifth transistor T5 is turned off.

[0037] During the backlight off phase: The transfer signal line Tran jumps to a high level, and the third transistor T3 is turned on; the reference signal line Vref jumps to a first low potential, and the first low potential is Vcom-Vop_max, so that the reference signal line Vref resets the pixel electrode Clc through the third transistor T3 and the second transistor T2; After the reset is completed, the reference signal line Vref jumps to the first high potential, which is Vcom+Vop_max. At this time, the second transistor T2 is fully turned on, so that the reference signal line Vref writes the pixel voltage VD to the pixel electrode Clc through the second transistor T3 and the third transistor T4. The potential of the second node B is VB=VD+Vth. When the second transistor T2 reaches the cut-off region, the potential of the third node Q is VQ=VB-Vth. Therefore, the potential of the input pixel electrode Clc is VQ, that is, VQ=VB-Vth=VD+Vth-Vth=VD. Therefore, VD is written into the pixel electrode Clc. After the pixel voltage is written, the transfer signal line Tran jumps to a low level, and the third transistor T3 is turned off; the row gate signal line Scan jumps to a high level, and the first transistor T1 is turned on; the setting signal line Set jumps to a high level, and the fourth transistor T4 is turned on; the reference signal line Vref jumps to a common level Vcom; The level of the data signal line Data is Vop_max at this time, and the data signal line Data makes the potential of the first node A Vop_max through the first transistor T1; The data signal line Data continues to discharge to the reference signal line Vref through the second transistor T2 and the fourth transistor T4 until reaching the cut-off region of the second transistor T2. At this time, the potentials of the second node B and the third node Q are both Vcom+Vth.

[0038] This embodiment is used for the control method of the specific circuits of Embodiment 1 and Embodiment 2, and the beneficial effects of this embodiment are the same as those of the above embodiments.

[0039] The above embodiments only express preferred implementation modes, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention. It should be pointed out that, for ordinary technicians in this field, several modifications and improvements can be made without departing from the invention, and these all belong to the protection scope of the invention.

Claims

1. A gate control circuit capable of realizing Vth self-compensation, characterized in that: It includes a pre-storage unit, a compensation unit and a driving unit; The compensation unit includes a second transistor (T2) and a fourth transistor (T4); the gate of the second transistor (T2) is coupled to the pre-storage unit, the first source and drain of the second transistor (T2) are coupled to the reference signal line (Vref), the second source and drain of the second transistor (T2) are coupled to the second source and drain of the fourth transistor (T4) and the driving unit; the first source and drain of the fourth transistor (T4) are coupled to the pre-storage unit, and the gate of the fourth transistor (T4) is coupled to the setting signal line (Set).

2. A gate control circuit capable of realizing Vth self-compensation according to claim 1, characterized in that: The pre-storage unit comprises a first transistor (T1) and a pre-storage capacitor (Cs1); The gate of the first transistor (T1) is coupled to a row gate signal line (Scan), and the first source and drain of the first transistor (T1) are coupled to a data signal line (Data); the second source and drain of the first transistor (T1) are coupled to one end of a pre-storage capacitor (Cs1), and the other end of the pre-storage capacitor (Cs1) is coupled to the gate of the second transistor (T2) and the first source and drain of the fourth transistor (T4).

3. A gate control circuit capable of realizing Vth self-compensation according to claim 2, characterized in that: The pre-storage unit further includes a holding capacitor (Cs3), one end of the holding capacitor (Cs3) is coupled to one end of the pre-storage capacitor (Cs1), and the other end of the holding capacitor (Cs3) is coupled to a common signal line (Com).

4. The gate control circuit capable of realizing Vth self-compensation according to claim 1, characterized in that: The driving unit includes a third transistor (T3) and a pixel electrode (Clc); The gate of the third transistor (T3) is coupled to the transfer signal line (Tran), the first source and drain of the third transistor (T3) are coupled to the second source and drain of the second transistor (T2), the second source and drain of the third transistor (T3) are coupled to the pixel electrode (Clc), and the other end of the pixel electrode (Clc) is coupled to the common signal line (Com).

5. A gate control circuit capable of realizing Vth self-compensation according to claim 4, characterized in that: The driving unit further comprises a holding capacitor (Cs2), one end of which is coupled to the second source-drain of the third transistor (T3), and the other end of which is coupled to the common signal line (Com).

6. A method for controlling a gate control circuit capable of realizing Vth self-compensation, applied to any pixel circuit according to claim 1 to claim 5, characterized in that: include: During the backlight on phase: The row gate signal line (Scan) jumps to a high level, the first transistor (T1) is turned on, and the data signal line (Data) pre-writes a data signal voltage into the pre-storage capacitor (Cs1), so that the potential of the first node (A) is the data signal voltage, and the potential of the second node (B) is the first potential; After the pre-writing is completed, the row gate signal line (Scan) jumps to a low level, and the fifth transistor (T5) is turned off; During the backlight off phase: The transfer signal line (Tran) jumps to a high level, and the third transistor (T3) is turned on; the reference signal line (Vref) jumps to a first low potential, so that the reference signal line (Vref) resets the pixel electrode (Clc) through the third transistor (T3) and the second transistor (T2); After the reset is completed, the reference signal line (Vref) jumps to the first high potential, and the second transistor (T2) is turned on, so that the reference signal line (Vref) writes the pixel voltage to the pixel electrode through the second transistor (T2) and the third transistor (T3); After the pixel voltage is written, the transfer signal line (Tran) jumps to a low level, and the third transistor (T3) is turned off; the row gate signal line (Scan) jumps to a high level, and the first transistor (T1) is turned on; The set signal line (Set) jumps to a high level, and the fourth transistor (T4) is turned on; the reference signal line (Vref) jumps to a common level; The data signal line (Data) makes the potential of the first node (A) high through the first transistor (T1); The data signal line (Data) continues to discharge to the reference signal line (Vref) through the second transistor (T2) and the fourth transistor (T4) until it reaches the cut-off region of the second transistor (T2). At this time, the potential of the second node (B) is the sum of the threshold voltage of the second transistor (T2) and the current voltage of the reference signal line (Vref).

7. A gate control circuit control method capable of realizing Vth self-compensation according to claim 6, characterized in that: Before the backlight-on stage of the first frame, a pre-extraction stage is also included; The pre-extraction stage includes: The row gate signal line (Scan) jumps to a high level, and the first transistor (T1) is turned on; the set signal line (Set) jumps to a high level, and the fourth transistor (T4) is turned on; the data signal line (Data) writes a high potential signal to the pre-storage capacitor (Cs1), and the potentials of the first node (A), the second node (B) and the third node (Q) are all high potentials; The row gate signal line (Scan) jumps to a low level, and the first transistor (T1) is turned off; the set signal line (Set) jumps to a low level, and the fourth transistor (T4) is turned off; The level of the reference signal line (Vref) jumps to a first high potential, and the second transistor (T2) is turned on; the transfer signal line (Tran) jumps to a high level, and the third transistor (T3) is turned on, and the reference signal line (Vref) writes a high potential to the pixel electrode; The transfer signal line (Tran) jumps to a low level, and the third transistor (T3) is turned off; The reference signal line (Vref) jumps to a common level, the second node (B) is at a high potential, the third node (Q) is at a high potential, and the third node (Q) discharges to the reference signal line (Vref) until the second transistor (T2) reaches the cut-off region. At this time, the potential of the second node (B) is the sum of the threshold voltage of the second transistor (T2) and the current voltage of the reference signal line (Vref).

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