半导体结构的制备方法、半导体结构、器件及设备
By forming CMOS transistors and memory cells back-to-back on a substrate, and employing curved channels and flip-chip technology, the process difficulty and complexity of embedded memory technology are solved, device performance is improved and leakage current and power consumption are reduced, and further scaling of semiconductor devices is supported.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- PEKING UNIV
- Filing Date
- 2024-10-23
- Publication Date
- 2026-07-17
AI Technical Summary
Existing embedded storage technologies suffer from high manufacturing difficulty, high complexity, and poor performance of the resulting devices, especially in complex computing scenarios such as high-performance computing and large artificial intelligence models.
A manufacturing process for independently fabricating logic circuits and memory cells is achieved by forming first and second active structures on a substrate, respectively fabricating CMOS transistors and memory cells, using curved channel memory cells and CMOS transistors for back-to-back integration, and achieving homogeneous integration through a flip-chip process.
It reduces the manufacturing difficulty and complexity of semiconductor structures, improves device performance, shortens signal delay, reduces leakage current and power consumption, and supports further scaling of semiconductor devices.
Smart Images
Figure CN119421414B_ABST