A high-reliability planar gate silicon carbide VDMOS and a preparation method thereof

Abstract

The invention provides a high-reliability planar gate silicon carbide VDMOS and a preparation method thereof. The invention comprises the following steps: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, and ion implanting to form a current-equalizing layer, a body region, a P-type well region, and an N-type source region; reforming the barrier layer, etching, and depositing to form an insulating dielectric layer; reforming the barrier layer, etching, and depositing to form a gate dielectric layer; reforming the barrier layer, etching, and depositing metal to form a gate metal layer and a source metal layer, and removing the barrier layer to complete the preparation. The gate reliability of the device and the freewheeling loss and reverse recovery speed of the body diode are effectively improved.

Description

Technical Field

[0001] The invention relates to a high-reliability planar gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide (SiC) vertical bipolar metal oxide semiconductor (VDMOS) power devices, with their excellent performance, occupy a pivotal position in the field of modern power electronics. They are not only the best in the SiC power device family, but also play an irreplaceable role in many high-tech fields such as electric vehicles, aerospace, and power conversion. These application fields have different focuses on the performance of SiC VDMOS devices, but in general, they all pursue the overall improvement of device performance.

[0003] First, higher voltage resistance is an indispensable feature of silicon carbide VDMOS devices in high-voltage applications; second, faster switching speed is the key to improving energy efficiency and reducing device size; third, higher reliability is the goal pursued by all power electronic devices; finally, lower body diode conduction loss is a key factor in improving energy efficiency and reducing costs.

[0004] In summary, the overall requirements for silicon carbide VDMOS devices are higher voltage withstand capability, faster switching speed, higher reliability and lower body diode conduction loss. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a high-reliability planar gate silicon carbide VDMOS and a preparation method thereof, which can effectively improve the gate reliability and body diode freewheeling loss and reverse recovery speed of the device.

[0006] In a first aspect, the present invention provides a method for preparing a high-reliability planar gate silicon carbide VDMOS, comprising the following steps:

[0007] Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer;

[0008] Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a current equalizing layer;

[0009] Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and implanting ions into the drift layer to form a body region;

[0010] Step 4: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a P-type well region;

[0011] Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the P-type well region to form an N-type source region;

[0012] Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the drift layer to form a groove, deposit an insulating medium, and form an insulating medium layer;

[0013] Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate dielectric layer;

[0014] Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer;

[0015] Step 9: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

[0016] In a second aspect, the present invention provides a high-reliability planar gate silicon carbide VDMOS, wherein the silicon carbide VDMOS is prepared by the method for preparing a high-reliability planar gate silicon carbide VDMOS described in the first aspect.

[0017] The advantages of the present invention are:

[0018] First, an insulating dielectric layer is constructed directly under the planar gate, and the P-type well region and the drift layer directly under the gate naturally form a space charge region. However, as the distance from the P-type well region increases, the depth of the space charge region decreases, and it becomes more difficult to withstand the drain voltage. The insulating dielectric layer constructed by the present invention has the ability to withstand high voltage, which can effectively improve the gate's ability to withstand the impact of the drain voltage and improve the reliability of the device;

[0019] Second, when the device is turned on by applying a positive voltage to the gate, the conductive channel formed is mainly distributed in an area about 400nm close to the P-type well region. The distance between the outer side of the constructed insulating dielectric layer and the inner side of the P-type well region is 500nm. This spacing setting can reduce the impact on the device's conduction performance;

[0020] 3. A current balancing layer is constructed. The current balancing layer can effectively redistribute the current from the N-type source region of the device in this area and divert it to the left and right sides of the device to avoid current concentration and thermal failure of the device. The width of the current balancing layer is 300nm smaller than the sum of the widths of the P-type well region and the N-type body region. Since the P-type well region and the N-type drift layer form a space charge region near the gate area to protect the device gate, the setting of the N-type current balancing layer improves the reliability of the device gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0022] Figure 1 The schematic diagram of a high-reliability planar gate silicon carbide VDMOS of the present invention is shown in FIG.

[0023] Figure 2 A cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS of the present invention Figure 1 .

[0024] Figure 3 A cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS of the present invention Figure 2 .

[0025] Figure 4 A cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS of the present invention Figure 3 .

[0026] Figure 5 A cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS of the present invention Figure 4 .

[0027] Figure 6 A cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS of the present invention Figure 5 .

[0028] Figure 7 A cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS of the present invention Figure 6 .

[0029] Figure 8 A cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS of the present invention Figure 7 .

[0030] Fig. 9 A cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS of the present invention Figure 8 .

[0031] Fig.10 A cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS of the present invention Figure 9 .

[0032] Fig.11 A cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS of the present invention Figure 10 . DETAILED DESCRIPTION

[0033] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0035] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0036] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0037] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0038] like Figures 1 to 11 As shown, the embodiment of the present application provides a method for preparing a high-reliability planar gate silicon carbide VDMOS, comprising the following steps:

[0039] Step 1: depositing metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 110; epitaxially growing on the side of the silicon carbide substrate 101 to form a drift layer 102;

[0040] Step 2: forming a barrier layer 111 on the drift layer 102, etching the barrier layer 111 to form a through hole, and performing ion implantation into the drift layer 102 to form a current-balancing layer 103;

[0041] Step 3, removing the original barrier layer 111, re-forming the barrier layer 111, etching the barrier layer 111 to form a through hole, and performing ion implantation into the drift layer 102 to form a body region 104;

[0042] Step 4: remove the original barrier layer 111, re-form the barrier layer 111, etch the barrier layer 111 to form a through hole, and perform ion implantation into the drift layer 102 to form a P-type well region 105;

[0043] Step 5, removing the original barrier layer 111, re-forming the barrier layer 111, etching the barrier layer 111 to form a through hole, and performing ion implantation into the P-type well region 105 to form an N-type source region 1051;

[0044] Step 6: remove the original barrier layer 111, re-form the barrier layer 111, etch the barrier layer 111 to form a through hole, etch the drift layer 102 to form a groove 10211, deposit an insulating dielectric to form an insulating dielectric layer 106;

[0045] Step 7, removing the original barrier layer 111, re-forming the barrier layer 111, etching the barrier layer 111 to form a through hole, and depositing to form a gate dielectric layer 107;

[0046] Step 8, removing the original barrier layer 111, re-forming the barrier layer 111, etching the barrier layer 111 to form a through hole, depositing metal, and forming a gate metal layer 109;

[0047] Step 9, remove the original barrier layer 111, re-form the barrier layer 111, etch the barrier layer 111 to form a through hole, deposit metal to form a source metal layer 108, remove the barrier layer 111, and complete the preparation.

[0048] In this embodiment, preferably, the distance between the outer side surface of the insulating dielectric layer 106 and the inner side surface of the P-type well region 105 is 500 nm.

[0049] In this embodiment, preferably, the total width of the P-type well region 105 and the body region 104 is greater than the width of the current balancing layer.

[0050] In this embodiment, preferably, the current balancing layer 103 and the body region 104 are both N-type.

[0051] In this embodiment, preferably, the doping concentration of the current equalizing layer 103 is greater than the doping concentration of the drift layer 102 .

[0052] In this embodiment, preferably, the doping concentration of the body region 104 is greater than the doping concentration of the current equalizing layer 103 , and the doping concentration of the body region 104 is greater than the doping concentration of the P-type well region 105 .

[0053] In this embodiment, preferably, the thickness of the insulating dielectric layer 106 is equal to the thickness of the P-type well region 105 .

[0054] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0055] Silicon carbide substrate 101,

[0056] A drift layer 102, wherein the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101, a protrusion 1021 is provided on the drift layer 102, and a groove 10211 is provided on the protrusion 1021;

[0057] A current balancing layer 103, wherein the lower side of the current balancing layer 103 is connected to the upper side of the drift layer 102, and the inner side of the current balancing layer 103 is connected to the outer side of the protrusion 1021;

[0058] A body region 104, wherein the lower side of the body region 104 is connected to the upper side of the current balancing layer 103;

[0059] A P-type well region 105, wherein the lower side of the P-type well region 105 is connected to the upper side of the current balancing layer 103; an N-type source region 1051 is disposed on the P-type well region 105; the outer side of the P-type well region 105 is connected to the inner side of the body region 104, and the inner side of the P-type well region 105 is connected to the protrusion 1021;

[0060] An insulating dielectric layer 106, wherein the insulating dielectric layer 106 is disposed in the groove 10211;

[0061] A gate dielectric layer 107, wherein the lower side of the gate dielectric layer 107 is respectively connected to the upper side of the P-type well region 105, the upper side of the protrusion 10211 and the upper side of the insulating dielectric layer 106;

[0062] A source metal layer 108, wherein the lower side of the source metal layer 108 is respectively connected to the upper side of the body region 104, the upper side of the P-type well region 105, and the upper side of the N-type source region 1051;

[0063] A gate metal layer 109, wherein the lower side of the gate metal layer 109 is connected to the upper side of the gate dielectric layer 107;

[0064] and a drain metal layer 110 , wherein the drain metal layer 110 is connected to the lower side of the silicon carbide substrate 101 .

[0065] In another embodiment, the silicon carbide substrate, the drift layer, the current balancing layer and the body region are all N-type, and the doping concentration of the N-type silicon carbide substrate 101 is 2-8e18cm -3 , the doping concentration of the N-type drift layer 102 is 1-5e17cm -3 The doping concentration of the N-type current balancing layer 103 is 0.8-1.2e18cm -3 , the doping concentration of the N-type body region 104 is 5-8e17cm -3 , the doping concentration of the P-type well region 105 is 5-8e17 cm -3 The material of the insulating dielectric layer 106 can be silicon dioxide or hafnium dioxide, the material of the gate dielectric layer 107 can be silicon dioxide, and the doping concentration of the N-type source region 1051 is 2-8e18cm -3 ; Among them, the concentration of the N-type silicon carbide substrate 101 is to ensure the formation of a low-resistance ohmic contact with the drain metal layer 110, thereby reducing the overall on-resistance of the device; the doping concentration of the N-type drift layer 102 is a compromise between the reverse withstand voltage and on-resistance of the device; the N-type current-balancing layer 103 has two functions, the first is to redistribute the electrons from the N-type source region 1051 to avoid thermal reliability problems caused by current concentration, and the second is to reduce the on-resistance of the device; the N-type body region 104 is to form a Schottky contact with the source metal layer 108, reduce the body diode conduction voltage drop of the device, and improve the reverse recovery speed of the device; the P-type well region 105 is to form the longitudinal withstand voltage structure of the device and the gate control structure of the device; the N-type source region 1051 is to form a low-resistance ohmic contact with the source metal layer 108.

[0066] The thickness of the N-type silicon carbide substrate 101 of the device is 1 μm, the thickness of the N-type drift layer 102 is 10-30 μm, and it is adjusted within the above range according to different requirements for the withstand voltage characteristics of the device. The thickness of the N-type current balancing layer 103 is 300nm-1 μm, the thickness of the N-type source region 1051 is 200nm, and the thickness of the P-type well region 105 is 600nm. This is to increase the height of the space charge region between the P-type well region 105 and the N-type drift region 102 directly below the gate and improve the gate reliability. The thickness of the gate dielectric layer 107 is 50nm, the thickness of the insulating dielectric layer 106 is 600nm, the thickness of the source metal layer 108 is 200nm, and the thickness of the gate metal layer 109 is 150nm;

[0067] An insulating dielectric layer 107 is constructed directly below the planar gate, and a space charge region is formed in the protrusion 1021 between the P-type well region 105 and the insulating dielectric layer 107. However, as the distance from the P-type well region 105 increases, the depth of the space charge region decreases, and it becomes more difficult to withstand the drain voltage. The insulating dielectric layer 107 constructed has the ability to withstand high voltage, which can effectively improve the gate's ability to withstand the impact of the drain voltage and improve the device reliability. The distance between the outer side of the insulating dielectric layer 107 and the inner side of the P-type well region 105 is 500nm. This is because when the device is turned on by applying a positive voltage to the gate, the conductive channel formed is mainly distributed in an area of ​​about 400nm close to the P-type well region 105. Setting the spacing in this way can reduce the impact on the device's conduction performance.

[0068] An N-type current balancing layer 103 is constructed, which can effectively redistribute the current from the N-type source region 1051 of the device in this region, and guide the current to the left and right sides of the device, thereby avoiding current concentration and causing thermal failure of the device;

[0069] An N-type current balancing layer 103 is constructed directly below the P-type well region 105 and the N-type body region 104 of the device. The width of the current balancing layer 103 is 600nm smaller than the sum of the widths of the P-type well region 105 and the N-type body region 104. The lateral distance between the N-type current balancing layer 104 and the insulating dielectric layer 106 is 300nm smaller than that of the P-type well region 105. The P-type well region 105 and the N-type drift layer 102 form a space charge region to protect the device gate. The provision of the N-type current balancing layer 103 can improve the reliability of the device gate.

[0070] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a high-reliability planar gate silicon carbide VDMOS, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a current equalizing layer; Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and implanting ions into the drift layer to form a body region; Step 4: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a P-type well region; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the P-type well region to form an N-type source region; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the drift layer to form a groove, deposit an insulating medium, and form an insulating medium layer; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate dielectric layer; Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer; Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal to form a source metal layer, removing the barrier layer, and completing the preparation; The drift layer is provided with a protrusion, the protrusion is provided with a groove, and the insulating dielectric layer is arranged in the groove; the lower side of the current balancing layer is connected to the upper side of the drift layer, and the inner side of the current balancing layer is connected to the outer side of the protrusion; the lower side of the body region is connected to the upper side of the current balancing layer; the lower side of the P-type well region is connected to the upper side of the current balancing layer; The total width of the P-type well region and the body region is greater than the width of the current balancing layer; the current balancing layer and the body region are both N-type.

2. The method for preparing a high-reliability planar gate silicon carbide VDMOS according to claim 1, characterized in that: The distance between the outer side surface of the insulating dielectric layer and the inner side surface of the P-type well region is 500 nm.

3. The method for preparing a high-reliability planar gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the current balancing layer is greater than the doping concentration of the drift layer.

4. The method for preparing a high-reliability planar gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the body region is greater than the doping concentration of the current balancing layer, and the doping concentration of the body region is greater than the doping concentration of the P-type well region.

5. The method for preparing a high-reliability planar gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the insulating dielectric layer is equal to the thickness of the P-type well region.

6. A high reliability planar gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by any one of the preparation methods described in claim 1 to claim 5.

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