A pixel driving circuit for field sequential display

Abstract

This invention discloses a pixel driving circuit for field-sequence display, including a reset pre-store unit and a driving unit. The reset pre-store unit includes a first transistor, a third transistor, and a pre-store capacitor. The gate of the first transistor is coupled to a row gate signal line, the first source-drain of the first transistor is coupled to a data signal line, and the second source-drain of the first transistor is coupled to the driving unit and the first source-drain of the third transistor. The second source-drain of the third transistor is coupled to one end of the pre-store capacitor, and the other end of the pre-store capacitor is coupled to a common signal line. The gate of the third transistor is coupled to a reset signal line. The beneficial effect achieved by this invention is that it greatly reduces the voltage range requirement for data signal line changes, thereby reducing the power consumption of the driving chip and the control row gate signal line output unit.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a pixel driving circuit for field-sequence display. Background Technology

[0002] In traditional field-sequential or color-sequential display driving technologies, the backlight can only be turned on after all data signal voltages for the entire display have been written and the liquid crystal has reached a stable deflection state. Otherwise, image distortion will occur. Therefore, the data signal voltage writing and liquid crystal deflection time greatly compress the backlight turn-on time, leading to difficulties in improving display brightness, refresh rate and resolution, increased power consumption, and increased backlight material costs. Therefore, how to accelerate the liquid crystal driving time and increase the backlight turn-on time is a crucial issue.

[0003] The current approach involves setting a pre-storage capacitor, which allows the data signal voltage required for the next frame to be stored in the pre-storage capacitor during the backlight illumination time. When switching frames, the pixel electrode can read the data signal voltage corresponding to the pre-storage capacitor, thereby saving the pixel data signal voltage writing time and correspondingly increasing the backlight illumination time.

[0004] However, this pixel circuit design faces the problem of voltage drop associated with charge sharing. Assuming the pre-storage capacitor's capacitance is the sum of the holding capacitor and the pixel electrode's capacitance, and the pixel electrode is at a common signal voltage of 0V before being reset, then according to the principle of charge conservation, the pre-storage capacitor needs to be pre-charged to 10V to charge the pixel electrode to 5V. Therefore, this pixel circuit design requires increasing the voltage supply range of the data signal lines to meet the LCD's operating voltage range, placing higher demands on the driver chip's output voltage range and significantly increasing power consumption. When the driver chip cannot meet these requirements, a larger pre-storage capacitor is needed. Only when the pre-storage capacitor is much larger than the holding capacitor and the pixel electrode will the voltage drop during charge sharing be smaller, but this will reduce the aperture ratio and increase the difficulty of pre-charging the pre-storage capacitor, which is detrimental to achieving high refresh rates and high resolutions.

[0005] Therefore, the present invention proposes a pixel driving circuit for field-sequence display. Summary of the Invention

[0006] The purpose of this invention is to propose a pixel driving circuit for field sequence display, which achieves a simple circuit structure and reduces the required data signal voltage range.

[0007] The present invention aims to provide a pixel driving circuit for field-sequence display through the following technical solution, including a reset pre-storage unit and a driving unit;

[0008] The reset pre-storage unit includes a first transistor, a third transistor, and a pre-storage capacitor; the gate of the first transistor is coupled to a row gate signal line, the first source and drain of the first transistor are coupled to a data signal line, the second source and drain of the first transistor are coupled to a driving unit and the first source and drain of the third transistor; the second source and drain of the third transistor are coupled to one end of the pre-storage capacitor, and the other end of the pre-storage capacitor is coupled to a common signal line; the gate of the third transistor is coupled to a reset signal line.

[0009] Furthermore, the driving unit includes a second transistor and a pixel electrode;

[0010] The gate of the second transistor is coupled to the transfer signal line, the first source and drain of the second transistor are coupled to the second source and drain of the first transistor, and the second source and drain of the second transistor are coupled to one end of the pixel electrode; the other end of the pixel electrode is coupled to the common signal line.

[0011] Furthermore, the driving unit also includes a holding capacitor; one end of the holding capacitor is coupled to the second source-drain of the second transistor, and the other end of the holding capacitor is coupled to a common signal line.

[0012] Furthermore, the driving timing of the pixel driving circuit is configured as follows:

[0013] During the backlight-on phase of the Nth frame, the voltage levels of the horizontal gate signal line and the reset signal line all jump to a high level, the first transistor and the third transistor are turned on, so that the data signal line writes the data signal voltage into the pre-storage capacitor through the first transistor and the third transistor. After the writing is completed, the horizontal gate signal, the reset signal line and the data signal line all jump to a low level, and the first transistor and the third transistor are turned off.

[0014] During the backlight-off phase of the Nth frame, the voltage levels of the horizontal gate signal line and the transfer signal line both jump to a high level, and the first transistor and the second transistor are turned on, so that the data signal line inputs the reset signal voltage through the first transistor and the second transistor to complete the reset of the pixel electrode. After the reset is completed, the horizontal gate signal line and the transfer signal line both jump to a low level, and the first transistor and the second transistor are turned off.

[0015] After the reset is completed, the voltage levels of the reset signal line and the transfer signal line both jump to high level, the second transistor and the third transistor are turned on, and the data signal voltage of the pre-stored capacitor is transferred to the pixel capacitor through the second transistor and the third transistor. After the transfer is completed, the voltage levels of the reset signal line and the transfer signal line both jump to low level, and the second transistor and the third transistor are turned off.

[0016] Furthermore, when the Nth frame is a positive polarity frame, the range of the reset signal voltage input from the data signal line to the pixel electrode is (Vcom, Vop_max + Vcom), where Vcom represents the common signal voltage and Vop_max represents the voltage corresponding to the maximum gray level.

[0017] Furthermore, when the Nth frame is a negative polarity frame, the range of the reset signal voltage input from the data signal line to the pixel electrode is (Vcom-Vop_max, Vcom).

[0018] The present invention has the following advantages:

[0019] This invention reuses the reset function of the data signal line when resetting the pixel electrode, enabling the pixel electrode to be reset to different potentials in positive and negative frames. In a positive frame, the input reset signal voltage range of the data signal line is (Vcom, Vop_max + Vcom), and the data signal voltage range required to be input to the pre-storage capacitor is (Vcom - Vop_max, Vcom + Vop_max). In a negative frame, the input reset signal voltage range of the data signal line is (Vcom - Vop_max, Vcom), and the data signal voltage range required to be output by the data signal line is (Vcom - Vop_max, Vcom + Vop_max). Therefore, when using this invention, the voltage variation range of the data signal line is (-Vop_max, +Vop_max), i.e., 2*Vop_max. This greatly reduces the voltage range requirement of the data signal line, thereby reducing the power consumption of the driver chip and the control row gate signal line unit.

[0020] This invention couples one end of a third transistor to a first transistor and the other end to a pre-storage capacitor. This allows the third transistor to be turned off when the pixel electrode is reset by inputting a reset signal voltage, without affecting the pre-stored data signal voltage in the pre-storage capacitor. At the same time, the potential of the pre-storage node and the pixel electrode can be changed to the corresponding reset signal voltage input to the data signal line, thereby reducing the transfer difficulty in the transfer stage and reducing the voltage range requirement initially pre-stored in the pre-storage capacitor.

[0021] Because this invention reduces the requirement for the varying voltage range of the data signal line, the maximum value of the input data signal voltage decreases, eliminating the need for a large pre-storage capacitor. Therefore, the limitation on the size of the pre-storage capacitor is removed. The size of the pre-storage capacitor is positively correlated with the area required to fabricate the capacitor, thus reducing the area requirement for fabricating the pre-storage capacitor and improving the aperture ratio. Attached Figure Description

[0022] Figure 1 This is a circuit diagram of the present invention;

[0023] Figure 2 This is a timing diagram of the present invention;

[0024] Figure 3 This is a comparison chart of voltage changes in this invention. Detailed Implementation

[0025] The present invention will be further described below with reference to the accompanying drawings, but the scope of protection of the present invention is not limited to the following description.

[0026] It should be noted that the orientation or positional relationship indicated by terms such as "left" and "right" is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the invention is usually placed during use, or the orientation or positional relationship in which those skilled in the art would conventionally understand it. Such terms are only for the convenience of describing the invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention.

[0027] It should be noted that, unless otherwise specified, the embodiments and features and technical solutions in the present invention can be combined with each other.

[0028] See Figure 1 This invention provides a pixel driving circuit for field-sequence display, including a reset pre-store unit and a driving unit; the reset pre-store unit includes a first transistor T1, a third transistor T3, and a pre-store capacitor Cs1; the gate of the first transistor T1 is coupled to the row gate signal line Scan, the first source and drain of the first transistor T1 are coupled to the data signal line Data, and the second source and drain of the first transistor T1 are coupled to the first source and drain of the second transistor T2 and the first source and drain of the third transistor T3; the second source and drain of the third transistor T3 are coupled to one end of the pre-store capacitor Cs1, and the other end of the pre-store capacitor Cs1 is coupled to the common signal line Com; the gate of the third transistor T3 is coupled to the reset signal line Reset.

[0029] Furthermore, the driving unit includes a second transistor T2, a pixel electrode Clc, and a holding capacitor Cs2; the gate of the second transistor T2 is coupled to the transfer signal line Tran, the first source and drain of the second transistor T2 are coupled to the second source and drain of the first transistor T1, and the second source and drain of the second transistor T2 are coupled to one end of the pixel electrode Clc; the other end of the pixel electrode Clc is coupled to the common signal line Com; one end of the holding capacitor Cs2 is coupled to the second source and drain of the second transistor T2, and the other end of the holding capacitor Cs2 is coupled to the common signal line Com.

[0030] When at work, refer to Figure 2 The driving timing of the pixel driving circuit is configured as follows:

[0031] During the backlight-on phase of the Nth frame, the horizontal gate signal line Scan and the reset signal line Reset both switch to a high level, turning on the first transistor T1 and the third transistor T3. This allows the data signal line Data to write the data signal voltage into the pre-storage capacitor Cs1 through the first transistor T1 and the third transistor T3. After the writing is completed, the horizontal gate signal Scan, the reset signal line Reset, and the data signal line Data all switch to a low level, and the first transistor T1 and the third transistor T3 turn off.

[0032] During the backlight-off phase of the Nth frame, the voltage levels of the row gate signal line Scan and the transfer signal line Tran both jump to high level, and the first transistor T1 and the second transistor T2 are turned on, so that the data signal line Data completes the reset of the holding capacitor Cs2 and the pixel electrode Clc through the first transistor T1 and the second transistor T2. After the reset is completed, the row gate signal line Scan and the transfer signal line Tran both jump to low level, and the first transistor T1 and the second transistor T2 are turned off.

[0033] When the Nth frame is a positive polarity frame, the range of the reset signal voltage input from the data signal line Data to the pixel electrode Clc is (Vcom, Vop_max + Vcom), where Vcom represents the common signal voltage and Vop_max represents the voltage corresponding to the maximum gray level; when the Nth frame is a negative polarity frame, the range of the reset signal voltage input from the data signal line Data to the pixel electrode Clc is (Vcom - Vop_max, Vcom).

[0034] After the reset is completed, the voltage levels of the reset signal line Reset and the transfer signal line Tran both jump to high level, the second transistor T2 and the third transistor T3 are turned on, and the data signal voltage of the pre-storage capacitor Cs1 is transferred to the pixel capacitor Clc through the second transistor T2 and the third transistor T3.

[0035] See Figure 3A comparison is made between the voltage range variations of existing technologies and the present invention. First, it is assumed that in both the existing and present inventions, the capacitance value of the pre-storage capacitor Cs1 is equal to the sum of the holding capacitor Cs2 and the pixel electrode Clc (i.e., Cs1 = Cs2 + Clc). Furthermore, under all grayscale levels of the data signal voltage, the voltage difference between the operating voltage of the pixel electrode Clc and the common signal voltage Vcom ranges from (0, Vop_max) to (Vop_max). Taking the pixel driving circuit of odd-numbered columns as an example, suppose that in the display stage of the Nth frame (N is a natural number), the pixel voltage of the odd-numbered column is negative (Vpixel-Vcom≤0). Then, due to the requirement of the polarity column reversal of the liquid crystal, the pixel voltage corresponding to the N+1th frame should be positive (Vpixel-Vcom≥0). Now, the working principle of the pre-storage method is adopted. Therefore, in the display time of the Nth frame, the data signal voltage of the N+1th frame will be written to the pre-storage capacitor Cs1. Therefore, a positive polarity data signal voltage needs to be written, that is, a voltage ≥Vcom. Therefore, the Nth frame corresponding to the data signal voltage that needs to be written with a positive polarity is called a positive polarity frame, and the frame with a negative polarity is called a negative polarity frame.

[0036] In the existing technology, during the backlight-off phase of the Nth frame (which is a positive frame), the reset signal line Reset jumps to a high level, turning on the third transistor T3 and resetting the voltage of the pixel electrode Clc to the common signal voltage Vcom. After the reset is complete, the transfer signal line Tran jumps to a high level, and the second transistor T2 transfers the data signal voltage on the pre-stored capacitor Cs1 to the pixel electrode Clc. Let the required operating voltage Vpixel of the pixel electrode Clc be Vop_max + Vcom (this is the maximum operating voltage required by the pixel electrode Clc when the Nth frame is a positive frame), and the data signal voltage pre-written into the pre-stored capacitor Cs1 be Vcs1. According to the principle of charge conservation:

[0037] (Vcs1-(Vop_max+Vcom))*Cs1=((Vop_max+Vcom)-Vcom)*(Cs2+Clc);

[0038] That is, Vcs1-Vop_max-Vcom=Vop_max, Vcs1= 2*Vop_max+Vcom.

[0039] Similarly, when the Nth frame is a negative polarity frame, and a negative polarity data signal voltage needs to be written to the pre-storage capacitor Cs1, let the required operating voltage Vpixle of the pixel electrode Clc be -Vop_max. According to the principle of charge conservation,

[0040] Vs1-(-Vop_max+Vcom)*Cs1=((-Vop_max+Vcom)-Vcom)*(Cs2+Clc);

[0041] That is, Vs1 + Vop_max - Vcom = -Vop_max, Vs1 = -2*Vop_max + Vcom; therefore, the required data signal input voltage range of the data signal line Data is (-2*Vop_max + Vcom, 2*Vop_max + Vcom), that is, the data signal voltage variation range is 4*Vop_max.

[0042] Using this invention: During the backlight-off phase of the Nth frame, the voltage levels of the row gate signal line Scan and the transfer signal line Tran both jump to a high level, turning on the first transistor T1 and the second transistor T2, so that the data signal line Data completes the reset of the holding capacitor Cs2 and the pixel electrode Clc through the first transistor T1 and the second transistor T2; after the reset is completed, the voltage levels of the reset signal line Reset and the transfer signal line Tran both jump to a high level, and the third transistor T3 and the second transistor T2 are turned on, transferring the data signal voltage on the pre-storage capacitor Cs1 to the pixel electrode Clc;

[0043] Similarly, when the Nth frame is a positive polarity frame, let the operating voltage Vpixel required by the pixel electrode Clc be Vop_max + Vcom. At this time, when the pixel electrode Clc is reset, its voltage is reset by the data signal line Data to the reset signal voltage Vop_max + Vcom. According to the principle of charge conservation:

[0044] (Vcs1-(Vop_max+Vcom))*Cs1=((Vop_max+Vcom)- (Vop_max +Vcom))*(Cs2+Clc),

[0045] That is, Vcs1-Vop_max-Vcom=0, Vcs1= Vop_max+Vcom;

[0046] When the Nth frame is a positive polarity frame, the minimum operating voltage Vpixel required by the pixel electrode Clc is Vcom. According to the principle of charge conservation:

[0047] (Vcs1-Vcom)*Cs1=(Vcom-(Vop_max +Vcom))*(Cs2+Clc), Vcs1-Vcom=Vcom-(Vop_max +Vcom), Vcs1=Vcom-Vop_max, that is, when the Nth frame is a positive polarity frame, the required data signal voltage range is (Vop_max+Vcom)-(Vcom-Vop_max)=2*Vop_max;

[0048] Similarly, when writing a negative polarity data signal voltage to the pre-storage capacitor Cs1 in the next frame, the working voltage required by the pixel electrode Clc in the negative polarity frame is calculated using the same formula in two cases: the minimum is -Vop_max and the maximum is Vcom. It can be deduced that the data signal voltage range is still (Vcom-Vop_max, Vop_max+Vcom). Therefore, for the pixel circuit used in this invention, the overall range of the data signal line Data is 2*Vop_max.

[0049] The overall range of the data signal line Data in the prior art is 4*Vop_max, while the overall range of the data signal line Data in this invention is 2*Vop_max. By resetting the pixel electrode Clc to different potentials, the data signal voltage range can be fully overlapped in both positive and negative polarities, thereby significantly reducing the data signal voltage range and further reducing the power consumption of the driver chip and the control row gate signal line output unit.

[0050] The charge sharing formula also shows that in existing driving circuits, the smaller the absolute value of the difference between the pre-storage capacitor Cs1 and the sum of the holding capacitor Cs2 and the pixel electrode Clc, the worse the charge sharing effect, and the larger the data signal voltage range is required. Otherwise, a larger pre-storage capacitor Cs1 and a smaller holding charge Cs2 and pixel electrode Clc are required.

[0051] The size of the capacitor is positively correlated with the area of ​​the overlapping region of the capacitors during the fabrication process. When the pre-storage capacitor Cs1 increases, the required area will increase accordingly, which will affect the aperture ratio. However, when the pixel electrode Clc and the holding capacitor Cs2 decrease, the pixel voltage Vpixel has a large leakage current in one frame, which is prone to flickering. Therefore, this type of circuit has a large limitation on the size of the pre-storage capacitor Cs1, the pixel electrode Clc and the holding capacitor Cs2.

[0052] When this invention is used, the overall range of the data signal line Data is greatly reduced, so there is no need for such a large capacity pre-storage capacitor Cs1. The limitation on the capacitance value of the pre-storage capacitor is removed, so it does not need to occupy too much fabrication area. Therefore, it is more conducive to improving the aperture ratio and realizing high refresh rate and high resolution.

[0053] The above embodiments only illustrate preferred implementation methods, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from this invention, and these all fall within the protection scope of this invention.

Claims

1. A pixel driving circuit for field-sequence display, characterized in that: Includes a reset pre-store unit and a drive unit; The reset pre-storage unit includes a first transistor (T1), a third transistor (T3), and a pre-storage capacitor (Cs1); the gate of the first transistor (T1) is coupled to the row gate signal line (Scan), the first source and drain of the first transistor (T1) are coupled to the data signal line (Data), and the second source and drain of the first transistor (T1) are coupled to the driving unit and the first source and drain of the third transistor (T3); the second source and drain of the third transistor (T3) are coupled to one end of the pre-storage capacitor (Cs1), and the other end of the pre-storage capacitor (Cs1) is coupled to the common signal line (Com); the gate of the third transistor (T3) is coupled to the reset signal line (Reset).

2. The pixel driving circuit for field-sequence display according to claim 1 is characterized in that, The driving unit includes a second transistor (T2) and a pixel electrode (Clc). The gate of the second transistor (T2) is coupled to the transfer signal line (Tran), the first source and drain of the second transistor (T2) are coupled to the second source and drain of the first transistor (T1), and the second source and drain of the second transistor (T2) are coupled to one end of the pixel electrode (Clc); the other end of the pixel electrode (Clc) is coupled to the common signal line (Com).

3. The pixel driving circuit for field-sequence display according to claim 2 is characterized in that, The driving timing of the pixel driving circuit is configured as follows: During the backlight-on phase of the Nth frame, the voltage levels of the horizontal gate signal line (Scan) and the reset signal line (Reset) all jump to a high level, turning on the first transistor (T1) and the third transistor (T3). This allows the data signal line (Data) to write the data signal voltage into the pre-storage capacitor (Cs1) through the first transistor (T1) and the third transistor (T3). After the writing is completed, the horizontal gate signal (Scan), the reset signal line (Reset), and the data signal line (Data) all jump to a low level, and the first transistor (T1) and the third transistor (T3) turn off. During the backlight-off phase of the Nth frame, the voltage levels of the row gate signal line (Scan) and the transfer signal line (Tran) both jump to a high level, and the first transistor (T1) and the second transistor (T2) are turned on, so that the data signal line (Data) inputs a reset signal voltage through the first transistor (T1) and the second transistor (T2) to complete the reset of the pixel electrode (Clc). After the reset is completed, the row gate signal line (Scan) and the transfer signal line (Tran) both jump to a low level, and the first transistor (T1) and the second transistor (T2) are turned off. After the reset is completed, the voltage levels of the reset signal line (Reset) and the transfer signal line (Tran) both jump to high level, the third transistor (T3) and the second transistor (T2) are turned on, and the data signal voltage of the pre-storage capacitor (Cs1) is transferred to the pixel capacitor (Clc) through the second transistor (T2) and the third transistor (T3). After the transfer is completed, the voltage levels of the reset signal line (Reset) and the transfer signal line (Tran) both jump to low level, and the second transistor (T2) and the third transistor (T3) are turned off.

4. The pixel driving circuit for field-sequence display according to claim 3 is characterized in that, When the Nth frame is a positive polarity frame, the range of the reset signal voltage input from the data signal line (Data) to the pixel electrode (Clc) is (Vcom, Vop_max + Vcom), where Vcom represents the common signal voltage and Vop_max represents the voltage corresponding to the maximum gray level.

5. The pixel driving circuit for field-sequence display according to claim 3 is characterized in that, When the Nth frame is a negative polarity frame, the range of the reset signal voltage input from the data signal line (Data) to the pixel electrode (Clc) is (Vcom-Vop_max, Vcom), where Vcom represents the common signal voltage and Vop_max represents the voltage corresponding to the maximum gray level.

6. The pixel driving circuit for field-sequence display according to claim 2 is characterized in that, The driving unit also includes a holding capacitor (Cs2). One end of the holding capacitor (Cs2) is coupled to the second source-drain of the second transistor (T2), and the other end of the holding capacitor (Cs2) is coupled to the common signal line (Com).

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