A gate-controlled field sequential circuit and method

Abstract

This invention discloses a gate-controlled field sequence circuit and method, including an M-row sub-circuit. The sub-circuit includes a compensation unit comprising a first transistor, a second transistor, a fourth transistor, and a fifth transistor. The second source-drain of the first transistor is coupled to the gate of the fourth transistor. The first source-drain of the fourth transistor is coupled to the second source-drains of the third and fifth transistors. The second source-drain of the fourth transistor is coupled to the second source-drain of the second transistor. The gate of the fifth transistor is coupled to the row gate signal line of the Nth row. The first source-drain of the fifth transistor is coupled to a data signal line. The second source-drain of the fifth transistor is coupled to the first source-drain of the fourth transistor. The beneficial effect of this invention is that by utilizing the conduction characteristics of transistors to eliminate threshold voltage, it avoids image abnormalities caused by threshold voltage drift.

Description

Technical Field

[0001] This invention relates to the field of pixel display technology, and in particular to a gate-controlled field sequence circuit and method. Background Technology

[0002] Field sequential or color sequential display driving technology leverages the persistence of vision to directly mix RGB three-color light sources, achieving full-color display effects. It eliminates the need for color filters, improving light source utilization and reducing power consumption. The backlight can only be turned on after all image data has been written and the liquid crystal has reached a stable state; otherwise, image distortion will occur. Therefore, a significant time must be allowed for the liquid crystal to deflect before the backlight is activated. This makes it difficult to achieve high brightness and high frequency display over an average time, while also increasing the requirements for backlight brightness specifications and lifespan, thus raising costs.

[0003] Due to the influence of transistor manufacturing processes, the threshold voltage of driving transistors at different spatial locations can vary. For hydrogenated amorphous silicon, low-temperature polycrystalline silicon, and oxide transistors, the threshold voltage also changes with the operating state, i.e., threshold voltage drift. Since the potential of the pixel electrode ultimately written under gate control is related to the threshold voltage, variations or inconsistencies in the threshold voltage of the driving transistors can cause unevenness in the liquid crystal display.

[0004] Therefore, this invention proposes a gate-controlled field sequence circuit and method to eliminate the influence of threshold voltage, thereby avoiding the impact of abnormal screen display. Summary of the Invention

[0005] The purpose of this invention is to propose a gate-controlled field sequence circuit and method that eliminates the influence of threshold voltage.

[0006] The present invention aims to achieve a gate-controlled field sequence circuit through the following technical solution, comprising M rows of sub-circuits, wherein the sub-circuit includes a compensation unit and a driving unit; The compensation unit includes a first transistor, a second transistor, a fourth transistor, a fifth transistor, and a pre-storage capacitor; The gate of the first transistor of the sub-circuit in the Nth row is coupled to the row gate signal line of the (N-1)th row, the first source and drain of the first transistor are coupled to the positive power supply line, the second source and drain of the first transistor are coupled to one end of the pre-storage capacitor, and the other end of the pre-storage capacitor is coupled to the common signal line. The second source-drain of the first transistor is also coupled to the gate of the fourth transistor, the first source-drain of the fourth transistor is coupled to the second source-drain of the third transistor and the fifth transistor, and the second source-drain of the fourth transistor is coupled to the second source-drain of the second transistor. The first source-drain of the second transistor in the sub-circuit of the Nth row is coupled to one end of the pre-storage capacitor, and the gate of the second transistor is coupled to the row gate signal line of the Nth row. The gate of the third transistor is coupled to the transfer signal line, and the first source and drain of the third transistor are coupled to the positive power supply line; The gate of the fifth transistor in the Nth row sub-circuit is coupled to the row gate signal line of the Nth row, the first source and drain of the fifth transistor are coupled to the data signal line, and the second source and drain of the fifth transistor are coupled to the first source and drain of the fourth transistor. The second source and drain of the fourth transistor are also coupled to the driving unit; M and N are positive integers, 1 <N≤M。

[0007] Furthermore, the driving unit includes a sixth transistor and a pixel electrode; the gate of the sixth transistor is coupled to a transfer signal line, the first source and drain of the sixth transistor are coupled to the second source and drain of the second transistor, the second source and drain of the sixth transistor are coupled to the pixel electrode, and the other end of the pixel electrode is coupled to a common signal line.

[0008] Furthermore, the driving unit also includes a storage capacitor, one end of which is coupled to the second source-drain of the sixth transistor, and the other end of which is coupled to a common signal line.

[0009] Furthermore, the sub-circuit also includes a reset unit, which includes a seventh transistor. The first source-drain of the seventh transistor is coupled to the driving unit, the second source-drain of the seventh transistor is coupled to the ground line, and the other end of the storage capacitor is coupled to the common signal line.

[0010] Furthermore, the sub-circuit also includes a selection unit, wherein the first source-drain of the first transistor, the first source-drain of the third transistor, and the first source-drain of the fifth transistor are all coupled to the selection unit; the gate of the first transistor is coupled to the reset signal line.

[0011] Furthermore, the selection unit includes an eighth transistor, a ninth transistor, and a power signal line; The gate of the eighth transistor is coupled to the data control signal line, the first source and drain of the eighth transistor are coupled to the data signal line, and the second source and drain of the eighth transistor are coupled to the second source and drain of the ninth transistor; the gate of the ninth transistor is coupled to the power control signal line, and the first source and drain of the ninth transistor are coupled to the power signal line.

[0012] The present invention also provides a gate-controlled field sequence circuit control method, comprising: Backlight activation phase of the sub-circuit in row N: When the row gate signal line of row N goes high, the second and fifth transistors are turned on. The data signal line maintains the potential of the second node at the data signal voltage through the fifth transistor; the pre-storage capacitor maintains the first node at a high potential, and at the same time maintains the third node at a high potential. At this time, the fourth transistor is turned on until it reaches saturation. When the fourth transistor is saturated, the first node and the second node discharge to the sum of the data signal voltage and the threshold voltage of the fourth transistor. When the row gate signal line of the Nth row goes low, the second and fifth transistors are turned off. Backlight off phase of the sub-circuit in row N: When the reset signal line goes high, the seventh transistor turns on, allowing the pixel electrode to be reset through the seventh transistor. After the reset is complete, the reset signal line goes low, and the seventh transistor is turned off; When the transfer signal line goes high, the third and sixth transistors are turned on. The positive power line, through the third transistor, makes the potential of the second node high; At this time, the pre-storage capacitor maintains the potential of the first node as the sum of the data signal line and the threshold voltage; causing the fourth transistor to saturate discharge, so that the potential of the third node is the data signal voltage when it is cut off, and the data signal voltage is written to the pixel electrode through the sixth transistor.

[0013] The present invention also provides a gate-controlled field sequence circuit control method, comprising: Backlight activation phase of the sub-circuit in row N: When the row gate signal line of the Nth row goes high, the second and fifth transistors are turned on; when the data signal control line goes high, the eighth transistor is turned on, and the data signal line, through the fifth and eighth transistors, keeps the potential of the second node at the data signal voltage; the second transistor connects the first and third nodes. The pre-storage capacitor maintains the first and third nodes at a high potential; At this time, the fourth transistor is turned on until it reaches saturation. When the fourth transistor is saturated, the first node and the second node discharge to the sum of the data signal voltage and the threshold voltage of the fourth transistor. When the row gate signal line of row N goes low, the second and fifth transistors are turned off; when the data control signal line goes low, the eighth transistor is turned off. Backlight off phase of the sub-circuit in row N: When the power control signal line jumps to a high level, the ninth transistor turns on, allowing the power signal line to input a preset square wave to the field sequence circuit through the ninth transistor. When the transfer signal line goes high, the third and sixth transistors are turned on. The power signal line, through the ninth transistor, the third transistor, and the sixth transistor, enables the pixel electrode to be reset by a preset square wave. After the reset is complete, the power signal line makes the potential of the second node high through the ninth transistor and the third transistor; At this time, the pre-storage capacitor maintains the potential of the first node as the sum of the data signal line and the threshold voltage; causing the fourth transistor to saturate discharge, so that the potential of the third node is the data signal voltage when it is cut off, and the data signal voltage is written to the pixel electrode through the sixth transistor.

[0014] Furthermore, a preset high phase is included before the backlight-on phase of the sub-circuit in the Nth row; The preset high-level phase includes: When the row gate signal line of the (N-1)th row jumps to a high level, the first transistor turns on, and the positive power line charges the pre-storage capacitor through the first transistor, making the potential of the first node high. When the row gate signal line of row N-1 goes low, the first transistor is turned off.

[0015] The present invention has the following advantages: This invention employs a compensation unit to pre-store a high potential in a pre-storage capacitor, ensuring the gate of the fourth transistor is at a high potential. By turning on the second transistor, the gate and source-drain connections of the fourth transistor are made connected, i.e., the first and third nodes are connected. Utilizing the transistor's conduction characteristics, the potential difference between the first and second nodes equals the threshold voltage of the fourth transistor, making the potential of the first node the sum of the data signal voltage and the threshold voltage. During writing, the data signal voltage and the threshold voltage are stored in the pre-storage capacitor. Again, the transistor's conduction characteristics ensure the potential of the third node is the data signal voltage. Because the threshold voltage is pre-compensated in the pre-storage capacitor, the influence of the threshold voltage is eliminated after conduction, reducing the impact of data signal writing to the pixel electrodes. This avoids display abnormalities caused by in-plane process inconsistencies and transistor threshold voltage drift over time. Attached Figure Description

[0016] Figure 1 This is a circuit diagram of Embodiment 1 of the present invention; Figure 2 This is a timing diagram of Embodiment 1 of the present invention; Figure 3 This is a circuit diagram of Embodiment 2 of the present invention; Figure 4 This is a circuit diagram of the selection unit in Embodiment 2 of the present invention; Figure 5 This is a timing diagram of Embodiment 2 of the present invention. Detailed Implementation

[0017] The present invention will be further described below with reference to the accompanying drawings, but the scope of protection of the present invention is not limited to the following description.

[0018] It should be noted that the orientation or positional relationship indicated by terms such as "left" and "right" is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the invention is usually placed during use, or the orientation or positional relationship in which those skilled in the art would conventionally understand it. Such terms are only for the convenience of describing the invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention.

[0019] It should be noted that, unless otherwise specified, the embodiments and features and technical solutions in the present invention can be combined with each other. Example

[0020] See Figure 1 The present invention provides a gate-controlled field sequence circuit, including M rows of sub-circuits, the sub-circuits including a compensation unit and a driving unit; The compensation unit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, and a pre-storage capacitor Cst1; The gate of the first transistor T1 in the Nth row sub-circuit is coupled to the row gate signal line ScanN-1 in the (N-1)th row. The first source and drain of the first transistor T1 are coupled to the positive power supply line Vdd. The second source and drain of the first transistor T1 are coupled to one end of the pre-storage capacitor Cst1. The other end of the pre-storage capacitor Cst1 is coupled to the common signal line Com. The second source and drain of the first transistor T1 are also coupled to the gate of the fourth transistor T4. The first source and drain of the fourth transistor T4 are coupled to the second source and drain of the third transistor T3 and the fifth transistor T5. The second source and drain of the fourth transistor T4 are coupled to the second source and drain of the second transistor T2. The first source-drain of the second transistor T2 in the Nth row sub-circuit is coupled to one end of the pre-storage capacitor Cst1, and the gate of the second transistor T2 is coupled to the row gate signal line ScanN of the Nth row; the gate of the third transistor T3 is coupled to the transfer signal line Tran, and the first source-drain of the third transistor T3 is coupled to the positive power supply line Vdd; the gate of the fifth transistor T5 is coupled to the row gate signal line ScanN of the Nth row, the first source-drain of the fifth transistor T5 is coupled to the data signal line Data, and the second source-drain of the fifth transistor T5 is coupled to the first source-drain of the fourth transistor T4; the second source-drain of the fourth transistor T4 is also coupled to the first source-drain of the sixth transistor T6.

[0021] Furthermore, the driving unit includes a sixth transistor T6, a pixel electrode Clc, and a storage capacitor Cst2; the gate of the sixth transistor T6 is coupled to the transfer signal line Tran, the first source and drain of the sixth transistor T6 are coupled to the second source and drain of the second transistor T2, the second source and drain of the sixth transistor T6 are coupled to the pixel electrode Clc, and the other end of the pixel electrode Clc is coupled to the common signal line Com; one end of the storage capacitor Cst2 is coupled to the second source and drain of the sixth transistor T6, and the other end of the storage capacitor Cst2 is coupled to the common signal line Com.

[0022] Furthermore, the sub-circuit also includes a reset unit, which includes a seventh transistor T7. The first source-drain of the seventh transistor T7 is coupled to the driving unit, the second source-drain of the seventh transistor T7 is coupled to the ground line Vss, and the other end of the storage capacitor Cst2 is coupled to the common signal line Com.

[0023] like Figure 2 As shown, a preset high stage is included before the backlight-on stage of the sub-circuit in the Nth row; The preset high stage includes: the row gate signal line ScanN-1 of the N-1th row jumps to a high level, the first transistor T1 is turned on, and the positive power supply line Vdd charges the pre-storage capacitor Cst1 through the first transistor T1, making the potential of the first node A high. At this time, the potential of the first node A VA = Vdd. When the row gate signal line ScanN-1 of row N-1 goes low, the first transistor T1 is turned off. The preset high stage is used to charge the pre-storage capacitor Cst1 to maintain the high potential of the first node A, so that the fourth transistor T4 can enter the preset on / off state in the subsequent stage.

[0024] Backlight activation phase of the sub-circuit in row N: The row gate signal line ScanN of the Nth row jumps to a high level, and the second transistor T2 and the fifth transistor T5 are turned on; the data signal line Data keeps the potential of the second node B at the data signal voltage through the fifth transistor T5, that is, VB=Vdata; the pre-storage capacitor Cst1 maintains the first node A at a high potential, and at the same time maintains the third node C at a high potential through the second transistor T2, that is, VA=VC=Vdd; The fourth transistor T4 is turned on until it reaches saturation. Since the second node B is maintained at the data signal voltage Vdata, when the fourth transistor T4 is saturated, the first node A and the third node C discharge to the sum of the data signal voltage Vdata and the threshold voltage Vth of the fourth transistor T4, that is, VA=VC=Vdata+Vth; the row gate signal line ScanN of the Nth row jumps to a low level, and the second transistor T2 and the fifth transistor T5 are turned off. During the backlight-on phase, the fourth transistor T4 works with the pre-storage capacitor Cst1, the second transistor T2, and the fifth transistor T5 to extract the threshold voltage Vth and store it in the first node A, thus pre-compensating the threshold voltage Vth.

[0025] Backlight off phase of the sub-circuit in row N: When the reset signal line Reset jumps to a high level, the seventh transistor T7 is turned on, so that the pixel electrode Clc is reset through the seventh transistor T7; After the reset is complete, the reset signal line Reset jumps to a low level, and the seventh transistor T7 is turned off; When the transfer signal line Tran jumps to a high level, the third transistor T3 and the sixth transistor T6 are turned on. The positive power supply line Vdd makes the potential of the second node B high through the third transistor T3, at which time VB=Vdd; At this time, the pre-storage capacitor Cst1 maintains the potential of the first node A as VA = Vdata + Vth, so that the fourth transistor T4 is in saturation. In the saturation state, the potential of the third node C is the data signal voltage Vdata when it is cut off, that is, VC = Vdata. When the sixth transistor T6 is turned on, the third node C writes the data signal voltage Vdata to the pixel electrode Clc through the sixth transistor T6.

[0026] During this stage, the accurate data signal voltage Vdata is written into the pixel electrode Clc through the third transistor T3, the fourth transistor T4, and the sixth transistor T6, so that the pixel voltage Vpixel = Vdata. By utilizing the saturation state characteristics of the fourth transistor T4, it can be canceled out with the pre-compensated threshold voltage Vth, thereby avoiding the influence of threshold voltage changes.

[0027] This invention uses a compensation unit and the law of charge conservation to stabilize the potential of the first node A at Vdd. The sum of these values ​​is used to maintain the potential of the second node B at Vdata via the data signal line Data. By controlling the on / off voltage characteristics of the fourth transistor T4, when the fourth transistor T4 reaches saturation, the first node A and the third node C discharge, stabilizing the transistor in a saturated state. At this point, VA = VC = Vdata + Vth. The threshold voltage of the fourth transistor T4 is pre-written into the first node A for storage, which is used to offset the threshold voltage Vth when the voltage of the pixel electrode Clc is subsequently written. During writing, the saturation discharge characteristic of the transistor is utilized again. At this time, VB=Vdd, VA=Vdata+Vth, so when stable, VC=Vdata. This eliminates the influence of the threshold voltage Vth on the data signal writing to the pixel electrode, thereby avoiding the abnormal display caused by in-plane process unevenness and the drift of the threshold voltage Vth of the transistor over time.

[0028] Example 2 like Figure 3 As shown in the figure, this embodiment is a gate-controlled field sequence circuit. In this second embodiment, the sub-circuit includes a selection unit, a compensation unit, and a driving unit. The compensation unit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, and a pre-storage capacitor Cst1; The first source and drain of the first transistor T1 are coupled to the selection unit; the gate of the first transistor T1 is coupled to the row gate signal line ScanN-1 (or the reset signal line Reset) of the (N-1)th row; the second source and drain of the first transistor T1 are coupled to one end of the pre-storage capacitor Cst1, and the other end of the pre-storage capacitor Cst1 is coupled to the common signal line Com; the second source and drain of the first transistor T1 are also coupled to the gate of the fourth transistor T4; the first source and drain of the fourth transistor T4 are coupled to the second source and drain of the third transistor T3 and the fifth transistor T5; the second source and drain of the fourth transistor T4 are coupled to the second source and drain of the second transistor T2. Source and drain; the first source and drain of the second transistor T2 are coupled to one end of the pre-storage capacitor Cst1, and the gate of the second transistor T2 is coupled to the row gate signal line ScanN of the Nth row; the gate of the third transistor T3 is coupled to the transfer signal line Tran, and the first source and drain of the third transistor T3 are coupled to the selection unit; the gate of the fifth transistor T5 is coupled to the row gate signal line ScanN of the Nth row, and the first source and drain of the fifth transistor T5 are coupled to the selection unit; the second source and drain of the fifth transistor T5 are coupled to the first source and drain of the fourth transistor T4; the second source and drain of the fourth transistor T4 are also coupled to the first source and drain of the sixth transistor T6.

[0029] Further as Figure 4As shown, the selection unit includes an eighth transistor T8, a ninth transistor T9, and power signal lines Vdd-Vss; the gate of the eighth transistor T8 is coupled to the data control signal line Data-Ctrl, the first source and drain of the eighth transistor T8 are coupled to the data signal line Data, and the second source and drain of the eighth transistor T8 are coupled to the second source and drain of the ninth transistor T9; the gate of the ninth transistor T9 is coupled to the power control signal line V-Ctrl, and the first source and drain of the ninth transistor T9 are coupled to the power signal lines Vdd-Vss; the selection unit is located outside the display area of ​​the field sequence circuit.

[0030] Furthermore, the driving unit includes a sixth transistor T6, a pixel electrode Clc, and a storage capacitor Cst2; the gate of the sixth transistor T6 is coupled to the transfer signal line Tran, the first source and drain of the sixth transistor T6 are coupled to the second source and drain of the second transistor T2, the second source and drain of the sixth transistor T6 are coupled to the pixel electrode Clc, and the other end of the pixel electrode Clc is coupled to the common signal line Com; one end of the storage capacitor Cst2 is coupled to the second source and drain of the sixth transistor T6, and the other end of the storage capacitor Cst2 is coupled to the common signal line Com.

[0031] like Figure 5 As shown, a preset high stage is included before the backlight-on stage of the sub-circuit in the Nth row; The preset high stage includes: the row gate signal line ScanN-1 of the N-1th row jumps to a high level, the first transistor T1 is turned on, and the positive power supply line Vdd charges the pre-storage capacitor Cst1 through the first transistor T1, making the potential of the first node A high. At this time, the potential of the first node A VA = Vdd. When the row gate signal line ScanN-1 of row N-1 goes low, the first transistor T1 is turned off. The preset high stage is used to charge the pre-storage capacitor Cst1 to maintain the high potential of the first node A, so that the fourth transistor T4 can enter the preset on / off state in the subsequent stage.

[0032] Backlight activation phase of the sub-circuit in row N: When the row gate signal line ScanN of row N goes high, the second transistor T2 and the fifth transistor T5 are turned on; when the data signal control line Data-Ctrl goes high, the eighth transistor T8 is turned on, and the data signal line Data, through the eighth transistor T8 and the fifth transistor T5, makes the potential of the second node B continuously the data signal voltage, i.e., VB=Vdata; when the second transistor T2 is turned on, the first node A and the third node C are connected. The pre-storage capacitor Cst1 maintains the first node A and the third node C at a high potential, i.e., VA=VC=Vdd; At this time, the fourth transistor T4 is turned on until it reaches saturation. Since the second node B is maintained at the data signal voltage Vdata, when the fourth transistor T4 is saturated, the first node A and the third node C discharge to the sum of the data signal voltage Vdata and the threshold voltage Vth of the fourth transistor T4, that is, VA=VC=Vdata+Vth; the row gate signal line ScanN of the Nth row jumps to a low level, and the second transistor T2 and the fifth transistor T5 are turned off. During the backlight-on phase, the fourth transistor T4 works with the pre-storage capacitor Cst1, the second transistor T2, and the fifth transistor T5 to extract the threshold voltage Vth and store it in the first node A, thus pre-compensating the threshold voltage Vth.

[0033] Backlight off phase of the sub-circuit in row N: When the power control signal line V-Ctrl jumps to a high level, the ninth transistor T9 turns on, allowing the power signal lines Vdd-Vss to input a preset square wave to the field sequence circuit through the ninth transistor T9. The preset square wave is a square wave that goes low first and then high, with Vss for the low phase and Vdd for the high phase. When the transfer signal line Tran jumps to a high level, the third transistor T3 and the sixth transistor T6 are turned on. The preset square wave output by the power signal line Vdd-Vss is at a low level, while the preset square wave output is at a high level. Vdd, through the ninth transistor T9 and the third transistor T3, makes the potential of the second node B high, that is, VB=Vdd. At this time, the pre-storage capacitor Cst1 maintains the potential of the first node A as VA=Vdata+Vth, so that the fourth transistor T4 is in saturation state until it reaches saturation state. At this time, the potential of the third node C is the data signal voltage Vdata when it is cut off, that is, VC=Vdata. When the sixth transistor T6 is turned on, the third node C writes the data signal voltage Vdata to the pixel electrode Clc through the sixth transistor T6.

[0034] During this stage, the accurate data signal voltage Vdata is written into the pixel electrode Clc through the third transistor T3, the fourth transistor T4, and the sixth transistor T6, so that the pixel voltage Vpixel = Vdata. By utilizing the saturation state characteristics of the fourth transistor T4, it can be canceled out with the pre-compensated threshold voltage Vth, thereby avoiding the influence of threshold voltage changes.

[0035] This invention uses a compensation unit and the law of charge conservation to stabilize the potential of the first node A at Vdd. The sum of these values ​​is used to maintain the potential of the second node B at Vdata via the data signal line Data. By controlling the switching on and off voltage characteristics of the fourth transistor T4, when the fourth transistor T4 reaches saturation, the first node A and the third node C discharge, stabilizing the transistor in a saturated state. At this point, VA = VC = Vdata + Vth. The threshold voltage of the fourth transistor T4 is pre-written into the first node A for storage, which is used to offset the threshold voltage Vth when the voltage of the pixel electrode Clc is written later. This avoids the abnormal display caused by in-plane process inhomogeneities and the drift of the threshold voltage Vth of the transistor over time.

[0036] This embodiment does not require a reset unit. The operation of the field sequence circuit can be completed by selecting the unit to input the corresponding signal into the plane at different time periods. This saves one transistor and improves the aperture ratio in the plane.

[0037] Example 3 This embodiment is a gate-controlled field sequence circuit control method.

[0038] In Embodiment 3, a preset high phase is included before the backlight-on phase of the sub-circuit in the Nth row. The preset high stage includes: the row gate signal line ScanN-1 of the N-1th row jumps to a high level, the first transistor T1 is turned on, and the positive power supply line Vdd charges the pre-storage capacitor Cst1 through the first transistor T1, making the potential of the first node A high. At this time, the potential of the first node A VA = Vdd. When the row gate signal line ScanN-1 of row N-1 goes low, the first transistor T1 is turned off. The preset high stage is used to charge the pre-storage capacitor Cst1 to maintain the high potential of the first node A, so that the fourth transistor T4 can enter the preset on / off state in the subsequent stage.

[0039] Backlight activation phase of the sub-circuit in row N: When the row gate signal line ScanN of the Nth row jumps to a high level, the second transistor T2 and the fifth transistor T5 are turned on; the data signal line Data, through the fifth transistor T5, makes the potential of the second node B continuously the data signal voltage, i.e., VB=Vdata; the second transistor T2 turns on, making the first node A and the third node C connected; The pre-storage capacitor Cst1 maintains the first node A and the third node C at a high potential, i.e., VA=VC=Vdd; At this time, the fourth transistor T4 is turned on until it reaches saturation. Since the second node B is maintained at the data signal voltage Vdata, when the fourth transistor T4 is saturated, the first node A and the third node C discharge to the sum of the data signal voltage Vdata and the threshold voltage Vth of the fourth transistor T4, that is, VA=VC=Vdata+Vth; the row gate signal line ScanN of the Nth row jumps to a low level, and the second transistor T2 and the fifth transistor T5 are turned off. During the backlight-on phase, the fourth transistor T4, together with the pre-storage capacitor Cst1, the second transistor T2, and the fifth transistor T5, extracts the threshold voltage Vth and stores it in the first node A to pre-compensate the threshold voltage Vth.

[0040] Backlight off phase of the sub-circuit in row N: When the reset signal line Reset jumps to a high level, the seventh transistor T7 is turned on, so that the pixel electrode Clc is reset through the seventh transistor T7; After the reset is complete, the reset signal line Reset jumps to a low level, and the seventh transistor T7 is turned off; When the transfer signal line Tran jumps to a high level, the third transistor T3 and the sixth transistor T6 are turned on. The positive power supply line Vdd makes the potential of the second node B high through the third transistor T3, at which time VB=Vdd; At this time, the pre-storage capacitor Cst1 maintains the potential of the first node A as VA = Vdata + Vth, so that the fourth transistor T4 is in saturation state, and the potential of the third node C is the data signal voltage Vdata when it is cut off, that is, VC = Vdata. When the sixth transistor T6 is turned on, the third node C writes the data signal voltage Vdata to the pixel electrode Clc through the sixth transistor T6.

[0041] During this stage, the accurate data signal voltage Vdata is written into the pixel electrode Clc through the third transistor T3, the fourth transistor T4, and the sixth transistor T6, so that the pixel voltage Vpixel = Vdata. By utilizing the saturation state of the fourth transistor T4, it can be canceled out with the pre-compensated threshold voltage Vth, thereby avoiding the influence of the threshold voltage Vth change.

[0042] This embodiment is used for the circuit of Embodiment 1 and its variants, and its beneficial effects are the same as those of Embodiment 1.

[0043] Example 4 This fourth embodiment is a gate-controlled field sequence circuit control method.

[0044] Before the backlight-on stage of the sub-circuit in row N, there is also a preset high stage; The preset high stage includes: the row gate signal line ScanN-1 of the N-1th row jumps to a high level, the first transistor T1 is turned on, and the positive power supply line Vdd charges the pre-storage capacitor Cst1 through the first transistor T1, making the potential of the first node A high. At this time, the potential of the first node A VA = Vdd. When the row gate signal line ScanN-1 of row N-1 goes low, the first transistor T1 is turned off. The preset high stage is used to charge the pre-storage capacitor Cst1 to maintain the high potential of the first node A, so that the fourth transistor T4 can enter the preset on / off state in the subsequent stage.

[0045] Backlight activation phase of the sub-circuit in row N: When the row gate signal line ScanN of row N goes high, the second transistor T2 and the fifth transistor T5 are turned on; when the data signal control line Data-Ctrl goes high, the eighth transistor T8 is turned on, and the data signal line Data, through the eighth transistor T8 and the fifth transistor T5, makes the potential of the second node B continuously the data signal voltage, i.e., VB=Vdata; when the second transistor T2 is turned on, the first node A and the third node C are connected. The pre-storage capacitor Cst1 maintains the first node A and the third node C at a high potential, i.e., VA=VC=Vdd; At this time, the fourth transistor T4 is turned on until it reaches saturation. Since the second node B is maintained at the data signal voltage Vdata, when the fourth transistor T4 is saturated, the first node A and the third node C discharge to the sum of the data signal voltage Vdata and the threshold voltage Vth of the fourth transistor T4, that is, VA=VC=Vdata+Vth; the row gate signal line ScanN of the Nth row jumps to a low level, and the second transistor T2 and the fifth transistor T5 are turned off. During the backlight-on phase, the fourth transistor T4 works with the pre-storage capacitor Cst1, the second transistor T2, and the fifth transistor T5 to extract the threshold voltage Vth and store it in the first node A, thus pre-compensating the threshold voltage Vth.

[0046] Backlight off phase of the sub-circuit in row N: When the power control signal line V-Ctrl jumps to a high level, the ninth transistor T9 turns on, allowing the power signal lines Vdd-Vss to input a preset square wave to the field sequence circuit through the ninth transistor T9. The preset square wave is a square wave that goes low first and then high, with Vss for the low phase and Vdd for the high phase. When the transfer signal line Tran jumps to a high level, the third transistor T3 and the sixth transistor T6 are turned on. The preset square wave output by the power signal line Vdd-Vss is at a low level, while the preset square wave output is at a high level. Vdd, through the ninth transistor T9 and the third transistor T3, makes the potential of the second node B high, that is, VB=Vdd. At this time, the pre-storage capacitor Cst1 maintains the potential of the first node A as VA=Vdata+Vth, so that the fourth transistor T4 is in saturation state until it reaches saturation state. At this time, the potential of the third node C is the data signal voltage Vdata when it is cut off, that is, VC=Vdata. When the sixth transistor T6 is turned on, the third node C writes the data signal voltage Vdata to the pixel electrode Clc through the sixth transistor T6.

[0047] During this stage, the accurate data signal voltage Vdata is written into the pixel electrode Clc through the third transistor T3, the fourth transistor T4, and the sixth transistor T6, so that the pixel voltage Vpixel = Vdata. By utilizing the saturation characteristics of the fourth transistor T4, it can be canceled out with the pre-compensated threshold voltage Vth, thereby avoiding the influence of the threshold voltage Vth change.

[0048] This embodiment provides a control method that differs from Embodiment 3, but its beneficial effects are the same as those of Embodiment 2.

[0049] The above embodiments only illustrate preferred implementation methods, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from this invention, and these all fall within the protection scope of this invention.

Claims

1. A gate-controlled field-sequence circuit, characterized in that: The system includes M rows of sub-circuits, each sub-circuit comprising a compensation unit and a driving unit. The compensation unit includes a first transistor (T1), a second transistor (T2), a fourth transistor (T4), a third transistor (T3), a fifth transistor (T5), and a pre-storage capacitor (Cst1). The gate of the first transistor (T1) of the sub-circuit in the Nth row is coupled to the row gate signal line (ScanN-1) of the (N-1)th row. The first source and drain of the first transistor (T1) are coupled to the positive power supply line (Vdd). The second source and drain of the first transistor (T1) are coupled to one end of the pre-storage capacitor (Cst1). The other end of the pre-storage capacitor (Cst1) is coupled to the common signal line (Com). The second source and drain of the first transistor (T1) are also coupled to the gate of the fourth transistor (T4), the first source and drain of the fourth transistor (T4) are coupled to the second source and drain of the third transistor (T3) and the fifth transistor (T5), and the second source and drain of the fourth transistor (T4) are coupled to the second source and drain of the second transistor (T2). The first source-drain of the second transistor (T2) in the Nth row sub-circuit is coupled to one end of the pre-storage capacitor (Cst1), and the gate of the second transistor (T2) is coupled to the row gate signal line (ScanN) of the Nth row. The gate of the third transistor (T3) of the sub-circuit in the Nth row is coupled to the transfer signal line (Tran), and the first source-drain of the third transistor (T3) is coupled to the positive power supply line (Vdd). The gate of the fifth transistor (T5) of the sub-circuit in the Nth row is coupled to the row gate signal line (ScanN) of the Nth row, the first source and drain of the fifth transistor (T5) are coupled to the data signal line (Data), and the second source and drain of the fifth transistor (T5) are coupled to the first source and drain of the fourth transistor (T4). The second source-drain of the fourth transistor (T4) in the sub-circuit of the Nth row is also coupled to the driving unit; M and N are positive integers, 1 <N≤M。 2. The gate-controlled field-sequence circuit according to claim 1, characterized in that, The driving unit includes a sixth transistor (T6) and a pixel electrode (Clc). The gate of the sixth transistor (T6) is coupled to the transfer signal line (Tran), the first source and drain of the sixth transistor (T6) are coupled to the second source and drain of the second transistor (T2), the second source and drain of the sixth transistor (T6) are coupled to the pixel electrode (Clc), and the other end of the pixel electrode (Clc) is coupled to the common signal line (Com).

3. The gate-controlled field-sequence circuit according to claim 2, characterized in that, The driving unit also includes a storage capacitor (Cst2), one end of which is coupled to the second source-drain of the sixth transistor (T6), and the other end of which is coupled to the common signal line (Com).

4. The gate-controlled field-sequence circuit according to claim 3, characterized in that, The sub-circuit also includes a reset unit, which includes a seventh transistor (T7). The first source-drain of the seventh transistor (T7) is coupled to the driving unit, and the second source-drain of the seventh transistor (T7) is coupled to the ground line (Vss).

5. A gate-controlled field-sequence circuit according to claim 2, characterized in that, The sub-circuit further includes a selection unit, wherein the first source and drain of the first transistor (T1), the first source and drain of the third transistor (T3), and the first source and drain of the fifth transistor (T5) are all coupled to the selection unit; the gate of the first transistor (T1) is coupled to the reset signal line (Reset).

6. The gate-controlled field-sequence circuit according to claim 5, characterized in that, The selection unit includes an eighth transistor (T8), a ninth transistor (T9), and power signal lines (Vdd-Vss). The gate of the eighth transistor (T8) is coupled to the data control signal line (Data-Ctrl), the first source and drain of the eighth transistor (T8) are coupled to the data signal line (Data), and the second source and drain of the eighth transistor (T8) are coupled to the second source and drain of the ninth transistor (T9); the gate of the ninth transistor (T9) is coupled to the power control signal line (V-Ctrl), and the first source and drain of the ninth transistor (T9) are coupled to the power signal line (Vdd-Vss).

7. A gate-controlled field-sequence circuit control method, applied to the field-sequence circuit of claim 4, characterized in that, include: Backlight activation phase of the sub-circuit in row N: When the row gate signal line (ScanN) of row N goes high, the second transistor (T2) and the fifth transistor (T5) are turned on. The data signal line (Data) keeps the potential of the second node (B) at the data signal voltage through the fifth transistor (T5); the pre-storage capacitor (Cst1) keeps the first node (A) at a high potential, and at the same time keeps the third node (C) at a high potential through the second transistor (T2); The fourth transistor (T4) is turned on until it reaches saturation, and the first node (A) and the third node (C) discharge to the sum of the data signal voltage and the threshold voltage of the fourth transistor (T4); When the row gate signal line (ScanN) of the Nth row goes low, the second transistor (T2) and the fifth transistor (T5) are turned off. Backlight off phase of the sub-circuit in row N: When the reset signal line (Reset) goes high, the seventh transistor (T7) turns on, allowing the pixel electrode (Clc) to be reset through the seventh transistor (T7); After the reset is complete, the reset signal line (Reset) goes low, and the seventh transistor (T7) is turned off; When the transfer signal line (Tran) goes high, the third transistor (T3) and the sixth transistor (T6) are turned on; The positive power line (Vdd) makes the potential of the second node (B) high through the third transistor (T3); The fourth transistor (T4) is saturated again, and the potential of the third node (C) is the data signal voltage. The data signal voltage is written into the pixel electrode (Clc) through the sixth transistor (T6).

8. A gate-controlled field-sequence circuit control method, applied to the field-sequence circuit of claim 6, characterized in that, include: Backlight activation phase of the sub-circuit in row N: The row gate signal line (ScanN) of the Nth row jumps to a high level, and the second transistor (T2) and the fifth transistor (T5) are turned on; the pre-storage capacitor (Cst1) maintains the first node (A) at a high potential, and at the same time maintains the third node (C) at a high potential through the second transistor (T2); When the data signal control line (Data-Ctrl) jumps to a high level, the eighth transistor (T8) turns on, and the data signal line (Data) maintains the potential of the second node (B) at the data signal voltage through the fifth transistor (T5) and the eighth transistor (T8). The fourth transistor (T4) is turned on until it reaches saturation. When the fourth transistor (T4) is saturated, the first node (A) and the second node (B) discharge to the sum of the data signal voltage and the threshold voltage of the fourth transistor (T4). When the row gate signal line (ScanN) of row N goes low, transistors 2 (T2) and 5 (T5) are turned off; when the data control line (Data-Ctrl) goes low, transistor 8 (T8) is turned off. Backlight off phase of the sub-circuit in row N: When the power control signal line (V-Ctrl) jumps to a high level, the ninth transistor (T9) turns on, allowing the power signal line (Vdd-Vss) to input a preset square wave to the field sequence circuit through the ninth transistor (T9); When the transfer signal line (Tran) goes high, the third transistor (T3) and the sixth transistor (T6) are turned on; The power signal lines (Vdd-Vss) enable the pixel electrode (Clc) to be reset by a preset square wave through the ninth transistor (T9), the third transistor (T3), and the sixth transistor (T6); After the reset is completed, the power signal lines (Vdd-Vss) make the potential of the second node (B) high through the ninth transistor (T9) and the third transistor (T3); The pre-storage capacitor (Cst1) maintains the potential of the first node (A) as the sum of the data signal line and the threshold voltage. The fourth transistor (T4) is saturated and discharged, so that the potential of the third node (C) is the data signal voltage when it is cut off. The data signal voltage is written to the pixel electrode (Clc) through the sixth transistor (T6).

9. The gate-controlled field-sequence circuit control method according to claim 7, characterized in that, include: Before the backlight-on stage of the sub-circuit in row N, there is also a preset high stage; The preset high-level phase includes: The row gate signal line (ScanN-1) of the N-1th row jumps to a high level, the first transistor (T1) turns on, and the positive power supply line (Vdd) charges the pre-storage capacitor (Cst1) through the first transistor (T1), making the potential of the first node (A) high. When the row gate signal line (ScanN-1) of row N-1 goes low, the first transistor (T1) is turned off.

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