Systems and methods for low density parity check (LDPC) codes with 3 / 4 code rate

Abstract

The present disclosure relates to systems and methods for low-density parity-check (LDPC) codes with 3 / 4 code rate. In some implementations, an apparatus can include a transmitter and one or more processors. The one or more processors can be configured to identify a first binary parity check matrix for a quasi-cyclic low-density parity-check, QC-LDPC, code according to a code rate of 3 / 4 and a code block size of 3888 bits. The first binary parity check matrix can correspond to a first exponent matrix having 144 values. The one or more processors can be configured to encode data using the first binary parity check matrix. The one or more processors can be configured to transmit the encoded data.

Description

[0001] Cross-citation of related applications

[0002] This application claims the benefit of priority to each of U.S. Provisional Patent Application No. 63 / 516,688, filed July 31, 2023; U.S. Provisional Patent Application No. 63 / 516,700, filed July 31, 2023; U.S. Provisional Patent Application No. 63 / 600,327, filed November 17, 2023; and U.S. Provisional Patent Application No. 63 / 600,331, filed November 17, 2023, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This disclosure generally relates to systems and methods for improving the encoding and / or decoding processes of communication systems using quasi-cyclic low-density parity-check (QC-LDPC) codes. Background Technology

[0004] Error correction codes enable the reliable exchange of information data between a transmitter communication system and a receiver communication system. The transmitter communication system encodes the information data to obtain codewords. A codeword is the encoded information data. The transmitter communication system transmits the codewords to the receiver communication system. Due to noise in the communication channel, the transmission received by the receiver communication system may differ from the transmitted codewords. Encoding the information data allows the receiver communication system, with an appropriate decoding process, to recover the information data from the received transmission despite such noise. For example, the transmitter communication system transmits parity bits to the receiver communication system. Parity bits allow the receiver communication system to verify whether the received transmission is a valid codeword, and if the received transmission is not a valid codeword, then correct the error in the transmission. In one approach, generating parity bits involves a complex process. Summary of the Invention

[0005] In one aspect, this disclosure provides a method comprising: identifying a first binary parity check matrix for quasi-cyclic low-density parity check (QC-LDPC) codes based on a 3 / 4 code rate and a 3888-bit code block size by one or more processors of a first device, the first binary parity check matrix corresponding to a first exponent matrix having 144 values; encoding data using the first binary parity check matrix by the one or more processors of the first device; and transmitting the encoded data by the one or more processors of the first device.

[0006] In another aspect, this disclosure provides an apparatus comprising: a transmitter and one or more processors, wherein the one or more processors are configured to: identify a first binary parity check matrix for quasi-cyclic low-density parity check (QC-LDPC) codes based on a 3 / 4 code rate and a 3888-bit code block size, the first binary parity check matrix corresponding to a first exponential matrix having 144 values; encode data using the first binary parity check matrix; and transmit the encoded data.

[0007] In another aspect, this disclosure provides an apparatus comprising: a receiver configured to receive encoded data; and one or more processors configured to: identify a first binary parity check matrix for quasi-cyclic low-density parity check (QC-LDPC) codes based on a 3 / 4 code rate and a 3888-bit code block size, the first binary parity check matrix corresponding to a first exponential matrix having 144 values; and decode the received encoded data using the first binary parity check matrix. Attached Figure Description

[0008] The various objectives, aspects, features, and advantages of this disclosure will become more apparent and better understood through a detailed description taken in conjunction with the accompanying drawings, in which similar reference numerals are used throughout to identify corresponding elements. In the drawings, similar reference numerals generally indicate identical, functionally similar, and / or structurally similar elements.

[0009] Figure 1 It is a diagram depicting an instance communication environment having a communication system according to one or more embodiments.

[0010] Figure 2 This is a schematic block diagram of a computing system according to an embodiment.

[0011] Figure 3 It is a graph depicting an instance index matrix according to one or more embodiments.

[0012] Figure 4 It is a diagram depicting an instance shifted identity matrix according to one or more embodiments for generating a parity check matrix.

[0013] Figure 5 It is a graph depicting an instance parity check matrix according to one or more embodiments.

[0014] Figure 6A and 6B It is a diagram depicting an instance code design that uses a prototype diagram to elevate a concept / method according to one or more embodiments.

[0015] Figure 7A , 7B7C and 7D are diagrams depicting instance code for concurrent decoding according to one or more embodiments.

[0016] Figure 8 This is a flowchart illustrating the process of encoding data using LDPC codes according to an embodiment.

[0017] Figure 9 This is a flowchart illustrating the process of encoding and / or decoding data using LDPC codes according to an embodiment.

[0018] Figure 10A , 10B Figures 10C, 10D, 10E, and 10F are diagrams depicting example simulation results using QC-LDPC codes according to one or more embodiments.

[0019] Details of various embodiments of the method and system are set forth in the accompanying drawings and the description below. Detailed Implementation

[0020] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, a first feature communicating or communicatively coupled to a second feature may include embodiments in which the first feature directly communicates with or is directly coupled to the second feature, and may also include embodiments in which an additional feature may be situated between the first and second features such that the first feature indirectly communicates with or is indirectly coupled to the second feature. Furthermore, reference numerals and / or letters may be repeated throughout the disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] The various embodiments disclosed herein relate to a device comprising a transmitter and one or more processors. The processors may be configured to determine quasi-cyclic low-density parity-check (QC-LDPC) codes in which multiple codebooks are embedded. The processors may be configured to select a codebook from the multiple codebooks based on a block size and a code rate. The processors may be configured to generate a parity check matrix based on the codebooks. A parity check matrix is ​​a matrix that defines the relationship between information bits and parity bits (e.g., a parity equation or constraint). A binary parity check matrix is ​​a parity check matrix in which all entries are 0 or 1. The processors may be configured to encode data using the generated parity check matrix. The processors may be configured to transmit the encoded data to another device via the transmitter.

[0022] In some embodiments, each of the plurality of codebooks may include a plurality of integers, and the number of the plurality of integers is equal to the number of elements of the parity check matrix divided by z, wherein z is an integer representing the lifting size of the QC-LDPC code.

[0023] In some embodiments, each of the plurality of codebooks may represent an exponent matrix of the parity check matrix. In some embodiments, each element of the exponent matrix may correspond to a cyclic shift value of an identity matrix. The size of the identity matrix is z×z, and the cyclic shift value d is an integer such that -1≤d<z, wherein Z is an integer representing the lifting size of the QC-LDPC code. The cyclic shift value d may represent a shifted identity matrix obtained by right-shifting the identity matrix by d. A cyclic shift value of -1 may represent a zero matrix in place of the identity matrix.

[0024] In some embodiments, when generating the parity check matrix based on the selected codebook, one or more processors may be configured to generate the exponent matrix based on the selected codebook. For each element of the exponent matrix, the one or more processors may be configured to generate a shifted identity matrix of the identity matrix based on the value of each element of the exponent matrix. The one or more processors may be configured to generate the parity check matrix such that the parity check matrix includes the generated shifted identity matrix as an element corresponding to each element of the exponent matrix.

[0025] In some implementations, the block size can be 3888 bits, and the code rate can be 3 / 4. The block size (denoted by n) refers to the total number of encoded or transmitted bits as a result of encoding data using error correction codes (e.g., LDPC). The number of information bits (denoted by k) refers to the number of bits carrying the data to be encoded using error correction codes. The code rate (denoted by R) is the ratio of the number of information bits to the block size (R = k / n). Multiple codebooks can contain one codebook, which includes [96 59 56 78 18 122-1-1-1 126 90 161-1-1-1 74 65 45 2 0-1-1-1-1 8 98 85 972261-1-1-1 98 35 82 74 31-1 108-1-1-1 0 0-1-1-1 71 153 156 102 74 70 42-1 35128-1-1-1 118 14-1-1 65-1-1 0 0-1-1 18 131 88 18 109 113 146 69 84-1-1-1 71-1-1-1 92 790-1-1 0 0-1 7 124 15 161 137 53-1 161 110-1 72-1 53-1 18-1 145-1-1-1-1-1 0 0 53151 66 42 138 118 6 77-1-1-1 70-1 125 72 53-1-1 2-1-1-1-1 0).

[0026] In one aspect, a parity check matrix is ​​defined as a set of equations satisfied by any valid codeword. Parity check matrices can be used to encode low-density parity check (“LDPC”) codes, described by Richardson and Urbanke in IEEE Transactions on Information Theory, Vol. 47, No. 2 (February 2001). Typically, many wireless and wired communication systems use LDPC as a forward error correction coding scheme. However, the longest block length (in bits) of coded data supported in the 802.11 standards (e.g., 802.11n to 802.11be) is 1944. Limited gain may exist in radio channels (e.g., 2x2 multiple-input multiple-output channels), which can be achieved using a block length of 1944.

[0027] To address this issue, according to certain aspects, embodiments of this disclosure relate to techniques for supporting or providing LDPC codes with a block length of 3888 and a code rate of 3 / 4. The block length of 3888 is twice the block length of the longest code supported in the 802.11n to 802.11be standards (e.g., a block length of 1944). In some embodiments, the LDPC code has a quasi-cyclic (QC) structure, which facilitates efficient encoding and decoding. In some embodiments, the QC-LDPC code can be a type of structured LDPC code that can be used in many practical applications, including the IEEE 802.11n, 802.11ac, 802.11ax, and 802.11be standards. In the QC-LDPC code, the parity check matrix has a cyclic structure that repeats itself in a quasi-cyclic manner, which simplifies the encoding and decoding process, thereby making the QC-LDPC code more efficient.

[0028] In some implementations, the LDPC encoder may take a block of k information bits and produce n encoded bits (with a code rate R = k / n). The LDPC decoder may operate on the n received bits (noisy version) and (ideally) recover the k information bits. In some implementations, the LDPC encoder may take a block of 2916 information bits (k = 2916) as input, encode the 2916-bit block to produce a block of 3888 encoded bits (n = 3888) with a code rate of 3 / 4 (R = k / n).

[0029] Typically, the parity check matrix of a code represents an equation for determining whether an error occurred during transmission. More formally, for all valid codewords (i.e., the error-free bits generated by the encoder), the following equation holds:

[0030] Hc=0…………….(Equation 1)

[0031] In Equation 1, "H" is the parity check matrix, "c" is the codeword vector, and "0" is a vector of all zeros. The parity check matrix H is one way to describe a code.

[0032] The code generator matrix G satisfies the following equation:

[0033] sG=c……………(Equation 2)

[0034] In Equation 2, “s” is a vector of information bits, “G” is a generator matrix, and “c” is the codeword corresponding to “s”. In some embodiments, a system (e.g., a communication system 108 including decoder 160) can use Equation 2 to decode codeword c to obtain decoded data s.

[0035] According to the matrix equations above, the parity check matrix and the generator matrix of the code are related. Generally, if the parity check matrix is ​​low-density, the corresponding generator matrix will be high-density, and vice versa. LCPC codes are thus characterized by a low-density parity check matrix and a high-density generator matrix. The density of the matrix is ​​related to the number of operations that must be performed to implement one of the above equations. Although it was recognized by 1995 that LDPC codes could be used to transmit data with very few errors, i.e., with an error rate as good as or better than turbine codes, a drawback of LDPC codes is that their generator matrices are high-density, which makes the encoding computationally intensive, thus making the codes impractical for many applications.

[0036] In some implementations, the parity check matrix may have a quasi-cyclic structure, for example, the parity check matrix for QC-LDPC codes (n = 3888, k = 2916, R = 3 / 4). For example, given a lift size Z, the parity check matrix may have multiple submatrices such that each submatrix is ​​a cyclically shifted version of an identity matrix of size (Z x Z), where Z = 162. The parity check matrix can be represented in two equivalent forms: (1) the parity check matrix H and (2) the block matrix or exponential matrix P = E(H).

[0037] In some implementations, the parity check matrix H can be a binary matrix of size m x n (where each of m and n is an integer). The elements of the parity check matrix are binary values. Given a block length n and a code rate R, the LDPC code (or QC-LDPC code) LDPC(n,R) satisfies the following equation:

[0038] k = nR……(Equation 3)

[0039] m = n(1-R)……(Equation 4)

[0040] In some implementations, a block matrix or an exponential matrix (QC-LDPC exponential matrix) can be obtained. Given a lift size Z, the exponential matrix P = E(H) can have a size of m / Z x n / Z. If n = 24Z (e.g., n = 3888, Z = 162), then the size of P = E(H) is 24(1-R) ​​x 24 (= n(1-R) / Z x n / Z). The elements of the exponential matrix can be integer values ​​corresponding to the cyclic shift values ​​of an identity matrix of size Z × Z. The parity matrix H can be a sparse binary matrix that can be derived from the exponential matrix P = E(H). The generator matrix G can have a size of n × k in binary form (e.g., the elements of the generator matrix G are binary values). The exponential matrix P = E(H) can have a structure containing multiple submatrices (e.g., A, B, C, D, E, T).

[0041] In some implementations, the binary QC-LDPC code LDPC(n,R) can be represented by the null space of an n(1-R)×n parity check matrix H. The parity check matrix H can be a binary sparse matrix containing a set of cyclic matrices of size Z×Z. The parity check matrix H of the QC-LDPC code can be equivalently represented by the exponent matrix P = E(H). This representation helps to illustrate the graphical structure of the underlying code as a base graph and the shift coefficients.

[0042] In some implementations, multiple codebooks may be provided to generate the parity check matrix. For example, multiple codebooks may comprise a single codebook. A codebook refers to a collection of codewords (or code vectors) or error correction codes (e.g., LDPC codes) used in error correction and / or data compression. A codeword is an encoded representation generated by applying error correction codes to the original data.

[0043] The codebook used to represent the block matrix P = E(H) can contain [96 59 56 78 18 122-1-1-1 126 90161-1-1-1 74 65 45 2 0-1-1-1-1 8 98 85 97 22 61-1-1-1 98 35 82 74 31-1 108-1-1-1 0 0-1-1-1 71 153 156 102 74 70 42-1 35 128-1-1-1 118 14-1-1 65-1-1 0 0-1-1 118 131 88 18 109113 146 69 84-1-1-1 71-1-1-1 92 79 0-1-1 0 0-1 7 124 15 161137 53-1 161 110-1 72-1 53-1 18-1 145-1-1-1-1-1 0 0 53 151 66 42 138 118 677-1-1-1 70-1 125 72 53-1-12-1-1-1-1 0]……(Codebook 1)

[0044] In some embodiments, a codebook may be used to generate a parity check matrix H from an exponent matrix P=E(H). The exponent matrix P=E(H) may include (as elements) shift values d in the range 0<=d<Z, as well as d=-1. For example, if Z=7, the shift values d may include -1, 0, 1, 2, 3, 4, 5, 6. The shift value d=0 may correspond to (or map to) a Z×Z identity matrix denoted by I(Z). The shift value d=-1 may correspond to (or map to) a Z×Z zero matrix (all elements are zero) denoted by 0*I(Z). Any other integer value d in [1, Z-1] may correspond to (or map to) a matrix cyclically right-shifted from I(Z). The parity check matrix H may be obtained from the exponent matrix P=E(H) by extending the exponent matrix P such that each element (as a shift value d) of the exponent matrix P is replaced by a matrix corresponding to the shift value.

[0045] In some embodiments, the exponent matrix P=E(H) may include a plurality of elements P₁,₁, P₁,₂, P₁,₃, ..., P₁,ń; P₂,₁, P₂,₂, P₂,₃, ..., P₂,ń; ..., P₁,₁, P₁,₂, P₁,₃, ..., which corresponds to the value of the codebook, where and ń satisfy the following equation:

[0046]

[0047] ń=n / Z ...... (Equation 6)

[0048] The exponent matrix (or permutation matrix) P=E(H) may be expressed as follows:

[0049]

[0050] By replacing each element (as a shift value d) of the matrix with a matrix C(d) corresponding to the shift value, the corresponding parity check matrix H may be obtained as follows:

[0051]

[0052] For example, the matrix C(1) may be expressed as follows:

[0053]

[0054] In some implementations, the encoder may use a generator matrix (e.g., using Equation 2) to generate codewords. In some implementations, the encoder may use a parity check matrix (instead of a generator matrix) to generate codewords from a vector of information bits. After obtaining the parity check matrix H (e.g., using a codebook), the parity check matrix H may have submatrices A, B, C, D, T, and E. The upper region O of submatrix T may correspond to a region in which the matrix contains all zeros, and the other regions may represent positions that may contain 1s.

[0055] In some implementations, the codeword c can be obtained through the following expression:

[0056] c = [s p1 p2]……(Equation 10),

[0057] Where “s” is the vector of information bits to be encoded, “p1” is the vector of the first g parity bits, and “p2” is the vector of the remaining mg parity bits.

[0058] Vectors p1 and p2 can be obtained through the following equation:

[0059] Φ=-ET -1 B+D……(Equation 11);

[0060] p1 T =-Φ -1 (-ET -1 A+C)s T ...(Equation 12); and

[0061] p2 T =-T -1 (As T +Bp1 T ... (Equation 13).

[0062] Although the various embodiments disclosed herein are described as being used for encoding data for wireless communication (e.g., wireless local area networks (WLANs) conforming to any IEEE 802.11 standard), the principles disclosed herein are applicable to other types of communication (e.g., wired communication) or any process for performing the encoding of LDPC codes.

[0063] In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to generate a first binary parity check matrix for QC-LDPC codes using a first matrix with 144 values ​​at a code rate of 3 / 4. The first matrix contains at least 142 values ​​selected from the following set: [96 59 56 78 18122 -1 -1 -1 126 90 161 -1 -1 -1 74 65 45 2 0 -1 -1 -1 -1 8 98 85 97 22 61 -1 -1 -1 98 35 82 74 31 -1 108 -1 -1 -1 0 0 -1 -1 -1 71 153 156 102 74 70 42 -1 35 128 -1 -1 -1 118 14 -1 -1 65 -1 -1 0 0 -1 -1 18 131 88 18 109 113 146 6984 -1 -1 -1 71 -1 -1 -1 92 79 0 -1 -1 0 0 -1 7 124 15 161 137 53 -1 161 110 -1 72 -1 53 -1 18 -1 145 -1 -1 -1 -1 -1 0 0 53 151 66 42 138 118 6 77 -1 -1 -170 -1 125 72 53 -1 -1 2 -1 -1 -1 -1 0]. One or more processors may be configured to encode data using the generated first binary parity matrix. One or more processors may be configured to cause a transmitter to transmit the encoded data. In some embodiments, the first binary parity matrix may be generated according to a size of 3888 bits. One or more processors may be further configured to shift one or two values ​​of the first matrix from one or more corresponding positive values ​​in a set of values ​​by -1 or +1. One or more corresponding positive values ​​in a set of values ​​may not be selected as at least 142 values.

[0064] The embodiments in this disclosure have at least the following advantages and benefits. First, the embodiments in this disclosure provide useful techniques for providing significant gain across all modulation schemes. For example, the block length of a QC-LDPC code (e.g., 3888 bits) according to some embodiments is at least twice the block length of the longest code supported in the 802.11n to 802.11be standards (e.g., 1994 bits). This QC-LDPC code can provide approximately 2 dB of gain in a 2x2 MIMO (Multiple-Input Multiple-Output) channel, and this gain is consistent across all modulation schemes with or without beamforming.

[0065] Second, the embodiments in this disclosure provide useful techniques for providing significant gains (e.g., a 0.5 dB to 1.2 dB gain in SNR (signal-to-noise ratio) relative to existing codes) across all modulation schemes. For example, the block length of a QC-LDPC code (e.g., 3888 bits) according to some embodiments is at least twice the block length of the longest code supported in the 802.11n to 802.11be standards (e.g., 1994 bits). This QC-LDPC code can provide approximately 2 dB of gain in a 2x2 MIMO channel, and this gain is consistent across all modulation schemes with or without beamforming.

[0066] Third, the embodiments in this disclosure may provide a codebook and a method for constructing the codebook. In some embodiments, QC-LDPC codes can be constructed by slightly pushing the cyclic shift values ​​of the parity check matrix.

[0067] refer to Figure 1 The illustration depicts an example communication environment 100 including communication systems (or communication devices) 105, 108 according to one or more embodiments. In one embodiment, communication system 105 includes a baseband circuit system 110 and a transmitter circuit system 120, and communication system 108 includes a baseband circuit system 150 and a receiver circuit system 140. In one aspect, communication system 105 is considered a transmitter communication system, and communication system 108 is considered a receiver communication system. These components operate together to exchange data (e.g., messages or frames) over a wireless medium. In one or more embodiments, these components are embodied as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or any combination thereof. In some embodiments, communication systems 105, 108 include more than Figure 1 The components shown may be more, fewer, or different. For example, each of communication systems 105, 108 includes a transceiver circuitry to allow bidirectional communication between communication systems 105, 108 or with other communication systems. In some embodiments, each of communication systems 105, 108 may have similar components as shown in the diagram. Figure 2 The configuration of the computing system 2000 shown in the figure.

[0068] The baseband circuitry 110 of the communication system 105 is a circuitry system that generates baseband data 115 for transmission. The baseband data 115 contains information data (e.g., signals) at a baseband frequency for transmission. In one method, the baseband circuitry 110 includes an encoder 130 that encodes the data and generates or outputs parity bits. In one aspect, the baseband circuitry 110 (or encoder 130) obtains a generator matrix or a parity matrix, or encodes the information data using a previously generated generator matrix or a previously generated parity matrix by applying the information data to the generator matrix or parity matrix to obtain codewords. In some embodiments, the baseband circuitry 110 stores one or more generator matrices or one or more parity matrices conforming to any IEEE 802.11 standard for WLAN communication. In response to detecting information data to be transmitted, or in response to receiving an instruction to encode the information data, the baseband circuitry 110 retrieves the stored generator matrix or the stored parity matrix. In one method, baseband circuitry 110 generates parity bits based on a portion of a generator matrix or using a parity matrix, and appends the parity bits to information bits to form a codeword. Baseband circuitry 110 generates baseband data 115 containing the codeword for communication system 108, and provides baseband data 115 to transmitter circuitry 120.

[0069] The transmitter circuitry 120 of the communication system 105 includes or corresponds to a circuitry that receives baseband data 115 from the baseband circuitry 110 and transmits a wireless signal 125 based on the baseband data 115. In one configuration, the transmitter circuitry 120 is coupled between the baseband circuitry 110 and an antenna (not shown). In this configuration, the transmitter circuitry 120 up-converts the baseband data 115 from the baseband circuitry 110 into a carrier signal to generate a wireless signal 125 at RF frequencies (e.g., 10 MHz to 60 GHz) and transmits the wireless signal 125 via the antenna.

[0070] The receiver circuitry 140 of communication system 108 is a circuitry that receives radio signal 125 from communication system 105 and obtains baseband data 145 from the received radio signal 125. In one configuration, receiver circuitry 140 is coupled between baseband circuitry 150 and an antenna (not shown). In this configuration, receiver circuitry 140 receives radio signal 125 through the antenna and down-converts the radio signal 125 at an RF frequency according to a carrier signal to obtain baseband data 145 from the radio signal 125. Receiver circuitry 140 then provides the baseband data 145 to baseband circuitry 150.

[0071] The baseband circuitry system 150 of the communication system 108 includes or corresponds to a circuitry system that receives baseband data 145 from the receiver circuitry system 140 and obtains information data from the received baseband data 145. In one embodiment, the baseband circuitry system 150 includes a decoder 160 that extracts information and parity bits from the baseband data 145. The decoder 160 decodes the baseband data 145 to obtain the information data generated by the baseband circuitry system 110 of the communication system 105.

[0072] In some implementations, each of the baseband circuit system 110 (including encoder 130), transmitter circuit system 120, receiver circuit system 140, and baseband circuit system 150 (including decoder 160) may be one or more processors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or any combination thereof.

[0073] Figure 2 This is a schematic block diagram of a computing system according to an embodiment. The illustrated example computing system 2000 includes one or more processors 2010 that communicate directly or indirectly with memory 2060 via a communication system 2040 (e.g., a bus), at least one network interface controller 2030 having a network interface port for connecting to a network (not shown), and other components, such as input / output (“I / O”) components 2050. Typically, the processors 2010 execute instructions (or computer programs) received from memory. The illustrated processors 2010 are incorporated into or connected to cache memory 2020. In some examples, instructions are read from memory 2060 into cache memory 2020 and executed by processor 2010 from cache memory 2020. The computing system 2000 may not necessarily contain... Figure 2 All of these components shown in the document, and may contain Figure 2 Other components not shown.

[0074] More specifically, processor 2010 can be any logic circuit system that processes instructions, such as those fetched from memory 2060 or cache 2020. In many embodiments, processor 2010 is a microprocessor unit or a dedicated processor. Computing system 2000 can be based on any processor or set of processors capable of operating as described herein. Processor 2010 can be a single-core or multi-core processor. Processor 2010 can be multiple different processors.

[0075] Memory 2060 may be any means suitable for storing computer-readable data. Memory 2060 may be a means having fixed storage or a means for reading removable storage media. Examples include all forms of volatile memory (e.g., RAM), non-volatile memory, media and memory devices, semiconductor memory devices (e.g., EPROM, EEPROM, SDRAM, and flash memory devices), magnetic disks, magneto-optical disks, and optical disks (e.g., CD ROM, DVD-ROM, or...). (Optical disc). The computing system 2000 may have any number of memory devices 2060.

[0076] Cache memory 2020 is typically a form of computer memory located near processor 2010 for fast read times. In some embodiments, cache memory 2020 is part of processor 2010 or on the same chip as processor 2010. In some embodiments, there are multiple levels of cache 2020, such as L2 and L3 cache layers.

[0077] Network interface controller 2030 manages data exchange via network interfaces (sometimes referred to as network interface ports). Network interface controller 2030 handles the physical and data link layers of the OSI model for network communication. In some embodiments, some of the tasks of the network interface controller are handled by one or more of the processors 2010. In some embodiments, network interface controller 2030 is part of processor 2010. In some embodiments, computing system 2000 has multiple network interfaces controlled by a single controller 2030. In some embodiments, computing system 2000 has multiple network interface controllers 2030. In some embodiments, each network interface is a connection point for a physical network link (e.g., a Category 5 Ethernet link). In some embodiments, network interface controller 2030 supports wireless network connectivity, and the interface port is a wireless (e.g., radio) receiver or transmitter (e.g., for IEEE 802.11, Near Field Communication "NFC", Bluetooth, ANT, or any other wireless protocol). In some embodiments, network interface controller 2030 implements one or more network protocols, such as Ethernet. Typically, the computing system 2000 exchanges data with other computing devices via a network interface through a physical or wireless link. The network interface may be directly linked to another device or linked to another device via an intermediate device that connects the computing system 2000 to a data network such as the Internet, such as a network device (e.g., a hub, bridge, switch, or router).

[0078] The computing system 2000 may include one or more input or output (“I / O”) devices, or provide interfaces thereto. Input devices include, but are not limited to, keyboards, microphones, touchscreens, foot pedals, sensors, MIDI devices, and pointing devices such as mice or trackballs. Output devices include, but are not limited to, video displays, speakers, refreshable Braille terminals, lights, MIDI devices, and 2-D or 3-D printers.

[0079] Other components may include I / O interfaces, external serial device ports, and any additional coprocessors. For example, computing system 2000 may include interfaces (e.g., a Universal Serial Bus (USB) interface) for connecting input devices, output devices, or additional memory devices (e.g., portable flash drives or external media drives). In some embodiments, computing system 2000 includes additional devices, such as coprocessors; for example, a math coprocessor may assist processor 2010 in performing high-precision or complex calculations.

[0080] Component 2050 may be configured to connect to external media, display 2070, input device 2080, or any other component or combination thereof in computing system 2000. Display 2070 may be a liquid crystal display (LCD), organic light-emitting diode (OLED) display, flat panel display, solid-state display, cathode ray tube (CRT) display, projector, printer, or other display device now known or hereafter developed for outputting defined information. Display 2070 may serve as an interface for a user to view the operation of processor 2010, or more specifically, as an interface to software stored in memory 2060.

[0081] Input device 2080 can be configured to allow a user to interact with any of the components of computing system 2000. Input device 2080 can be multiple pads, a keyboard, a cursor control device (e.g., a mouse), or a joystick. Alternatively, input device 2080 can be a remote control, a touchscreen display (which can be a combination of display 2070 and input device 2080), or any other device operable to interact with computing system 2000, such as any device operable to act as an interface between the user and computing system 2000.

[0082] Figure 3 This is a diagram depicting an instance exponent matrix (QC-LDPC exponent matrix) 300 according to one or more embodiments. Given a lift size Z, the exponent matrix 300 may have a size of m / Z x n / Z. If n = 24Z (e.g., n = 3888, Z = 162), then the size of P = E(H) is 24(1-R) ​​x 24 (= n(1-R) / Z x n / Z). The elements of the exponent matrix may be integer values ​​corresponding to the cyclic shift values ​​of an identity matrix of size Z x Z. The parity check matrix H (see...) Figure 5 ) can be a sparse binary matrix derivable from the exponent matrix P=E(H). The generator matrix G may have a size of n x k in binary form (for example, the elements of the generator matrix G are binary values). Reference Figure 3 , the exponent matrix P=E(H) may have a structure comprising a plurality of sub-matrices (for example, A310, B 312, C 316, D 318, E 320, T 314).

[0083] Figure 4 is a diagram 400 depicting example shifted identity matrices 409, 410, 411, 412, 413, 414, 415, 416 for generating a parity check matrix in accordance with one or more embodiments. A codebook (for example, codebook 1) may be used to generate the parity check matrix H from the exponent matrix P=E(H) (for example, exponent matrix 300). As shown in Equation 7, the exponent matrix P=E(H) may comprise (as elements) shift values d in the range 0<=d<Z and d=-1. Referring to the equation, for example, if Z=7, then the shift values d may comprise -1, 0, 1, 2, 3, 4, 5, 6 (see Figure 4 ). The shift value d=0 may correspond to (or map to) an identity matrix of size Z x Z denoted by I(Z) (for example, matrix 410). The shift value d=-1 may correspond to (or map to) a zero matrix of size Z x Z (all elements are zero) denoted by 0*I(Z) (for example, matrix 409). Any other integer value d in [1, Z-1] may correspond to (or map to) a matrix cyclically right-shifted from I(Z) (for example, matrices 411, 412, 413, 414, 415, 416). As shown in Equation 8, the parity check matrix H may be obtained from the exponent matrix P=E(H) by expanding the exponent matrix P such that each element (as a shift value d) of the exponent matrix P is replaced by a matrix corresponding to the shift value.

[0084] Figure 5 is a diagram depicting an example parity check matrix 500 in accordance with one or more embodiments. In some embodiments, an encoder (for example, encoder 130) may generate codewords using a generator matrix (for example, using Equation 2). In some embodiments, an encoder (for example, encoder 130) may generate codewords from a vector of information bits using a parity check matrix (instead of a generator matrix). After obtaining the parity check matrix H (for example, using a codebook), the parity check matrix H (for example, parity check matrix 500) may have sub-matrices A 510, B 512, C 516, D 518, T 514, E 520. The upper region O 515 of sub-matrix T 514 (for example, Figure 5 the white region in) may correspond to a region where the matrix contains all zeros, and other regions (for example, Figure 5The gray area in the diagram can represent a position that may contain 1. The parity check matrix 500 can be m x n in size, where the submatrix D 518 is g x g in size, and the submatrix T is (mg) x (mg) in size. In some implementations, given a vector s of information bits to be encoded, the encoder can obtain the codeword c using equations 10, 11, 12, and 13.

[0085] In some implementations, codebooks for R=3 / 4 LDPC codes with a block length of 3888 bits can provide high-performance error correction and / or a gain of up to 1.2 dB relative to existing LDPC codes specified in the Wi-Fi standard. In some implementations, a set of LDPC codes with a block length of 3888 bits (2x1944) supports all code rates in the Wi-Fi standard (e.g., 802.11be). Codes (e.g., R=3 / 4 LDPC codes with a block length of 3888 bits) can be used directly in existing 64-QAM modulation in IEEE 802.11be and potentially in combination with further combinations of QAM sizes in IEEE 802.bn.

[0086] A collection of LDPC codes with a block length of 3888 bits (2x1944) can provide significant performance improvements in ultra-high reliability (UHR) across a variety of communication scenarios while maintaining manageable complexity. Performance comparisons are made between these codes and the LDPC codes specified in the IEEE 802.11be standard, as well as recently proposed codes with a block length of 4x1944. The results of the performance comparisons demonstrate comprehensive and verifiable gains (e.g., channel, PHY bandwidth, MIMO, modulation and coding scheme (MCS), transmit beamforming). For example, according to some implementations, LDPC codes with a block length of 3888 bits can provide a gain of 0.5 to 1.0 dB relative to current 802.11 LDPC codes, depending on channel conditions. LDPC codes with a block length of 4x1944 bits can provide an additional gain of 0.0 to 0.5 dB, depending on channel conditions.

[0087] The longest LDPC code specified in the 802.11be standard has a block length of 1944 bits. In terms of performance, the LDPC code specified in the 802.11be standard is approximately 2.7 dB shorter than the optimal random code (e.g., Bit-Interleaved Coded Modulation (BICM) - Added White Gaussian Noise (AWGN) - QAM (Quadrature Amplitude Modulation) R = 3 / 4 limit). According to the finite-length scaling theorem, longer block-length random codes (e.g., the asymptotic case of the Shannon limit when the block length becomes infinite) can lead to enhanced coding gain. Suboptimal deterministic codes can exhibit scaling gains significantly greater than those of the optimal random code. For example, in AWGN, the multiplication effect is known to be true.

[0088] In some implementations, LDPC codes have a block length of 2 x 1944 = 3888 bits (twice the size of the largest supported block length in the current 802.11be standard). In some implementations, LDPC codes with a block length of 3888 bits support all existing code rates (e.g., R = 1 / 2, 2 / 3, 3 / 4, and 5 / 6). In some implementations, LDPC codes with a block length of 3888 bits maintain the structural integrity of 802.11be codes (specifically, QC-LDPC), except for matrix size expansion. This adaptation facilitates the reuse of existing implementations and enables concurrent encoding and decoding.

[0089] Figure 6A and 6B It is a diagram depicting an instance code design that uses a prototype diagram to elevate a concept / method according to one or more embodiments.

[0090] Figure 6A Figure 600 is a design / generation / creation / definition of an example code design using the protograph enhancement concept / method according to one or more embodiments. A “protograph” can refer to a bipartite graph having two disjoint and independent vertex sets (e.g., the left vertex set indicated by circles and the right vertex set indicated by rectangles in protograph 611) to represent a matrix (e.g., parity matrix 611). Systems according to some embodiments (e.g., communication systems 105 or 108) can use a code with a block length of 1944 as the base code (e.g., protograph 611 and the corresponding (parity) matrix 612). The system can enhance (e.g., copy) the base code 2 (e.g., protograph 621 and the corresponding (parity) matrix 622). The system can (1) permutate / move / shift / migrate the edges of the prototype graph (e.g., from prototype graph 621 to prototype graph 631; equivalently permuting the columns of matrix 622 to obtain matrix 632); and / or (2) remove four cycles (and any possible short cycles) from the prototype graph (e.g., prototype graph 631 and the (parity) matrix 632 corresponding to prototype graph 631) to obtain prototype graph 641. For example, as Figure 6A As shown, the loop represented by submatrix 633 in the prototype diagram 631 (see submatrix 643) can be removed in the prototype diagram 641 corresponding to matrix 642. Similarly, the loop represented by submatrix 634 in the prototype diagram 631 corresponding to matrix 642 (see submatrix 644) can be removed.

[0091] In some implementations, the system can generate / define / design / create (as a design goal) codes representing protographs with a perimeter > 6. The "perimeter" of an undirected graph can refer to the length of the shortest cycle contained in the graph. In some implementations, the system can generate / define / design / create (as a design goal) codes corresponding to protographs with a perimeter > 10. For example, as... Figure 6A As shown, the prototype 631 (and its corresponding parity matrix 632) has a perimeter of 4, while prototypes 641 and 651 (and their corresponding parity matrices 642) each have a perimeter greater than 6. In some implementations, the system can add and / or remove edges to improve performance without increasing the perimeter. For example, edges can be added to and / or removed from parity matrix 642 to improve performance without increasing the perimeter of prototypes 641 and 651 (or the perimeter of their corresponding parity matrix 642).

[0092] Figure 6B Figure 650 depicts an example parity check matrix of a QC-LDPC code according to one or more embodiments. In some embodiments, a system according to some embodiments (e.g., communication system 105 or 108) can obtain a parity check matrix 642 (see Figure 6) of the same new code as parity check matrix 762 by embedding a 2x2 binary matrix in the original parity check matrix H (e.g., parity check matrix 612 as the base code). For example, the system can (1) use a 2x2 binary identity matrix Replace the element "1" in the original parity check matrix 612; and / or (2) further modify the replaced identity matrix. For example, after embedding a 2x2 binary identity matrix, the system may modify some of the embedded 2x2 binary identity matrix to produce modified binary matrices 651, 652, which correspond to the modified edges in the corresponding original model diagram.

[0093] In some implementations, a system (e.g., communication systems 103, 108) may include one or more processors (e.g., one or more processors 2010) configured to select a codebook for QC-LDPC codes from a plurality of codebooks based on a first size (e.g., 1944 bits) and a code rate of 3 / 4. The first size may be the size of a code block as a result of encoding an information block, and the code rate may be the ratio of the information block size to the first size. The one or more processors may be configured to generate a first parity check matrix (e.g., based on at least the codebook) Figure 6A (Parity check matrix 612 in the example). For example, the first parity check matrix may correspond to a block length of 1944 bits and a code rate of 3 / 4. One or more processors may use two examples of the first parity check matrix (e.g., Figure 6ATwo examples of parity check matrix 612 in the example are used to generate a second parity check matrix corresponding to the second size and code rate (e.g., Figure 6A (The parity check matrix in the first part is 642). The second size can be twice the size of the first. For example, the second parity check matrix can correspond to a block length of 3888 bits and a code rate of 3 / 4.

[0094] In some implementations, the system may use a first prototype (e.g., prototype 611) corresponding to the first parity check matrix to generate a second parity check matrix. The system may (1) lift (e.g., copy) the first prototype 2 (e.g., lift prototype 611 2 to create prototype 631); and / or (2) permutate / move / shift / migrate the edges of the lifted prototype (e.g., prototype 631) to remove one or more short cycles from the lifted prototype, thereby obtaining a second prototype (e.g., prototype 651) such that the perimeter of the second prototype is greater than 6 (or greater than 10). In some implementations, the system may further add one or more edges to the second prototype without increasing the perimeter of the prototype, or delete one or more edges from the second prototype. The second prototype (or a prototype as a result of further addition / removal of edges) may correspond to a second parity check matrix (e.g., parity check matrix 642).

[0095] In some implementations, the system can generate a second parity matrix by embedding a 2x2 binary matrix into the first parity matrix. For example, as... Figure 6B As shown, the system can replace each element of a first parity matrix with a value of "1" with a 2x2 binary matrix (e.g., a 2x2 binary identity matrix), and / or further modify the replaced binary matrix (e.g., modified binary matrices 651, 652) to obtain a second parity matrix (e.g., parity matrix 642).

[0096] Figure 7A , 7B 7C and 7D are diagrams depicting instance code for concurrent decoding according to one or more embodiments. Figure 7A Figure 700 depicts an example submatrix structure according to one or more embodiments. Four different diagram representations (or prototype diagrams) 701, 702, 703, 704 and corresponding submatrix structures 711, 712, 713, 714 may exist respectively. In the submatrix structure, the (i,j) element (entry) of the submatrix indicates the j-th column (e.g., ...). Figure 7A Vertex v1 or v'1 in the i-th row (e.g., Figure 7ADoes an edge exist between vertices c1 or c'1 in the matrix? For example, submatrix structure 712 indicates (1) there is no edge between v1 and c1; (2) there is no edge between v'1 and c'1; (3) there is an edge between v1 and c'1; and (4) there is an edge between v'1 and c1.

[0097] Figure 7B , 7C Figures 720, 740, and 760 are illustrations of instance codes for concurrent decoding according to one or more embodiments. LDPC codes according to some embodiments allow concurrent decoding using two decoders, each processing a 1944-bit block simultaneously. Figure 7B The original diagram 720 shows the edges indicating the first set of vertices (e.g., {v1, v'1, v2, v'2, v3, v'3, v4, v'4}) and the second set of vertices (e.g., {c1, c'1, c2, c'2, c3, c'3}). Figure 7C A matrix 740 (e.g., a parity check matrix) corresponding to the original model diagram 720 is shown. Systems according to some embodiments (e.g., communication system 108) may use... Figure 7A The mapping between the original model diagram and the corresponding submatrix structure shown in the figure is obtained from the original model diagram 720 to obtain matrix 740.

[0098] refer to Figure 7D Figure 760 illustrates an example of concurrent decoding via decoder 1 (761) and decoder 2 (762), enabling the two decoders to concurrently execute two 1944-block runs (as two layers). In some embodiments, the two decoders may be implemented in a decoder of a communication system (e.g., decoder 160 of communication system 108). For example, the first block run may correspond to a first subgraph 770 of the protograph 720, indicating the edge between vertex set {v1, v2, v3, v4} and vertex set {c1, c2, c3}. The second block run may correspond to a second subgraph 780 of the protograph 720, indicating the edge between vertex set {v'1, v'2, v'3, v'4} and vertex set {c'1, c'2, c'3}. In some embodiments, the two decoders 761, 762 may execute cross-layer messages across the connection edges between the two subgraphs of the protograph 720 (e.g., connection edges in portion 763, connection edges in portion 764). The connecting edges in parts 763 and 764 correspond to the 2x2 cyclic matrices 741 and 742 of matrix 740, respectively (see...) Figure 7C). Here, a circulant matrix may refer to a square matrix in which all rows consist of the same elements, and each row is rotated one element to the right relative to the previous row. Due to (or using) submatrix structures (e.g., 2x2 circulant matrices 741 and 742), the system can perform such concurrent decoding. In some embodiments, the 2x2 embedding can be modified for performance without affecting concurrent decoding, as it is a fixed edge mapping between two decoding layers.

[0099] Figure 8 is a flowchart illustrating a process 800 for encoding data using LDPC codes according to an embodiment. In some embodiments, process 800 is executed by one or more processors (e.g., communication system 105, encoder 130, or processor 2010). In other embodiments, process 800 is executed by other entities. In some embodiments, process 800 includes more than Figure 8 more, fewer, or different steps than those shown in.

[0100] At step 802, one or more processors may determine a QC-LDPC code in which multiple codebooks (e.g., codebook 1) are embedded. In some embodiments, each codebook of the multiple codebooks may include multiple integers (e.g., P1,1, P1,2, P1,3, ..., P1,ń; P2,1, P2,2, P2,3, ..., P2,ń; ..., P1,1, P1,2, P1,3, ..., ) as shown in Equation 7, and the number of the plurality of integers is equal to the number of elements of the parity check matrix divided by z, where z is an integer representing the lifting size of the QC-LDPC code (e.g., Z=162). See Equation 5 and Equation 6.

[0101] In some embodiments, each codebook (e.g., codebook 1) of the plurality of codebooks may represent an exponent matrix (e.g., matrix 300) of a parity check matrix (e.g., matrix 500). Each element of the exponent matrix may correspond to a cyclic shift value of an identity matrix. The size of the identity matrix may be z x z, and the cyclic shift value d may be an integer such that -1≤d<z, where Z is an integer representing the lifting size of the QC-LDPC code. The cyclic shift value d may represent a shifted identity matrix obtained by right-shifting the identity matrix by d (when z=7, see Figure 4 ). A cyclic shift value of -1 may represent a zero matrix of the identity matrix (see Figure 4 matrix 409 in).

[0102] In some implementations, the block size can be 3888 bits and the code rate can be 3 / 4. Multiple codebooks can contain a codebook (codebook 1), which includes [96 59 56 78 18 122-1-1-1 126 90 161-1-1-1 74 65 45 2 0-1-1-1-18 9885 97 22 61-1-1-1 98 35 82 74 31-1 108-1-1-1 0 0-1-1-1 71 153 156 102 7470 42-1 35128-1-1-1 118 14-1-1 65-1-1 0 0-1-1 18 131 88 18 109 113 146 69 84-1-1-1 71-1-1-1 92 79 0-1-1 0 0-1 7 124 15 161 137 53-1 161 110-1 72-1 53-118-1 145-1-1-1-1-10 0 53 151 66 42 138 118 6 77-1-1-1 70-1 125 72 53-1-1 2-1-1-1-1 0).

[0103] At step 804, one or more processors may select a codebook from a plurality of codebooks based on the code block size (e.g., n = 3888) and the code rate (e.g., R = 3 / 4).

[0104] At step 806, one or more processors may generate a parity check matrix (e.g., parity check matrix 500) based on a codebook (e.g., codebook 1). In some embodiments, when generating the parity check matrix based on the selected codebook, one or more processors may generate an exponent matrix (e.g., matrix 300) based on the selected codebook. For each element of the exponent matrix, one or more processors may generate a shifted identity matrix (e.g., matrices 410, 411, 412, 413, 414, 415, 416) of the identity matrix based on the value of each element of the exponent matrix (e.g., d = 0, 1, 2, 3, 4, 5, 6). One or more processors may generate a parity check matrix such that the parity check matrix contains the generated shifted identity matrix as an element corresponding to each element of the exponent matrix (see Equation 8).

[0105] At step 808, one or more processors may encode the data using the generated parity check matrix (e.g., using Equations 10, 11, 12 and 13).

[0106] At step 810, one or more processors may transmit encoded data to another device (e.g., communication system 108) via a transmitter of the device (e.g., transmitter circuitry 120 of communication system 105).

[0107] In one method, an apparatus may include a transmitter (e.g., transmitter circuitry 120 of communication system 105) and one or more processors (e.g., encoder 130 or processor 2010 of communication system 105). The one or more processors may be configured to identify (e.g., identify / select from a codebook) a first binary parity check matrix (e.g., parity check matrix H) for QC-LDPC codes based on a 3 / 4 code rate and a 3888-bit code block size. The first binary parity check matrix may correspond to a first exponential matrix (e.g., exponential matrix P = E(H)) having 144 values. The one or more processors may be configured to encode data using the first binary parity check matrix (e.g., using Equations 10, 11, 12, and 13). The one or more processors may be configured to transmit the encoded data. For example, a first device (e.g., communication system 105) may transmit the encoded data to a second device (e.g., communication system 108).

[0108] In some embodiments, one or more processors may be further configured to generate the first exponential matrix by selecting at least 142 values ​​from a second exponential matrix having the same dimensions as the first exponential matrix (e.g., 6x24; 6 rows and 24 columns). In some embodiments, the first exponential matrix may be generated by one or more processors of the first device (e.g., encoder 130 of communication system 105). In some embodiments, the first exponential matrix may be generated by another device (e.g., a device other than communication system 105) and transmitted to the first device.

[0109] One or more processors may be further configured to shift (or perturb) one or two values ​​of the first exponential matrix from one or more corresponding positive values ​​of the second exponential matrix by -1 or +1. The one or more corresponding positive values ​​of the second exponential matrix may not be selected as at least 94 values. In some implementations, the second exponent matrix may contain the following set of values: [96 59 56 7818122-1-1-1 126 90 161-1-1-1 74 65 45 2 0-1-1-1-1 8 98 85 97 22 61-1-1-1 98 358274 31-1 108-1-1-1 0 0-1-1-1 71 153 156 102 74 70 42-1 35 128-1-1-1 118 14-1-1 65-1-1 0 0-1-1 18 131 88 18 109 113 146 69 84-1-1-1 71-1-1-1 92] 79 0-1-10 0-1 7 12415 161 137 53-1 161 110-1 72-1 53-1 18-1 145-1-1-1-1-1 0 0 53 15166 42 138 118 677-1-1-1 70-1 125 72 53-1-1 2-1-1-1-1 0]. The first exponential matrix (e.g., the permutation matrix P) can be generated by perturbing one or both values ​​from the second exponential matrix. For example, based on the second exponential matrix, the first matrix can be generated as [95 59 55 78 18 122-1-1-1 126 90 161-1-1-1 74 65 45 2 0-1-1-1-1 8 98 85 9722 61-1-1-1 98 35 82 74 31-1 108-1-1-1 0 0-1-1-1 71 153 156102 74 70 42-1 35 128-1-1-1 118 14-1-1 65-1-1 0 0-1-1 18 131 88 18 109 113146 69 84-1-1-1 71-1-1-1 9279 0-1-1 0 0-1 7 124 15 161 137 53-1 161 110-1 72-1 53-1 18-1 145-1-1-1-1-1 0 0 53151 66 42 138 118 6 77-1-1-1 70-1 125 72 53-1-1 2-1-1-1-1 0], where the first value 95 and the third value 55 are shifted from 96 and 56 respectively.

[0110] In some implementations, a first exponent matrix (e.g., P) can be used to generate a first binary parity matrix (e.g., H matrix). For example, the first binary parity matrix (e.g., H matrix) can be generated by expanding the exponent matrix P such that each element of the exponent matrix P (as a shift value d) is replaced by a matrix (e.g., Z x Z matrix; Z = 162) shifted by the shift value from the identity matrix (e.g., Z x Z identity matrix; Z = 162).

[0111] In some implementations, one or more processors may be further configured to identify a second binary parity matrix in which one or more columns of the first binary parity matrix are permuted. The second binary parity matrix may have the same dimensions as the first binary parity matrix. For example, the second binary parity matrix can be generated by permuting the first and second columns of the first binary parity matrix. The second binary parity matrix may have the same dimensions as the first binary parity matrix (e.g., m x n; n = 3888; m = n(1-3 / 4) = 972). In some implementations, one or more processors may be further configured to encode data using the second binary parity matrix.

[0112] In some implementations, one or more processors may be further configured to identify a third binary parity matrix corresponding to a second exponential matrix in which one or more columns of the first exponential matrix are permuted. The second exponential matrix may have the same dimensions as the first exponential matrix (e.g., 6x24; 6 rows and 24 columns). For example, the second exponential matrix may be generated by permuting the first and second columns of the first exponential matrix. One or more processors may be configured to encode data using the third binary parity matrix.

[0113] In some implementations, one or more processors may be further configured to generate the first binary parity matrix (e.g., matrix H) using (1) a matrix product of the first binary parity matrix and the first exponential matrix (e.g., H x P), or (2) a matrix product of the first exponential matrix and the first binary parity matrix (e.g., P x H). For example, the H matrix can be generated by multiplying the matrix product H x P (right) by the inverse of the first exponential matrix (e.g., P... -1 ) to generate.

[0114] In one method, an apparatus (e.g., communication system 108) may include a receiver (e.g., receiver circuitry 140) configured to receive encoded data and one or more processors (e.g., processor 2010). The one or more processors may be configured to identify (e.g., identify / select from a codebook) a first binary parity matrix (e.g., parity matrix H) for QC-LDPC codes based on a 3 / 4 code rate and a 3888-bit code block size. The first binary parity matrix may correspond to a first exponential matrix (e.g., exponential matrix P = E(H)) having 144 values. In some embodiments, a second apparatus may identify the first binary parity matrix before receiving the encoded data. In some embodiments, in response to or after receiving the encoded data, one or more processors of the second apparatus may identify (e.g., identify / select from a codebook) the first binary parity matrix. The one or more processors may be configured to decode the received encoded data using the first binary parity matrix. For example, information bits s can be obtained by decoding encoded data (e.g., codeword c) using Equations 1 and 10 to 13.

[0115] In some implementations, the first exponent matrix may contain the following set of values: [96 59 56 78 18 122-1-1-1126 90 161-1-1-1 74 65 45 2 0-1-1-1-1 8 98 85 97 22 61-1-1-1 98 35 82 7431-1 108-1-1-1 0 0-1-1-1 71 153 156 102 74 70 42-1 35 128-1-1-1 118 14-1-165-1-1 0 0-1-1 18131 88 18 109 113 146 69 84-1-1-1 71-1-1-1 92 79 0-1-1 0 0-17 124 15 161 137 53-1161 110-1 72-1 53-1 18-1 145-1-1-1-1-1 0 0 53 151 66 42138 118 6 77-1-1-1 70-1125 72 53-1-1 2-1-1-1-1 0).

[0116] In some implementations, the first exponential matrix may contain at least 94 values ​​selected from a second exponential matrix having the same dimensions as the first exponential matrix (e.g., 6x24; 6 rows and 24 columns). The first exponential matrix may contain one or two values ​​from one or more corresponding positive values ​​of the second exponential matrix shifted (or perturbed) by -1 or +1. One or more corresponding positive values ​​of the second exponential matrix may not be selected as at least 94 values. In some implementations, the second exponent matrix may contain the following set of values: [96 59 56 78 18 122-1-1-1 126 90 161-1-1-1 74 65 45 2 0-1-1-1-18 98 8597 22 61-1-1-1 98 35 82 74 31-1 108-1-1-1 0 0-1-1-1 71 153 156 102 74 70 42-135 128-1-1-1 118 14-1-1 65-1-1 0 0-1-1 18 131 88 18 109 113 146 69 84-1-1-171-1-1-1 92 79 0-1-1 0 0-1 7 124 15 161 137 53-1 161 110-1 72-1 53-1 18-1145-1-1-1

[0117] -1-1 0 0 53 151 66 42 138 118 6 77-1-1-1 70-1 125 72 53-1-1 2-1-1-1-10]. The first exponential matrix (e.g., the permutation matrix P) may contain one or two values ​​perturbed from the second exponential matrix. For example, the first matrix may contain the following set of values: [95 59 55 78 18 122-1-1-1 126 90 161-1-1-1 74 65 45 20-1-1-1-18 98 85 97 22 61-1-1-1 98 35 82 74 31-1 108-1-1-1 0 0-1-1-1 71 153 156 102 74 70 42-1 35 128-1-1-1 118 14-1-1 65-1-1 0 0-1-1 18 131 88 18 109 113 146 69 84-1-1-1 71-1-1-1 92 79 0-1-1 0 0-1 7 124 15 161 137 53-1 161 110-1 72-1 53-1 18-1 145-1-1-1

[0118] -1-1 0 0 53 151 66 42 138 118 6 77-1-1-1 70-1 125 72 53-1-1 2-1-1-1-10], where the first value 95 and the third value 55 are shifted from 96 and 56 respectively.

[0119] In some embodiments, one or more processors may be configured to identify a second binary parity matrix in which one or more columns of a first binary parity matrix are permuted. The second binary parity matrix may have the same dimensions as the first binary parity matrix. For example, the second binary parity matrix may correspond to a matrix in which the first and second columns of the first binary parity matrix are permuted. The second binary parity matrix may have the same dimensions as the first binary parity matrix (e.g., m x n; n = 3888; m = n(1-3 / 4) = 92). In some embodiments, one or more processors may be configured to decode received encoded data using the second binary parity matrix (e.g., using Equations 1 and 10 to 13).

[0120] In certain scenarios, a parity check matrix H can be created / calculated / computed / generated / obtained through a hierarchical lifting process. This process may involve generating smaller matrices by applying cyclic shifts of varying sizes (e.g., Z / 2, Z / 4, etc.). These smaller matrices can then be selectively grouped together to form an equivalent matrix H.

[0121] Figure 9 This is a flowchart illustrating a process 900 for encoding and / or decoding data using LDPC codes according to an embodiment. In some embodiments, process 900 is executed by one or more processors (e.g., encoder 130 or processor 2010) of a first device (e.g., communication system 105), or by one or more processors (e.g., decoder 160 or processor 2010) of a second device (e.g., communication system 108). In other embodiments, process 900 is executed by other entities. In some embodiments, process 900 includes more than Figure 9 The more, fewer, or different steps shown in the document.

[0122] At step 902, one or more processors of the first device may identify (e.g., identify / select from a codebook) a first binary parity check matrix (e.g., parity check matrix H) for the quasi-cyclic low-density parity check (QC-LDPC) code based on a 3 / 4 code rate and a 3888-bit code block size. The first binary parity check matrix may correspond to a first exponential matrix (e.g., exponential matrix P = E(H)) having 144 values.

[0123] In some implementations, the first exponential matrix can be generated by selecting at least 94 values ​​from a second exponential matrix having the same dimensions as the first exponential matrix (e.g., 6x24; 6 rows and 24 columns). In some embodiments, the first exponential matrix may be generated by one or more processors of the first device (e.g., encoder 130 of communication system 105). In some embodiments, the first exponential matrix may be generated by another device (e.g., a device other than communication system 105) and transmitted to the first device.

[0124] In some implementations, one or two values ​​of the first exponential matrix may be shifted (or perturbed) by -1 or +1 from one or more corresponding positive values ​​of the second exponential matrix. The one or more corresponding positive values ​​of the second exponential matrix may not be selected as at least 142 values. In some implementations, the second exponent matrix may contain the following set of values: [96 59 56 78 18 122-1-1-1 126 90 161-1-1-1 74 65 45 2 0-1-1-1-1 8 98 85 97 22 61-1-1-1 98 35 82 7431-1108-1-1-1 0 0-1-1-1 71 153 156 102 74 70 42-1 35 128-1-1-1 118 14-1-1 65-1-1 0 0-1-1 18 131 88 18 109 113 146 69 84-1-1-1 71-1-1-1 92 79 0-1-1 0 0-1 7124 15 161137 53-1 161 110-1 72-1 53-1 18-1 145-1-1-1-1-1 0 0 53 151 66 42138 118 6 77-1-1-1 70-1 125 72 53-1-1 2-1-1-1-1 0]. The first exponential matrix (e.g., the permutation matrix P) can be generated by perturbing one or both values ​​from the second exponential matrix. For example, based on the second exponential matrix, the first matrix can be generated as [95 59 55 78 18 122-1-1-1 126 90 161-1-1-1 74 65 45 2 0-1-1-1-1 898 85 97 22 61-1-1-1 98 35 82 74 31-1 108-1-1-1 0 0-1-1-1 71 153 156 102 7470 42-1 35 128-1-1-1118 14-1-1 65-1-1 0 0-1-1 18 131 88 18 109 113 146 69 84-1-1-1 71-1-1-1 92 79 0-1-1 0 0-1 7 124 15 161 137 53-1 161 110-1 72-1 53-118-1 145-1-1-1-1-1 0 0 53 151 6642 138 118 6 77-1-1-1 70-1 125 72 53-1-1 2-1-1-1-1 0], where the first value 95 and the third value 55 are shifted from 96 and 56 respectively.

[0125] In some implementations, a first exponent matrix (e.g., P) can be used to generate a first binary parity matrix (e.g., H matrix). For example, the first binary parity matrix (e.g., H matrix) can be generated by expanding the exponent matrix P such that each element of the exponent matrix P (as a shift value d) is replaced by a matrix (e.g., Z x Z matrix; Z = 162) shifted by the shift value from the identity matrix (e.g., Z x Z identity matrix; Z = 162).

[0126] In some implementations, the first binary parity matrix (e.g., matrix H) can be generated using (1) the matrix product of the first binary parity matrix and the first exponential matrix (e.g., H x P), or (2) the matrix product of the first exponential matrix and the first binary parity matrix. In some embodiments, the first binary parity matrix can be generated by one or more processors of the first device (e.g., P x H). For example, the H matrix can be generated by multiplying the matrix product H x P (right) by the inverse of the first exponential matrix (e.g., P...). -1 ) to generate.

[0127] At step 904, one or more processors of the first device may encode data using a first binary parity matrix (e.g., using Equations 10, 11, 12, and 13). In some embodiments, a second binary parity matrix may be identified in which one or more columns of the first binary parity matrix are permuted. For example, the second binary parity matrix may be generated by permuting the first and second columns of the first binary parity matrix. The second binary parity matrix may have the same dimensions as the first binary parity matrix (e.g., m x n; n = 3888; m = n(1 - 3 / 4) = 912). In some embodiments, one or more processors of the first device may encode data using the second binary parity matrix.

[0128] In some implementations, a third binary parity matrix can be identified corresponding to a second exponential matrix in which one or more columns of the first exponential matrix are permuted. The second exponential matrix may have the same dimensions as the first exponential matrix (e.g., 6x24; 6 rows and 24 columns). For example, the second exponential matrix can be generated by permuting the first and second columns of the first exponential matrix. In some implementations, one or more processors of the first device may use the third binary parity matrix to encode data.

[0129] At step 906, one or more processors of the first device may transmit encoded data. For example, the first device (e.g., communication system 105) may transmit encoded data to the second device (e.g., communication system 108).

[0130] At step 908, one or more processors of the second device (e.g., decoder 160 of communication system 108) may identify the first binary parity check matrix. For example, one or more processors of the second device may identify (e.g., identify / select from codebook) the first binary parity check matrix (e.g., parity check matrix H) for the QC-LDPC code based on a 3 / 4 code rate and a 3888-bit code block size. The first binary parity check matrix may correspond to a first exponential matrix (e.g., exponential matrix P = E(H)) having 144 values.

[0131] At step 910, one or more processors of the second device may receive encoded data from the first device. In some embodiments, prior to receiving the encoded data in step 910, one or more processors of the second device may identify a first binary parity matrix in step 908. In some embodiments, in response to receiving the encoded data or after receiving the encoded data, one or more processors of the second device may identify (e.g., identify / select from a codebook) the first binary parity matrix.

[0132] In some implementations, the first exponential matrix may contain at least 142 values ​​selected from a second exponential matrix having the same dimensions as the first exponential matrix (e.g., 6x24; 6 rows and 24 columns). The first exponential matrix may contain one or two values ​​from one or more corresponding positive values ​​of the second exponential matrix shifted (or perturbed) by -1 or +1. One or more corresponding positive values ​​of the second exponential matrix may not be selected as at least 142 values. In some implementations, the second exponent matrix may contain the following set of values: [96 59 56 78 18 122 -1 -1 -1 126 90 161 -1 -1 -1 74 65 45 2 0 -1 -1 -1 -1 8 98 85 97 22 61 -1 -1 -1 98 35 82 74 31 -1 108 -1 -1 -1 0 0 -1 -1 -1 71153 156 102 74 70 42 -1 35 128 -1 -1 -1 118 14 -1 -1 65 -1 -1 0 0 -1 -1 18131 88 18 109 113 146 69 84 -1 -1 -1 71 -1 -1 -1 92 79 0 -1 -1 0 0-1 7 124 15161 137 53 -1 161 110 -1 72 -1 53 -1 18 -1 145 -1 -1 -1 -1 -1 0 0 53 151 6642 138 118 6 77 -1 -1 -1 70 -1 125 72 53 -1 -1 2 -1 -1 -1 -1 0]. The first exponential matrix (e.g., the permutation matrix P) may contain one or both values ​​perturbed from the second exponential matrix.For example, the first matrix may contain the following set of values: [95 59 55 78 18 122 -1 -1 -1 126 90 161 -1 -1 -1 74 65 45 2 0 -1 -1-1 -1 8 98 85 97 22 61 -1 -1 -1 98 35 82 74 31 -1 108 -1 -1 -1 0 0 -1 -1 -1 71 153 156 102 74 70 42 -1 35 128 -1 -1 -1 118 14 -1 -1 65 -1 -1 0 0 -1 -1 18131 88 18 109 113 146 69 84 -1 -1 -1 71 -1 -1 -1 92 79 0 -1 -1 0 0-1 7 124 15161 137 53 -1 161 110 -1 72 -1 53 -1 18 -1 145 -1 -1 -1 -1 -1 0 0 53 151 6642 138 118 6 77 -1 -1 -1 70 -1 125 72 53 -1 -1 2 -1 -1 -1 -1 0], where the first value 95 and the third value 55 are shifted from 96 and 56 respectively.

[0133] At step 912, one or more processors of the second device may use the first binary parity check matrix to decode the encoded data. For example, the encoded data (e.g., codeword c) may be decoded using Equations 1 and 10 to 13 to obtain information bits s.

[0134] In some implementations, one or more processors may be configured to identify a second binary parity matrix in which one or more columns of a first binary parity matrix are permuted. The second binary parity matrix may have the same dimensions as the first binary parity matrix. For example, the second binary parity matrix may correspond to a matrix in which the first and second columns of the first binary parity matrix are permuted. The second binary parity matrix may have the same dimensions as the first binary parity matrix (e.g., m x n; n = 3888; m = n(1-3 / 4) = 912). In some implementations, one or more processors may be configured to use the second binary parity matrix (e.g., using Equations 1 and 10 to 13) to decode received encoded data.

[0135] Figure 10A , 10BFigures 10C, 10D, 10E, and 10F are diagrams depicting example simulation results of QC-LDPC codes at a code rate of 3 / 4 according to one or more embodiments. The results were obtained using the following simulation settings. The packet error rate (PER) values ​​are averaged over 5000 to 10000 independent channel implementations, with a gain reference of PER = 1%. One channel example spans four orthogonal frequency division multiplexing (OFDM) symbols. The channel model includes (1) “DNLOS” indicating a non-line-of-sight 802.11 MIMO channel model type D, which; (2) “BLOS” indicating a line-of-sight 802.11 channel model type B; and (3) AWGN indicating a flat channel with additional white Gaussian noise. No radio frequency (RF) impairments are included. The payload size remains the same; and therefore, for a block length of 1944q, the number of codewords can be inversely proportional to q. Decoding is performed using a belief propagation (BP)-based decoder (e.g., using hierarchical scheduling with a maximum of 20 iterations). The MIMO-2x2 channel uses a near-optimal maximum likelihood detector with reduced complexity. The SISO (Single-Input Single-Output) 1x1 channel uses a linear detector.

[0136] Figure 10A , 10C 10E is a graph showing PER for different SNRs; Figure 10B , 10D 10F and 10F represent the spectral efficiency (SpecEff) for different SNRs. PER is the number of erroneous packets divided by the total number of received packets. SpecEff is the information rate (or bit rate or effective data rate) on a given bandwidth in a communication system (in bits per second / Hz). SpecEff can be a normalized transmit rate such that the actual transmit rate (bits per second) = SpecEff x bandwidth (Hz).

[0137] Figure 10A and 10B Simulation results are presented for an AWGN (frequency-flat) channel. (Reference) Figure 10A Lines 1001, 1003, 1005, 1007, 1009, and 1011 correspond to the simulation results (PER vs. SNR) of LDPC codes with a block length of 3888 using modulations of 4-QAM, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, respectively; and lines 1002, 1004, 1006, 1008, 1010, and 1012 correspond to the simulation results of LDPC codes with a block length of 1944 using modulations of 4-QAM, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, respectively. (Reference) Figure 10BLines 1021, 1023, 1025, 1027, 1029, and 1031 correspond to the simulation results (SpecEff vs. SNR) of LDPC codes with a block length of 3888 using modulations of 4-QAM, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, respectively; and lines 1022, 1024, 1026, 1028, 1030, and 1032 correspond to the simulation results of LDPC codes with a block length of 1944 using modulations of 4-QAM, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, respectively.

[0138] Figure 10C and 10D Simulation results are shown for a 2x2 MIMO channel using D-NLOS signal propagation. (Reference) Figure 10C Lines 1041, 1043, 1045, 1047, 1049, and 1051 correspond to the simulation results (PER vs. SNR) of LDPC codes with a block length of 3888 using modulations of 4-QAM, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, respectively; and lines 1042, 1044, 1046, 1048, 1050, and 1052 correspond to the simulation results of LDPC codes with a block length of 1944 using modulations of 4-QAM, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, respectively. (Reference) Figure 10D Lines 1061, 1063, 1065, 1067, 1069, and 1071 correspond to the simulation results (SpecEff vs. SNR) of LDPC codes with a block length of 3888 using modulations of 4-QAM, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, respectively; and lines 1062, 1064, 1066, 1068, 1070, and 1072 correspond to the simulation results of LDPC codes with a block length of 1944 using modulations of 4-QAM, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, respectively.

[0139] Figure 10E and 10F Simulation results are shown for a 2x2 MIMO channel using BLOS signal propagation. (Reference) Figure 10ELines 1081, 1083, 1085, 1087, 1089, and 1091 correspond to the simulation results (PER vs. SNR) of LDPC codes with a block length of 3888 using modulations of 4-QAM, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, respectively; and lines 1082, 1084, 1086, 1088, 1090, and 1092 correspond to the simulation results of LDPC codes with a block length of 1944 using modulations of 4-QAM, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, respectively. (Reference) Figure 10F Lines 1101, 1103, 1105, 1107, 1109, and 1111 correspond to the simulation results (SpecEff vs. SNR) of LDPC codes with a block length of 3888 using modulations of 4-QAM, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, respectively; and lines 1102, 1104, 1106, 1108, 1110, and 1112 correspond to the simulation results of LDPC codes with a block length of 1944 using modulations of 4-QAM, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, respectively.

[0140] A reference to "or" can be interpreted as inclusive, such that any item described using "or" can refer to a single, more than one, or any of all the described items. A reference to at least one of a connected list of items can be interpreted as inclusive "or," indicating a single, more than one, or any of all the described items. For example, a reference to "at least one of 'A' and 'B'" includes only 'A', only 'B', and 'A' and 'B'. Such references used in conjunction with "include" or other open terms can include additional items.

[0141] The term "coupling" and its variations encompass two components joined directly or indirectly to each other. The term "electrical coupling" and its variations encompass two components joined directly or indirectly to each other via a conductive material (e.g., a metal or copper trace). Such coupling (for both "coupling" and "electrical coupling") can be static (e.g., permanent or fixed) or movable (e.g., removable or releasable). Such coupling (for both "coupling" and "electrical coupling") can be achieved by directly coupling two components to each other, wherein the two components are coupled to each other using a separate intervening component and any additional intermediate component coupled to each other, or wherein the two components are coupled to each other using an intervening component integrally formed with one of the two components as a single integral body. If "coupling" or its variations are modified by an additional term (e.g., direct coupling), then the general definition of "coupling" provided above is modified by the colloquial meaning of the additional term (e.g., "direct coupling" means two components joined without any separate intervening component), resulting in a narrower definition than the general definition of "coupling" provided above. Such coupling can be mechanical, electrical, or fluid.

[0142] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0143] It should be noted that, for the purpose of identifying or distinguishing one from another or others, certain paragraphs of this disclosure may refer to terms associated with stripes, data blocks, data lines, and devices, such as “first” and “second”. These terms are not intended to relate entities (e.g., first device and second device) solely in time or according to sequence, although in some cases these entities may include such relationships. These terms also do not limit the number of possible entities that can operate in the system or environment. It should be understood that the system described above may provide any or more of those components, and these components may be located on a standalone machine, or, in some embodiments, on multiple machines in a distributed system. Furthermore, the above-described system and methods may be provided as one or more computer-readable programs or executable instructions embodied on or within one or more articles of manufacture (e.g., floppy disk, hard disk, CD-ROM, flash memory card, PROM, RAM, ROM, or magnetic tape). The program may be implemented in any programming language (e.g., LISP, PERL, C, C++, C#) or in any bytecode language (e.g., JAVA). Software programs or executable instructions may be stored as object code on or within one or more artifacts.

[0144] While the foregoing written description of the methods and systems enables those skilled in the art to make and use embodiments thereof, those skilled in the art will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiments, methods, and examples herein. Therefore, the methods and systems should not be limited to the embodiments, methods, and examples described above, but should be limited to all embodiments and methods within the scope and spirit of this disclosure.

Claims

1. An encoding method, comprising: The baseband circuit system of the first device identifies the first binary parity check matrix for the quasi-cyclic low-density parity check (QC-LDPC) code based on a code rate of 3 / 4 and a code block size of 3888 bits. The first binary parity check matrix corresponds to a first exponential matrix with 144 values. The encoder of the baseband circuit system of the first device encodes the data using the first binary parity check matrix; The encoded data is transmitted by the transmitter of the first device over a wireless channel; and The baseband circuit system of the first device generates the first exponential matrix by selecting at least 142 values ​​from a second exponential matrix having the same dimensions as the first exponential matrix.

2. The encoding method according to claim 1, further comprising: Shift one or two values ​​of the first exponent matrix from one or more corresponding positive values ​​of the second exponent matrix by -1 or +1. The one or more corresponding positive values ​​of the second exponential matrix are not selected as the at least 142 values.

3. The encoding method according to claim 1, wherein the second exponential matrix comprises the following set of values: [96 59 56 78 18 122 -1 -1 -1 126 90 161 -1 -1 -1 74 65 45 2 0 -1 -1 -1 -18 98 85 97 22 61 -1 -1 -1 98 35 82 74 31 -1 108 -1 -1 -1 0 0 -1 -1 -1 71 153156 102 74 70 42 -1 35 128 -1 -1 -1 118 14 -1 -1 65 -1 -1 0 0 -1 -1 18 131 8818 109 113 146 69 84 -1 -1 -1 71 -1 -1 -1 92 79 0 -1 -1 0 0 -1 7 124 15 161137 53 -1 161 110 -1 72 -1 53 -1 18 -1 145 -1 -1 -1 -1 -1 0 0 53 151 66 42138 118 6 77 -1 -1 -1 70 -1 125 72 53 -1 -1 2 -1 -1 -1 -1 0 ]， The values ​​are arranged in a row-matrix of 6 rows × 24 columns.

4. The encoding method according to claim 1, further comprising: Identify a second binary parity matrix in which one or more columns of the first binary parity matrix are permuted, the second binary parity matrix having the same dimensions as the first binary parity matrix; and The encoder of the baseband circuit system uses the second binary parity check matrix to encode further data.

5. The encoding method according to claim 1, further comprising: Identify a third binary parity check matrix corresponding to a second exponential matrix in which one or more columns of the first exponential matrix are permuted, wherein the second exponential matrix has the same dimension as the first exponential matrix; and The encoder of the baseband circuit system encodes further data using the third binary parity check matrix.

6. The encoding method according to claim 1, further comprising: The first binary parity check matrix is ​​generated by (1) the matrix product of the first binary parity check matrix and the first exponent matrix, or (2) the matrix product of the first exponent matrix and the first binary parity check matrix.

7. The encoding method according to claim 1, further comprising: The first binary parity check matrix is ​​identified by the second device; The encoded data is received from the first device by the second device; and The second device uses the first binary parity check matrix to decode the encoded data.

8. A communication device comprising: Transmitter and baseband circuitry system, wherein the baseband circuitry system is configured to: The first binary parity check matrix for quasi-cyclic low-density parity check (QC-LDPC) codes is identified based on a 3 / 4 code rate and a 3888-bit code block size. The first binary parity check matrix corresponds to a first exponential matrix with 144 values. The encoder using the baseband circuit system encodes the data using the first binary parity check matrix; and The encoded data is transmitted over a wireless channel using a transmitter. The first exponent matrix includes the following set of values: [96 59 56 78 18 122 -1 -1 -1 126 90 161 -1 -1 -1 74 65 45 2 0 -1 -1 -1 -18 98 85 97 22 61 -1 -1 -1 98 35 82 74 31 -1 108 -1 -1 -1 0 0 -1 -1 -1 71 153156 102 74 70 42 -1 35 128 -1 -1 -1 118 14 -1 -1 65 -1 -1 0 0 -1 -1 18 131 8818 109 113 146 69 84 -1 -1 -1 71 -1 -1 -1 92 79 0 -1 -1 0 0 -1 7 124 15 161137 53 -1 161 110 -1 72 -1 53 -1 18 -1 145 -1 -1 -1 -1 -1 0 0 53 151 66 42138 118 6 77 -1 -1 -1 70 -1 125 72 53 -1 -1 2 -1 -1 -1 -1 0 ]， The values ​​are arranged in a row-matrix of 6 rows × 24 columns.

9. The communication device according to claim 8, wherein the baseband circuit system is further configured to: The first exponential matrix is ​​generated by selecting at least 142 values ​​from a second exponential matrix that has the same dimensions as the first exponential matrix.

10. The communication device of claim 9, wherein the baseband circuit system is further configured to: Shift one or two values ​​of the first exponent matrix from one or more corresponding positive values ​​of the second exponent matrix by -1 or +1. The one or more corresponding positive values ​​of the second exponential matrix are not selected as the at least 142 values.

11. The communication device of claim 8, wherein the baseband circuit system is further configured to: Identify a second binary parity matrix in which one or more columns of the first binary parity matrix are permuted, the second binary parity matrix having the same dimensions as the first binary parity matrix; and The encoder using the baseband circuit system encodes further data using the second binary parity check matrix.

12. The communication device of claim 8, wherein the baseband circuit system is further configured to: Identify a third binary parity check matrix corresponding to a second exponential matrix in which one or more columns of the first exponential matrix are permuted, wherein the second exponential matrix has the same dimension as the first exponential matrix; and The encoder using the baseband circuit system encodes further data using the third binary parity check matrix.

13. The communication device of claim 8, wherein the baseband circuit system is further configured to: The first binary parity check matrix is ​​generated by (1) the matrix product of the first binary parity check matrix and the first exponent matrix, or (2) the matrix product of the first exponent matrix and the first binary parity check matrix.

14. A communication device comprising: A receiver configured to receive encoded data over a wireless channel; and The baseband circuit system is configured to: The first binary parity check matrix for quasi-cyclic low-density parity check (QC-LDPC) codes is identified based on a 3 / 4 code rate and a 3888-bit code block size. The first binary parity check matrix corresponds to a first exponential matrix with 144 values. Identify a second binary parity matrix in which one or more columns of the first binary parity matrix are permuted, the second binary parity matrix having the same dimensions as the first binary parity matrix; and The decoder using the baseband circuit system decodes the received encoded data using the second binary parity check matrix.

15. The communication device of claim 14, wherein the first exponential matrix comprises at least 142 values ​​selected from a second exponential matrix having the same dimensions as the first exponential matrix.

16. The communication device of claim 15, wherein the first exponent matrix comprises one or two values ​​shifted by -1 or +1 from one or more corresponding positive values ​​of the second exponent matrix. The one or more corresponding positive values ​​of the second exponential matrix are not selected as the at least 142 values.

17. The communication device of claim 15, wherein the second exponential matrix comprises the following set of values: [96 59 56 78 18 122 -1 -1 -1 126 90 161 -1 -1 -1 74 65 45 2 0 -1 -1 -1 -18 98 85 97 22 61 -1 -1 -1 98 35 82 74 31 -1 108 -1 -1 -1 0 0 -1 -1 -1 71 153156 102 74 70 42 -1 35 128 -1 -1 -1 118 14 -1 -1 65 -1 -1 0 0 -1 -1 18 131 8818 109 113 146 69 84 -1 -1 -1 71 -1 -1 -1 92 79 0 -1 -1 0 0 -1 7 124 15 161137 53 -1 161 110 -1 72 -1 53 -1 18 -1 145 -1 -1 -1 -1 -1 0 0 53 151 66 42138 118 6 77 -1 -1 -1 70 -1 125 72 53 -1 -1 2 -1 -1 -1 -1 0 ]， The values ​​are arranged in a row-matrix of 6 rows × 24 columns.

Images