A back contact battery with a multi-layer gradient suede structure and its preparation method and application

Abstract

The present invention belongs to the technical field of back contact batteries, and specifically relates to a back contact battery with a multi-layer gradient velvet structure, a method for manufacturing the same, and an application thereof, wherein the second semiconductor opening region further comprises: a first platform region and a second platform region sequentially arranged from the edge to the non-transition region in the width direction, and a first bevel region between the first platform region and the second platform region, and a second bevel region between the second platform region and the non-transition region; wherein the first platform region is a polished surface, the second platform region is a pyramid velvet, and the heights of the first platform region, the second platform region, and the non-transition region gradually decrease, and the first platform region, the first bevel region, the second platform region, the second bevel region, and the non-transition region continuously form a multi-layer gradient velvet structure. The present invention can prevent the second semiconductor layer in the second semiconductor opening region from being well covered on its surface and side due to a large height difference, thereby reducing the carrier recombination rate at the boundary, thereby improving the open circuit voltage and battery conversion efficiency.

Description

Technical Field

[0001] The present invention belongs to the technical field of back contact batteries, and in particular relates to a back contact battery with a multi-layer gradient suede structure and a preparation method and application thereof. Background Art

[0002] At present, the use of post-texturing technology to prepare back-contact cells has obvious advantages. The post-texturing process generally includes: depositing the first semiconductor layer on the back of the silicon wafer, etching an opening to form a second semiconductor opening area, then performing texturing and cleaning, and then depositing the second semiconductor layer, then etching an opening in the second semiconductor layer to form a first semiconductor opening area, and then depositing a conductive film layer.

[0003] In the prior art, the velvet surface structure obtained after a velvet cleaning with a velvet liquid is as follows: Figure 1 As shown, it consists of a first platform area, an intermediate slope area, and a non-transition area. The first platform area is a polished surface, and the non-transition area is a pyramid velvet structure. The velvet-making liquid is an aqueous solution containing alkali and velvet-making additives.

[0004] However, in the above-mentioned post-texturing structure of the back-contact battery, the height difference between the second semiconductor opening area and the non-opening area (i.e., the first semiconductor layer) is large, resulting in poor quality of the film layer (especially the second semiconductor layer) at the boundary during the coating process, thereby affecting the battery conversion efficiency.

[0005] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or known technology. Summary of the invention

[0006] The purpose of the present invention is to overcome the defect of the existing back-contact battery that the height difference between the second semiconductor opening area and the non-opening area on the back side is large, resulting in poor film quality at the boundary, thus affecting the battery conversion efficiency. A back-contact battery with a multi-layer gradient suede structure and its preparation method and application are provided, which can avoid the second semiconductor layer in the second semiconductor opening area not being well coated on its surface and side due to the large height difference, reduce the carrier recombination rate at the boundary, thereby improving the open circuit voltage and battery conversion efficiency, and at the same time greatly save the material cost of subsequent conventional conductive film layers and printed screens, which is conducive to mass production.

[0007] In order to achieve the above-mentioned purpose, in a first aspect, the present invention provides a back contact battery with a multi-layer gradient suede structure, comprising a silicon wafer, first semiconductor layers arranged at intervals in the width direction of the back side of the silicon wafer, a second semiconductor opening area formed between two adjacent first semiconductor layers, the second semiconductor opening area comprising a non-transition area located in the middle, the surface of the non-transition area being a pyramid suede, the second semiconductor opening area further comprising: a first platform area and a second platform area arranged in sequence from the edge to the non-transition area in the width direction, and a first bevel area between the first platform area and the second platform area, and a second bevel area between the second platform area and the non-transition area; wherein the first platform area is a polished surface, the second platform area is a pyramid suede, and the heights of the first platform area, the second platform area and the non-transition area gradually decrease. The first platform area, the first bevel area, the second platform area, the second bevel area, and the non-transition area continuously form a multi-layer gradient suede structure; the width of the second platform area is 3-8μm, and the ratio of the width of the second platform area to the first platform area and the non-transition area is 1: (0.01-0.17): (50-270), and the distance T2 between the top of the pyramid suede of the second platform area and the surface of the silicon wafer area corresponding to the first semiconductor layer is 1-3μm; the back contact battery also includes a second semiconductor layer alternately arranged with the first semiconductor layer, and the second semiconductor layer is attached to the multi-layer gradient suede structure of the second semiconductor opening area, and its two ends extend outward to cover the part of the back side of the adjacent first semiconductor layer, and a first semiconductor opening area that does not cover the second semiconductor layer is opened on the back side of the first semiconductor layer.

[0008] In some preferred embodiments of the present invention, the distances from the polished surface of the first platform area and the top of the pyramid velvet surface in the non-transition area to the surface of the corresponding silicon wafer area of ​​the first semiconductor layer are respectively counted as T1 and T3, T1 is 70-300nm, and T3 satisfies: T2:T3=1:(1.7-10).

[0009] In some preferred embodiments of the present invention, T3 is 5-10 μm.

[0010] In some preferred embodiments of the present invention, the width of the first platform region is 0.1-0.5 μm, and the width of the non-transition region is 97%-99.9% of the total width W1 of the second semiconductor opening region.

[0011] In some preferred embodiments of the present invention, the total width W1 of the second semiconductor opening region is 400-800 μm.

[0012] In some preferred embodiments of the present invention, the pyramid velvet surface in the non-transition zone satisfies: the height of the pyramid is in the range of 1-2 μm, and the radial dimension of the pyramid is in the range of 1-3 μm; the pyramid velvet surface in the second platform zone satisfies: the height of the pyramid is in the range of 0.5-1 μm, and the radial dimension of the pyramid is in the range of 0.8-1.5 μm.

[0013] In some preferred embodiments of the present invention, the size of the pyramids corresponding to the non-transition region is larger than the size of the pyramids in the second platform region.

[0014] In some preferred embodiments of the present invention, the first bevel area includes a first ridge structure and a first pyramid tip located at the top of the first ridge structure, and the second bevel area includes a second ridge structure and a second pyramid tip located at the top of the second ridge structure, and the following conditions are satisfied: the distribution density of the first pyramid tip in the first bevel area as a percentage of area is 1%-10%, and the distribution density of the second pyramid tip in the second bevel area as a percentage of area is 1%-50%.

[0015] In some preferred embodiments of the present invention, the silicon wafer area corresponding to the first semiconductor opening area is a polishing area; the front side of the silicon wafer is a pyramid textured surface and satisfies: the height of the pyramid is in the range of 1-2 μm, and the radial dimension of the pyramid is in the range of 1-3 μm.

[0016] In some preferred embodiments of the present invention, the second semiconductor opening region is arranged at an interval with the first semiconductor opening region and the area between them is a spacing region; in the spacing region, a mask layer is arranged between the first semiconductor layer and the second semiconductor layer or no mask layer is arranged; the back contact battery also includes a front passivation layer and an anti-reflection layer formed on the front side of the silicon wafer, a metal electrode arranged on the back side, and a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer, an isolation groove is opened on the portion of the conductive film layer located in the spacing region, and the isolation groove at least spans the polishing area corresponding to the first semiconductor opening region and the first platform area and the second platform area of ​​the second semiconductor opening region and part of the non-transition area; the metal electrode is arranged on the outer surfaces of the corresponding conductive film layers in the second semiconductor opening region and the first semiconductor opening region.

[0017] Further preferably, the thickness of the conductive film layer is 40-60 nm.

[0018] In some preferred embodiments of the present invention, the first semiconductor layer includes a first passivation layer and a first doped silicon layer, the second semiconductor layer includes a second passivation layer and a second doped silicon layer, the first passivation layer and the second passivation layer are each independently a tunneling oxide layer or an intrinsic silicon layer, and the first doped silicon layer and the second doped silicon layer are each independently polycrystalline silicon, amorphous silicon or microcrystalline silicon.

[0019] In a second aspect, the present invention provides a post-texturing preparation method for a back contact battery, which is used to prepare the back contact battery with a multi-layer gradient velvet structure as described in the first aspect, and the post-texturing preparation method comprises the following steps:

[0020] S101, provide double-sided polished silicon wafers;

[0021] S102, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer;

[0022] S103, performing a first etching opening in a preset area of ​​the back surface obtained in S102, removing the mask layer and a corresponding portion of the first semiconductor layer, and forming a second semiconductor opening area arranged at intervals;

[0023] S104, then performing a first solution etching, so that the first semiconductor layer is etched below the edge of the mask layer to form a first platform area, and at the same time a first groove structure is formed in the second semiconductor opening area, the first groove structure includes a first transition slope and a non-transition middle area, and a first texturing is performed on the front side of the silicon wafer;

[0024] S105, then performing a second solution etching, and then selecting whether to remove the mask layer as needed; the second solution etching forms a second platform area on the first transition slope, and parts of the first transition slope located on both sides of the second platform area form a first slope area and a second slope area respectively, and the non-transition middle area forms a non-transition area, and a second texturing is performed on the front side of the silicon wafer to form a pyramid texture surface;

[0025] S106, depositing a second semiconductor layer on the back side;

[0026] S107 , performing a second etching opening on a portion of the second semiconductor layer on the back side to form a first semiconductor opening region spaced apart from the second semiconductor opening region.

[0027] In some preferred embodiments of the present invention, the first etching solution used in the first solution etching in S104 is an aqueous solution containing alkali and optional texturing additives, and the mass percentage of the alkali contained in it is 5%-10%. When the first etching solution contains the texturing additive, the mass percentage of the texturing additive is 0.1%-0.5%; the conditions of the first solution etching include: etching time is 1-5min, and etching temperature is 75℃-85℃.

[0028] In some preferred embodiments of the present invention, the second etching solution used in the second solution etching in S105 is an aqueous solution containing alkali and texturing additives, the mass percentage of alkali contained in it is 1%-3%, and the mass percentage of texturing additives contained in it is 0.5%-1%; the conditions of the second solution etching include: etching time is 8-12min, and etching temperature is 75℃-85℃.

[0029] In some preferred embodiments of the present invention, the post-texturing preparation method of the back contact battery further comprises:

[0030] S106 also includes forming a front passivation layer and an anti-reflection layer on the front side of the silicon wafer;

[0031] S108, depositing a conductive film layer on the back surface obtained in S107;

[0032] S109, performing a third etching opening on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove;

[0033] S110 , forming metal electrodes on the outer surfaces of the conductive film layers corresponding to the first semiconductor opening region and the second semiconductor opening region.

[0034] In a third aspect, the present invention provides a photovoltaic module, which includes the back contact cell with a multi-layer gradient velvet structure described in the first aspect, or a back contact cell prepared by the post-texturing preparation method of the back contact cell described in the second aspect.

[0035] Beneficial effects:

[0036] The present invention adopts the above technical scheme, especially in the second semiconductor opening area, the first platform area, the first slope area, the second platform area, the second slope area, and the non-transition area are set to continuously form a multi-layer gradient velvet structure, and the transition area from the first semiconductor to the second semiconductor is more gentle. Correspondingly, the area of ​​the transition area of ​​the second semiconductor opening area is also significantly increased. When the second semiconductor layer is set, due to the increase in the contact surface area of ​​the second semiconductor opening area, the passivation film layer can be better coated on its side, reducing the carrier recombination rate at the boundary, and can avoid the second semiconductor layer in the second semiconductor opening area cannot be well coated on its surface and side due to the large height difference, thereby improving the open circuit voltage and battery conversion efficiency, and at the same time greatly saving the material cost of subsequent conventional conductive film layers and printing screens, which is conducive to mass production. The single-layer gradient velvet structure obtained by the velvet cleaning of the conventional back contact battery has a transition area that is not as gentle as the multi-layer gradient velvet structure of the present invention, and the area of ​​the transition area of ​​the second semiconductor opening area is reduced by 1 / 3 or more than the multi-layer gradient velvet structure of the present invention, so its passivation effect is significantly worse than that of the back contact battery of the multi-layer gradient velvet structure of the present invention.

[0037] The present invention controls the width of the second platform area within a suitable range, and the ratio of the width of the second platform area to the first platform area and the non-transition area within a suitable ratio range, so as to avoid the failure of the subsequent coating layer to play a good slope buffering role due to its too small width and inappropriate width ratio. The present invention also cooperates to control the height distance of the second platform area within a suitable range, which is conducive to achieving the best film passivation effect in conjunction with the width of the second platform area. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 This is the SEM image of the post-texture structure of a conventional back-contact battery.

[0040] Figure 2 It is a SEM image of the post-texture structure of a back-contact battery with a multi-layer gradient texture structure at a first magnification according to a specific embodiment of the present invention.

[0041] Figure 3 This is a SEM image at a second magnification of a post-texture structure of a back-contact battery with a multi-layer gradient texture structure according to a specific embodiment of the present invention.

[0042] Figure 4 It is a schematic diagram of the longitudinal structure of forming a second semiconductor layer on the back side of a silicon wafer according to an embodiment of the present invention.

[0043] Description of Reference Numerals

[0044] 1. Silicon wafer, 2. Tunneling silicon oxide layer, 3. First doped N-type polycrystalline layer, 4. Intrinsic amorphous silicon layer, 5. Second doped P-type amorphous silicon layer; 21. First platform region, 22. Second platform region, 23. Non-transition region. DETAILED DESCRIPTION

[0045] In the present invention, unless otherwise specified, directional words such as "upper, lower, left, right" are generally understood in conjunction with the directions shown in the drawings and actual applications.

[0046] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0047] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0048] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they may be included or not included (or may be present or not).

[0049] In the present invention, the area close to the silicon wafer is referred to as the inside, and the area far from the silicon wafer is referred to as the outside.

[0050] In a first aspect, the present invention provides a back contact battery with a multi-layer gradient suede structure, comprising a silicon wafer, first semiconductor layers spaced apart in the width direction of the back side of the silicon wafer, a second semiconductor opening region formed between two adjacent first semiconductor layers, the second semiconductor opening region comprising a non-transition region located in the middle, the surface of the non-transition region being a pyramid suede, the second semiconductor opening region further comprising: a first platform region and a second platform region sequentially arranged from the edge to the non-transition region in the width direction, a first bevel region between the first platform region and the second platform region, and a second bevel region between the second platform region and the non-transition region; Among them, the first platform area is a polished surface, the second platform area is a pyramid velvet surface, and the heights of the first platform area, the second platform area, and the non-transition area gradually decrease, and the first platform area, the first bevel area, the second platform area, the second bevel area, and the non-transition area continuously form a multi-layer gradient velvet structure; and the width of the second platform area is 3-8μm, and the ratio of the width of the second platform area to the first platform area and the non-transition area is 1: (0.01-0.17): (50-270), and the distance T2 between the top of the pyramid velvet surface of the second platform area and the surface of the silicon wafer area corresponding to the first semiconductor layer is 1-3μm, preferably 2-3μm. The present invention controls the width of the second platform area within a certain range to avoid the subsequent coating layer not having a good slope buffering effect due to its too small width.

[0051] The width ratio of the second platform area to the first platform area and the non-transition area is 1: (0.01-0.17): (50-270), and specifically can be 1: 0.01: 50, 1: 0.05: 50, 1: 0.06: 50, 1: 0.07: 50, 1: 0.1: 50, 1: 0.15: 50, 1: 0.17: 50, 1: 0.01: 60, 1: 0.01: 70, 1: 0.05: 70, 1: 0.17: 50. : 0.05:80, 1: 0.08:50, 1: 0.08:80, 1: 0.17:80, 1: 0.17:100, 1: 0.17:150, 1: 0.17:200, 1: 0.17:250, 1: 0.17:270, etc. and the range between any two point values, preferably 1: 0.08-0.17:80-270, further preferably 1: 0.08-0.17:80-230.

[0052] It can be understood that the first platform area and the second platform area are symmetrically arranged on both sides of the width direction of the third non-transition area. Figure 4 As shown, there is a first slope region between the first platform region and the second platform region, and there is a second slope region between the second platform region and the non-transition region.

[0053] The back-contact battery also includes a second semiconductor layer alternately arranged with the first semiconductor layer, the second semiconductor layer is attached to the multi-layer gradient suede structure of the second semiconductor opening area, and its two ends extend outward to cover the part of the back side of the adjacent first semiconductor layer, and a first semiconductor opening area that does not cover the second semiconductor layer is opened on the back side of the first semiconductor layer.

[0054] In some preferred embodiments of the present invention, the distances from the polished surface of the first platform area and the top of the pyramid velvet surface of the non-transition area to the surface of the silicon wafer area corresponding to the first semiconductor layer are respectively counted as T1 and T3, T1 is 70-300nm, and T3 satisfies: T2: T3 = 1: (1.7-10), preferably 1: (1.7-3.5). By adopting this preferred solution, the slope gentleness from the surface of the silicon wafer area corresponding to the first semiconductor layer to the non-transition area can be reduced, achieving the best film coating effect, thereby being more conducive to improving the passivation quality of the film layer.

[0055] The present invention can further select a specific value within the above T2:T3 range. In some preferred embodiments of the present invention, T3 is 5-10 μm.

[0056] In some preferred embodiments of the present invention, the width of the first terrace region is 0.1-0.5 μm.

[0057] Preferably, the width of the non-transition region is 97%-99.9% of the total width W1 of the second semiconductor opening region.

[0058] In some preferred embodiments of the present invention, the total width W1 of the second semiconductor opening region is 400-800 μm.

[0059] Preferably, the width W2 of the first semiconductor opening region is 100-300 μm, and the width Wg of the isolation trench is 20-200 μm.

[0060] In some preferred embodiments of the present invention, the pyramid velvet surface in the non-transition zone satisfies: the height of the pyramid is in the range of 1-2 μm, and the radial dimension of the pyramid is in the range of 1-3 μm.

[0061] Preferably, the pyramid velvet surface of the second platform region satisfies: the height of the pyramid is in the range of 0.5-1 μm, and the radial dimension of the pyramid is in the range of 0.8-1.5 μm.

[0062] The corresponding height and radial dimension of the pyramid velvet surface in the present invention are obtained by SEM test measurement.

[0063] In some preferred embodiments of the present invention, the size of the pyramids corresponding to the non-transition region is larger than the size of the pyramids in the second platform region.

[0064] In the present invention, the pyramid velvet surfaces of the second platform area and the non-transition area are controlled to have respective appropriate sizes, wherein the pyramid velvet surface of the second platform area is smaller, which is more conducive to increasing the surface area of ​​the transition region between the first semiconductor area and the second semiconductor area and reducing the carrier recombination rate at the boundary; the pyramid velvet surface of the non-transition area is larger, which is conducive to enhancing the anti-reflection effect on the back side and improving the current density of the battery.

[0065] In some preferred embodiments of the present invention, the silicon wafer region corresponding to the first semiconductor opening region is a polishing region.

[0066] Preferably, the front side of the silicon wafer is a pyramid textured surface and satisfies: the height of the pyramid is within the range of 1-2 μm, and the radial dimension of the pyramid is within the range of 1-3 μm. Using a silicon wafer front side with a suitable pyramid size is more conducive to effectively reducing the reflectivity of the front side, thereby increasing the current density of the battery.

[0067] In some preferred embodiments of the present invention, the first bevel region includes a first ridgeline structure and a first pyramid tip located at the top of the first ridgeline structure, and the second bevel region includes a second ridgeline structure and a second pyramid tip located at the top of the second ridgeline structure, and the following conditions are satisfied: the distribution density of the first pyramid tip in the first bevel region as a percentage of area is 1%-10%, and the distribution density of the second pyramid tip in the second bevel region as a percentage of area is 1%-50%. The corresponding indicators of each bevel region are obtained by SEM measurement. The second bevel region and the first bevel region with suitable structures of the present invention are more conducive to increasing the surface area of ​​the transition region and improving the film passivation quality of the second semiconductor layer.

[0068] It can be understood that the distribution density refers to the percentage of the area of ​​the corresponding pyramid tip to the total area of ​​the corresponding slope area.

[0069] In some preferred embodiments of the present invention, the second semiconductor opening region and the first semiconductor opening region are arranged in an interval and the area between them is a spacing region.

[0070] Further preferably, in the spacing region, a mask layer is disposed between the first semiconductor layer and the second semiconductor layer or no mask layer is disposed. The type and thickness of the mask layer can refer to the prior art, for example, the thickness of the mask layer is 50-80 nm.

[0071] Preferably, in the present invention, the back contact cell further comprises a front passivation layer and an anti-reflection layer formed on the front side of the silicon wafer.

[0072] Preferably, in the present invention, the back contact battery further comprises a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer, and an isolation groove is provided on a portion of the conductive film layer located in the spacer region.

[0073] Further preferably, the back-contact battery further comprises a metal electrode arranged on the back side, and the metal electrode is arranged on the outer surface of the conductive film layer corresponding to each of the second semiconductor opening region and the first semiconductor opening region.

[0074] Further preferably, the isolation groove at least spans the polishing area corresponding to the first semiconductor opening area and the first platform area and the second platform area of ​​the second semiconductor opening area and part of the non-transition area. The isolation groove structure of the present invention is used in combination with the multi-layer gradient velvet structure of the present invention, so that when the subsequent film layer is printed, the buffering effect of the multi-layer gradient velvet structure of the second semiconductor opening area prolongs the service life of the screen, thereby reducing the consumables cost of the printing screen, and significantly improving leakage and short circuit phenomena. In the prior art, in order to improve leakage and short circuit phenomena, the isolation groove needs to span the polishing area and the adjacent velvet area at the same time, so that the opening of the printing screen is located within a larger height difference range during printing. After multiple printings, the service life of the screen is significantly reduced, and the consumables cost of the screen is increased.

[0075] Further preferably, the thickness of the conductive film layer is 40-80nm, preferably 40-60nm. Due to the multi-layer gradient velvet structure of the second semiconductor opening region, the conductive film layer can be well formed on its surface and side without thickening, thereby ensuring that the carrier transmission of the passivation film layer at the boundary is not affected. In order not to affect the conductivity at the boundary, conventional post-velvet structures usually adopt the method of thickening the conductive film layer to avoid this defect, thereby significantly increasing the material cost of the conductive film layer.

[0076] In some preferred embodiments of the present invention, the first semiconductor layer includes a first passivation layer and a first doped silicon layer, the second semiconductor layer includes a second passivation layer and a second doped silicon layer, the first passivation layer and the second passivation layer are each independently a tunneling oxide layer or an intrinsic silicon layer, and the first doped silicon layer and the second doped silicon layer are each independently polycrystalline silicon, amorphous silicon or microcrystalline silicon. The thickness and doping concentration of each corresponding film layer can refer to the prior art and be selected according to actual needs. One of the first doped silicon layer and the second doped silicon layer is N-type and the other is P-type.

[0077] Preferably, the first semiconductor layer includes a tunneling oxide layer and a first doped polycrystalline layer sequentially arranged on the back side, and the second semiconductor layer includes an intrinsic silicon layer and a second doped silicon layer sequentially arranged on the back side. The second doped silicon layer is amorphous silicon or microcrystalline silicon. The preferred combined passivation structure of the present invention is used in combination with a multi-layer gradient velvet structure, which is more conducive to improving the passivation performance of the second semiconductor layer.

[0078] Further preferably, the thickness of the tunnel oxide layer is 1-2 nm, the thickness of the first doped polycrystalline layer is 70-300 nm, and the effective doping concentration is greater than 5e18 cm -3The thickness of the intrinsic silicon layer is 5-15nm, the thickness of the second doped silicon layer is 5-20nm, and the effective doping concentration is 1e18cm -3 -9e20cm -3 .

[0079] In a second aspect, the present invention provides a post-texturing preparation method for a back contact battery, which is used to prepare the back contact battery with a multi-layer gradient velvet structure as described in the first aspect, and the post-texturing preparation method comprises the following steps:

[0080] S101, provide double-sided polished silicon wafers;

[0081] S102, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer;

[0082] S103, performing a first etching opening in a preset area of ​​the back surface obtained in S102, removing the mask layer and a corresponding portion of the first semiconductor layer, and forming a second semiconductor opening area arranged at intervals;

[0083] S104, then performing a first solution etching, so that the first semiconductor layer is etched below the edge of the mask layer to form a first platform area, and at the same time a first groove structure is formed in the second semiconductor opening area, the first groove structure includes a first transition slope and a non-transition middle area, and a first texturing is performed on the front side of the silicon wafer;

[0084] S105, then performing a second solution etching, and then selecting whether to remove the mask layer as needed; the second solution etching forms a second platform area on the first transition slope, and parts of the first transition slope located on both sides of the second platform area form a first slope area and a second slope area respectively, and the non-transition middle area forms a non-transition area, and a second texturing is performed on the front side of the silicon wafer to form a pyramid texture surface;

[0085] S106, depositing a second semiconductor layer on the back side;

[0086] S107 , performing a second etching opening on a portion of the second semiconductor layer on the back side to form a first semiconductor opening region spaced apart from the second semiconductor opening region.

[0087] In the post-texturing preparation method of the present invention, the principle of forming a multi-layer gradient texture structure by the first solution etching and the second solution etching can be speculated as follows:

[0088] During the first solution etching process in S104, the corresponding first etching solution, in addition to etching downward, will also etch the first semiconductor layer below the edge of the mask layer along the plane. Since the first semiconductor layer is a structure of a tunneling oxide layer and a first doped polysilicon layer, it is easier to etch than a silicon wafer. Therefore, a portion of the doped polycrystalline layer below the edge of the mask layer is removed by side etching. During the first solution etching process, the first semiconductor layer under the mask layer at the edge of the second semiconductor opening area will be gradually removed during the texturing process. Since the tunneling oxide layer in the mask layer and the first semiconductor layer has the function of preventing etching, a first platform area of ​​the polishing surface is formed, and a first groove structure is formed at the same time. The first groove structure includes a first transition bevel and a non-transition middle area. During the first solution etching, the first etching solution will cause side etching of a portion of the first semiconductor layer in the area below the edge of the mask layer, causing the mask layer to separate from the silicon wafer, and to be concave downward and suspended in the corresponding solution. In the subsequent cleaning process, the suspended portion of the mask layer in the side etching area will be removed;

[0089] After the second solution etching, the first transition slope forms a first slope area, a second platform area, and a second slope area. At the same time, the non-transition middle area is subjected to secondary texturing etching to form a non-transition area, thereby forming a second semiconductor layer with a multi-layer gradient texture structure. In a specific embodiment, the SEM image of the multi-layer gradient texture structure is as follows: Figure 2 As shown, in another specific embodiment, the SEM image of the multi-layer gradient suede structure is as shown Figure 3 As shown, Figure 2 and Figure 3 It can be clearly seen that it has a first platform area 21, a second platform area 22 and a non-transition area 23. The width of the second platform area is related to the corrosion rate of the second etching solution used in the second solution etching. The faster the corrosion rate, the wider its width. By adjusting the alkali concentration and reaction temperature of the second etching solution, the width of the second platform area can be controlled within a suitable range and its ratio with the width of the first platform area and the non-transition area can be appropriate, so as to avoid the poor slope buffering effect on the subsequent coating layer due to its too small width and inappropriate width ratio.

[0090] The first bevel region and the second bevel region of the present invention are inclined surfaces with a certain angle, and both the first bevel region and the second bevel region include a corresponding ridgeline structure and a cross-sectional structure of a first pyramid tip located at the top of the ridgeline structure. <100> Face to face <111> The corrosion rate of the surface varies greatly, up to 100-400 times, so the silicon <111> The surface will stop by itself during the corrosion process, forming a parallel ridge structure.

[0091] In some preferred embodiments of the present invention, the first etching solution used in the first solution etching in S104 is an aqueous solution containing alkali and optional texturing additives, and the mass percentage of the alkali contained in it is 5%-10%, preferably 6%-10%. When the first etching solution contains the texturing additive, the mass percentage of the texturing additive is 0.1%-0.5%; the conditions of the first solution etching include: etching time is 1-5min, and etching temperature is 75℃-85℃.

[0092] In some preferred embodiments of the present invention, the second etching solution used in the second solution etching in S105 is an aqueous solution containing alkali and a texturing additive, the mass percentage of alkali contained in it is 1%-3%, preferably 1.6%-3%, and the mass percentage of the texturing additive contained in it is 0.5%-1%; the conditions of the second solution etching include: etching time is 8-12min, and etching temperature is 75℃-85℃.

[0093] In the present invention, the alkali can be potassium hydroxide and / or sodium hydroxide.

[0094] The texturing additive in the present invention is a commercially available product in the art and can be obtained through commercial purchase, so it will not be described in detail here.

[0095] In the present invention, the size and structure of the first platform area, the first bevel area, the second platform area, the second bevel area, and the non-transition area can be regulated by controlling the composition of the corresponding etching solution and the etching conditions.

[0096] The method for removing the mask layer in S105 of the present invention can refer to the prior art, for example, it can be preferably treated by solution etching, and the etching solution used is a mixed solution of hydrofluoric acid and water, and the mass concentration of hydrofluoric acid is 5%-10%. Further preferably, the conditions for solution etching treatment include: treatment temperature of 20°C-30°C, reaction time of 60-600s.

[0097] The present invention S102 may also include other conventional steps, such as removing the phosphosilicate glass layer on the surface of the first semiconductor layer after forming the first semiconductor layer (preferably by using a hydrofluoric acid aqueous solution), and then depositing a mask layer.

[0098] In some preferred embodiments of the present invention, the post-texturing preparation method of the back contact battery further comprises:

[0099] S106 also includes forming a front passivation layer and an anti-reflection layer on the front side of the silicon wafer;

[0100] S108, depositing a conductive film layer on the back surface obtained in S107;

[0101] S109, performing a third etching opening on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove;

[0102] S110 , forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

[0103] In a third aspect, the present invention provides a photovoltaic module, which includes the back contact cell with a multi-layer gradient velvet structure described in the first aspect, or a back contact cell prepared by the post-texturing preparation method of the back contact cell described in the second aspect.

[0104] The embodiments of the present invention are described in detail below, which are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0105] Example 1

[0106] A back contact battery is prepared by the following method:

[0107] S1, providing a double-sided polished silicon wafer 1;

[0108] S2. Using LPCVD method, a first semiconductor layer is formed on the back side of the silicon wafer 1. The first semiconductor layer includes a tunneling silicon oxide layer 2 and a first doped N-type polycrystalline layer 3 formed in sequence on the back side. The thickness of the tunneling silicon oxide layer 2 is 1.5 nm, the thickness of the first doped N-type polycrystalline layer 3 is 100 nm, and the effective doping concentration is 5e19 cm -3 .

[0109] S3, cleaning and removing the PSG layer on the surface of the first semiconductor layer;

[0110] S4. Using a tubular PECVD method, a mask layer is deposited on the first semiconductor layer; the mask layer is a silicon nitride mask layer, and the thickness of the silicon nitride is 60 nm.

[0111] S5. Perform a first etching on the mask layer and the corresponding part of the first semiconductor layer in the preset area on the back side of the silicon wafer 1 to remove the mask layer and part of the first semiconductor layer to form second semiconductor opening areas distributed at intervals; the total width W1 of the formed second semiconductor opening areas is 500 μm.

[0112] S6, first solution etching:

[0113] The second semiconductor opening area on the back side and the front side of the silicon wafer 1 are subjected to the first solution etching, and the first etching solution used is a mixed solution of potassium hydroxide, a texturing additive (commercially available), and water, wherein the mass percentage of potassium hydroxide is 8%, the mass percentage of the texturing additive is 0.2%, the etching time is 3 minutes, and the etching temperature is 80° C. The mask layer is not removed in the first solution etching.

[0114] S7, second solution etching:

[0115] The second semiconductor opening area on the back side and the front side of the silicon wafer 1 are subjected to a second solution etching. The second etching solution used is a mixed solution of potassium hydroxide, a texturing additive and water, wherein the mass percentage of potassium hydroxide is 2.5%, the mass percentage of the texturing additive is 0.8%, the etching time is 8 minutes, and the etching temperature is 78°C.

[0116] After two times of solution etching, a first platform area 21, a first slope area, a second platform area 22, a second slope area, and a non-transition area 23 are formed. Figure 4 The multi-layer gradient velvet structure shown in FIG. 1 has SEM images of the multi-layer gradient velvet structure at different magnifications. Figure 2 , Figure 3 As shown. The width of the second platform area 22 is 5μm, and the ratio of the width of the second platform area 22 to the first platform area 21 and the non-transition area 23 is 1:0.1:99. The distance T2 between the top of the pyramid velvet surface of the second platform area 22 and the surface of the first semiconductor layer corresponding to the silicon wafer 1 area is 3μm. The distance T1 between the polished surface of the first platform area 21 and the surface of the first semiconductor layer corresponding to the silicon wafer 1 area is 100nm, and the distance T3 between the top of the pyramid velvet surface of the non-transition area 23 and the surface of the first semiconductor layer corresponding to the silicon wafer 1 area satisfies: T2:T3=1:2. It is calculated that the width of the non-transition area 23 is 99% of the total width W1 of the second semiconductor opening area.

[0117] The pyramid velvet surface of the obtained non-transition area 23 satisfies: the height of the pyramid is in the range of 1.0-1.5 μm, and the radial dimension of the pyramid is in the range of 1.0-2.0 μm; the pyramid velvet surface of the second platform area 22 satisfies: the height of the pyramid is in the range of 0.5-0.8 μm, and the radial dimension of the pyramid is in the range of 0.8-1.0 μm. The final pyramid velvet surface of the front side of the silicon wafer 1 satisfies: the height of the pyramid is in the range of 1.0-1.5 μm, and the radial dimension of the pyramid is in the range of 1.0-2.0 μm.

[0118] The first bevel area includes a first ridge line structure and a first pyramid tip located at the top of the first ridge line structure, and the second bevel area includes a second ridge line structure and a second pyramid tip located at the top of the second ridge line structure, and meets the following conditions: the distribution density of the first pyramid tip in the first bevel area as a percentage of area is 5%, and the distribution density of the second pyramid tip in the second bevel area as a percentage of area is 40%.

[0119] The mask layer is removed by solution etching, the solution is a mixed solution of hydrofluoric acid and water, the mass concentration of hydrofluoric acid is 8%, the processing temperature is 25° C., and the reaction time is 300 s.

[0120] S8, forming a front passivation layer and an anti-reflection layer on the front side of the silicon wafer 1, and then forming a second semiconductor layer on the back side, wherein the second semiconductor layer includes an intrinsic amorphous silicon layer 4 and a second doped P-type amorphous silicon layer 5 sequentially formed on the back side;

[0121] The thickness of the intrinsic amorphous silicon layer 4 is 10 nm, the thickness of the second doped P-type amorphous silicon layer 5 is 15 nm, and the effective doping concentration is 5e20 cm -3 .

[0122] S9. Use laser to perform second etching on the film layer corresponding to the polishing area on the back of the silicon wafer 1 to remove the second semiconductor layer in the area to expose the first semiconductor layer and form a first semiconductor opening area; the width W2 of the formed first semiconductor opening area is 200 μm.

[0123] S10, forming a transparent conductive film layer on the back side of the silicon wafer 1 to fully cover the entire surface; the thickness of the transparent conductive film layer is 50 nm.

[0124] S11, performing a third etching on the conductive film layer corresponding to the overlapping area of ​​the first semiconductor layer and the second semiconductor layer in the thickness direction on the back side of the silicon wafer 1 to form an isolation groove;

[0125] The isolation groove spans a portion of the polished area corresponding to the first semiconductor layer and a portion of the textured area on the second semiconductor opening area. The width Wg of the isolation groove is 100 μm. After etching, the resistance between the first semiconductor and the second semiconductor is greater than 1 kΩ.

[0126] S12, forming metal electrodes respectively on the outer surfaces of the first semiconductor opening region and the second semiconductor opening region corresponding to the back side of the silicon wafer 1.

[0127] Example 2

[0128] The method of Example 1 is referred to, except that the etching temperature of the second solution etching in S105 is adjusted to 83°C so that the width of the first platform area 22 is 7μm and the height remains unchanged. The ratio of the width of the first platform area 22 to the first platform area 21 and the non-transition area 23 is calculated to be 1:0.07:70.7.

[0129] Correspondingly, the pyramid velvet surface of the obtained non-transition zone 23 satisfies: the height of the pyramid is in the range of 1.0-1.5μm, and the radial dimension of the pyramid is in the range of 1.5-3μm; the pyramid velvet surface of the first platform zone 22 satisfies: the height of the pyramid is in the range of 0.5-0.8μm, and the radial dimension of the pyramid is in the range of 1.0-1.5μm.

[0130] The front side of the silicon wafer 1 is a pyramid textured surface and satisfies the following conditions: the height of the pyramid is within the range of 1-1.5 μm, and the radial dimension of the pyramid is within the range of 1.5-3 μm.

[0131] Example 3

[0132] The method of Example 1 is referred to, except that the mass content of potassium hydroxide in the second solution etching in S105 is adjusted to 1% so that the corresponding T2 of the first platform area 22 is 1.5 μm and the width remains unchanged. After calculation, T2:T3 is 1:4.

[0133] Accordingly, the pyramid velvet surface of the obtained non-transition zone 23 satisfies: the pyramid height is within the range of 1-1.2 μm, and the pyramid radial dimension is within the range of 1-1.8 μm. The pyramid velvet surface of the first platform zone 22 satisfies: the pyramid height is within the range of 0.5-0.8 μm, and the pyramid radial dimension is within the range of 0.8-1.0 μm.

[0134] The final pyramid textured surface on the front side of the silicon wafer 1 satisfies the following conditions: the height of the pyramid is within the range of 1-1.2 μm, and the radial dimension of the pyramid is within the range of 1-1.8 μm.

[0135] Example 4

[0136] The method of Example 1 is referred to, except that the mass content of potassium hydroxide in the first solution etching in S104 is adjusted to 5% so that the width of the first platform area 21 is 0.3 μm and the height remains unchanged, the width and height of the first platform area 22 and the non-transition area 23 remain unchanged, and the ratio of the width of the first platform area 22 to the width of the first platform area 21 is calculated to be 1:0.06.

[0137] Accordingly, the pyramid velvet surface of the obtained non-transition zone 23 satisfies: the height of the pyramid is within the range of 1-1.2 μm, and the radial dimension of the pyramid is within the range of 1-2 μm.

[0138] The final pyramid textured surface on the front side of the silicon wafer 1 satisfies the following conditions: the height of the pyramid is within the range of 1-1.2 μm, and the radial dimension of the pyramid is within the range of 1-2 μm.

[0139] Comparative Example 1

[0140] The method of Example 1 is referred to, except that S105 is not performed, but a common one-time texturing and cleaning step is adopted: only S104 is performed to form Figure 1 The ordinary texturing structure shown is: the first platform area, the middle bevel area, and the non-transition area (that is, there is no second platform area) are arranged in sequence from the edge of the second semiconductor opening area to the inside. The width of the first platform area is 0.2μm and the corresponding T1 is 10nm. The width of the non-transition area remains unchanged and the corresponding T3 is 8μm.

[0141] Comparative Example 2

[0142] The method of Example 1 is referred to, except that the etching temperature in the second solution etching in S105 is adjusted to 65°C so that the width of the second platform area is 1 μm and the height remains unchanged. The ratio of the width of the second platform area to the first platform area and the non-transition area is calculated to be 1:0.5:495.

[0143] Test Case

[0144] The back contact cells obtained in the above examples and comparative examples were subjected to performance tests, and the results are shown in Table 1.

[0145] Table 1

[0146]

[0147] It can be seen from the above results that, compared with the comparative example, the embodiment scheme of the present invention can reduce the carrier recombination rate at the boundary, thereby increasing the open circuit voltage and current density, thereby improving the battery conversion efficiency, while greatly saving the material cost of subsequent conventional conductive film layers and printed screens, which is conducive to mass production.

[0148] Furthermore, according to Example 1 and Examples 2-4, it can be seen that the preferred back-contact battery structure of the present invention is more conducive to improving the open circuit voltage and current density, and further improving the battery conversion efficiency.

[0149] The preferred embodiments of the present invention are described in detail above, but the present invention is not limited thereto. Within the technical concept of the present invention, the technical solution of the present invention can be subjected to a variety of simple modifications, including the combination of various technical features in any other suitable manner, and these simple modifications and combinations should also be regarded as the contents disclosed by the present invention and belong to the protection scope of the present invention.

Claims

1. A back contact battery with a multi-layer gradient suede structure, comprising a silicon wafer, first semiconductor layers spaced apart in the width direction of the back side of the silicon wafer, a second semiconductor opening region formed between two adjacent first semiconductor layers, the second semiconductor opening region comprising a non-transition region located in the middle, the surface of the non-transition region being a pyramid suede, characterized in that: The second semiconductor opening region also includes: a first platform region and a second platform region sequentially arranged from the edge to the non-transition region in the width direction, and a first bevel region between the first platform region and the second platform region, and a second bevel region between the second platform region and the non-transition region; wherein the first platform region is a polished surface, the second platform region is a pyramid velvet surface, and the heights of the first platform region, the second platform region, and the non-transition region gradually decrease, and the first platform region, the first bevel region, the second platform region, the second bevel region, and the non-transition region continuously form a multi-layer gradient velvet structure; and the width of the second platform region is 3-8μm, and the ratio of the width of the second platform region to the first platform region and the non-transition region is 1: (0.01-0.17): (50-270), and the second platform region The distance T2 between the top of the pyramid velvet surface and the surface of the silicon wafer area corresponding to the first semiconductor layer is 1-3μm; and the back contact battery also includes a second semiconductor layer alternately arranged with the first semiconductor layer, the second semiconductor layer is attached to the multi-layer gradient velvet structure in the second semiconductor opening area, and its two ends respectively extend outward to cover the outside of the partial back side of the adjacent first semiconductor layer, and a first semiconductor opening area that does not cover the second semiconductor layer is opened on the back side of the first semiconductor layer, and the distances between the polished surface of the first platform area and the top of the pyramid velvet surface in the non-transition area and the surface of the silicon wafer area corresponding to the first semiconductor layer are respectively counted as T1 and T3, T1 is 70-300nm, and T3 satisfies T2:T3=1:(1.7-10).

2. The back contact battery with a multi-layer gradient suede structure according to claim 1, characterized in that: T3 is 5-10μm.

3. The back contact battery with a multi-layer gradient suede structure according to claim 1 or 2, characterized in that: The width of the first platform region is 0.1-0.5 μm, and the width of the non-transition region is 97%-99.9% of the total width W1 of the second semiconductor opening region.

4. The back contact battery with a multi-layer gradient suede structure according to claim 1, characterized in that: The total width W1 of the second semiconductor opening region is 400-800 μm.

5. The back contact battery with a multi-layer gradient suede structure according to claim 1, characterized in that: The pyramid velvet surface in the non-transition zone meets the following requirements: the height of the pyramid is within the range of 1-2 μm, and the radial dimension of the pyramid is within the range of 1-3 μm; The pyramid velvet surface of the second platform area satisfies: the height of the pyramid is in the range of 0.5-1μm, and the radial size of the pyramid is in the range of 0.8-1.5μm.

6. The back contact battery with a multi-layer gradient suede structure according to claim 1 or 5, characterized in that: The size of the pyramid corresponding to the non-transition region is greater than the size of the pyramid corresponding to the second platform region.

7. The back contact battery with a multi-layer gradient suede structure according to claim 1, characterized in that: The first bevel area includes a first ridge line structure and a first pyramid tip located at the top of the first ridge line structure, and the second bevel area includes a second ridge line structure and a second pyramid tip located at the top of the second ridge line structure, and meets the following requirements: the distribution density of the first pyramid tip in the first bevel area as a percentage of area is 1%-10%, and the distribution density of the second pyramid tip in the second bevel area as a percentage of area is 1%-50%.

8. The back contact battery with a multi-layer gradient suede structure according to claim 1, characterized in that: The silicon wafer area corresponding to the first semiconductor opening area is a polishing area; the front side of the silicon wafer is a pyramid textured surface and satisfies: the height of the pyramid is within the range of 1-2 μm, and the radial dimension of the pyramid is within the range of 1-3 μm.

9. The back contact battery with a multi-layer gradient suede structure according to claim 1, characterized in that: The second semiconductor opening region is arranged at intervals with the first semiconductor opening region, and the area between them is the interval region; in the interval region, a mask layer is arranged between the first semiconductor layer and the second semiconductor layer, or no mask layer is arranged; the back contact battery also includes a front passivation layer and an anti-reflection layer formed on the front side of the silicon wafer, a metal electrode arranged on the back side, and a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer, an isolation groove is provided on the portion of the conductive film layer located in the interval region, and the isolation groove at least spans the polishing area corresponding to the first semiconductor opening region and the first platform area and the second platform area of ​​the second semiconductor opening region and part of the non-transition area; the metal electrode is arranged on the outer surface of the conductive film layer corresponding to each of the second semiconductor opening region and the first semiconductor opening region; wherein the thickness of the conductive film layer is 40-80nm; and / or, The first semiconductor layer includes a first passivation layer and a first doped silicon layer, the second semiconductor layer includes a second passivation layer and a second doped silicon layer, the first passivation layer and the second passivation layer are each independently a tunneling oxide layer or an intrinsic silicon layer, and the first doped silicon layer and the second doped silicon layer are each independently polycrystalline silicon, amorphous silicon or microcrystalline silicon.

10. A post-texturing preparation method for a back contact battery, characterized in that: It is used to prepare a back contact battery with a multi-layer gradient velvet structure as described in any one of claims 1 to 9, and the subsequent velvet preparation method comprises the following steps: S101, provide double-sided polished silicon wafers; S102, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer, wherein the first semiconductor layer includes a tunneling oxide layer and a first doped polysilicon layer; S103, performing a first etching opening in a preset area of ​​the back surface obtained in S102, removing the mask layer and a corresponding portion of the first semiconductor layer, and forming a second semiconductor opening area arranged at intervals; S104, then performing a first solution etching, so that the first semiconductor layer is etched below the edge of the mask layer to form a first platform area, and at the same time a first groove structure is formed in the second semiconductor opening area, the first groove structure includes a first transition slope and a non-transition middle area, and a first texturing is performed on the front side of the silicon wafer; S105, then performing a second solution etching, and then selecting whether to remove the mask layer as needed; the second solution etching forms a second platform area on the first transition slope, and parts of the first transition slope located on both sides of the second platform area form a first slope area and a second slope area respectively, and the non-transition middle area forms a non-transition area, and a second texturing is performed on the front side of the silicon wafer to form a pyramid texture surface; S106, depositing a second semiconductor layer on the back side; S107 , performing a second etching opening on a portion of the second semiconductor layer on the back side to form a first semiconductor opening region spaced apart from the second semiconductor opening region.

11. The post-texturing preparation method of a back contact battery according to claim 10, characterized in that: The first etching solution used in the first solution etching in S104 is an aqueous solution containing alkali and a texturing additive or an aqueous solution containing alkali, wherein the mass percentage of the alkali contained in the first etching solution is 5%-10%, and when the first etching solution contains a texturing additive, the mass percentage of the texturing additive is 0.1%-0.5%; The conditions of the first solution etching include: etching time of 1-5 min, etching temperature of 75° C. -85° C.; and / or, The second etching solution used in the second solution etching in S105 is an aqueous solution containing alkali and texturing additives, wherein the mass percentage of alkali contained in it is 1%-3%, and the mass percentage of texturing additive contained in it is 0.5%-1%; the conditions of the second solution etching include: etching time is 8-12min, and etching temperature is 75℃-85℃.

12. The post-texturing preparation method of a back contact battery according to claim 10, characterized in that: The post-texturing preparation method of the back contact battery also includes: S106 also includes forming a front passivation layer and an anti-reflection layer on the front side of the silicon wafer; S108, depositing a conductive film layer on the back surface obtained in S107; S109, performing a third etching opening on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove; S110 , forming metal electrodes on the outer surfaces of the conductive film layers corresponding to the first semiconductor opening region and the second semiconductor opening region.

13. A photovoltaic module, characterized in that: It includes a back contact battery with a multi-layer gradient velvet structure as described in any one of claims 1 to 9, or a back contact battery prepared by a post-texturing preparation method of a back contact battery as described in any one of claims 10 to 12.

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