Display panel and display device
By employing a non-layered interconnection structure in the display panel, the problems of color shift and reduced light transmittance caused by an excessive number of vias are solved, resulting in higher light transmittance and a simplified manufacturing process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUHAN TIANMA MICRO ELECTRONICS CO LTD
- Filing Date
- 2024-11-06
- Publication Date
- 2026-05-29
Smart Images
Figure CN119451428B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology
[0002] With the continuous development of display technology, display products are increasingly moving towards narrow bezels. In order to better achieve a narrow bottom bezel in display products, related technologies have adopted the technique of placing some fanout lines in the display area (Fanout inAA, FIAA) to reduce the width of the bottom bezel.
[0003] However, FIAA's design may result in an excessive number of vias during the cross-line design process, which may affect the flatness of the film layer in the light-emitting area, causing color shift in the display panel. In addition, an excessive number of vias may reduce the light-transmitting area and affect the light transmittance of the display panel. Summary of the Invention
[0004] To address the aforementioned technical problems, this disclosure provides a display panel and a display device that reduce color shift and improve light transmittance of the display panel.
[0005] In a first aspect, this disclosure provides a display panel, including:
[0006] A display area and a non-display area, wherein the non-display area is located on at least one side of the display area;
[0007] The display area includes multiple first data lines extending along a second direction and arranged along the first direction, wherein the first direction intersects the second direction;
[0008] The non-display area includes multiple fan-out lines;
[0009] The display area also includes multiple connecting lines. The first data line is connected to the fan-out line through the connecting lines. The connecting lines include a first connecting line extending along the first direction and a second connecting line extending along the second direction. The first connecting line is electrically connected to the second connecting line, the first connecting line is electrically connected to the first data line, and the second connecting line is electrically connected to the fan-out line.
[0010] The same first connecting line includes a first sub-segment and a second sub-segment disposed in different layers. Both the first sub-segment and the second sub-segment extend along the first direction. The first sub-segment and the second sub-segment are electrically connected. The first sub-segment and the second connecting line are disposed in different layers, and the second sub-segment and the second connecting line are disposed in the same layer.
[0011] Multiple auxiliary signal lines extend along the second direction and are arranged along the first direction; the auxiliary signal lines and the second sub-segment are disposed in different layers, and the auxiliary signal lines and the second sub-segment overlap along the thickness direction of the display panel.
[0012] In a second aspect, this disclosure also provides a display device, including a display panel as described in the first aspect.
[0013] The technical solution provided in this disclosure has the following advantages compared with the prior art:
[0014] This disclosure provides a display panel and a display device. The display panel includes: a display area and a non-display area, the non-display area being located on at least one side of the display area; the display area includes a plurality of first data lines extending along a second direction and arranged along a first direction, the first direction intersecting the second direction; the non-display area includes a plurality of fan-out lines; the display area also includes a plurality of connecting lines, the first data lines being connected to the fan-out lines via connecting lines, the connecting lines including a first connecting line extending along the first direction and a second connecting line extending along the second direction, the first connecting line being electrically connected to the second connecting line, the first connecting line being electrically connected to the first data lines, and the second connecting line being electrically connected to the fan-out lines; the same first connecting line includes a first sub-segment and a second sub-segment disposed on different layers, both the first sub-segment and the second sub-segment extending along the first direction, the first sub-segment and the second sub-segment being electrically connected, the first sub-segment and the second connecting line being disposed on different layers, and the second sub-segment and the second connecting line being disposed on the same layer; a plurality of auxiliary signal lines, the auxiliary signal lines extending along the second direction and arranged along the first direction; the auxiliary signal lines and the second sub-segments being disposed on different layers, and the auxiliary signal lines and the second sub-segments overlapping along the thickness direction of the display panel. Therefore, by setting the first sub-segment and the second connecting line on different layers and setting the second sub-segment and the second connecting line on the same layer, this disclosure requires only two vias on the first connecting line to achieve the crossing of auxiliary signal lines. No vias are required between the second sub-segment and the second connecting line. This avoids the problem in the prior art where vias are still needed to electrically connect the second sub-segment and the second connecting line when crossing the first connecting line extending along the first direction using auxiliary signal lines, resulting in an excessive number of vias. This reduces the number of vias in the display panel. The reduction in the number of vias also improves the flatness of the insulating film layer corresponding to the drilling position and reduces the unevenness of the insulating film layer, thereby reducing the color shift of the display panel. Furthermore, the reduction in the number of vias also reduces the area of metal used and improves the light transmittance of the display panel. Attached Figure Description
[0015] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.
[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present disclosure;
[0018] Figure 2 for Figure 1 A magnified view of a portion of region AA' in the middle;
[0019] Figure 3 This is a schematic diagram of another display panel structure provided in an embodiment of the present disclosure;
[0020] Figure 4 This is a schematic diagram of the structure of a first connecting line, an auxiliary signal line, and a first data line in a pixel circuit provided in an embodiment of the present disclosure.
[0021] Figure 5 for Figure 2 A magnified view of a portion of the BB' region;
[0022] Figure 6 A cross-sectional structural diagram of a display panel provided in an embodiment of this disclosure;
[0023] Figure 7 A cross-sectional structural schematic diagram of another display panel provided in an embodiment of this disclosure;
[0024] Figure 8 This is a schematic diagram of a pixel circuit provided in an embodiment of the present disclosure;
[0025] Figure 9 for Figure 7 A schematic diagram of the structure after the active layer, the first metal layer, the second metal layer, the third metal layer and the capacitor metal layer are stacked.
[0026] Figure 10 This is a schematic diagram of the structure of a display device provided in an embodiment of the present disclosure. Detailed Implementation
[0027] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.
[0028] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.
[0029] In related technologies, the FIAA design may result in an excessive number of vias during the cross-line design process, which may affect the flatness of the film layer in the light-emitting area, causing color shift in the display panel. In addition, an excessive number of vias may reduce the light-transmitting area and affect the transmittance of the display panel.
[0030] To address the aforementioned problems, this disclosure provides a display panel comprising: a display area and a non-display area, the non-display area being located on at least one side of the display area; the display area comprising multiple first data lines extending along a second direction and arranged along a first direction, the first direction intersecting the second direction; the non-display area comprising multiple fan-out lines; the display area further comprising multiple connecting lines, the first data lines being connected to the fan-out lines via connecting lines, the connecting lines comprising a first connecting line extending along the first direction and a second connecting line extending along the second direction, the first connecting line being electrically connected to the second connecting line, the first connecting line being electrically connected to the first data line, and the second connecting line being electrically connected to the fan-out lines; the same first connecting line comprising a first sub-segment and a second sub-segment disposed on different layers, both the first sub-segment and the second sub-segment extending along the first direction, the first sub-segment and the second sub-segment being electrically connected, the first sub-segment and the second connecting line being disposed on different layers, and the second sub-segment and the second connecting line being disposed on the same layer; multiple auxiliary signal lines, the auxiliary signal lines extending along the second direction and arranged along the first direction; the auxiliary signal lines and the second sub-segments being disposed on different layers, and the auxiliary signal lines and the second sub-segments overlapping along the thickness direction of the display panel. Therefore, by setting the first sub-segment and the second connecting line to different layers, and setting the second sub-segment and the second connecting line to the same layer, only two vias are needed on the first connecting line to achieve the crossing of the auxiliary signal line. No vias are needed between the second sub-segment and the second connecting line. This avoids the problem in the prior art where vias are still needed to electrically connect the second sub-segment and the second connecting line when crossing the first connecting line extending along the first direction using the auxiliary signal line, resulting in an excessive number of vias. This reduces the number of vias in the display panel. The reduction in the number of vias also improves the flatness of the insulating film layer corresponding to the drilling position and reduces the unevenness of the insulating film layer, thereby reducing the color shift of the display panel. Furthermore, the reduction in the number of vias also reduces the area of metal used and improves the light transmittance of the display panel.
[0031] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present disclosure. Figure 2 for Figure 1 A magnified view of a portion of region AA'. (Combined with...) Figure 1 and Figure 2The display panel 100 includes a display area AA and a non-display area NA that at least partially surrounds the display area AA. The display area AA is used to display images, and the non-display area NA is located on at least one side of the display area AA, at least partially surrounding the display area AA. For example, the non-display area NA can be disposed within at least a portion of the space on at least one side of the display area AA, for routing peripheral circuits and wiring to transmit display signals such as drive signals and power signals to the display area AA. The non-display area NA is not used to display images and can also be referred to as the bezel area. The smaller its proportion in the planar area of the display panel 100, the higher the proportion of the display area AA, and the easier it is to achieve a narrow bezel full-screen display.
[0032] Figure 1 The illustration exemplarily shows a display area AA comprising multiple first data lines 11 extending along a second direction Y and arranged along a first direction X. These first data lines 11 can, for example, be used to provide data voltage signals to pixel circuits electrically connected to them in the display panel 100, i.e., to provide drive signals for the display panel 100 to perform display functions. This disclosure embodiment Figure 1 This example illustrates the concept of the first direction Y and the second direction X being perpendicular to each other in a direction parallel to the plane where the display panel 100 is located. The subsequent figures can be used as a reference for understanding, and will not be elaborated further.
[0033] The non-display area NA also includes, for example, a fan-out area A1, which includes multiple fan-out lines 3. The display area AA also includes multiple connecting lines 2, through which the first data line 11 is electrically connected to the fan-out lines 3. The connecting lines 2 include a first connecting line 21 extending along a first direction X and a second connecting line 22 extending along a second direction Y. The first end of the first connecting line 21 is electrically connected to the first data line 11, the second end of the first connecting line 21 is electrically connected to the first end of the second connecting line 22, and the second end of the second connecting line 22 is electrically connected to the fan-out lines 3.
[0034] The same first connecting line 21 extending along the first direction X includes a first sub-segment 211 and a second sub-segment 212, both of which extend along the first direction X, and the first sub-segment 211 and the second sub-segment 212 are electrically connected.
[0035] Continue to combine Figure 1 and Figure 2The display panel 100 also includes multiple auxiliary signal lines 4. The auxiliary signal lines 4 extend along the second direction Y and are arranged along the first direction X. The auxiliary signal lines 4 are used to balance voltage drops at different locations within the display panel 100, which helps improve display uniformity. The auxiliary signal lines 4 and the second sub-segment 212 are disposed on different layers, and overlap along the thickness direction of the display panel 100. Therefore, only the first sub-segment 211 and the second sub-segment 212 need to be electrically connected vias on one side of the auxiliary signal line 4, and on the other side vias. Furthermore, the first sub-segment 211 and the second connecting line 22 are disposed on different layers, while the second sub-segment 212 and the second connecting line 22 are disposed on the same layer. Figure 2 Different filling patterns represent different film layers, and the same filling pattern represents the same film layer. Only two vias are needed on the first connecting line 21 to achieve the crossing of the auxiliary signal line 4. No vias are needed between the second sub-segment 212 and the second connecting line 22. This avoids the problem in the prior art where vias are still needed to electrically connect the second sub-segment 212 and the second connecting line 22 when the auxiliary signal line 4 is used to cross the first connecting line 21 extending along the first direction X, resulting in an excessive number of vias. This reduces the number of vias in the display panel 100. The reduction in the number of vias also improves the flatness of the film layer corresponding to the drilling position and reduces the unevenness of the film layer, thereby reducing the color shift of the display panel 100. In addition, the reduction in the number of vias also reduces the area of metal used and improves the light transmittance of the display panel 100.
[0036] Figure 3 This is a schematic diagram of another display panel provided in an embodiment of the present disclosure. Figure 4 This is a schematic diagram illustrating the structure of a first connecting line, an auxiliary signal line, and a first data line in a pixel circuit according to an embodiment of this disclosure. Optionally, in conjunction with... Figure 3 and Figure 4 The display panel 100 also includes a plurality of pixel circuits 5 arranged in an array, wherein the number of first connection lines 21 in the pixel circuits 5 is less than the number of auxiliary signal lines 4.
[0037] Figure 3 The example shows that the display panel 100 also includes a plurality of pixel circuits 5 arranged in an array. The light-emitting elements driven by the pixel circuits 5 can be, for example, organic light-emitting diodes, or light-emitting elements can be micro light-emitting diodes or sub-millimeter light-emitting diodes, etc. This embodiment is not limited.
[0038] Since the number of auxiliary signal lines 4 in pixel circuit 5 is greater than the number of first connecting lines 21, in related technologies, the number of vias required when using auxiliary signal lines 4 to cross first connecting lines 21 is greater than the number of vias required when using first connecting lines 21 to cross auxiliary signal lines 4. Figure 4 The example shows that only two vias are needed on a first connecting line 21 to achieve the crossing of two auxiliary signal lines 4, which greatly reduces the number of vias, improves the flatness of the film layer corresponding to the punching position, reduces the unevenness of the film layer, improves the color shift problem of the display panel 100, and improves the transmittance of the display panel 100.
[0039] Figure 5 for Figure 2 A magnified view of a portion of the BB' region. Optionally, in conjunction with... Figure 2 and Figure 5 The first sub-segment 211 includes a first part 2111 and a second part 2112 that are disconnected from each other. Along the first direction X, the first part 2111 and the second part 2112 are located on opposite sides of the auxiliary signal line 4.
[0040] Specifically, in combination Figure 2 and Figure 5 In this embodiment, the first sub-segment 211 extending along the first direction X includes a first part 2111 and a second part 2112 that are disconnected from each other. The first part 2111 and the second part 2112 are located on opposite sides of the auxiliary signal line 4, thereby avoiding the auxiliary signal line 4 on the same layer as the first sub-segment 211 by disconnecting the first part 2111 and the second part 2112. While realizing the electrical connection between the first sub-segment 211 and the second sub-segment 212 that are set on different layers, the short circuit problem between the first sub-segment 211 and the auxiliary signal line 4 is avoided, thus improving the manufacturing yield of the display panel 100.
[0041] Optionally, combined Figure 2 and Figure 5 The first part 2111 is electrically connected to the second sub-segment 212 through the first via K1, and the second part 2112 is electrically connected to the second sub-segment 212 through the second via K2. Along the first direction X, the first via K1 and the second via K2 are located on opposite sides of the auxiliary signal line 4.
[0042] Specifically, in combination Figure 2 and Figure 5The first sub-segment 211 and the second sub-segment 212, which are configured in different layers, can be electrically connected through vias K. Along the first direction X, the first part 2111 on one side of the auxiliary signal line 4 is electrically connected to the second sub-segment 212 through the first via K1, and the second part 2112 on the other side of the auxiliary signal line 4 is electrically connected to the second sub-segment 212 through the second via K2. This achieves the electrical connection of the first part 2111 of the first sub-segment 211 on one side of the auxiliary signal line 4, the second sub-segment 212 that crosses the auxiliary signal line 4, and the second part 2112 of the first sub-segment 211 on the other side of the auxiliary signal line 4. It also satisfies that the first part 2111 and the second sub-segment 212 at least partially overlap, and the second part 2112 at least partially overlaps with the second sub-segment 212. This reduces the impedance of the first connecting line 21, and by disconnecting the first part 2111 and the second part 2112, it avoids short circuit between the first sub-segment 211 and the auxiliary signal line 4 on the same layer, thus ensuring the manufacturing yield of the display panel 100.
[0043] Figure 2 The diagram also exemplarily illustrates that the first data line 11 is electrically connected to the first sub-segment 211 via the third via K3.
[0044] Optionally, combined Figure 2 , Figure 4 and Figure 5 The second sub-segment 212 and the second connecting line 22 are an integral structure.
[0045] Specifically, in combination Figure 2 , Figure 4 and Figure 5 The first sub-segment 211 and the second connecting line 22 are disposed on different layers, while the second sub-segment 212 and the second connecting line 22 are disposed on the same layer. This allows the co-layered second sub-segment 212 and the second connecting line 22 to be integrated into a single structure. This reduces the number of vias and eliminates the need to separately fabricate the second sub-segment 212 and the second connecting line 22, thereby simplifying the fabrication process of the display panel 100 and improving its fabrication efficiency. It should be noted that... Figure 2 , Figure 4 and Figure 5 For clarity, the transparency of the film filling pattern of the second sub-segment 212 has been adjusted. The second sub-segment 212 and the second connecting line 22 can still be regarded as being set in the same layer and as an integral structure.
[0046] Figure 6 This is a schematic cross-sectional view of a display panel provided in an embodiment of this disclosure. Optionally, as... Figure 6 As shown, along the thickness direction of the display panel 100, the first segment 211 and the second segment 212 are distributed in adjacent metal layers of the display panel 100. Figure 6 Only a portion of the metal layer is shown as an example; for specific film layer configurations, please refer to the accompanying drawings of subsequent embodiments.
[0047] Specifically, such as Figure 6 As shown, along the thickness direction of the display panel 100, the first sub-segment 211 and the second sub-segment 212 are disposed on adjacent metal layers of the display panel 100, so that the distance between the first sub-segment 211 and the second sub-segment 212 along the thickness direction of the display panel 100 is minimized, thereby shortening the distance of the via between the first sub-segment 211 and the second sub-segment 212, reducing the difficulty of making electrical connections between the first sub-segment 211 and the second sub-segment 212 through vias, and improving the manufacturing efficiency of the display panel 100.
[0048] Figure 7 This is a cross-sectional structural diagram of another display panel provided in an embodiment of this disclosure. It can be understood that... Figure 7 This is merely to illustrate the positions of the first sub-segment 211, auxiliary signal line 4, and second sub-segment 212, etc., in the thickness direction of the display panel 100, and does not represent their positional relationship in the transverse direction, i.e., parallel to the plane of the display panel 100. Optionally, such as Figure 7 As shown, the display panel 100 also includes a substrate 10, a first metal layer 6, and a second metal layer 7; the second metal layer 7 is located on the side of the first metal layer 6 away from the substrate 10; the first metal layer 6 includes a first sub-segment 211 and an auxiliary signal line 4, and the second metal layer 7 includes a second sub-segment 212.
[0049] Specifically, such as Figure 7 As shown, the display panel 100 includes a substrate 10, which supports and protects the film layer located thereon. The substrate 10 can be a rigid substrate, such as a glass substrate 101. The substrate 10 can also be a flexible substrate, for example, the material of the substrate 10 can include one or more combinations of polymer resins selected from polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, and cellulose acetate propionate. This disclosure does not specifically limit the material of the substrate 10.
[0050] The first metal layer 6 is located on one side of the substrate 10. The first metal layer 6 can serve as the source and drain metal layers of the transistor T, for example. The second metal layer 7 is located on the side of the first metal layer 6 facing away from the substrate 10. The first metal layer 6 may include, for example, a first sub-segment 211 and an auxiliary signal line 4, and the second metal layer 7 may include, for example, a second sub-segment 212.
[0051] In this embodiment, by placing the first sub-segment 211 and the auxiliary signal line 4 on the first metal layer 6 and the second sub-segment 212 on the second metal layer 7, the first sub-segment 211 and the auxiliary signal line 4 are distributed in two adjacent metal layers, which reduces the difficulty of electrically connecting the first sub-segment 211 and the second sub-segment 212. Furthermore, by placing the first sub-segment 211 and the auxiliary signal line 4 on the same metal layer, the thickness of the display panel 100 is reduced, which is beneficial for the thinning and lightening of the display device.
[0052] Figure 8 This is a schematic diagram of a pixel circuit provided in an embodiment of the present disclosure. Figure 9 for Figure 7 A schematic diagram of the structure consisting of the active layer, the first metal layer, the second metal layer, the third metal layer, and the capacitor metal layer stacked together. Optionally, combined with... Figure 8 and Figure 9 The display panel 100 also includes a power signal line PVDD, which extends along the second direction Y and is arranged along the first direction X; the second metal layer 7 also includes the power signal line PVDD, the first data line 11, and the second connecting line 22.
[0053] For example, pixel circuit 5 refers to the smallest repeating unit of the circuit structure that drives the corresponding light-emitting element D1 to emit light. Figure 8 The diagram exemplarily illustrates a pixel circuit 5 comprising seven transistors T1 to T7 and a capacitor Cst. A first light-emitting control transistor T1 and a second light-emitting control transistor T6 are turned off when the light-emitting control signal provided by the light-emitting control signal line EMIT is high, and turned on when the light-emitting control signal is low, causing the light-emitting element D1 to emit light during the light-emitting phase. A first reset transistor T5, for example, can be a dual-gate transistor, turned on when the first scan signal provided by the first scan signal line S1 is low, for writing a reference voltage signal provided by the reference signal line Vref to the first node N1. A data writing transistor T2 writes a data signal provided by the data signal line DATA to the driving transistor T3 when the third scan signal provided by the third scan signal line SP is low. The data signal line DATA may include, for example, a first data line 11 and a second data line 12. A threshold compensation transistor T4 is turned on when the second scan signal provided by the second scan signal line S2 is low. A second reset transistor T7 is turned on when the second scan signal provided by the second scan signal line S2 is low, writing an anode reset signal provided by the reference signal line Vref to the fourth node N4. The second terminal of the first light-emitting control transistor T1, the first terminal of the driving transistor T3, and the first terminal of the data writing transistor T2 are all connected to the N2 node, and the second terminal of the driving transistor T3, the second terminal of the threshold compensation transistor T4, and the first terminal of the second light-emitting control transistor T6 are all connected to the N3 node.
[0054] Reference Figure 8 and Figure 9 The display panel 100 also includes, for example, a power signal line PVDD. The power signal line PVDD can be used to provide power signals to each pixel circuit 5 in the display area AA. The power signal line PVDD extends along the second direction Y and is arranged along the first direction X.
[0055] Figure 9 In this design, the same filling pattern represents the same layer, and different filling patterns represent different layers. The second metal layer 7 also includes, for example, a power signal line PVDD, a first data line 11, and a second connecting line 22. Placing the power signal line PVDD, the first data line 11, and the second connecting line 22 on the same film layer reduces the amount of metal film occupied, lowers the thickness of the display panel 100, and facilitates the thinning and lightening of the display device. Furthermore, placing both the second connecting line 22 and the second sub-segment 212 on the second metal layer 7 facilitates the integration of the second connecting line 22 and the second sub-segment 212 into a single structure, thereby simplifying the manufacturing process of the display panel 100 and improving its manufacturing efficiency. In addition, both the first connecting line 21 and the second connecting line 22 are made using the film layer that is already present in the display panel 100. This eliminates the need to add a new conductive film layer to the display panel 100, avoids additional masking processes, reduces process steps, and helps save on the overall manufacturing cost of the display panel 100. Furthermore, by not adding a new conductive film layer, coupling problems between the introduced new conductive film layer and the conductive structure in the existing film layer can be avoided, thus reducing the wiring difficulty of the display panel 100.
[0056] Optionally, combined Figure 7 and Figure 9 The display panel 100 also includes a third metal layer 8 and a capacitor metal layer 9. The third metal layer 8 is located on the side of the first metal layer 6 near the substrate 10, and the capacitor metal layer 9 is located between the first metal layer 6 and the third metal layer 8. The third metal layer 8 includes a first scan signal line S1 and a second scan signal line S2, and the capacitor metal layer 9 includes a reference signal line Vref. The reference signal line Vref, the first scan signal line S1, and the second scan signal line S2 all extend along the first direction X and are arranged along the second direction Y.
[0057] Specifically, in combination Figure 7 and Figure 9The display panel 100 further includes a third metal layer 8, which is located between the substrate 10 and the first metal layer 6. The third metal layer 8 may include, for example, the gate metal layer of a transistor T. The third metal layer 8 also includes a first scan signal line S1 and a second scan signal line S2, and for example, a light emission control signal line E1. The reference signal line Vref, the first scan signal line S1, and the second scan signal line S2 all extend along a first direction X and are arranged along a second direction Y. The first electrode Cst1 of the storage capacitor Cst may be located in the capacitor metal layer 9, and the second electrode Cst2 of the storage capacitor Cst may be located in the third metal layer 8.
[0058] Reference Figure 7 The display panel 100 may also include, for example, an active layer Poly, which is located between the third metal layer 8 and the substrate 10. When the transistor T in the pixel circuit 5 of the display panel 100 includes a polysilicon transistor, the active layer Poly is, for example, a polysilicon layer; when the transistor T in the pixel circuit 5 of the display panel 100 includes a metal oxide transistor, the active layer Poly is, for example, a metal oxide semiconductor layer. The display panel 100 may also include, for example, an anode metal layer RE, which is located on the side of the second metal layer 7 facing away from the substrate 10.
[0059] Optionally, such as Figure 9 As shown, auxiliary signal line 4 is electrically connected to reference signal line Vref.
[0060] Specifically, such as Figure 9 As shown, the auxiliary signal line 4 and the reference signal line Vref are arranged in different layers. For example, the auxiliary signal line 4 can be electrically connected to the reference signal line Vref through a via to transmit the reference signal. Since the auxiliary signal line 4 extends along the second direction Y and is arranged along the first direction X, and the reference signal line Vref extends along the first direction X and is arranged along the second direction Y, the auxiliary signal line 4 and the reference signal line Vref can form a grid structure, which can balance the voltage drop of the reference signal at different positions in the display panel 100 and help improve the display uniformity of the display panel 100.
[0061] Optionally, such as Figure 1 As shown, along the second direction Y, the display area AA includes a second display area AA2 and a first display area AA1 located on opposite sides of the second display area AA2. The first data line 11 is located in the first display area AA1. The display panel 100 also includes a plurality of second data lines 12 extending along the second direction Y and arranged along the first direction X. The second data lines 12 are located in the second display area AA2 and are electrically connected to the fan-out line 3.
[0062] Specifically, the display area AA includes, for example, a first display area AA1 and a second display area AA2, to... Figure 1Taking the direction shown as an example, the second display area AA2 is located to the left and / or right of the first display area AA1. In other embodiments, the second display area AA2 may also be located in other positions, which are not limited here.
[0063] The first data line 11 is located in the first display area AA1. The first data line 11 is electrically connected to the fan-out line 3 through the first connecting line 21 and the second connecting line 22. The display panel 100 also includes a second data line 12, which extends along the second direction Y and is arranged along the first direction X. The second data line 12 is located in the second display area AA2. One end of the second data line 12 can be directly electrically connected to other fan-out lines 3 in the non-display area NA within the area corresponding to the second display area AA2. The second data line 12 is also used to provide data voltage signals to the pixel circuits electrically connected to it in the display panel 100.
[0064] The display panel provided in this embodiment includes: a display area and a non-display area, the non-display area being located on at least one side of the display area; the display area includes multiple first data lines extending along a second direction and arranged along a first direction, the first direction intersecting the second direction; the non-display area includes multiple fan-out lines; the display area also includes multiple connecting lines, the first data lines being connected to the fan-out lines via connecting lines, the connecting lines including a first connecting line extending along the first direction and a second connecting line extending along the second direction, the first connecting line being electrically connected to the second connecting line, the first connecting line being electrically connected to the first data line, and the second connecting line being electrically connected to the fan-out lines; the same first connecting line includes a first sub-segment and a second sub-segment disposed in different layers, both the first sub-segment and the second sub-segment extending along the first direction, the first sub-segment and the second sub-segment being electrically connected, the first sub-segment and the second connecting line being disposed in different layers, and the second sub-segment and the second connecting line being disposed in the same layer; multiple auxiliary signal lines, the auxiliary signal lines extending along the second direction and arranged along the first direction; the auxiliary signal lines and the second sub-segments being disposed in different layers, and the auxiliary signal lines and the second sub-segments overlapping along the thickness direction of the display panel. Therefore, by setting the first sub-segment and the second connecting line in different layers and setting the second sub-segment and the second connecting line in the same layer, only two vias are needed on the first connecting line to achieve the crossing of the auxiliary signal line. No vias are needed between the second sub-segment and the second connecting line. This avoids the problem in the prior art where vias are still needed to electrically connect the second sub-segment and the second connecting line when crossing the first connecting line extending along the first direction using the auxiliary signal line, resulting in an excessive number of vias. This reduces the number of vias in the display panel. The reduction in the number of vias also improves the flatness of the insulating film layer corresponding to the drilling position and reduces the unevenness of the insulating film layer, thereby reducing the color shift of the display panel. Furthermore, the reduction in the number of vias also reduces the area of metal used and improves the light transmittance of the display panel.
[0065] Based on the same inventive concept, this disclosure also provides a display device, including a display panel as described in any of the above-described display panel embodiments. Therefore, this display device possesses the technical features of the display panel provided in this disclosure and can achieve the beneficial effects of the display panel provided in this disclosure. Similarities can be found in the above description of the display panel provided in this disclosure, and will not be repeated here.
[0066] For example, Figure 10 This is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Figure 10 As shown, the display device provided in this embodiment includes the display panel 100 provided in any of the above embodiments of this disclosure. Figure 10 The embodiments use mobile phones as an example to illustrate the display device. It is understood that the display device provided in the embodiments of this application can be any electronic product with display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop monitors, tablets, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc. The embodiments of this invention do not make any special limitations in this regard.
[0067] The display device provided in this disclosure includes the above-described display panel, and therefore can solve the same technical problems as the above-described display panel embodiments and achieve the same technical effects, which will not be repeated here.
[0068] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.
[0069] The above are merely specific embodiments of this disclosure, enabling those skilled in the art to understand or implement this disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to these embodiments, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A display panel, characterized in that, include: A display area and a non-display area, wherein the non-display area is located on at least one side of the display area; The display area includes multiple first data lines extending along a second direction and arranged along a first direction, wherein the first direction intersects the second direction; The non-display area includes multiple fan-out lines; The display area also includes multiple connecting lines. The first data line is connected to the fan-out line through the connecting lines. The connecting lines include a first connecting line extending along the first direction and a second connecting line extending along the second direction. The first connecting line is electrically connected to the second connecting line, the first connecting line is electrically connected to the first data line, and the second connecting line is electrically connected to the fan-out line. The same first connecting line includes a first sub-segment and a second sub-segment disposed in different layers. Both the first sub-segment and the second sub-segment extend along the first direction. The first sub-segment and the second sub-segment are electrically connected. The first sub-segment and the second connecting line are disposed in different layers. The second sub-segment and the second connecting line are disposed in the same layer and are electrically connected. Multiple auxiliary signal lines extend along the second direction and are arranged along the first direction; the auxiliary signal lines and the second sub-segment are disposed in different layers, and the auxiliary signal lines and the second sub-segment overlap along the thickness direction of the display panel; The first sub-segment includes a first part and a second part that are disconnected from each other, and along the first direction, the first part and the second part are respectively located on opposite sides of the auxiliary signal line; The first part is electrically connected to the second sub-segment through a first via, and the second part is electrically connected to the second sub-segment through a second via. Along the first direction, the first via and the second via are located on opposite sides of the auxiliary signal line.
2. The display panel according to claim 1, characterized in that, Also includes: In an array of multiple pixel circuits, the number of the first connecting lines is less than the number of the auxiliary signal lines.
3. The display panel according to claim 1, characterized in that, The second sub-segment and the second connecting line are an integral structure.
4. The display panel according to claim 1, characterized in that, Along the thickness direction of the display panel, the first segment and the second segment are distributed in adjacent metal layers of the display panel.
5. The display panel according to claim 1, characterized in that, It also includes a substrate, a first metal layer, and a second metal layer; The second metal layer is located on the side of the first metal layer that faces away from the substrate; The first metal layer includes the first sub-segment and the auxiliary signal line, and the second metal layer includes the second sub-segment.
6. The display panel according to claim 5, characterized in that, It also includes power signal lines, which extend along the second direction and are arranged along the first direction; The second metal layer also includes the power signal line, the first data line, and the second connection line.
7. The display panel according to claim 6, characterized in that, It also includes a third metal layer and a capacitor metal layer, wherein the third metal layer is located on the side of the first metal layer closer to the substrate, and the capacitor metal layer is located between the first metal layer and the third metal layer; The third metal layer includes a first scan signal line and a second scan signal line, and the capacitor metal layer includes a reference signal line; wherein the reference signal line, the first scan signal line and the second scan signal line all extend along a first direction and are arranged along a second direction.
8. The display panel according to claim 7, characterized in that, The auxiliary signal line is electrically connected to the reference signal line.
9. The display panel according to any one of claims 1-8, characterized in that, Along the second direction, the display area includes a second display area and a first display area located on opposite sides of the second display area, and the first data line is located in the first display area; It also includes multiple second data lines extending along a second direction and arranged along the first direction, the second data lines being located in the second display area and electrically connected to the fan-out line.
10. A display device, characterized in that, Includes the display panel as described in any one of claims 1-9.