Frequency curve output method and system

Abstract

The invention discloses a frequency curve output method and system. The method comprises the following steps: designing a double-CPU system architecture of a main CPU and a sub-CPU; the sub-CPUs adaptively output frequency pulses with different widths according to the data issued by the main CPU; through a message header and a CRC (Cyclic Redundancy Check) mechanism, a communication protocol of whole-packet data transmission and point-to-point check between the main CPU and the sub-CPU is designed; frequency pulses are uniformly output through a main cycle and interruption mechanism; channel coefficient compensation is carried out through segmented compensation calculation of the main CPU and output of the sub-CPUs; and through interruption control, accurate output of a frequency curve is realized. According to the invention, by outputting 4-20mA direct-current analog quantity, uniform issuing of a frequency curve is realized through a hard contact wiring mode, and high frequency output precision is achieved.

Description

Technical Field

[0001] The invention relates to the technical field of primary frequency modulation active testing, and in particular to a frequency curve output method and system. Background Art

[0002] With the rapid development of new energy and the increase in UHV DC transmission, the startup capacity of conventional power sources with rotational inertia is constantly being squeezed, and the available fast frequency regulation resources of the power grid are gradually reduced. In order to verify the frequency regulation performance of the unit under large frequency difference, it is urgent to accelerate the construction of the primary frequency regulation active test system, conduct large disturbance simulation tests on grid-connected units regularly, strengthen the management of the unit's primary frequency regulation performance, and improve the power grid's ability to resist faults.

[0003] During the construction of the primary frequency modulation active test system, the dispatcher sends the frequency curve to the intermediate devices such as PMU or primary frequency modulation active test substation, and the intermediate device then sends the curve to the control device such as DCS in the station that actually performs frequency adjustment. If the control device in the power plant receives the frequency curve through the communication protocol, it is necessary to adjust the software architecture or the device does not originally have redundant communication interfaces. At the same time, the multi-link software communication delay is uncontrollable, which is not conducive to accurately grasping the duration of the primary frequency modulation active test process. On the other hand, the power plant control device often has a 4-20mA DC analog input interface reserved or can be expanded through spare parts, and has the conditions to transmit the frequency curve to the power plant control device through the DC analog pure hardware interface in a "three-out-of-two" manner. "Three-out-of-two" means that the primary frequency modulation active test will open three channels at the same time to the power plant control device at the same time. The power plant control device confirms that the correct frequency input is allowed to respond only when at least two of the three inputs have the same value and are within the allowable range. Therefore, this method is both simple and safe.

[0004] The PMU device does not have three or more DC signal outputs. If the primary frequency modulation active test system uses a primary frequency modulation active test substation as an intermediate device, the substation device often uses an industrial control platform based on operating systems such as Linux. The industrial control platform implements advanced functions such as multiple communication protocols and interface display by deploying software, and it is difficult to directly control the hardware loop and achieve a 4-20mA DC output with controllable pulse width. Summary of the invention

[0005] The purpose of this section is to summarize some aspects of embodiments of the present invention and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section and the specification abstract and the invention title of this application to avoid blurring the purpose of this section, the specification abstract and the invention title, and such simplifications or omissions cannot be used to limit the scope of the present invention.

[0006] In view of the above existing problems, the present invention is proposed.

[0007] Therefore, the present invention provides a method and system for issuing a frequency curve to solve the problem that the prior art has difficulties in issuing a frequency curve to a frequency control device of a power plant.

[0008] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0009] In a first aspect, the present invention provides a method for extracting a frequency curve, comprising:

[0010] Design dual CPU system architecture of main CPU and sub-CPU;

[0011] Based on the dual-CPU system architecture, the sub-CPU adaptively outputs frequency pulses of different widths according to the data sent by the main CPU;

[0012] Based on frequency pulses of different widths, the communication protocol for whole-packet data transmission and point-to-point verification between the main CPU and the sub-CPU is designed through the message header and CRC verification mechanism;

[0013] Based on the communication protocol, the frequency pulses are output evenly through the main loop and interrupt mechanism;

[0014] Based on the result of uniform output frequency pulse, channel coefficient compensation is performed through segmented compensation calculation of the main CPU and output of the sub-CPU;

[0015] Based on channel coefficient compensation, accurate output of frequency curve is achieved through interrupt control.

[0016] As a preferred solution of the frequency curve extraction method of the present invention, wherein:

[0017] The dual CPU system architecture of the main CPU and the sub-CPU is designed, including the main CPU and the sub-CPU;

[0018] The main CPU receives and checks the frequency curve and transmits it to the sub-CPU via the bus;

[0019] The sub-CPU uses a specific data flow strategy to output at least three paths of the received frequency curve point by point with a fixed pulse width and a 4-20 mA direct current.

[0020] As a preferred solution of the frequency curve extraction method of the present invention, wherein:

[0021] The sub-CPU adaptively outputs frequency pulses of different widths according to the data sent by the main CPU, including the following steps:

[0022] The main CPU verifies the received frequency curve data;

[0023] The frequency curve data is segmented and packaged in the form of one data packet per second, and each data packet contains 1 second of frequency data;

[0024] The main CPU transmits the data packet to the sub-CPU via the bus at time zero of each second, and sends it sequentially until all the data has been sent;

[0025] The pulse width of each frequency point is equal and needs to be greater than the unit execution time. For newly commissioned units, the pulse width is 20ms; for units that have been in operation for more than 5 years, the pulse width is 100ms;

[0026] When the sub-CPU outputs a continuous pulse width of 20ms at a frequency point, the main CPU reads each frequency point and puts it into the data area to be sent. One packet of data contains 50 points.

[0027] When the sub-CPU outputs a continuous pulse width of 100ms at a frequency point, the main CPU reads one frequency point each time and copies it into 5 frequency points and puts them into the data area to be sent;

[0028] The main CPU writes the frequency data of 50 points per packet to the sub-CPU through the bus at time zero of each second, and writes the data N times continuously during the entire test period;

[0029] When the sub-CPU receives the data, it writes it to the corresponding 4-20mA channel for 20ms.

[0030] As a preferred solution of the frequency curve extraction method of the present invention, wherein:

[0031] The design of the communication protocol for whole packet data transmission and point-to-point verification between the main CPU and the sub-CPU includes the following steps:

[0032] When the main CPU sends a packet of 50-point data, the data of each frequency point is organized according to the 1-point communication message format;

[0033] The sub-CPU parses the data stream point by point. Each data point in the frequency curve is received and stored in the receiving buffer after the message header is confirmed and the CRC check is correct.

[0034] The data of each frequency point is 12 bytes in total, including the message header, message length, point sequence number, frequency values ​​of 3 channels and checksum.

[0035] As a preferred solution of the frequency curve extraction method of the present invention, wherein:

[0036] The method of uniformly outputting frequency pulses through the main loop and interrupt mechanism includes the following steps:

[0037] The sub-CPU establishes a main loop and receives frequency curve data through the bus;

[0038] The main loop stores the received data into the temporary buffer area temp_buf after the message header is confirmed and the CRC check is correct. The length of the temp_buf data area is not less than 2 packets of data, that is, 100 points.

[0039] The sub-CPU establishes an interrupt with an interrupt time of no more than 0.5ms and processes data through the interrupt mechanism;

[0040] The interruption reads 1 point from the temp_buf buffer to the Buf buffer every 20ms. The length of the Buf buffer exceeds the dual CPU lag time, which is set to 500ms. One point is read out every 20ms, and the buffer stores 25 frequency points in a loop.

[0041] When the Buf buffer is full for the first time, the flag that allows the test to be opened is set. When a complete test is completed, the flag is cleared.

[0042] If the flag for allowing output is set, the interruption takes out 1 point from the Buf buffer and outputs a 20ms DC analog quantity, and repeats this cycle until all the buffer data is output;

[0043] After receiving the first packet of data, the sub-CPU delays 500ms to start DC switching until the test is completed.

[0044] As a preferred solution of the frequency curve extraction method of the present invention, wherein:

[0045] The channel coefficient compensation is performed through the segmented compensation calculation of the main CPU and the output of the sub-CPU, including the following steps:

[0046] According to the characteristics of the DC DAC chip, determine the specific value of the 4-20mA DC current channel;

[0047] D and I are established by the first and second transformations w The positive proportional relationship;

[0048] Based on the established direct proportional relationship, the compensation coefficient of each channel is calculated;

[0049] According to the minimum and maximum values ​​of the frequency curve configured by the primary frequency modulation active test system, calculate the minimum and maximum values ​​of the theoretical current corresponding to the range of [4mA, 20mA] to determine the final value of the compensation coefficient;

[0050] Based on the measurement results, the compensation coefficients k1, k2, and k3 of the three DC output channels are measured respectively and stored in a power-off retainable medium controlled by the main CPU;

[0051] Based on the stored compensation coefficient, the main CPU converts the frequency curve into the corresponding current value I according to the set current range. OUTCurve, select the 1s data to be sent;

[0052] According to the current value of each point, the three channel coefficients are adjusted respectively, and the frequency output value of each channel is calculated and filled in the communication message format.

[0053] The specific value of the 4-20mA DC current channel is expressed as:

[0054]

[0055] Where D is the decimal equivalent of the two-byte length loaded into the DAC chip, D = 0 corresponds to an output of 4mA, and D = 0xFFFF corresponds to an output of 20mA;

[0056] The first transformation is expressed as:

[0057] D=2 12 (I out -4)

[0058] The second transformation is expressed as:

[0059] D=2 12 I w ,I w =(I out -4)

[0060] The calculation of the compensation coefficient of each channel is expressed as:

[0061]

[0062] The frequency output value of each channel is calculated as follows:

[0063] D n =k n 2 12 (I out -4).

[0064] As a preferred solution of the frequency curve extraction method of the present invention, wherein:

[0065] The interrupt control is used to achieve accurate output of the frequency curve, including:

[0066] When the 500ms data loop storage area set in the sub-CPU interrupt is full, the output logic is started, and each point continues to output for 20ms and is hard-wired to the frequency control device of the power plant.

[0067] In a second aspect, the present invention provides a frequency curve extraction system, comprising:

[0068] System architecture design module, used to design dual CPU system architecture of main CPU and sub-CPU;

[0069] The frequency pulse generation module is used to adaptively output frequency pulses of different widths based on the data sent by the main CPU based on the dual CPU system architecture;

[0070] The communication protocol design module is used to design the communication protocol for whole-packet data transmission and point-to-point verification between the main CPU and the sub-CPU based on frequency pulses of different widths through the message header and CRC verification mechanism;

[0071] The frequency pulse output module is used to output frequency pulses uniformly through the main loop and interrupt mechanism based on the communication protocol;

[0072] The channel coefficient compensation module is used to perform channel coefficient compensation based on the result of uniform output frequency pulses through segmented compensation calculation of the main CPU and output of the sub-CPU;

[0073] The frequency curve output module is used to achieve accurate output of the frequency curve through interrupt control based on channel coefficient compensation.

[0074] In a third aspect, the present invention provides a computing device, comprising:

[0075] Memory, used to store programs;

[0076] The processor is used to execute the computer executable instructions, and the computer executable instructions, when executed by the processor, implement the steps of the frequency curve extraction method.

[0077] In a fourth aspect, the present invention provides a computer-readable storage medium, comprising: when the program is executed by a processor, the steps of implementing the frequency curve opening method are implemented.

[0078] Beneficial effects of the present invention: each frequency point of the present invention is emitted using a fixed-length pulse, and three channels are opened at each frequency point to meet the "three out of two" requirement of the power plant receiving measurement. For wiring requirements exceeding three channels, the sub-CPU continues to be expanded in channels or multiple sub-CPU boards are expanded. The present invention has low performance requirements for the sub-CPU and does not require any fixed value or configuration setting for the sub-CPU, which facilitates the expansion of the primary frequency modulation active test substation device. This pure hardware DC output technology allows safe primary frequency modulation active testing to be performed between the substation and the power plant frequency control equipment without the need for software communication, which facilitates the implementation of the primary frequency modulation active test system. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0080] Figure 1 A schematic diagram of a frequency curve sending path of a frequency curve generating method provided by an embodiment of the present invention;

[0081] Figure 2 A delay analysis diagram of data transmission between a master and a slave CPU of a frequency curve extraction method provided by an embodiment of the present invention;

[0082] Figure 3 A data flow diagram between a main CPU and a sub-CPU and a data flow diagram inside a sub-CPU of a frequency curve extraction method provided by an embodiment of the present invention;

[0083] Figure 4 A schematic diagram of a method for calculating a DC output channel compensation coefficient of a frequency curve extraction method provided by an embodiment of the present invention;

[0084] Figure 5 A basic flow chart of a frequency curve extraction method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0085] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the drawings of the specification. Obviously, the described embodiments are part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary persons in the art without creative work should fall within the scope of protection of the present invention.

[0086] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0087] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments.

[0088] The present invention is described in detail with reference to schematic diagrams. When describing the embodiments of the present invention, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0089] At the same time, in the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "upper, lower, inner and outer" are based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present invention. In addition, the terms "first, second or third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0090] In the present invention, unless otherwise clearly specified and limited, the terms "install, connect, connect" should be understood in a broad sense, for example: it can be a fixed connection, a detachable connection or an integral connection; it can also be a mechanical connection, an electrical connection or a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0091] Example 1

[0092] Reference Figure 1-5 Table 1 is an embodiment of the present invention, which provides a method for extracting a frequency curve. Figure 1 As shown, the following steps are included:

[0093] S1: Design the dual CPU system architecture of main CPU and sub-CPU;

[0094] In the embodiment of the present application, a system architecture is designed in which dual CPUs work together, one of which is a high-performance main CPU running a mainstream operating system, which is responsible for receiving and saving the main station frequency curve and completing the frequency calibration, and then sending it to the sub-CPU through the bus; the other is a sub-CPU with a single function, which does not require parameter configuration and uses a specific data flow strategy to output at least three outputs of 4-20mA DC with a fixed pulse width point by point, and the frequency accuracy meets the requirements of the power plant.

[0095] In the embodiment of the present application, the dual CPUs use USB 2.0 or other universal bus protocols with a communication delay requirement within 2ms, and the frequency curve sending path of the primary frequency modulation active test system is as follows: Figure 2As shown in the figure, the master station sends the frequency curve to the slave station through communication, and the slave station checks the frequency curve. After the check is correct, the slave station converts the original value of the frequency curve point by point into a 4-20 mA analog quantity through the algorithm in this article, and outputs it to the power plant frequency control device such as the governor or DCS in a hard contact manner. The continuous output time of each frequency point can be selected as 20 ms or 100 ms according to the unit characteristics.

[0096] S2: Based on the dual-CPU system architecture, the slave CPU adaptively outputs frequency pulses of different widths according to the data sent by the master CPU;

[0097] In the embodiment of the present application, the duration of the frequency curve in the primary frequency modulation active test process is 60-120 s, which is identified by a constant N (60 < N < 120). After the master CPU completes the verification of the frequency curve data, it segments and packages the frequency curve according to "1 packet / 1 second frequency data", and transmits it to the slave CPU through the bus at the zero moment of each second (0 second 0 millisecond), and sends it sequentially until all the data is sent.

[0098] In the embodiment of the present application, the primary frequency modulation active test system requires that the pulses output at each frequency point be uniform, that is, the width of the output level at each frequency point is equal, which is convenient for the power plant control device such as the DCS device that receives the frequency to identify. The pulse width needs to be greater than the unit execution time, which is 20 ms for newly commissioned units and 100 ms for units that have been in operation for more than 5 years.

[0099] In the embodiment of the present application, the constant CN_PULSE (20 ms - 100 ms) is used to represent the pulse width of the output of the slave CPU at one frequency point. When CN_PULSE is 20 ms, the master CPU reads 1 frequency point and puts it into the data area to be sent, and 1 packet of data contains 50 points. When CN_PULSE is 100 ms, the master CPU reads 1 frequency point and copies it into 5 frequency points and puts them into the data area to be sent. That is, regardless of whether the pulse to be output is 20 ms or 100 ms, the master CPU packs and transmits 50 points per second to the slave CPU, that is, each packet of frequency data is 50 points. The master CPU writes data to the slave CPU through the bus at the zero moment of each second, and continuously writes N times during the entire test period. In this way, the slave CPU does not require any configuration. Every time it receives a piece of data, it fixedly writes it to the corresponding 4-20 mA channel for 20 ms, and can meet the requirements of the DC level pulse width within 20 ms or 100 ms.

[0100] S3: Based on frequency pulses of different widths, through the message header and CRC check mechanism, design a communication protocol for the whole packet data transmission and point-to-point verification between the master CPU and the slave CPU;

[0101] In the embodiment of the present application, when the main CPU sends a packet of 50-point data, the data of each frequency point is organized according to Table 1; when the sub-CPU parses the data stream, it parses by point, and stores each received point in the receiving buffer after the message header is confirmed and the CRC check is correct. As can be seen from Table 1, 1 point of data has a total of 12 bytes, including the message header, message length, the point sequence number, the frequency value of the 3 channels, and the checksum.

[0102] Table 1 1-point communication message format

[0103]

[0104]

[0105] It should be noted that the communication protocol for whole-packet data transmission and point-to-point verification between the main and sub-CPUs takes into account both reliability and the speed of frequency curve opening, so as to avoid the main CPU from mistakenly opening the frequency curve during power-on, initialization or other abnormal processes.

[0106] S4: Based on the communication protocol, the frequency pulse is output evenly through the main loop and interrupt mechanism;

[0107] In an embodiment of the present application, the 1-second timer of the mainstream operating system has an error within 1ms. When the errors are all positive, the lag time of the sub-CPU receiving data relative to the data sent by the main CPU is the longest. Taking into account the 2ms error of the bus scheduling delay, the maximum lag time for the sub-CPU to receive data is 3ms per second. After all the test curve data is sent down, the theoretical maximum lag time of the last packet of data of the sub-CPU is 3*N milliseconds. That is, the longer the test curve, the greater the theoretical lag time. When the frequency curve corresponds to the longest test time of 120s, when the last packet of data arrives at the sub-CPU, the maximum lag time of the sub-CPU relative to the start time of the main CPU test is 360ms.

[0108] In the embodiment of the present application, the delay analysis of data transmission between the main and sub CPUs is as follows: Figure 3 As shown, the test curve data is sent in packets. As mentioned above, each packet contains a 1s frequency curve. After a packet of data is sent, the sub-CPU receives it at the latest after 3ms; by analogy, the theoretical maximum lag time of the last packet of data of the sub-CPU is 3*N milliseconds. That is, the longer the test curve, the greater the theoretical lag time. When the frequency curve corresponds to the longest test time of 120s, when the last packet of data arrives at the sub-CPU, the maximum lag time of the sub-CPU relative to the start time of the main CPU test is 360ms.

[0109] In the embodiment of the present application, the sub-CPU establishes a main loop and an interrupt with an interrupt time of no more than 0.5ms, and realizes the frequency curve opening through the mechanism of receiving frequency curve data in the main loop and disconnecting the DC quantity. The data received by the main loop through the bus is stored in the temporary buffer area temp_buf in sequence, and the length of the temp_buf data area is not less than 2 packets of data, that is, 100 points. A Buf circular buffer with a length exceeding the dual CPU lag time is designed in the interrupt, and its length is set to 500ms with a certain margin relative to the theoretical maximum lag time of 360ms. According to the conversion of opening one point in 20ms, the buffer cyclically stores 25 frequency points.

[0110] In the embodiment of the present application, the data flow between the main and sub-CPUs and the data flow within the sub-CPU are as follows: Figure 4 As shown, during the test, the main CPU sends a packet of data per second. The sub-CPU main loop receives the data and stores it in temp_buf after verification. The interrupt reads 1 point from the temp_buf buffer to the Buf buffer every 20ms. After the Buf buffer reaches 25 points, the data is full and the flag is set. Once the flag is set, it will not be clear until a complete test is completed. If the flag is set, the interrupt takes out 1 frequency point from the Buf buffer according to the first-in-first-out principle and continuously opens 20ms DC analog quantity; this cycle continues until all the buffer data is opened. Because each point needs to be opened for 20ms, that is, the sub-CPU delays 500ms after receiving the first packet of data before opening until the test is completed. In this way, the uneven data points caused by the main CPU operating system are effectively avoided, and the data flow process between the main and sub-CPUs is clear, and the entire test time is controllable.

[0111] S5: Based on the result of uniform output frequency pulse, channel coefficient compensation is performed through segmented compensation calculation of the main CPU and output of the sub-CPU;

[0112] It should be noted that the channel coefficient compensation method based on the direct proportional relationship reduces the inherent error in the 4-20mA DC output channel hardware and improves the frequency output accuracy. The sub-CPU is a single-chip CPU with limited ability to perform floating-point calculations. Therefore, the main CPU is used to calculate the segmented compensation of the channel coefficient and use it for frequency adjustment in the downstream link.

[0113] In the embodiment of the present application, according to the output characteristics of the DC DAC chip, the specific value of the 4-20mA DC current channel is determined by the following formula:

[0114]

[0115] Where D is the decimal equivalent of two bytes loaded into the DAC chip, D = 0 corresponds to an output of 4mA, and D = 0xFFFF corresponds to an output of 20mA. The relationship between D and the DC channel is:

[0116] D=2 12 I out -2 14 (2)

[0117] It should be noted that the relationship between D and I presents the characteristic of "D=kI+b". Based on the above characteristics, the existing DC channel calibration scheme needs to calculate two parameters, namely, the proportional coefficient k and the amplitude deviation b, which requires a large amount of calculation.

[0118] In the embodiment of the present application, the above formula is transformed to obtain formula (3):

[0119] D=2 12 (I out -4) (3)

[0120] In the embodiment of the present application, the transformation is continued to obtain:

[0121] D=2 12 I w ,I w =(I out -4) (4)

[0122] In the embodiment of the present application, a positive proportional relationship between D and Iw as shown in formula (4) is established through equivalent substitution. When calibrating a certain channel, firstly according to the set value I OUT D is calculated by formula (3), and then written into the DC ADC chip, the actual measured value of the DC channel is read out, and the proportional coefficient k between the two is calculated. k is the compensation coefficient of the DC output channel.

[0123]

[0124] In the embodiments of the present application, Figure 5 As shown, according to the minimum and maximum values ​​of the frequency curve configured by the primary frequency modulation active test system, the theoretical minimum and maximum values ​​of the current [Iw_min, Iw_max] corresponding to the range of [4mA, 20mA] are calculated. D is calculated by formula (4) from the theoretical minimum and maximum values ​​of the current, and written into the DAC chip to generate the DC analog quantity. The output value of the DC analog quantity [Ir_min, Ir_max] is measured by the instrument, and then substituted into formula (5) to obtain the proportional coefficients corresponding to the minimum and maximum values, and the average value of the two times is taken as the compensation coefficient k.

[0125] In the embodiment of the present application, the compensation coefficients k1, k2, and k3 of the three DC output channels are measured respectively and stored in a power-off retentive medium controlled by the main CPU. Once the compensation coefficient is determined, it is used repeatedly, but considering that the device characteristics may change during operation, the coefficient can be reviewed with the annual inspection of the device.

[0126] In the embodiment of the present application, when executing the test function, the main CPU first converts the frequency curve into the corresponding current value I according to the set current range. out The curve is then selected, and the 1s data to be sent is calculated according to the current value of each point, and the three channel coefficients are adjusted according to formula (6) to calculate D n (n=1, 2, 3), fill in the corresponding positions in Table 1.

[0127] D n =k n 2 12 (I out -4) (6)

[0128] S6: Based on channel coefficient compensation, accurate output of frequency curve is achieved through interrupt control.

[0129] As mentioned above, after the 500ms data loop storage area set in the sub-CPU interrupt is full, the output logic is started in a first-in-first-out order, and each point is continuously output for 20ms and is hard-wired to the frequency control device of the power plant.

[0130] This embodiment also provides a frequency curve generation system, including:

[0131] System architecture design module, used to design dual CPU system architecture of main CPU and sub-CPU;

[0132] The frequency pulse generation module is used to adaptively output frequency pulses of different widths based on the data sent by the main CPU based on the dual CPU system architecture;

[0133] The communication protocol design module is used to design the communication protocol for whole-packet data transmission and point-to-point verification between the main CPU and the sub-CPU based on frequency pulses of different widths through the message header and CRC verification mechanism;

[0134] The frequency pulse output module is used to output frequency pulses uniformly through the main loop and interrupt mechanism based on the communication protocol;

[0135] The channel coefficient compensation module is used to perform channel coefficient compensation based on the result of uniform output frequency pulses through segmented compensation calculation of the main CPU and output of the sub-CPU;

[0136] The frequency curve output module is used to achieve accurate output of the frequency curve through interrupt control based on channel coefficient compensation.

[0137] Furthermore, it also includes:

[0138] Memory, used to store programs;

[0139] A processor is used for loading the program to execute the frequency curve extraction method.

[0140] This embodiment also provides a computer-readable storage medium storing a program, and when the program is executed by a processor, the frequency curve extraction method is implemented.

[0141] The storage medium proposed in this embodiment and the frequency curve extraction method proposed in the above embodiment belong to the same inventive concept. The technical details not fully described in this embodiment can be referred to the above embodiment, and this embodiment has the same beneficial effects as the above embodiment.

[0142] Through the above description of the implementation methods, the technicians in the relevant field can clearly understand that the present invention can be implemented by means of software and necessary general hardware, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as a computer floppy disk, read-only memory (ReadOnly, Memory, ROM), random access memory (RandomAccess Memory, RAM), flash memory (FLASH), hard disk or optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform the methods of various embodiments of the present invention.

[0143] Example 2

[0144] This is an embodiment of the present invention, which provides a frequency curve output system, including a system architecture design module, a frequency pulse generation module, a communication protocol design module, a frequency pulse output module, a channel coefficient compensation module and a frequency curve output module;

[0145] In the embodiment of the present application, the system architecture design module includes designing a dual CPU system architecture of a main CPU and a sub-CPU;

[0146] In the embodiment of the present application, the dual-CPU system architecture designed for the main CPU and the sub-CPU includes a high-performance main CPU running a mainstream operating system, which is responsible for receiving and saving the main station frequency curve, and after completing the frequency verification, sending it to the sub-CPU through the bus; the other is a sub-CPU with a single performance, which does not require parameter configuration, and outputs at least three channels of the received frequency curve point by point according to a fixed pulse width with a 4-20 mA DC output through a specific data flow strategy, and the frequency accuracy meets the requirements of the power plant.

[0147] In the embodiment of the present application, the frequency pulse generation module includes that the sub-CPU adaptively outputs frequency pulses of different widths according to the data sent by the main CPU;

[0148] In the embodiment of the present application, the frequency pulse generation module further includes that the duration of the frequency curve in the primary frequency regulation active test process is 60-120 s, which is identified by a constant N (60 < N < 120). After the main CPU completes the verification of the frequency curve data, the frequency curve is segmented and packed at a rate of "1 packet / 1 second frequency data", and is transmitted to the sub-CPU through the bus at the zero moment (0 second 0 millisecond) per second, and is sent sequentially until all the data is sent. The primary frequency regulation active test system requires that the pulses output at each frequency point be uniform, that is, the width of the level duration output at each frequency point is equal, which is convenient for the power plant control device such as the DCS device that receives the frequency to identify. The pulse width needs to be greater than the execution time of the unit, which is 20 ms for newly commissioned units and 100 ms for units that have been in operation for more than 5 years. The constant CN PULSE (20 ms - 100 ms) represents the pulse width of the output of the sub-CPU at one frequency point. When CN PULSE is 20 ms, the main CPU reads 1 frequency point and puts it into the data area to be sent, and 1 packet of data contains 50 points. When CN PULSE is 100 ms, the main CPU reads 1 frequency point and copies it into 5 frequency points and puts them into the data area to be sent. In this way, no matter whether the pulse to be output is 20 ms or 100 ms, the main CPU packs and transmits 50 points per second to the sub-CPU, that is, each packet of frequency data is 50 points. The main CPU writes data to the sub-CPU through the bus at the zero moment per second, and continuously writes data N times during the entire test period. In this way, the sub-CPU does not require any configuration. Every time it receives a piece of data, it fixedly writes it to the corresponding 4-20 mA channel for 20 ms, and can meet the requirements of the DC level pulse width within 20 ms or 100 ms.

[0149] In the embodiment of the present application, the communication protocol design module includes designing a communication protocol for the whole packet data transmission and point-to-point verification between the main CPU and the sub-CPU through a message header and a CRC verification mechanism;

[0150] In the embodiment of the present application, the communication protocol design module also includes that when the main CPU sends a package of 50 points of data, the data of each frequency point is organized according to the 1-point communication message format; when the sub-CPU parses the data stream, it parses by point, and each point received is stored in the receiving buffer after the message header is confirmed and the CRC check is correct. 1 point of data has a total of 12 bytes, including the message header, message length, the point sequence number, the frequency value of 3 channels and the checksum.

[0151] In an embodiment of the present application, the frequency pulse output module includes a main loop and an interrupt mechanism to uniformly output frequency pulses; a 1-second timer of a mainstream operating system with an error within 1ms. When the errors are all positive, the lag time of the sub-CPU receiving data relative to the data sent by the main CPU is the longest. Taking into account the 2ms error of the bus scheduling delay, the maximum lag time for the sub-CPU to receive data is 3ms per second. After all the test curve data is sent down once, the theoretical maximum lag time of the last packet of data of the sub-CPU is 3*N milliseconds. That is, the longer the test curve, the greater the theoretical lag time. When the frequency curve corresponds to the longest test time of 120s, when the last packet of data arrives at the sub-CPU, the maximum lag time of the sub-CPU relative to the start time of the main CPU test is 360ms.

[0152] In an embodiment of the present application, the frequency pulse output module also includes a sub-CPU establishing a main loop and an interrupt with an interrupt time of no more than 0.5ms, and the frequency curve is opened by the mechanism of receiving frequency curve data through the main loop and disconnecting the DC quantity. The data received by the main loop through the bus is stored in the temporary buffer area temp_buf in sequence, and the length of the temp_buf data area is not less than 2 packets of data, that is, 100 points. A Buf circular buffer with a length exceeding the dual CPU lag time is designed in the interrupt, and its length is set to 500ms with a certain margin relative to the theoretical maximum lag time of 360ms. According to the conversion of opening one point in 20ms, the buffer cyclically stores 25 frequency points.

[0153] In the embodiment of the present application, the frequency pulse output module also includes a test process in which the sub-CPU main loop stores the received data into temp_buf after checking that it is correct, and an interrupt reads 1 point from the temp_buf buffer to the Buf buffer every 20ms. After the Buf buffer is full for the first time, a flag is set to allow the output, and the flag is cleared after a complete test is completed.

[0154] In the embodiment of the present application, the frequency pulse output module also includes that if the flag allowing the output is set, the interruption takes out 1 point from the Buf buffer according to the first-in-first-out principle, and outputs a 20ms DC analog quantity; this cycle is repeated until all the buffer data is output. That is, after the sub-CPU receives the first packet of data, it delays 500ms before outputting the DC quantity until the test is completed. In this way, the uneven data points caused by the main CPU operating system are effectively avoided, and the data flow process between the main and sub-CPUs is clear, and the entire test time is controllable.

[0155] In the embodiment of the present application, the channel coefficient compensation module includes performing channel coefficient compensation through segmented compensation calculation of the main CPU and output of the sub-CPU; according to the output characteristics of the DC DAC chip, the specific value of the 4-20mA DC current channel is established through equivalent replacement of D and I w When calibrating a channel, first set the output value I OUT Calculate D, write it into the DC ADC chip, read the actual measured value of the DC channel, calculate the proportional coefficient k between the two, k is the compensation coefficient of the DC output channel. According to the minimum and maximum values ​​of the frequency curve configured by the primary frequency modulation active test system, calculate the theoretical minimum and maximum values ​​of the current corresponding to the range of [4mA, 20mA]. Calculate D from the theoretical minimum and maximum values ​​of the current, write it into the DAC chip to open the DC analog quantity. Use the instrument to measure the output value of the DC analog quantity, and then derive the proportional coefficient, and take the average of the two times as the compensation coefficient k. Measure the compensation coefficients k1, k2, and k3 of the three DC output channels respectively, and store them in the power-off retentive medium controlled by the main CPU. Once the compensation coefficient is determined, it can be used repeatedly, but considering that the device characteristics may change during operation, the coefficient can be reviewed with the annual inspection of the device. When executing the test function, the main CPU first converts the frequency curve into the corresponding current value Iout curve according to the set current range, and then selects the 1s data to be sent according to the current value of each point, and adjusts it through the three channel coefficients respectively to calculate the frequency output value Dn (n=1, 2, 3).

[0156] In the embodiment of the present application, the frequency curve output module includes an interrupt control to achieve accurate output of the frequency curve. After the 500ms data cycle storage area set in the sub-CPU interrupt is full, the output logic is started in the first-in-first-out order, and each point is continuously output for 20ms, which is hard-wired to the frequency control device of the power plant.

[0157] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A method for generating a frequency curve, characterized in that: include: Design dual CPU system architecture of main CPU and sub-CPU; Based on the dual-CPU system architecture, the sub-CPU adaptively outputs frequency pulses of different widths according to the data sent by the main CPU; Based on frequency pulses of different widths, the communication protocol for whole-packet data transmission and point-to-point verification between the main CPU and the sub-CPU is designed through the message header and CRC verification mechanism; Based on the communication protocol, the frequency pulses are output evenly through the main loop and interrupt mechanism; Based on the result of uniform output frequency pulse, channel coefficient compensation is performed through segmented compensation calculation of the main CPU and output of the sub-CPU; Based on channel coefficient compensation, accurate output of frequency curve is achieved through interrupt control.

2. The frequency curve generation method according to claim 1, characterized in that: The dual CPU system architecture of the main CPU and the sub-CPU is designed, including the main CPU and the sub-CPU; The main CPU receives and checks the frequency curve and transmits it to the sub-CPU via the bus; The sub-CPU uses a specific data flow strategy to output at least three paths of the received frequency curve point by point with a fixed pulse width and a 4-20 mA direct current.

3. The frequency curve drawing method according to claim 1 or 2, characterized in that: The sub-CPU adaptively outputs frequency pulses of different widths according to the data sent by the main CPU, including the following steps: The main CPU verifies the received frequency curve data; The frequency curve data is segmented and packaged in the form of one data packet per second, and each data packet contains 1 second of frequency data; The main CPU transmits the data packet to the sub-CPU via the bus at time zero of each second, and sends it sequentially until all the data has been sent; The pulse width of each frequency point is equal and needs to be greater than the unit execution time. For newly commissioned units, the pulse width is 20ms; for units that have been in operation for more than 5 years, the pulse width is 100ms; When the sub-CPU outputs a continuous pulse width of 20ms at a frequency point, the main CPU reads each frequency point and puts it into the data area to be sent. One packet of data contains 50 points. When the sub-CPU outputs a continuous pulse width of 100ms at a frequency point, the main CPU reads one frequency point each time and copies it into 5 frequency points and puts them into the data area to be sent; The main CPU writes the frequency data of 50 points per packet to the sub-CPU through the bus at time zero of each second, and writes the data N times continuously during the entire test period; When the sub-CPU receives the data, it writes it to the corresponding 4-20mA channel for 20ms.

4. The frequency curve generation method according to claim 3, characterized in that: The design of the communication protocol for whole-packet data transmission and point-to-point verification between the main CPU and the sub-CPU includes the following steps: When the main CPU sends a packet of 50-point data, the data of each frequency point is organized according to the 1-point communication message format; The sub-CPU parses the data stream point by point. Each data point received from the frequency curve is stored in the receiving buffer after being confirmed by the message header and CRC check. The data of each frequency point is 12 bytes in total, including the message header, message length, point sequence number, frequency values ​​of 3 channels and checksum.

5. The frequency curve generation method according to claim 4, characterized in that: The method of uniformly outputting frequency pulses through the main loop and interrupt mechanism includes the following steps: The sub-CPU establishes a main loop and receives frequency curve data through the bus; The main loop stores the received data into the temporary buffer area temp_buf after the message header is confirmed and the CRC check is correct. The length of the temp_buf data area is not less than 2 packets of data, that is, 100 points. The sub-CPU establishes an interrupt with an interrupt time of no more than 0.5ms and processes data through the interrupt mechanism; The interruption reads 1 point from the temp_buf buffer to the Buf buffer every 20ms. The length of the Buf buffer exceeds the dual CPU lag time, which is set to 500ms. One point is read out every 20ms, and the buffer stores 25 frequency points in a loop. When the Buf buffer is full for the first time, the flag that allows the test to be opened is set. When a complete test is completed, the flag is cleared. If the flag for allowing output is set, the interruption takes out 1 point from the Buf buffer and outputs a 20ms DC analog quantity, and repeats this cycle until all the buffer data is output; After receiving the first packet of data, the sub-CPU delays 500ms to start DC switching until the test is completed.

6. The frequency curve generation method according to claim 5, characterized in that: The channel coefficient compensation is performed through the segmented compensation calculation of the main CPU and the output of the sub-CPU, including the following steps: According to the characteristics of the DC DAC chip, determine the specific value of the 4-20mA DC current channel; D and I are established by the first and second transformations w The positive proportional relationship; Based on the established direct proportional relationship, the compensation coefficient of each channel is calculated; According to the minimum and maximum values ​​of the frequency curve configured by the primary frequency modulation active test system, calculate the minimum and maximum values ​​of the theoretical current corresponding to the range of [4mA, 20mA] to determine the final value of the compensation coefficient; Based on the measurement results, the compensation coefficients k1, k2, and k3 of the three DC output channels are measured respectively and stored in a power-off retainable medium controlled by the main CPU; Based on the stored compensation coefficient, the main CPU converts the frequency curve into the corresponding current value I according to the set current range. OUT Curve, select the 1s data to be sent; According to the current value of each point, the three channel coefficients are adjusted respectively, and the frequency output value of each channel is calculated and filled in the communication message format. The specific value of the 4-20mA DC current channel is expressed as: Where D is the decimal equivalent of the two-byte length loaded into the DAC chip, D = 0 corresponds to an output of 4mA, and D = 0xFFFF corresponds to an output of 20mA; The first transformation is expressed as: D=2 12 (I out -4) The second transformation is expressed as: D=2 12 I w ,I w =(I out -4) The calculation of the compensation coefficient of each channel is expressed as: The frequency output value of each channel is calculated as follows: D n =k n 2 12 (I out -4)。 7. The frequency curve generation method according to claim 6, characterized in that: The interrupt control is used to achieve accurate output of the frequency curve, including: When the 500ms data loop storage area set in the sub-CPU interrupt is full, the output logic is started, and each point continues to output for 20ms and is hard-wired to the frequency control device of the power plant.

8. A system based on the frequency curve generation method according to claim 1, characterized in that: System architecture design module, used to design dual CPU system architecture of main CPU and sub-CPU; The frequency pulse generation module is used to adaptively output frequency pulses of different widths based on the data sent by the main CPU based on the dual CPU system architecture; The communication protocol design module is used to design the communication protocol for whole-packet data transmission and point-to-point verification between the main CPU and the sub-CPU based on frequency pulses of different widths through the message header and CRC verification mechanism; The frequency pulse output module is used to output frequency pulses uniformly through the main loop and interrupt mechanism based on the communication protocol; The channel coefficient compensation module is used to perform channel coefficient compensation based on the result of uniform output frequency pulses through segmented compensation calculation of the main CPU and output of the sub-CPU; The frequency curve output module is used to achieve accurate output of the frequency curve through interrupt control based on channel coefficient compensation.

9. An electronic device, characterized in that: include: Memory, used to store programs; A processor is used to load the program to execute the steps of the frequency curve extraction method according to any one of claims 1 to 7.

10. A computer-readable storage medium storing a program, characterized in that: When the program is executed by a processor, the steps of the frequency curve extraction method according to any one of claims 1 to 7 are implemented.

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