Pcie peripheral secondary scanning link building method based on loongson 3a5000 and 7a1000 chipsets
By using the secondary scanning link establishment method for PCIe peripherals based on the Loongson 3A5000 and 7A1000 chipsets, the problem of difficult function switching was solved, and dynamic switching of PCIe peripheral functions and improved device flexibility were realized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUHAN SHIP COMM RES INST (NO 722 RES INST OF CHINA STATE SHIPBUILDING CORP)
- Filing Date
- 2024-11-27
- Publication Date
- 2026-07-21
AI Technical Summary
When replacing traditional x86 architecture processors and northbridge/southbridge chipsets with Loongson 3A5000 and 7A1000 chipsets, secondary scanning and link establishment of PCIe peripherals cannot be achieved, making function switching difficult.
By using the built-in function loading module of the PCIe peripheral to perform secondary loading of the FPGA logic, and combining the hardware design of the Loongson 3A5000 and 7A1000 chipsets, new function logic files are loaded in an active or passive manner. The configuration register values are read through the operating system tools to realize the function change and re-establishment of the PCIe peripheral.
It enables dynamic switching of PCIe peripheral functions, ensuring that the switching process is transparent and does not affect normal use, increasing the flexibility and expandability of the device, and possessing high practical and commercial value.
Smart Images
Figure CN119473980B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic information technology, and in particular to a method for establishing a secondary scanning connection for PCIe peripherals based on the Loongson 3A5000 and 7A1000 chipsets. Background Technology
[0002] The PCIe interface is a high-speed interface for communication between the processor and peripherals. PCIe peripherals with dedicated custom functions are usually implemented using FPGA chips with integrated PCIe hard cores. When the functions of custom PCIe peripherals need to switch between multiple function modes, but the FPGA chip has limited resources and power consumption, it is impossible to implement all functions at the same time. In order to effectively reduce the size, power consumption and cost of PCIe peripherals, the functions of PCIe peripherals can be dynamically changed as needed, thereby improving the versatility and flexibility of the device.
[0003] More and more devices are adopting domestic alternatives. Previously, when PCIe peripherals were used with x86 architecture processors and northbridge / southbridge chipsets, the secondary scanning and link establishment for PCIe peripherals could be completed simply by unloading the driver, unloading the device, and then scanning the device. However, when replacing traditional x86 architecture processors and northbridge / southbridge chipsets with the Loongson 3A5000 domestic processor and 7A1000 chipset, the x86 technology cannot be used to achieve secondary scanning and link establishment for PCIe peripherals. Summary of the Invention
[0004] This invention provides a secondary scanning and link establishment method for PCIe peripherals based on Loongson 3A5000 and 7A1000 chipsets. When it is necessary to replace the functional mode of a PCIe device, the function loading module built into the PCIe peripheral is used to perform secondary loading of the FPGA logic, and then the method described in this invention is used to perform secondary scanning and link establishment on the PCIe device to realize the functional change of the PCIe peripheral.
[0005] This invention provides a method for establishing a secondary scan connection between a PCIe peripheral based on the Loongson 3A5000 and 7A1000 chipsets, comprising: establishing a link between the Loongson 3A5000 and the PCIe peripheral; loading the PCIe driver of the PCIe peripheral; and obtaining the PCIe node number and related configuration register values of the PCIe peripheral. The Loongson 3A5000 connects to the PCIe peripheral via the 7A1000 chipset. When it is necessary to switch the function of the PCIe peripheral, the Loongson peripheral is notified to prepare to switch to the new function, and the current PCIe driver is uninstalled. The FPGA chip of the PCIe peripheral loads the logic file of the new function using either an active or passive method. The link between the Loongson 3A5000 and the PCIe peripheral is disconnected. Using the previously read PCIe node number and related configuration register values, the relevant configuration registers of the PCIe peripheral are written back, and the PCIe peripheral is enabled. The PCIe peripheral is uninstalled first, and then a secondary scan is performed on the PCIe peripheral to complete the re-establishment of the link between the Loongson 3A5000 and the PCIe peripheral.
[0006] The PCIE peripheral secondary scanning link establishment method based on Loongson 3A5000 and 7A1000 chipsets provided by the present invention further includes: loading the driver of the new function mode of the PCIE peripheral to complete the invocation of the new function of the PCIE peripheral.
[0007] According to the present invention, a secondary scanning connection method for PCIe peripherals based on Loongson 3A5000 and 7A1000 chipsets is provided. The hardware design for the connection between the 7A1000 chipset and the gold fingers of the PCIe peripheral includes: shielding the reset signal of the PCIe interface of the 7A1000 chipset and using the global reset signal on the PCB.
[0008] According to the present invention, a secondary scanning connection establishment method for PCIE peripherals based on Loongson 3A5000 and 7A1000 chipsets is provided. The values of the relevant configuration registers of the PCIE peripherals are read using the busybox tool of the Loongson 3A5000 operating system.
[0009] According to the present invention, a method for secondary scanning and link establishment of PCIe peripherals based on Loongson 3A5000 and 7A1000 chipsets is provided. The method first unloads the PCIe peripherals and then performs a secondary scan on the PCIe peripherals. The method includes: unloading the PCIe peripherals using a first instruction and the PCIe node number of the PCIe peripherals; and performing a secondary scan on the PCIe peripherals of Loongson 3A5000 using a second instruction to complete the re-establishment of the link between Loongson 3A5000 and the PCIe peripherals.
[0010] The present invention provides a secondary scanning link establishment method for PCIE peripherals based on Loongson 3A5000 and 7A1000 chipsets, enabling PCIE peripherals, including: enabling PCIE peripherals by configuring the status and command registers of PCIE peripherals.
[0011] According to the present invention, a PCIE peripheral secondary scanning and connection establishment method based on Loongson 3A5000 and 7A1000 chipsets is provided, wherein the FPGA chip actively loads the logic file of the new function, including: the FPGA chip actively downloads and loads the new function logic file through a network or local storage device.
[0012] According to the present invention, a secondary scanning and link establishment method for PCIe peripherals based on Loongson 3A5000 and 7A1000 chipsets is provided. The FPGA chip passively loads the logic file of the new function, including: the FPGA chip receiving the logic file of the new function transmitted by Loongson 3A5000 through a specific communication protocol.
[0013] The PCIe peripheral secondary scan connection establishment method based on the Loongson 3A5000 and 7A1000 chipsets provided by this invention has the following beneficial effects:
[0014] (1) The PCIE peripheral secondary scanning link establishment method based on Loongson 3A5000 and 7A1000 chipsets provided by the present invention realizes the dynamic switching of PCIE peripheral functions in the environment of Loongson 3A5000 and 7A1000 chipsets, ensuring that the switching process is transparent to the user and does not affect normal use, which can further increase the flexibility and scalability of the device, and has very high practical and commercial value.
[0015] (2) The PCIE peripheral secondary scanning link establishment method based on Loongson 3A5000 and 7A1000 chipsets provided by the present invention can also realize the secondary scanning link establishment of PCIE peripherals using the domestic 3A5000 processor, and achieve the same function as the imported x86 processor. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0017] Figure 1 This is a flowchart illustrating the PCIE peripheral secondary scanning link establishment method based on the Loongson 3A5000 and 7A1000 chipsets provided by the present invention.
[0018] Figure 2 This is a schematic diagram showing the connection between the Loongson 3A5000 and PCIE peripherals provided by this invention. Detailed Implementation
[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.
[0020] It should be noted that, in the description of the embodiments of the present invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0021] The terms "first," "second," etc., used in this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more.
[0022] The following is combined Figures 1-2 This invention describes a method for establishing a secondary scan connection for PCIe peripherals based on the Loongson 3A5000 and 7A1000 chipsets, as provided in embodiments of the present invention.
[0023] Figure 1 This is a flowchart illustrating the PCIe peripheral secondary scan connection establishment method based on the Loongson 3A5000 and 7A1000 chipsets provided by the present invention, as shown below. Figure 1 As shown, including but not limited to the following steps:
[0024] Step 101: Establish the link between Loongson 3A5000 and PCIe peripheral, load the PCIe driver of the PCIe peripheral, and obtain the PCIe node number and related configuration register values of the PCIe peripheral; wherein, Loongson 3A5000 connects to the PCIe peripheral through the 7A1000 chipset.
[0025] Ensure that the Loongson 3A5000 processor and PCIe devices are powered on simultaneously; when the system starts, enumerate all devices and load the default PCIe drivers.
[0026] When waiting for the PCIe peripheral to power on and complete its first link establishment, the PCIe node number of the PCIe peripheral is determined. The values of the relevant configuration registers BAR10, BAR54, BAR58, BAR18, BAR1C, BAR20, BAR24 and BAR30 are read sequentially by the busybox tool of the Loongson 3A5000 operating system and cached locally as intermediate values.
[0027] Figure 2 This is a schematic diagram of the connection between the Loongson 3A5000 and PCIe peripherals provided by this invention, as shown below. Figure 2 As shown, the Loongson 3A5000 processor is connected to the Loongson 7A1000 bridge chip via the HyperTransport X16 interface. This bridge chip is responsible for transferring CPU data to the PCIe bus. The PCIe hard core is integrated into an FPGA chip, which implements the PCIe 2.0 standard specification, allowing the FPGA to function as a PCIe peripheral. Finally, within the FPGA, the functional logic of the PCIe peripheral can be loaded actively or passively to achieve different functions.
[0028] It is important to note that the hardware design of the gold fingers of the Loongson 3A5000 and 7A1000 chipsets and PCIe peripherals requires attention to the design of the reset signal: the reset signal of the PCIe interface of the 7A1000 chipset needs to be shielded during the design, and the global reset signal on the PCB should be used instead to ensure that no reset signal is sent to the FPGA chip of the PCIe peripheral when the Loongson 3A5000 is operating on the registers.
[0029] Step 102: When it is necessary to switch the function of a PCIe peripheral, notify the PCIe peripheral to prepare to switch to the new function and uninstall the current PCIe driver.
[0030] When the Loongson 3A5000 processor needs to change the function of a PCIe peripheral, it notifies the PCIe peripheral to change the specified function and uninstalls the driver of the PCIe peripheral to prevent the program from communicating with the PCIe peripheral and blocking the PCIe channel.
[0031] Step 103: The FPGA chip of the PCIe peripheral loads the logic file of the new function in an active or passive manner.
[0032] Active loading includes: the FPGA chip actively downloading and loading new functional logic files via a network or local storage device;
[0033] Passive loading includes: the FPGA chip receiving the logic file of new functions transmitted by the host system (Loongson 3A5000) through a specific communication protocol.
[0034] Optionally, the specific communication protocol includes the following two:
[0035] JTAG is a standard testing protocol commonly used for boundary scan testing and programming of chips. FPGA chips typically have a JTAG interface, through which they can be programmed.
[0036] SPI is a synchronous serial communication interface commonly used for short-distance communication. FPGA chips can load new functional logic from external memory (such as SPI Flash) through the SPI interface.
[0037] Step 104: Disconnect the connection between Loongson 3A5000 and the PCIe peripheral. Using the previously read PCIe node number and the value of the relevant configuration register, write back the relevant configuration register of the PCIe peripheral and enable the PCIe peripheral.
[0038] After the FPGA finishes loading the logic file, the Loongson 3A5000 sequentially writes back the values of the relevant configuration registers. Finally, it writes back the status and command registers of the PCIe peripherals to enable them.
[0039] Step 105: First, uninstall the PCIe peripheral, then perform a second scan on the PCIe peripheral to complete the re-establishment of the connection between the Loongson 3A5000 and the PCIe peripheral.
[0040] Optionally, the present invention can use the first instruction and the PCIE node number of the PCIE peripheral to unload the PCIE peripheral; and the present invention can use the second instruction to perform a second scan on the PCIE peripheral of Loongson 3A5000, and complete the re-establishment of the link between Loongson 3A5000 and the PCIE peripheral.
[0041] Optionally, the PCIE peripheral secondary scanning link establishment method based on the Loongson 3A5000 and 7A1000 chipsets provided by the present invention further includes: loading the driver of the new functional mode of the PCIE peripheral to complete the invocation of the new function of the PCIE peripheral.
[0042] Based on the above embodiments, as an optional embodiment, the PCIe peripheral secondary scan connection establishment method based on the Loongson 3A5000 and 7A1000 chipsets provided by the present invention includes the following steps:
[0043] Step 1: The hardware design of the PCIe signal of the 7A1000 domestic bridge chip requires shielding the reset signal of the PCIe interface of the 7A1000 bridge chip and using the global reset signal on the PCB instead.
[0044] Step 2: Wait for the Loongson 3A5000 and the PCIe peripheral to power on simultaneously. The initial functions of the PCIe peripheral will be loaded by default. At this time, record the PCIe node number and the values of the relevant configuration registers. After the operating system starts up, the default driver will be loaded to call the PCIe peripheral.
[0045] Step 3: When it is necessary to switch the function of the PCIe peripheral, first notify the PCIe peripheral to switch to the specified function, then uninstall the PCIe peripheral driver and wait for the new function of the PCIe peripheral's FPGA chip to be loaded.
[0046] Step 4: Depending on the hardware design, the FPGA chip of the PCIe peripheral can be either actively or passively loaded with logic files for specific functions.
[0047] Step 5: After the FPGA resources of the PCIe peripheral are fully loaded, the 3A5000 will disconnect from the PCIe peripheral. You need to write back the registers using the previously read PCIe register values, and finally configure the PCIe command and status registers to re-enable the device.
[0048] Step 6: First remove the PCIe peripheral, then execute the PCIe peripheral's rescan function to complete the secondary link establishment between the 3A5000 and the PCIe peripheral.
[0049] Step 7: Load the driver for the new PCIe peripheral function to complete the invocation of the new PCIe peripheral function.
[0050] Based on the above embodiments, as an optional embodiment, the PCIe peripheral secondary scan connection establishment method based on the Loongson 3A5000 and 7A1000 chipsets provided by the present invention includes the following steps:
[0051] A. The PCIe peripheral is powered on along with the Loongson 3A5000 processor. The slot node number of the PCIe peripheral is queried, and the relevant configuration register information of the node is read.
[0052] B. When the PCIe peripheral function needs to be switched, the Loongson 3A5000 processor first notifies the PCIe peripheral to switch to the specified function, then uninstalls the PCIe peripheral driver, and the FPGA of the PCIe peripheral actively or passively loads the logic file of the specified function.
[0053] C. After the new logic function of the PCIe peripheral FPGA is loaded, the Loongson 3A5000 will lose its connection with the PCIe peripheral;
[0054] D. The Loongson 3A5000 processor sequentially writes back the configuration register of the previously read PCIe peripheral and enables the command and status register of the PCIe peripheral, thus enabling the PCIe peripheral.
[0055] E. The Loongson 3A5000 processor first removes the PCIe device using instructions, and then performs a second scan of the PCIe device using instructions to re-establish the connection between the Loongson 3A5000 processor and the PCIe peripheral.
[0056] F. Reloading the PCIe peripheral driver on the Loongson 3A5000 processor will allow you to access the new functions of that PCIe peripheral.
[0057] In summary, the PCIe peripheral secondary scanning connection establishment method based on the Loongson 3A5000 and 7A1000 chipsets provided by this invention has the following beneficial effects:
[0058] (1) The function of the PCIE peripheral can be switched at will, achieving seamless switching of the PCIE peripheral function;
[0059] (2) The 3A5000 domestic processor can also be used to perform secondary scanning and link establishment of PCIE peripherals, achieving the same function as imported x86 processors.
[0060] The foregoing description is merely an exemplary embodiment of this disclosure and should not be construed as limiting the scope of this disclosure. Any equivalent changes and modifications made in accordance with the teachings of this disclosure shall still fall within the scope of this disclosure. Those skilled in the art will readily conceive of embodiments of this disclosure upon considering the specification and practicing the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not described herein. The specification and embodiments are to be considered exemplary only, and the scope and spirit of this disclosure are defined by the claims.
[0061] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0062] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A method for secondary scanning and link establishment of PCIe peripherals based on Loongson 3A5000 and 7A1000 chipsets, characterized in that, include: Establish a link between the Loongson 3A5000 and the PCIe peripheral, load the PCIe driver for the PCIe peripheral, and obtain the PCIe node number and related configuration register values of the PCIe peripheral. The related configuration registers include BAR10, BAR54, BAR58, BAR18, BAR1C, BAR20, BAR24, and BAR30. The Loongson 3A5000 connects to the PCIe peripheral via the 7A1000 chipset. When it is necessary to switch the function of a PCIe peripheral, notify the PCIe peripheral to prepare to switch to the new function and uninstall the current PCIe driver. The FPGA chip of the PCIe peripheral loads the logic file of the new function in an active or passive manner; Disconnect the connection between Loongson 3A5000 and PCIE peripherals, use the previously read PCIE node number and related configuration register values to write back the relevant configuration registers of the PCIE peripherals, and enable the PCIE peripherals by configuring the status and command registers of the PCIE peripherals; First, uninstall the PCIe peripherals, then perform a second scan on the PCIe peripherals to complete the re-establishment of the link between the Loongson 3A5000 and the PCIe peripherals. The hardware design for connecting the 7A1000 chipset to the gold fingers of PCIe peripherals includes: shielding the reset signal of the 7A1000 chipset's PCIe interface and using a global reset signal on the PCB.
2. The PCIe peripheral secondary scan connection establishment method based on Loongson 3A5000 and 7A1000 chipsets according to claim 1, characterized in that, Also includes: Load the driver for the new function mode of the PCIe peripheral to enable the invocation of the new function of the PCIe peripheral.
3. The PCIe peripheral secondary scan connection establishment method based on Loongson 3A5000 and 7A1000 chipsets according to claim 1, characterized in that, The values of the relevant configuration registers for PCIe peripherals are read using the busybox tool in the Loongson 3A5000 operating system.
4. The PCIe peripheral secondary scan connection establishment method based on Loongson 3A5000 and 7A1000 chipsets according to claim 1, characterized in that, First, uninstall the PCIe peripherals, then perform a second scan of the PCIe peripherals, including: Unload the PCIe peripheral using the first instruction and the PCIe node number of the PCIe peripheral; and, The second instruction is used to perform a secondary scan of the PCIe peripherals of the Loongson 3A5000, and to re-establish the link between the Loongson 3A5000 and the PCIe peripherals.
5. The PCIe peripheral secondary scan connection establishment method based on Loongson 3A5000 and 7A1000 chipsets according to claim 1, characterized in that, FPGA chips actively load logic files for new functions, including: The FPGA chip actively downloads and loads new functional logic files via a network or local storage device.
6. The PCIe peripheral secondary scan connection establishment method based on Loongson 3A5000 and 7A1000 chipsets according to claim 1, characterized in that, FPGA chips passively load logic files for new functions, including: The FPGA chip receives the logic file for new functions transmitted by Loongson 3A5000 through a specific communication protocol.