Compact k-xor-sat filtering using cams

Abstract

Examples of the technology of the present disclosure relate to compact k-XOR-SAT filtering with CAMs. Specifically, CAM-based circuits are provided that are specifically constructed to implement Boolean satisfiability problems involving k-XOR-SAT clauses. By strategically adding auxiliary counting and logic circuits that evaluate the match line voltage output of a CAM at k discrete times to determine whether the counted number of matches returned by the match line satisfies a predetermined parity condition (where k represents the number of literal values of a k-XOR-SAT clause of the Boolean satisfiability problem), the circuits of the present technology can utilize a common CAM (i.e., the same CAM) to implement both k-XOR-SAT clauses and k-SAT clauses. Thus, as compared to existing hardware accelerators, such versatile circuits can be used to implement k-XOR-SAT and k-SAT-k-XOR-SAT mixed problems in less time and with less hardware and power consumption.

Description

Background Technology

[0001] The Boolean satisfiability problem (i.e., the propositional satisfiability problem, abbreviated as satisfiability, SAT, or B-SAT) involves determining whether there exists an interpretation that satisfies a Boolean formula (sometimes referred to in this text as a Boolean satisfiability formula). For example, the SAT problem attempts to determine whether the variables of a Boolean formula can be consistently replaced by true or false values ​​in such a way that the Boolean formula evaluates to true. If this is the case, the Boolean formula is said to be satisfiable. For example, the Boolean formula "a AND NOT b" is satisfiable because the values ​​a = true and b = false would make the Boolean formula "a AND NOT b" = true. On the other hand, if the variables of a Boolean formula cannot be consistently replaced by true or false values ​​in such a way that the Boolean formula evaluates to true, then the Boolean formula is unsatisfiable. For example, "a AND NOT a" is unsatisfiable.

[0002] Content-addressable memory (“CAM”) is a type of computational memory in which stored data is searched by its content rather than its location. When a “word” is input into a CAM, the CAM searches for the word in its content. If the CAM finds the word (i.e., “returns a match”), the CAM returns the address of the location where the found word resides. The individual cells of the CAM (i.e., CAM cells) can be arranged in rows and columns. CAM cells of a common row can be connected along a common match line. Words can be stored along rows of the CAM, and each CAM cell in a given row can store an entry of the stored word. When the CAM receives an input word (e.g., a series of voltage signals, each voltage signal representing an entry of the input word, sometimes referred to herein as an input vector), the CAM can search for the input word entry by entry along the columns of the CAM (i.e., the first entry of the input word can be searched down along the first column of the CAM, the second entry of the input word can be searched down along the second column of the CAM, and so on). If all CAM cells in a given row return a match for their respective entries of the input word, then the CAM has “found” the input word in that given row. Attached Figure Description

[0003] This disclosure is described in detail with reference to the following accompanying drawings, based on one or more various embodiments. The drawings are provided for illustrative purposes only and are merely examples.

[0004] Figure 1 An example CAM unit is depicted, illustrating an example of the technology according to this disclosure.

[0005] Figure 2 An example CAM depicts an example of the technology according to this disclosure.

[0006] Figure 3A Another example of CAM depicting an example of the technology according to this disclosure.

[0007] Figure 3B Examples of the technology according to this disclosure are depicted for use Figure 3A Example truth table for evaluating the CAM to k-SAT clause.

[0008] Figure 4A An example CAM-based circuit for implementing the k-XOR-SAT clause is depicted, illustrating an example of the technology according to this disclosure.

[0009] Figure 4B Examples of the technology according to this disclosure are depicted for use Figure 4A An example truth table for evaluating the k-XOR-SAT formula using a CAM-based circuit.

[0010] Figure 5 An example diagram illustrating an example of the technology according to this disclosure is provided, illustrating a comparison between a threshold voltage and the voltage output of a matching line associated with a row of CAM cells, which are programmed to store k-XOR-SAT clauses.

[0011] Figure 6 An example flowchart illustrating an example of the technology according to this disclosure for solving Boolean satisfiability problems using CAM-based circuitry is provided.

[0012] Figure 7 A block diagram of an example computer system is depicted, in which the various examples described herein can be implemented.

[0013] The accompanying drawings are not exhaustive and do not limit this disclosure to the precise form disclosed. Detailed Implementation

[0014] The k-SAT problem is a type of SAT problem characterized by the number of variables V, the number of literals k, and the number of clauses C. A k-SAT clause typically consists of k literals. The literals in a k-SAT clause are either variables or their negations. Conjunctive Normal Form (CNF) (specifically, where each k-SAT clause has k = 3 literals) is often considered the canonical representation of a k-SAT formula. In CNF, k-SAT clauses are disjunctions of literals (i.e., logical OR operations), and k-SAT formulas are conjunctions of k-SAT clauses (i.e., logical AND operations). A k-SAT formula can also be converted to Disjunctive Normal Form (DNF), where k-SAT clauses are conjunctions of literals (i.e., logical AND operations), and k-SAT formulas are disjunctions of k-SAT clauses (i.e., logical OR operations). The k-SAT problem is a nondeterministic polynomial-time (NP) hard problem and is among the first problems proven to be NP-complete. All problems in the NP-hard complexity class (which includes a wide range of natural decision and optimization problems) are at most as difficult to solve as the k-SAT problem.

[0015] Because the k-SAT problem is a cornerstone of many industrial and scientific problems (such as electronic design automation and cryptography), various hardware accelerators have been specifically designed to implement (i.e., represent and evaluate) the k-SAT problem. For example, certain solvers based on quadratic unconstrained bivariate optimization (QUBO), Ising machines, and CAMs have been specifically designed to implement the k-SAT problem. In the case of a specially designed CAM, clauses of the k-SAT problem / formula can be programmed into the corresponding rows of the CAM, and each CAM cell in a given row can be programmed to represent the literal value of the corresponding k-SAT clause. An input vector (e.g., representing a set of variables) can then be applied down the columns of the CAM to evaluate whether the set of variables represented by that input vector satisfies the k-SAT clause programmed into the CAM.

[0016] While many industrial and scientific optimization problems can be formulated as k-SAT problems, some optimization problems are better formulated in different ways. For example, some optimization problems (such as low-density parity checking (LDPC) in networked systems) are best represented as k-XOR-SAT problems (i.e., Boolean satisfiability problems expressed using k-XOR-SAT clauses). Relatedly, some optimization problems are best represented as "k-SAT-k-XOR-SAT hybrid problems" that include combinations of k-SAT clauses and k-XOR-SAT clauses.

[0017] Unlike k-SAT clauses (in CNF) which include a logical OR operation between constituent literals, k-XOR-SAT clauses include a logical XOR operation between their constituent literals. This seemingly minor difference has a significant impact on problem type / classification. For example, k-SAT problems (i.e., Boolean satisfiability problems expressed using k-SAT clauses) are NP-hard problems, while k-XOR-SAT problems (i.e., Boolean satisfiability problems expressed using k-XOR-SAT clauses) are polynomial (P) problems. P problems can be solved in polynomial time and are generally easier to represent and solve than NP-hard problems. Therefore, representing native k-XOR-SAT optimization problems as k-XOR-SAT problems instead of k-SAT problems (or using k-XOR-SAT clauses instead of k-SAT clauses) reduces the complexity of the optimization problem.

[0018] Unfortunately, the aforementioned hardware accelerators, specifically designed for implementing (i.e., representing and evaluating) the k-SAT problem, typically cannot natively implement k-XOR-SAT clauses. Therefore, implementing the k-XOR-SAT problem using these existing hardware accelerators usually involves restating the k-XOR-SAT problem as a k-SAT problem, which generally increases problem complexity (e.g., the number of variables involved) and shifts the evaluation of the k-XOR-SAT problem from polynomial time to non-polynomial time. Thus, restating the k-XOR-SAT problem as a k-SAT problem generally increases the amount of time, hardware, and power required to implement the k-XOR-SAT problem. Relatedly, implementing hybrid k-SAT-k-XOR-SAT problems (i.e., problems expressed using a combination of k-SAT clauses and k-XOR-SAT clauses) using these existing hardware accelerators usually involves restating the constituent k-XOR-SAT clauses as k-SAT clauses. Furthermore, such restatements increase the complexity of the problem, thereby increasing the amount of time, hardware, and power required to implement the k-SAT-k-XOR-SAT hybrid problem.

[0019] In this context, examples of the techniques disclosed herein provide CAM-based circuits specifically designed to implement Boolean satisfiability problems involving k-XOR-SAT clauses. By strategically adding auxiliary counting and logic circuitry to evaluate the CAM's matching line voltage output at k discrete times to determine whether the counted matches returned by the matching line satisfy a predetermined parity condition (where k represents the number of literals in the k-XOR-SAT clause of the Boolean satisfiability problem), the circuits of this technique can implement both k-XOR-SAT clauses and k-SAT clauses using a common CAM (i.e., the same CAM). Therefore, such highly versatile circuits can be used to implement k-XOR-SAT and k-SAT-k-XOR-SAT hybrid problems in less time and with less hardware and power consumption compared to existing hardware accelerators.

[0020] The circuitry of this disclosure may include: (1) a row CAM unit programmed to store a k-XOR-SAT clause of a Boolean satisfiability problem; (2) a sense amplifier that, in response to an input vector being applied to the row CAM unit, compares the voltage output of the matching line associated with the row CAM unit with a threshold voltage over k discrete times, where k represents the number of literals in the k-XOR-SAT clause; (3) a counter circuit that counts the number of matches returned by the matching line based on the k voltage comparisons by the sense amplifier (e.g., the counted number of matches may correspond to the number of k voltage comparisons in which the voltage output of the matching line exceeds the threshold voltage); and (4) a logic circuit that outputs a signal indicating that the input vector satisfies the k-XOR-SAT clause based on the counted number of matches satisfying a predetermined parity condition (e.g., the counted number of matches includes odd matches). The row CAM unit may include at least k literal-representation CAM units. One of the k literal representation CAM cells can be programmed to store a literal of a k-XOR-SAT clause.

[0021] In various examples, a literal representation CAM cell can be programmed to: (a) store a first value when the literal value is negated in a k-XOR-SAT clause; and (b) store a second value when the literal value is not negated in a k-XOR-SAT clause. As will be described in more detail below, programming a literal representation CAM cell to store the literal value of a k-XOR-SAT clause may include programming the conductance of one or more memristors included in the literal representation CAM cell. As mentioned above, the circuit can also be used to represent / evaluate k-SAT clauses of Boolean satisfiability problems. In other words, Boolean satisfiability problems may include mixed k-SAT and k-XOR-SAT problems. For example, the circuit may further include: (1) a second row CAM unit programmed to store a k-SAT clause of a Boolean satisfiability problem; and (2) a processor that determines, in response to receiving: (a) a signal indicating that the input vector satisfiability problem is satisfied by: (a) a signal indicating that the input vector satisfiability problem is satisfied by a k-XOR-SAT clause; and (b) a second signal indicating that the input vector satisfiability problem is satisfied by a k-SAT clause (such signal may be based on a comparison between a threshold voltage and the voltage of a matching line associated with the second row CAM unit).

[0022] As mentioned above, the CAM-based circuitry of this technique offers numerous advantages over existing hardware accelerators used to implement the Boolean satisfiability problem.

[0023] For example, existing CAMs designed to implement k-SAT problems typically require restating k-XOR-SAT clauses to k-SAT clauses in order to implement k-XOR-SAT problems and / or mixed k-SAT-k-XOR-SAT problems. Such restatements increase problem complexity, thereby increasing the amount of time, hardware, and power required to represent and evaluate such problems. In contrast, the CAM-based circuitry of this technique can utilize a common CAM to implement k-XOR-SAT clauses and k-SAT clauses by strategically adding auxiliary counting and logic circuitry to evaluate the CAM's matched line voltage output at k discrete times to determine whether the counted matches returned by the matched line satisfy a predetermined parity condition (where k represents the number of literals in the k-XOR-SAT clause of the Boolean satisfiability problem). Therefore, this highly versatile circuitry can be used to implement k-XOR-SAT and mixed k-SAT-k-XOR-SAT problems in less time and with less hardware and power consumption compared to existing CAMs.

[0024] Using CAM-based circuits to implement k-XOR-SAT problems and / or mixed k-SAT-k-XOR-SAT problems can be faster / more efficient than using other types of hardware accelerators (e.g., QUBO-based solvers and Ising machines). For example, leveraging the unique parallel search capabilities of CAM, the circuits of this disclosure can evaluate the input vector against all (potentially many) clauses of the Boolean satisfiability problem in a single search operation. In other words, for the CAM-based circuits of this disclosure, the amount of time required to evaluate the Boolean satisfiability problem remains approximately constant, even as the number of clauses used to express the Boolean satisfiability problem (e.g., k-XOR-SAT clauses and / or k-SAT clauses) increases. Therefore, compared to other types of hardware accelerators that lack this unique parallel search capability (e.g., QUBO-based solvers and Ising machines), the CAM-based circuitry of this disclosure can evaluate large / complex Boolean satisfiability problems (i.e., Boolean satisfiability problems expressed using a large number of k-XOR-SAT clauses and / or k-SAT clauses) much faster.

[0025] Examples of the techniques disclosed herein will be described in more detail with the help of the following figures.

[0026] Figure 1 An example CAM cell 100 is depicted, illustrating an example of the technology according to this disclosure. CAM cell 100 may be an example of a 4-transistor-2-memristor (4T2M) CAM cell, which can be used in CAM-based circuits of the technology of this disclosure. For example, CAM cell 100 may be programmed to represent a literal value of a k-XOR-SAT clause or a k-SAT clause.

[0027] As depicted, the CAM unit 100 includes a switching transistor T1 connected to the data line SL and a reverse data line. The switching transistor T2. As mentioned above, the data line SL and the reverse data line... The voltages across the terminals can correspond to the values / entries (e.g., voltage signals) of the input vector applied to the CAM (CAM unit 100 is part of the CAM). For example, the voltages across the data line SL can correspond to the values / entries (e.g., logic 1) of the input vector, while the voltages across the reverse data line... The voltage across the terminals corresponds to the negation form of the input vector value / entry (e.g., logic 0). Memristor M2 is connected to switching transistor T1, and memristor M1 is connected to switching transistor T2. As depicted, the gate terminals of switching transistors T1 and T2 are connected to word line WL, which biases switching transistors T1 and T2. Immediately before and during the search / match operation, the voltage across word line WL can increase above a threshold, thereby activating switching transistors T1 and T2. When switching transistor T1 is activated, it provides an electrical connection between data line SL and memristor M2. In contrast, when switching transistor T1 is not activated (i.e., when the voltage across word line WL is below a threshold), data line SL and memristor M2 are electrically disconnected. Similarly, when switching transistor T2 is activated, it can reverse the data line. An electrical connection is provided between the transistor and memristor M1. In contrast, when the switching transistor T2 is not activated (i.e., when the voltage across word line WL is below a threshold), the reverse data line... Memristor M1 can be electrically disconnected. Therefore, including switching transistors T1 and T2 ensures that memristors M1 and M2 are disconnected from the data lines of CAM unit 100 when no search / match operation is performed, which can reduce the overall power consumption of CAM unit 100.

[0028] As depicted, memristors M1 and M2 are connected in series to form a resistive voltage divider 102. The output voltage of the resistive voltage divider 102 (i.e., the voltage at the common node G) is applied to the gate of the matching line transistor T4 to control its activation. When the matching line transistor T4 is activated, it can discharge (i.e., "pull down") the voltage across the matching line ML. For example, if the voltage applied to the gate of the matching line transistor T4 exceeds a threshold, the matching line transistor T4 will activate and discharge (i.e., "pull down") the voltage across the matching line ML, thus returning to mismatch. In contrast, when the voltage applied to the gate of the matching line transistor T4 is less than or equal to the threshold, the matching line transistor T4 may not be activated. Therefore, the matching line transistor T4 will not discharge (i.e., "pull down") the voltage across the matching line ML, thus returning to match. Although in Figure 1 The specific example describes the "pull-down" logic, but it should be understood that in other examples, CAM unit 100 may instead implement the "pull-up" logic.

[0029] As mentioned above, CAM unit 100 can be programmed to store the literal value of a k-XOR-SAT clause or a k-SAT clause by programming the conductances of memristors M1 and M2. While the programmed conductances of memristors M1 and M2 will generally remain the same, unless reprogrammed, the output voltage of the resistor divider 102 (i.e., the voltage at the common node G) will be based on the voltage generated by memristors M2 and M1 from the data line SL and the reverse data line, respectively. The voltage value received changes. For example, memristors M1 and M2 can be programmed to a first conductance state (e.g., a logic 0 conductance state, which may correspond to a negative literal value), when the voltage is received from the data line SL and the reverse data line. When the received voltage represents logic 1, this first conductance state causes the output voltage of the resistor divider to be high (e.g., exceeding a threshold), thus activating the matching line transistor T4 and when the data line SL and the reverse data line... A voltage across the terminals indicates a logic 1, returning a mismatch. In contrast, memristors M1 and M2 can be programmed to a second conductance state (e.g., a logic 1 conductance state, which corresponds to a non-negative literal value), when connected from the data line SL and the reverse data line. When the received voltage represents logic 0, this second conductance state causes the output voltage of the resistor divider to be high (e.g., exceeding a threshold), thus activating the matching line transistor T4 and when the data line SL and the reverse data line... The voltage across the terminals indicates a logic 0, returning a mismatch. As described in more detail below, in various examples, memristors M1 and M2 can be programmed to a third conductance state (e.g., a wildcard conductance state, which may correspond to a variable not included in a k-XOR-SAT or k-SAT clause), which causes the output voltage of the resistive voltage divider to remain low (e.g., below a threshold), regardless of the voltage from the data line SL and the reverse data line. The received voltage indicates either logic 0 or logic 1, therefore ensuring that the matching line transistor T4 remains inactive, and when the data line SL and the reverse data line... The voltage at both ends indicates a match when logic 0 or logic 1 is represented.

[0030] As depicted, the service line transistor T3 can work in conjunction with the switching transistor T1 and / or the switching transistor T2 to program the conductance of memristors M1 and M2 using the service line SX.

[0031] It should be understood that CAM unit 100 is merely one example of a CAM unit that may be included in CAM-based circuits of the present technology. Generally, any type of CAM unit that can be programmed to represent literal values ​​of k-XOR-SAT or k-SAT clauses can be used. For example, examples of the technology disclosed herein may utilize a six-transistor-two-memristor (6T2M) CAM unit, a three-terminal CAM unit, a 16-transistor (16T) ternary CAM (TCAM) unit, etc.

[0032] Figure 2 Example CAM 200 is depicted as an example of the technology according to this disclosure. CAM 200 can be programmed to represent Boolean satisfiability problems, such as k-SAT problems, k-XOR-SAT problems, or mixed k-SAT-k-XOR-SAT problems.

[0033] As described above, a content-addressable memory (“CAM”) is a type of computational memory in which stored data is searched by its content rather than its location. When a “word” is input into a CAM, the CAM searches for that word in its content. If the CAM finds the word (i.e., “returns a match”), the CAM returns the address of the location where the found word resides. The individual cells of the CAM (i.e., CAM cells) can be arranged in rows and columns. CAM cells of a common row can be connected along a common match line. Words can be stored along rows of the CAM, and each CAM cell in a given row can store an entry of the stored word. When the CAM receives an input word (e.g., a series of voltage signals, each voltage signal representing an entry of the input word, sometimes referred to herein as an input vector), the CAM can search for the input word entry by entry along the columns of the CAM (i.e., the first entry of the input word can be searched down along the first column of the CAM, the second entry of the input word can be searched down along the second column of the CAM, and so on). If all CAM cells in a given row return a match for their respective entries of the input word, then the CAM has “found” the input word in that given row.

[0034] Because the k-SAT problem is a cornerstone of many industrial and scientific problems (such as electronic design automation and cryptography), various hardware accelerators have been specifically designed to implement (i.e., represent and evaluate) the k-SAT problem. For example, certain CAMs (e.g., CAM 200) have been specifically designed to implement the k-SAT problem. For instance, clauses of a k-SAT problem / formula can be programmed into the corresponding rows of a CAM 200, and each CAM cell in a given row can be programmed to represent the literal value of the corresponding k-SAT clause. An input vector (e.g., representing a set of variables) can then be applied down the columns of the CAM 200 to evaluate whether the set of variables represented by that input vector satisfies the k-SAT clause programmed into the CAM 200.

[0035] As described above, while many industrial and scientific optimization problems can be formulated as k-SAT problems, some optimization problems are better formulated in different ways. For example, some optimization problems (such as low-density parity checking (LDPC) in networked systems) are better represented as kk-XOR-SAT problems (i.e., Boolean satisfiability problems expressed using k-XOR-SAT clauses). Relatedly, some optimization problems are better represented as "k-SAT-k-XOR-SAT hybrid problems" that include combinations of k-SAT clauses and k-XOR-SAT clauses.

[0036] Unlike k-SAT clauses (in CNF) which include a logical OR operation between constituent literals, k-XOR-SAT clauses include a logical XOR operation between their constituent literals. This seemingly minor difference has a significant impact on problem type / classification. For example, k-SAT problems (i.e., Boolean satisfiability problems expressed using k-SAT clauses) are NP-hard problems, while k-XOR-SAT problems (i.e., Boolean satisfiability problems expressed using k-XOR-SAT clauses) are polynomial (P) problems. P problems can be solved in polynomial time and are generally easier to represent and solve than NP-hard problems. Therefore, representing native k-XOR-SAT optimization problems as k-XOR-SAT problems instead of k-SAT problems (or using k-XOR-SAT clauses instead of k-SAT clauses) reduces the complexity of the optimization problem.

[0037] Unfortunately, many hardware accelerators (e.g., CAM 200) specifically designed for implementing (i.e., representing and evaluating) the k-SAT problem often cannot natively implement k-XOR-SAT clauses. Therefore, implementing the k-XOR-SAT problem on the CAM 200 using conventional techniques typically involves restating the k-XOR-SAT problem as a k-SAT problem, which generally increases problem complexity (e.g., the number of variables involved) and shifts the evaluation of the k-XOR-SAT problem from polynomial time to non-polynomial time. Thus, restating the k-XOR-SAT problem as a k-SAT problem generally increases the amount of time, hardware, and power required to implement the k-XOR-SAT problem. Relatedly, implementing a hybrid k-SAT-k-XOR-SAT problem (i.e., a problem expressed using a combination of k-SAT clauses and k-XOR-SAT clauses) on the CAM 200 using conventional techniques typically involves restating the constituent k-XOR-SAT clauses as k-SAT clauses. Furthermore, such restatements increase the complexity of the problem, thereby increasing the amount of time, hardware, and power required to implement the k-SAT-k-XOR-SAT hybrid problem.

[0038] To address the aforementioned drawbacks of conventional techniques / crafts, examples of the techniques disclosed herein provide CAM-based circuits specifically constructed to implement Boolean satisfiability problems involving k-XOR-SAT clauses. By strategically adding auxiliary counting and logic circuitry to evaluate the CAM's matching line voltage output at k discrete times to determine whether the counted matches returned by the matching line satisfy a predetermined parity condition (where k represents the number of literals in the k-XOR-SAT clause of the Boolean satisfiability problem), the circuits of this technique can implement both k-XOR-SAT clauses and k-SAT clauses using a common CAM (i.e., the same CAM). Therefore, such highly versatile circuits can be used to implement k-XOR-SAT and k-SAT-k-XOR-SAT hybrid problems in less time and with less hardware and power consumption compared to existing hardware accelerators.

[0039] The circuitry of this disclosure may include: (1) a row CAM unit programmed to store k-XOR-SAT clauses of a Boolean satisfiability problem (e.g., a row CAM 200); (2) a sense amplifier ( Figure 2 Not described in the text, but Figure 4A (described in the text), which, in response to the input vector applied to the row CAM cell, compares the voltage output of the matching line associated with the row CAM cell with a threshold voltage over k discrete times, where k represents the literal number of the k-XOR-SAT clause; (3) Counter circuit ( Figure 2 Not described in the text, but Figure 4A (described in the text), which counts the number of matches returned from the matching line based on k voltage comparisons of the sensing amplifier (e.g., the counted number of matches corresponds to the number of k voltage comparisons in which the voltage output of the matching line exceeds the threshold voltage); and (4) logic circuitry ( Figure 2 Not described in the text, but Figure 4A (As described in the text), it outputs a signal indicating that the input vector satisfies the k-XOR-SAT clause based on the counted number of matches satisfying a predetermined parity condition (e.g., the counted number of matches includes odd matches). This row of CAM units may include at least k literal representation CAM units. One of the k literal representation CAM units (e.g., ...) Figure 2 The CAM unit 100 can be programmed to store a literal value of a k-XOR-SAT clause.

[0040] In various examples, a literal representation CAM cell can be programmed to: (a) store a first value when the literal value is negated (e.g., logic 0) in a k-XOR-SAT clause; and (b) store a second value when the literal value is not negated (e.g., logic 1) in a k-XOR-SAT clause. As will be described in more detail below, programming a literal representation CAM cell to store the literal value of a k-XOR-SAT clause may include programming the conductance of one or more memristors included in the literal representation CAM cell (e.g., programming the conductance of memristors M1 and M2 of CAM cell 100). As mentioned above, the circuit can also be used to implement k-SAT clauses for Boolean satisfiability problems. In other words, Boolean satisfiability problems may include mixed k-SAT and k-XOR-SAT problems. For example, the circuit may further include: (1) a second row CAM unit (e.g., second row CAM 200) programmed to store a k-SAT clause of a Boolean satisfiability problem; and (2) a processor (not depicted) that determines, in response to receiving: (a) a signal indicating that the input vector satisfiability problem is satisfied by: (a) a signal indicating that the input vector satisfiability problem is satisfied by a k-XOR-SAT clause; and (b) a second signal indicating that the input vector satisfiability problem is satisfied by a k-SAT clause (such signal may be based on a comparison between a threshold voltage and the voltage of a matching line associated with the second row CAM unit).

[0041] Refer again Figure 2Certain CAMs (e.g., CAM 200) can be classified as “ternary”. A ternary CAM (“TCAM”) can evaluate an input vector containing binary bits 0, 1, and / or wildcard values ​​for TCAM cells that store / represent bits 0, 1, or wildcard values ​​(as mentioned above, wildcard values ​​are sometimes referred to as “don’t care” or “always match” values). For example, and as mentioned above, one or more memristors of a TCAM cell can be programmed to a first conductance state (e.g., logic 0) that returns to a match when a voltage signal representing logic 0 or a wildcard value is applied to the TCAM cell. In contrast, the one or more memristors of a TCAM cell can be programmed to a second conductance state (e.g., logic 1) that returns to a match when a voltage signal representing logic 1 or a wildcard value is applied to the TCAM cell. Additionally, the one or more memristors of the TCAM unit can be programmed to a third conductance state (e.g., a wildcard conductance state) that returns to a match when a voltage signal representing a logic 0, 1, or wildcard value is applied to the TCAM unit. In various embodiments, CAM 200 may include a TCAM. However, in other embodiments, CAM 200 may include a higher-order CAM (e.g., a quaternary CAM (“QCAM”), an analog CAM (“aCAM”), etc.).

[0042] As depicted, CAM 200 includes columns 202A, 202B, ..., 202L. The number of columns in CAM 200 may be equal to the number of variables V in the total set of variables x1, x2, ..., xL that can be set as the same or as their negation in the Boolean satisfiability formula. Therefore, the columns of CAM 200 may correspond to variables x1, x2, ..., xL, respectively. CAM 200 also includes rows 204A, 204B, ..., 204S. The number of rows in CAM 200 may be equal to the number S of clauses (e.g., k-XOR-SAT clauses and / or k-SAT clauses) that make up the Boolean satisfiability formula. As depicted, the CAM cells of each row may be connected to a common matching line. For example, the CAM cells of row 204A are connected to matching line 212A, the CAM cells of row 204B are connected to matching line 212B, the CAM cells of row 204S are connected to matching line 212S, and so on. As mentioned above, CAM 200 can be an "AND" type CAM, which performs logical AND operations between CAM units in a common row.

[0043] As depicted, CAM cells in a common row can also be connected to a common word line. For example, the CAM cell in row 204A is connected to word line 213A, the CAM cell in row 204B is connected to word line 213B, the CAM cell in row 204S is connected to word line 213S, and so on. As mentioned above, the word lines of CAM 200 can bias the switching transistors that make up the CAM cells, such that the memristors that make up the CAM cells immediately before and during the match / search operation are only electrically connected to the data / reverse data lines of CAM 200, which can reduce the power consumption of CAM 200.

[0044] As depicted, each column of CAM 200 includes a data line (e.g., SL 206A for column 202A, SL 206B for column 202B, SL 206L for column 202L, and so on) and a reverse data line (e.g., for column 202A). 207A, used for column 202B 207B, used for column 202L 207L, and so on). Each column may also include a service line for programming the CAM unit (e.g., SX 208A for column 202A, SX 208B for column 202B, SX 208L for column 202L, and so on).

[0045] As mentioned above, CAM 200 can be programmed to implement (i.e., represent and evaluate) both k-SAT and k-XOR-SAT clauses for the Boolean satisfiability problem. For illustration, this will be discussed in the following paragraphs (including combinations of...). Figures 3A-3B The following describes an exemplary implementation of k-SAT formula 250. As mentioned above, an example of implementing k-SAT clauses on CAM 200 that may not require the techniques of this disclosure is the auxiliary counting and logic circuitry used to implement k-XOR-SAT clauses on CAM-based circuitry.

[0046] As described above, the canonical representation of k-SAT formula 250 can be in conjunctive normal form (CNF). However, k-SAT formula 250 can also be converted to disjunctive normal form (DNF), where: (1) DNF k-SAT formula 252 (i.e., k-SAT formula 250 converted to DNF) is a disjunction (i.e., logical OR operation) of DNF k-SAT clauses; (2) each DNF k-SAT clause (i.e., k-SAT clause converted to DNF) is a conjunction (i.e., logical AND operation) of literals; and (3) the literals of the corresponding DNF k-SAT clauses are the negations of the literals of the corresponding k-SAT clauses in the CNF. For example, if k-SAT formula 250 is represented in the CNF as Then the DNF k-SAT formula 252 can be expressed as: As mentioned above, DNF can be naturally mapped to AND-type CAM (e.g., CAM 200), where the literal value of the DNF k-SAT clause is programmed into the individual CAM cells of the corresponding row.

[0047] For example, by programming the CAM cell in row 204A to correspond to the variable assignments in the DNF k-SAT clause, the DNF k-SAT clause of DNF-k-SAT formula 252 can be programmed into row 204A. Here, the DNF k-SAT clause programmed into row 204A may include the first clause of DNF-k-SAT formula 252. As mentioned above, the columns of CAM 200 may correspond to the total number of V variables in the DNF-k-SAT clause. For example, column 202B may correspond to the second variable x2 in the total set of V variables x1, x2, ..., xV, and therefore the corresponding variable assignment corresponds to variable x2.

[0048] Each DNF k-SAT clause of DNF k-SAT formula 252 can be programmed into the corresponding row of CAM 200 according to the mapping order. Therefore, the inherent AND property of CAM 200 can be used to solve DNF k-SAT formula 252, and by extension, to solve k-SAT formula 250. For example, since (1) DNF k-SAT formula 252 includes multiple DNF k-SAT clauses connected by logical OR, and (2) each DNF k-SAT clause includes multiple literals connected by logical AND, the DNF k-SAT clauses of DNF k-SAT formula 252 can be divided into the corresponding rows of CAM 200 without interfering with DNF k-SAT formula 252. Once DNF k-SAT formula 252 is mapped into rows, each variable within a row can be arranged into a column, so that a guess (i.e., an input vector) can be applied to each variable via each column.

[0049] like Figure 3A As seen, example CAM 300 (which may have the same / similar construction as CAM 200) includes multiple columns 307 and rows 305. Each DNF k-SAT clause of DNF k-SAT formula 252 can be mapped to row 305 of the multiple CAM units 306 according to a mapping order. In one embodiment, the mapping order includes programming a first DNF k-SAT clause including multiple literals to a first row 305A, and programming a second DNF k-SAT clause including multiple literals to a second row 305B. Each of the multiple literals may further include a first value assigned to each non-negative literal (e.g., z), and a value assigned to each negative literal (e.g., z). The second value of ).

[0050] exist Figure 3A In a specific example, k-SAT formula 250 (and by extension, DNF k-SAT formula 252) includes an exemplary 2-SAT formula that includes two literals (i.e., k = 2), three variables (i.e., V = 3), and two k-SAT clauses (i.e., C = 2). In this example, CAM 300 includes an array of CAM cells comprising two rows and three columns. Each DNF k-SAT clause of DNF k-SAT formula 252 is mapped to a row of CAM 300. For example, the first DNF k-SAT clause is mapped to the first row 305A, and the second DNF k-SAT clause is mapped to the second row 305B. Furthermore, each column of CAM 300 includes a variable (e.g., 1, 0, or a wildcard value (“X”)). Each DNF k-SAT clause has k literals chosen from among the V variables. In this example, each DNF k-SAT clause includes two literals. Non-negative literals are programmed as 1 in their corresponding CAM cells, and negative literals are programmed as 0 in their corresponding CAM cells. Variables that do not exist in the DNF k-SAT clause are programmed as 'X' (i.e., wildcard values) in their corresponding CAM cells.

[0051] As mentioned above, the k-SAT formula 250 can be represented in CNF as follows: Then, the k-SAT formula 250 can be converted to DNF as follows: The DNF k-SAT formula 252 can be programmed (i.e., mapped) onto CAM 300. In this example, the first DNF k-SAT clause (x∧y) is programmed into the first line 305A, and the second DNF k-SAT clause... The values ​​are programmed into the second row, 305B. Each literal value within each DNF k-SAT clause is mapped to its own corresponding column, 307A-C. For example, x is mapped to the first column, 307A, y to the second column, 307B, and z to the third column, 307C. Furthermore, depending on whether the literal value is a negative literal, a non-negative literal value, or a non-existent literal value in the corresponding DNF k-SAT clause, a bit value (ternary 0, 1, or "X") is assigned to each literal value. Here, a negative literal value may be assigned a bit value of 0, a non-negative literal value may be assigned a bit value of 1, and a non-existent literal value may be assigned a bit value of 'X' (i.e., a wildcard value). For example, the first DNF k-SAT clause includes the literals x and y. The values ​​of x and y are programmed into CAM 300 such that x is represented as 1 in cell 311, y as 1 in cell 312, and z as "X" in cell 313. Figure 3A Further observation reveals the second DNFk-SAT clause. The second line 305 of CAM 300 is programmed so that x is represented as "X" in cell 314. In cell 315, z is represented as "0", and in cell 316, z is represented as "1". Therefore, the DNF k-SAT expression... The first DNF k-SAT clause (x∧y) is represented as 1 1X in the first line, and the second DNF k-SAT clause It is represented as X 0 1 in the second line.

[0052] like Figure 3A As depicted, each row includes a matching line. For example, cells 311-313 in the first row 305A are connected to the first matching line ML1, and cells 314-316 in the second row 305B are connected to the second matching line ML2.

[0053] As mentioned above, the circuitry of this disclosure can apply each entry (representing a variable) of an input vector (a set of variables to be evaluated for a Boolean satisfiability problem) in parallel to each column of a CAM to determine which clauses of the Boolean satisfiability problem are satisfied. Figure 3A In a specific example, because the k-SAT clause is programmed into CAM300 in DNF, a satisfied DNF k-SAT clause (e.g., corresponding to the matching line output 1) can correspond to an unsatisfied CNF k-SAT clause (and vice versa). For example, if the first DNF k-SAT clause (x∧y) of DNF k-SAT formula 252 is satisfied, then the corresponding first CNF k-SAT clause of k-SAT formula 250... It may not be satisfied (and vice versa). For example, such as Figure 3AAs seen, if the input vector [1 1 0] is applied to CAM 300, the matching line ML1 will return a high voltage value (e.g., a high-order bit value of 1). Here, the matching line ML1 will return a high voltage value because each variable of the input vector (i.e., the input value / entry) matches the value stored in cells 311, 312, and 313, respectively. Additionally, the matching line ML2 will return a low voltage value (e.g., a low-order bit value of 0) because the input vector [1 1 0] does not match the value stored in cells 314, 315, and 316. Therefore, the first CNF k-SAT clause (i.e., the original first k-SAT clause in the CNF) is not satisfied because the corresponding first DNF k-SAT clause is satisfied, while the second CNF k-SAT clause (i.e., the original second k-SAT clause in the CNF) is satisfied because the second DNF k-SAT clause is not satisfied. In contrast, if the input vector [0 0 0] is applied to CAM 300, ML1 and ML2 will return low values ​​(e.g., low-order bit values ​​0) because the input vector does not match the values ​​stored in cells 311, 312, 313, 314, 315, and 316. Since both matching lines ML1 and ML2 return low values, both original CNF k-SAT clauses (i.e., both k-SAT clauses of the Boolean satisfiability formula in CNF) are satisfied, whereas both DNF k-SAT clauses are not satisfied.

[0054] Figure 3B The truth table 370 of the k-SAT formula 250 is described in the figure. When At that time, solve k-SAT formula 250. Each row can be connected to an OR gate to verify whether k-SAT formula 250 is satisfied.

[0055] In an alternative embodiment, the analog value of each matched line can be passed through an analog adder. This analog adder combines the analog values ​​of each matched line (i.e., non-binary signals) to calculate a sum. The sum of the analog values ​​can be returned as an output, which can be used to solve the Boolean satisfiability formula.

[0056] Figure 4AExample CAM-based circuit 400 for implementing k-XOR-SAT clauses, illustrating various examples of the techniques according to this disclosure. Before describing the CAM-based circuit 400 in more detail, some background on the k-XOR-SAT problem / clause may be enlightening. As mentioned above, unlike (in CNF) k-SAT clauses which include a logical OR operation between constituent literals, k-XOR-SAT clauses include a logical XOR operation between their constituent literals. This seemingly minor difference has a significant impact on problem type / classification. For example, the k-SAT problem (i.e., the Boolean satisfiability problem expressed using k-SAT clauses) is an NP-hard problem, while k-XOR-SAT (i.e., the Boolean satisfiability problem expressed using k-XOR-SAT clauses) is a polynomial (P) problem. P problems can be solved in polynomial time and are generally easier to represent and solve than NP-hard problems. Therefore, representing the native k-XOR-SAT optimization problem as a k-XOR-SAT problem instead of a k-SAT problem (or using k-XOR-SAT clauses instead of k-SAT clauses) can reduce the complexity of the optimization problem.

[0057] The k-XOR-SAT formula can be viewed as a system of linear equations with a modulus of 2, and can be solved in polynomial time (e.g., O(V0)). 3 Solving within the O(V) timescale. In other words, if the k-XOR-SAT formula involves V variables, solving the k-XOR-SAT formula may require O(V) timescales. 3 (Number of iterations)

[0058] Example k-XOR-SAT formula 450 may include Here, k-XOR-SAT formula 450 includes four variables (i.e., p, q, r, s) and two k-XOR-SAT clauses (i.e., ... and The input vector (or more specifically, the variable assignments represented by the input vector) satisfies a k-XOR-SAT clause if the number of matches between the input vector and the literals of the corresponding k-XOR-SAT clause satisfies a predetermined parity condition. For example, if the input vector matches the number of odd-numbered literals in a k-XOR-SAT clause, the input vector satisfies the k-XOR-SAT clause. Conversely, if the input vector matches the number of even-numbered literals in a k-XOR-SAT clause, the input vector violates the k-XOR-SAT clause. As mentioned above, the k-XOR-SAT formula is satisfied when both constituent k-XOR-SAT clauses of formula 450 are satisfied. The k-XOR-SAT formula is not satisfied when at least one of the constituent k-XOR-SAT clauses of the k-XOR-SAT formula 450 is not satisfied.

[0059] Refer again Figure 4A The CAM-based circuit 400 includes a CAM 410. In some embodiments, the constituent CAM units of CAM 410 may have the same characteristics as... Figure 1 The CAM unit 100 has the same / similar construction, but this is not required. Generally, any CAM unit that can be programmed to two possible values ​​(e.g., logic 1 or logic 0) can be used in CAM 410.

[0060] As depicted, CAM 410 includes bottom row CAM cells and top row CAM cells. The bottom row CAM cells are associated with a first matching line ML1, and the top row CAM cells are associated with a second matching line ML2. As described in more detail below, the bottom row CAM cells are programmed to store the first k-XOR-SAT clause of the k-XOR-SAT formula 450 (i.e., ), and the CAM cells in the top row are programmed to store the second k-XOR-SAT clause of k-XOR-SAT formula 450 (i.e., Although in Figure 4A In a specific implementation, CAM 410 comprises two rows (i.e., one row for each clause of the k-XOR-SAT formula 450), but in other implementations, CAM 410 may comprise a different number of rows. For example, if the CAM-based circuit 400 is used to implement an arbitrary Boolean satisfiability problem (e.g., including one or more k-XOR-SAT clauses), then the number of rows in CAM 410 may be equivalent to the number of clauses in the Boolean satisfiability problem.

[0061] CAM 410 also includes four columns, and therefore each row of CAM 410 includes four CAM cells. As depicted, the first column of CAM 410 (i.e., the leftmost column) is associated with the variable p of k-XOR-SAT formula 450. The second column of CAM 410 is associated with the variable q of k-XOR-SAT formula 450, the third column of CAM 410 is associated with the variable r of k-XOR-SAT formula 450, and the fourth column of CAM 410 is associated with the variable s of k-XOR-SAT formula 450. Therefore, when an input vector is applied to CAM 410, the first entry of the input vector associated with variable p (e.g., a first voltage signal) can be applied to the first column of CAM 410, the second entry of the input vector associated with variable q (e.g., a second voltage signal) can be applied to the second column of CAM 410, the third entry of the input vector associated with variable r (e.g., a third voltage signal) can be applied to the third column of CAM 410, and the fourth entry of the input vector associated with variable s (e.g., a fourth voltage signal) can be applied to the fourth column of CAM 410. Although in Figure 4A In a specific implementation, CAM 410 includes four columns (i.e., one column for each variable in the k-XOR-SAT formula 450), but in other implementations, CAM 410 may include a different number of columns. For example, if the CAM-based circuit 400 is used to implement an arbitrary Boolean satisfiability problem (e.g., including one or more k-XOR-SAT clauses), then the number of columns in CAM 410 may be equivalent to the number of variables in the Boolean satisfiability problem.

[0062] As mentioned above, the bottom row of CAM 410 is programmed to store the first k-XOR-SAT clause of k-XOR-SAT formula 450 (i.e., ).exist Figure 4A In the example in the specification, logic 1 is used to represent a literal value / variable that is not negated in the clause, logic 0 is used to represent a literal value / variable that is negated in the clause, and the wildcard value (i.e., "X") is used to represent a variable that does not appear in the k-XOR-SAT clause.

[0063] Therefore, because the variable q is not included in the first k-XOR-SAT clause of k-XOR-SAT formula 450, the second CAM unit in the bottom row is programmed to always return a matching wildcard value. This ensures that the second CAM unit in the bottom row does not interrupt the evaluation of the first k-XOR-SAT clause of k-XOR-SAT formula 450. The first, third, and fourth CAM units in the bottom row can be called literal representation CAM units because they are programmed to store the literal values ​​of the first k-XOR-SAT clause of k-XOR-SAT formula 450. In contrast, the second CAM unit in the bottom row can be called a non-literal representation CAM unit because it is programmed to use wildcard values ​​to indicate the fact that the first k-XOR-SAT clause of k-XOR-SAT formula 450 does not include the variable q.

[0064] The top row of CAM 410 is programmed to store the second k-XOR-SAT clause of k-XOR-SAT formula 450 in the same / similar manner (i.e., As depicted, the second to fourth CAM cells in the top row are literal CAM cells, while the first CAM cell in the top row is a non-literal CAM cell, which is programmed to a wildcard value to indicate the fact that the second k-XOR-SAT clause of k-XOR-SAT formula 450 does not include the variable p.

[0065] The CAM-based circuit 400 also includes auxiliary circuitry connected to the first matching line ML1 and the second matching line ML2, respectively. As mentioned above (and described in more detail below), these auxiliary circuitries enable the CAM-based circuit 400 to implement the k-XOR-SAT clause using the same CAM hardware (e.g., CAM 410) used to implement the k-SAT clause.

[0066] As described above, unlike the k-SAT clause (in CNF) which includes a logical OR operation between its constituent literals, the k-XOR-SAT clause includes a logical XOR operation between its constituent literals. Because the XOR operation effectively performs anti-parity checking, an input vector (or more specifically, a set of variable assignments represented by the input vector) satisfies a k-XOR-SAT clause if the number of matches between the input vector and the literals of the corresponding k-XOR-SAT clause satisfies a predetermined parity condition. For example, an input vector satisfies a k-XOR-SAT clause if it matches the number of odd-numbered literals in the clause.

[0067] As the examples of the technology disclosed herein are designed for aesthetic purposes, the voltage of the match line typically decays at a different rate depending on the number of mismatches returned by the CAM unit connected to the match line (in various embodiments, this may be equivalent to the Hamming distance between the input vector and the stored word). That is, as the number of mismatches increases, the voltage of the match line will typically decay faster. In other words, relative to the number of mismatches, as the number of matches increases, the voltage of the match line will typically decay slower. Based on this insight, the examples of the technology disclosed herein can count the number of matches (or conversely, the number of mismatches) returned by the CAM unit connected to the match line based on the decay rate of the match line voltage. For example, the examples can compare the match line voltage to a threshold voltage at multiple discrete times (e.g., at time intervals of 0.25 au seconds) to count the number of matches returned by the match line. For example, the number of matches returned by the match line may correspond to the number of comparisons in which the match line voltage exceeds the threshold voltage.

[0068] Combining the above insights with programming k-XOR-SAT clauses into rows of a CAM, an example can be made to count the number of matches between an input vector and a k-XOR-SAT clause comprising k literals by: (1) comparing a threshold voltage with the voltage of a matching line associated with a row of CAM cells at k discrete times (e.g., at 0.25 au seconds), the row of CAM cells being programmed to store the k-XOR-SAT clauses; and (2) counting the number of matches returned by the matching line based on k voltage comparisons (e.g., the number of comparisons in which the matching line voltage exceeds the threshold voltage). For conceptual illustration, Figure 5 Example graph 500 illustrates a comparison between a threshold voltage and the voltage output of a matching line associated with a row of CAM cells, which are programmed to store a k-XOR-SAT clause comprising k = 3 literal values. As depicted, the threshold voltage is 0.9 au volts, and the matching line voltage is compared to the threshold voltage at three discrete times: t = 10.00 au seconds; t = 10.25 au seconds; and t = 10.50 au seconds. If the matching line returns three matches (as illustrated by curve 502), the matching line voltage will exceed the threshold voltage three times. If the matching line returns two matches (as illustrated by curve 504), the matching line voltage will exceed the threshold voltage twice. If the matching line returns one match (as illustrated by curve 506), the matching line voltage will exceed the threshold voltage once. If the matching line returns zero matches (as illustrated by curve 508), the matching line voltage will exceed the threshold voltage zero times. Here, the threshold voltage and sensing / comparison time can be strategically chosen to accommodate this relationship.

[0069] Refer again Figure 4ACAM 400 includes auxiliary voltage comparison, counting, and logic circuitry for implementing the methods described above. For example, a sensing amplifier 410 is electrically connected to a first matching line ML1 associated with the bottom row of CAM 410. Therefore, the sensing amplifier 410 can receive the voltage output of the first matching line ML1 and compare the voltage output of the first matching line ML1 with a threshold voltage over k = 3 discrete time intervals.

[0070] As depicted, counter circuit 420 is electrically connected to sense amplifier 410 and accordingly receives the output from sense amplifier 410. Based on the output from sense amplifier 410, counter circuit 420 can count the number of matches returned by first matching line ML1 (e.g., count the number of comparisons in which the voltage of first matching line ML1 exceeds a threshold voltage).

[0071] As depicted, logic circuit 430 is electrically connected to counter circuit 420 and accordingly receives the output from counter circuit 420. Based on the output from counter circuit 420, logic circuit 430 can determine whether the counted match number satisfies a predetermined parity condition (e.g., odd match number) and the output indicates whether the input vector satisfies or violates the k-XOR-SAT clause programmed to the bottom row of the CAM unit (i.e., () signal.

[0072] Similarly, the sensing amplifier 412 is electrically connected to the second matching line ML2 associated with the top row of CAM 410. Therefore, the sensing amplifier 412 can receive the voltage output of the second matching line ML2 and compare the voltage output of the second matching line ML2 with a threshold voltage over k = 3 discrete times.

[0073] As depicted, counter circuit 422 is electrically connected to sense amplifier 412 and accordingly receives the output from sense amplifier 412. Based on the output from sense amplifier 412, counter circuit 422 can count the number of matches returned by second matching line ML2 (e.g., count the number of comparisons in which the voltage of second matching line ML2 exceeds a threshold voltage).

[0074] As depicted, logic circuit 432 is electrically connected to counter circuit 422 and accordingly receives the output from counter circuit 422. Based on the output from counter circuit 422, logic circuit 432 can determine whether the counted match number satisfies a predetermined parity condition (e.g., odd match number) and the output indicates whether the input vector satisfies or violates the k-XOR-SAT clause programmed into the top row of the CAM cell (i.e., ...). () signal.

[0075] In various implementations, logic circuits 430 and 432 may be connected to a processor (or, in some implementations, to additional logic circuitry) that determines whether an input vector satisfies k-XOR-SAT formula 450. For example, if the processor receives signals from both logic circuits 430 and 432 indicating that the input vector satisfies their respective k-XOR-SAT clauses, the processor may determine that the input vector satisfies k-XOR-SAT formula 450. Figure 4B The table 470 depicts the truth table for evaluating the k-XOR-SAT formula 450 using a CAM-based circuit 400. As depicted, the k-XOR-SAT formula 450 is solved when (f = 1).

[0076] As mentioned above, the CAM-based circuit 400 can also be used to implement larger Boolean satisfiability problems. For example, the CAM-based circuit 400 may include additional lines programmed to store additional clauses for larger Boolean satisfiability problems. These additional lines may be programmed to store k-XOR-SAT clauses, but may also store k-SAT clauses. In the case where the CAM-based circuit 400 is also used to implement k-SAT clauses, the matching line associated with the k-SAT clause may not include a combination. Figure 4A The described auxiliary counting and logic circuitry. This is because implementing the k-SAT clause may not involve counting the number of matches returned by the CAM cell of the common row. In the case where the k-SAT clause is implemented in DNF (such as in combination with...) Figure 2 and Figures 3A-3B As described, the matching line output associated with the DNF k-SAT clause (or alternatively, the matching line output associated with the k-XOR-SAT clause) can be connected to logic circuitry and / or inverters to illustrate the fact that the original k-SAT clause, which is converted to DNF for CAM programming, satisfies a mismatch, while the k-XOR-SAT clause implemented on the CAM-based circuit 400 satisfies a match.

[0077] Figure 6 Example flowcharts depicting various examples of the techniques according to this disclosure for solving Boolean satisfiability problems using CAM-based circuits are provided.

[0078] Operation 606 includes comparing the voltage output of the matching line associated with a row of CAM cells with a threshold voltage over k discrete time intervals. The row of CAM cells can be programmed to store a k-XOR-SAT clause of a Boolean satisfiability problem. k may represent the number of literals in the k-XOR-SAT clause. Therefore, the row of CAM cells may include at least k literal-representation CAM cells. One of the k literal-representation CAM cells can be programmed to store a literal value of the k-XOR-SAT clause. The literal-representation CAM cell can be programmed to store a first value (e.g., logic 0 or logic 1) when the literal value is negated in the k-XOR-SAT clause. The literal-representation CAM cell can be programmed to store a second value (e.g., another of logic 0 and logic 1) when the literal value is not negated in the k-XOR-SAT clause. As mentioned above, programming the literal-representation CAM cell may include programming the conductance of one or more memristors of the literal-representation CAM cell. As described above, operation 606 can be performed by a sensing amplifier electrically connected to the matching line.

[0079] Operation 608 includes counting the number of matches returned by the matching line based on k voltage comparisons. As mentioned above, counting the number of matches returned by the matching line based on k voltage comparisons may include counting the number of k voltage comparisons in which the voltage output of the matching line exceeds a threshold voltage. As described above, operation 608 may be performed by a counting circuit electrically connected to the sense amplifier.

[0080] Operation 610 includes determining that the input vector satisfies a k-XOR-SAT clause based on the counted number of matches satisfying a predetermined parity condition. In some embodiments, the predetermined parity condition may include an odd number of matches. In other embodiments, the predetermined parity condition may include an even number of matches. As described above, operation 610 can be performed by a processor that receives output from logic circuitry electrically connected to the counting circuitry. The output from the logic circuitry may be a signal indicating that the input vector satisfies a k-XOR-SAT clause based on the counted number of matches satisfying a predetermined parity condition.

[0081] As depicted, in some embodiments, the flowchart may further include operations 612-616. Here, it should be understood that, due to the parallel search capability of CAM, operations 612-616 may be performed in parallel (i.e., approximately concurrently) with operations 606-610.

[0082] For example, operation 612 may include comparing the voltage output of the second matching line associated with the second row CAM unit with a threshold voltage over k discrete time intervals. The second row CAM unit may be programmed to store a second k-XOR-SAT clause for a Boolean satisfiability problem. In some implementations, the second k-XOR-SAT clause may include fewer than k literal values. For example, the second k-XOR-SAT clause may include (kn) literal values. Therefore, the second row CAM unit may include (kn) literal value representation CAM units and n non-literal value representation CAM units. As mentioned above, the n non-literal value representation CAM units may be programmed to store wildcard values ​​that always return a match, such that they do not interrupt the evaluation of the second k-XOR-SAT clause programmed into the second row CAM unit. As described above, operation 612 may be performed by a second sensing amplifier electrically connected to the second matching line.

[0083] Operation 614 includes counting the number of matches returned by the second matching line based on k voltage comparisons associated with the voltage output of the second matching line. As mentioned above, counting the number of matches returned by the second matching line may include counting the number of k voltage comparisons associated with the voltage output of the second matching line, wherein the voltage output of the second matching line exceeds a threshold voltage. As described above, operation 614 may be performed by a second counting circuit electrically connected to the second sense amplifier.

[0084] Operation 616A includes determining that the input vector satisfies a second k-XOR-SAT clause based on the counted number of matches satisfying a predetermined parity condition. Alternatively, operation 616B includes determining that the input vector violates the second k-XOR-SAT clause based on the counted number of matches violating a predetermined parity condition. As described above, operations 616A-B can be executed by a processor that receives output from a second logic circuit electrically connected to the second counting circuit. A first output from the second logic circuit (corresponding to operation 616A) can be a signal indicating that the input vector satisfies the k-XOR-SAT clause based on the counted number of matches satisfying a predetermined parity condition. A second output from the second logic circuit (corresponding to operation 616B) can be a signal indicating that the input vector violates the k-XOR-SAT clause based on the counted number of matches violating a predetermined parity condition. In various embodiments, a common (i.e., identical) processor can execute operations 616A-B and operation 610. In some implementations, the processor may also determine whether an input vector satisfies or violates the Boolean satisfiesability problem based on the output of the logic circuitry from the CAM-based circuitry. For example, if the processor receives clauses indicating that the input vector satisfies all clauses programmed into the CAM-based circuitry, the processor may determine that the input vector satisfies the Boolean satisfiesability problem.

[0085] Figure 7 A block diagram of an example computer system 700 is depicted, in which various examples described herein can be implemented.

[0086] Computer system 700 includes a bus 712 or other communication mechanism for conveying information, and one or more hardware processors 704 connected to the bus 712 for processing information. The hardware processors 704 may be, for example, one or more general-purpose microprocessors.

[0087] Computer system 700 also includes main memory 706 (such as random access memory (RAM), cache, and / or other dynamic storage devices), which is connected to bus 712 for storing information and instructions to be executed by processor 704. Main memory 706 can also be used to store temporary variables or other intermediate information during the execution of instructions to be executed by processor 704. When stored in a storage medium accessible to processor 704, such instructions cause computer system 700 to behave as a special-purpose machine customized to perform the operations specified in the instructions.

[0088] The computer system 700 further includes a read-only memory (ROM) 712 or other static storage device coupled to the bus 712 for storing static information and instructions for the processor 704. A storage device 714 (such as a disk, optical disk, or USB thumb drive (flash drive)) is provided and coupled to the bus 712 for storing information and instructions.

[0089] Computer system 700 additionally includes hardware accelerator 708. Hardware accelerator 708 may be configured to execute instructions (i.e., programming or software code) stored in main memory 706, read-only memory (ROM) 712, and / or storage device 714 to encode a set of logical rules embodied in a Boolean satisfiability problem (e.g., the k-XOR-SAT problem) into CAM-based circuitry 710. In an example implementation, exemplary hardware accelerator 708 may include multiple integrated circuits, which may further include application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other very large-scale integrated circuits (VLSIs). The integrated circuits of exemplary hardware accelerator 708 may be specifically optimized to perform a discrete subset of computer processing operations in an accelerated manner or to execute a discrete subset of computer-executable instructions. For example, hardware accelerator 708 may be configured or manufactured to implement a set of logical rules embodied in a Boolean satisfiability problem (e.g., the k-XOR-SAT problem) into CAM-based circuitry 710.

[0090] The CAM-based circuit 710 may include non-volatile memory constructed using techniques including, for example, resistive switched memory (i.e., memristors), phase-change memory, magnetoresistive memory, ferroelectric memory, some other resistive random access memory device (Re-RAM), or combinations thereof. More generally, the CAM-based circuit 710 may be implemented using techniques that allow the CAM-based circuit 710 to retain its contents even when power is lost or otherwise removed. Therefore, data in the CAM-based circuit 710 is "persistent," and the CAM-based circuit 710 can function as a so-called "non-volatile memory."

[0091] Computer system 700 may be connected via bus 712 to display 716 (such as a liquid crystal display (LCD) (or touchscreen)) for displaying information to a computer user. Input device 718 (including alphanumeric keys and other keys) is connected to bus 712 for conveying information and command selections to processor 704. Another type of user input device is cursor control 720 (such as a mouse, trackball, or arrow keys) for conveying directional information and command selections to processor 704 and for controlling cursor movement on display 716. In some embodiments, the same directional information and command selections as with cursor control can be implemented by receiving touches on a touchscreen without a cursor.

[0092] The computing system 700 may include a user interface module for implementing a GUI, which may be stored as executable software code executed by (or more) computing devices in a mass storage device. For example, this module and other modules may include components such as software components, object-oriented software components, class components and task components, processes, functions, properties, procedures, subroutines, program code segments, drivers, firmware, microcode, circuit systems, data, databases, data structures, tables, arrays, and variables.

[0093] Generally, as used herein, the terms “component,” “engine,” “system,” “database,” “data storage device,” etc., can refer to logic embodied in hardware or firmware, or to a set of software instructions that may have entry and exit points written in a programming language such as, for example, Java, C, or C++. Software components may be compiled and linked into executable programs installed in dynamic link libraries, or may be written in interpreted programming languages ​​such as, for example, BASIC, Perl, or Python. It will be understood that software components may be callable from other components or themselves, and / or callable in response to detected events or interrupts. Software components configured for execution on a computing device may be provided on computer-readable media such as compact optical discs, digital video discs, flash drives, magnetic disks, or any other tangible media, or provided as digital downloads (and may initially be stored in a compressed or installable format that requires installation, decompression, or decryption prior to execution). Such software code may be stored, in part or in whole, on a memory device executing the computing device for execution by the computing device. Software instructions may be embedded in firmware such as EPROM. As will be further understood, hardware components may include connected logic units (such as gates and flip-flops), and / or may include programmable units (such as programmable gate arrays or processors).

[0094] Computer system 700 may implement the techniques described herein using custom hard-wired logic, one or more ASICs or FPGAs, firmware, and / or program logic, which, in combination with the computer system, cause computer system 700 to become a special-purpose machine or to be programmed as such. According to one embodiment, the techniques herein are executed by computer system 700 in response to processor(s) 704 executing one or more sequences of one or more instructions contained in main memory 706. Such instructions may be read into main memory 706 from another storage medium (such as storage device 714). Execution of the instruction sequence contained in main memory 706 causes processor(s) 704 to perform the process steps described herein. In alternative embodiments, a hard-wired circuit system may be used instead of or in combination with software instructions.

[0095] As used herein, the term "non-transitory media" and similar terms refer to any medium that stores data and / or instructions that cause a machine to operate in a particular manner. Such non-transitory media may include non-volatile media and / or volatile media. Non-volatile media include, for example, optical discs or magnetic disks, such as storage device 714. Volatile media include dynamic memory, such as main memory 706. Common forms of non-transitory media include, for example, floppy disks, floppy disks, hard disks, solid-state drives, magnetic tape or any other magnetic data storage media, CD-ROMs, any other optical data storage media, any physical media with a perforated pattern, RAM, PROMs and EPROMs, FLASH-EPROMs, NVRAMs, any other memory chips or cassette tapes, and their network versions.

[0096] Non-transitory media differ from transmission media, but can be used in conjunction with them. Transmission media participate in transferring information between non-transitory media. Examples of transmission media include coaxial cables, copper wires, and optical fibers, including cables that incorporate bus 712. Transmission media can also take the form of sound waves or light waves, such as those generated during radio wave and infrared data communication.

[0097] Computer system 700 also includes a communication / network interface 722 coupled to bus 712. Network interface 722 provides bidirectional data communication connectivity to one or more network links connected to one or more local networks. For example, communication interface 722 may be an Integrated Services Digital Network (ISDN) card, a cable modem, a satellite modem, or a modem used to provide data communication connectivity to a corresponding type of telephone line. As another example, network interface 722 may be a Local Area Network (LAN) card to provide data communication connectivity to a compatible LAN (or a WAN component communicating with a WAN). Wireless links may also be implemented. In any such implementation, network interface 718 transmits and receives electrical, electromagnetic, or optical indicators carrying streams of digital data representing various types of information.

[0098] Network links typically provide data communication to other data devices via one or more networks. For example, a network link may provide a connection to a host computer or to a data device operated by an Internet Service Provider (ISP) via a local network. The ISP, in turn, provides data communication services through a global packet data communication network now commonly referred to as the "Internet." Both local networks and the Internet use electrical, electromagnetic, or optical indicators that carry digital data streams. Indicators across various networks and on network links via communication interface 722 carry digital data to and from computer system 700; these indicators are example forms of transmission media.

[0099] Computer system 700 can send messages and receive data, including program code, through multiple networks, network links, and communication interfaces 718. In the Internet example, the server can transmit code requested by the application through the Internet, ISP, local network, and communication interface 722.

[0100] The received code may be executed by processor 704 upon receipt and / or stored in storage device 714 or other non-volatile storage device for later execution.

[0101] Each of the processes, methods, and algorithms described in the foregoing sections may be embodied in code components executed by one or more computer systems or computer processors, including computer hardware, and may be fully or partially automated by these code components. The one or more computer systems or computer processors may also be operable to support the performance of the associated operations in a “cloud computing” environment or as “Software as a Service” (SaaS). These processes and algorithms may be implemented, partially or wholly, in a dedicated circuit system. The various features and processes described above may be used independently of each other or may be combined in various ways. Different combinations and sub-combinations are intended to fall within the scope of this disclosure, and certain method or process blocks may be omitted in some embodiments. The methods and processes described herein are not limited to any particular sequence, and the blocks or states associated with them may be executed in other suitable sequences, or may be executed in parallel, or may be executed in some other way. Blocks or states may be added to or removed from the disclosed example embodiments. The execution of certain operations or processes may be distributed across computer systems or computer processors, not only residing within a single machine but also deployed across several machines.

[0102] As used herein, circuits can be implemented using any form of hardware, software, or a combination thereof. For example, one or more processors, controllers, ASICs, PLAs, PALs, CPLDs, FGAs, logic components, software routines, or other mechanisms can be implemented to constitute the circuit. In implementations, the various circuits described herein can be implemented as discrete circuits, or the described functions and features can be shared partially or entirely in one or more circuits. Even if various features or elements of a function can be described or claimed separately as separate circuits, these features and functions can be shared in one or more common circuits, and such descriptions should not require or imply the need for separate circuits to implement such features or functions. When circuits are implemented wholly or partially using software, such software can be implemented to operate with a computing or processing system (such as computer system 700) capable of implementing the functions described herein.

[0103] As used herein, the term “or” may be interpreted in an inclusive or exclusive sense. Furthermore, descriptions of resources, operations, or structures in the singular form should not be construed as excluding the plural. Conditional language (such as, among others, “may,” “may,” “perhaps,” or “can”) is generally intended to convey, unless specifically stated otherwise or understood in the context in which it is used, that certain embodiments include certain features, elements, and / or steps, while other embodiments do not.

[0104] Unless otherwise expressly stated, the terms and phrases used in this document, and their variations thereof, should be interpreted as open-ended, not restrictive. Adjectives and terms with similar meanings such as “regular,” “traditional,” “normal,” “standard,” “known,” and similar expressions should not be interpreted as limiting the described item to a given time period or items available at a given time, but should be interpreted as encompassing regular, traditional, normal, or standard techniques that may be available or known at any time now or in the future. In some cases, the appearance of expansive words and phrases (such as “one or more,” “at least,” “but not limited to,” or other similar phrases) should not be interpreted as indicating an intention or need for a narrower scope where such expansive phrases might not be present.

Claims

1. A circuit comprising: A single-line content-addressable memory (CAM) cell is programmed to store a k-XOR-SAT clause for a Boolean satisfiability problem; The sensing amplifier operates in response to an input vector being applied to the row of CAM units as follows: The voltage output of the matching line associated with the row CAM unit is compared with a threshold voltage at k discrete times, where k represents the number of literals of the k-XOR-SAT clause; A counter circuit that counts the number of matches returned from the matching line based on k voltage comparisons of the sensing amplifier; and A logic circuit that outputs a signal indicating that the input vector satisfies the k-XOR-SAT clause based on the counted number of matches satisfying a predetermined parity condition, wherein the predetermined parity condition is that the counted number of matches is an odd number of matches.

2. The circuit according to claim 1, wherein: The row of CAM units includes k literal-representation CAM units; and One of the k literal representation CAM cells is programmed to store the literal value of the k-XOR-SAT clause.

3. The circuit according to claim 1, wherein, The counted number of matches corresponds to the number of k voltage comparisons in which the voltage output of the matched line exceeds the threshold voltage.

4. The circuit according to claim 2, wherein, Programming the literal representation CAM unit to store the literal value of the k-XOR-SAT clause includes: The literal representation CAM unit is programmed to store a first value when the literal value is negated in the k-XOR-SAT clause; and The literal representation CAM unit is programmed to store a second value when the literal value is not negated in the k-XOR-SAT clause.

5. The circuit according to claim 4, wherein: The row CAM unit further includes a non-literal CAM unit programmed to store wildcard values.

6. The circuit according to claim 2, wherein, Programming the literal representation CAM unit to store the literal value of the k-XOR-SAT clause includes: The conductance of the memristor included in the literal representation CAM unit is programmed.

7. The circuit according to claim 1, further comprising: The second row of CAM cells is programmed to store the second k-XOR-SAT clause of the Boolean satisfiability problem; The second sensing amplifier operates in response to the input vector being applied to the second row of CAM cells as follows: The voltage output of the second matching line associated with the second row CAM unit is compared with the threshold voltage during the k discrete time intervals. The second counter circuit counts the number of matches returned by the second matching line based on the k voltage comparisons of the second sensing amplifier. as well as The second logic circuit outputs a signal indicating that the input vector satisfies the second k-XOR-SAT clause, based on the counted number of matches satisfying the predetermined parity condition.

8. The circuit of claim 7, further comprising a processor, the processor performing the following operations in response to receiving the signal from the first logic circuit and the signal from the second logic circuit: Determine whether the input vector satisfies the Boolean satisfiability problem.

9. A method for solving the Boolean satisfiability problem using content-addressable memory (CAM) based circuitry, the method comprising: The voltage output of the matching line associated with a row of CAM cells is compared with a threshold voltage over k discrete time intervals, where: The CAM-based circuit includes the row of CAM units, wherein the input vector is applied to the row of CAM units. The row of CAM cells is programmed to store the k-XOR-SAT clause of the Boolean satisfiability problem, and k represents the number of literal values ​​in the k-XOR-SAT clause; The number of matches returned by the matching line is counted based on k voltage comparisons; and The input vector is determined to satisfy the k-XOR-SAT clause based on the number of counted matches satisfying a predetermined parity condition, wherein the predetermined parity condition is that the number of counted matches is an odd number of matches.

10. The method of claim 9, further comprising: The voltage output of the second matching line associated with the second row CAM unit is compared with the threshold voltage at the k discrete time intervals, where: The CAM-based circuit includes the second row of CAM units. The second row of CAM cells is programmed to store the second k-XOR-SAT clause of the Boolean satisfiability problem. The number of matches returned by the second matching line is counted based on the k voltage comparisons associated with the voltage output of the second matching line; and The input vector is determined to satisfy the second k-XOR-SAT clause based on the count of matches returned by the second matching line satisfying the predetermined parity condition.

11. The method of claim 9, further comprising: The voltage output of the second matching line associated with the second row CAM unit is compared with the threshold voltage at the k discrete time intervals, where: The CAM-based circuit includes the second row of CAM units. The second row of CAM cells is programmed to store the second k-XOR-SAT clause of the Boolean satisfiability problem. The number of matches returned by the second matching line is counted based on the k voltage comparisons associated with the voltage output of the second matching line; and The input vector is determined to violate the second k-XOR-SAT clause based on the count of matches returned by the second matching line violating the predetermined parity condition.

12. The method of claim 10, further comprising: Determine whether the input vector satisfies the Boolean satisfiability problem.

13. The method of claim 11, further comprising: Determine that the input vector violates the Boolean satisfiability problem.

14. The method according to claim 9, wherein: The row of CAM units includes k literal-representation CAM units; and One of the k literal representation CAM cells is programmed to store the literal value of the k-XOR-SAT clause.

15. The method of claim 14, further comprising: The literal value representation CAM unit is programmed to store a first value when the literal value is negated in the k-XOR-SAT clause; as well as The CAM unit is programmed to store a second value when the literal value is not negated in the k-XOR-SAT clause.

16. The method of claim 14, further comprising: The literal representation CAM unit is programmed to store the literal value of the k-XOR-SAT clause by programming the conductance of the memristor included in the literal representation CAM unit.

17. A circuit based on content-addressable memory (CAM), comprising: A single CAM cell is configured to store a k-XOR-SAT clause for the Boolean satisfiability problem, where: k represents the number of literal values ​​in the k-XOR-SAT clause. The row of CAM units includes k literal representation CAM units, and One of the k literal representation CAM units is programmed to store the literal value of the k-XOR-SAT clause; The sensing amplifier operates in response to an input vector being applied to the row of CAM units as follows: The voltage output of the matching line associated with the row of CAM units is compared with the threshold voltage over k discrete time intervals; A counter circuit that counts the number of matches returned from the matching line based on k voltage comparisons of the sensing amplifier; and A logic circuit that outputs a signal indicating that the input vector satisfies the k-XOR-SAT clause based on the counted number of matches satisfying a predetermined parity condition, wherein the predetermined parity condition is that the counted number of matches is an odd number of matches.

18. The CAM-based circuit according to claim 17, wherein, The counted number of matches corresponds to the number of k voltage comparisons in which the voltage output of the matched line exceeds the threshold voltage.

19. The CAM-based circuit according to claim 17, wherein, Programming the literal representation CAM unit to store the literal value of the k-XOR-SAT clause includes: The literal representation CAM unit is programmed to store a first value when the literal value is negated in the k-XOR-SAT clause; and The literal representation CAM unit is programmed to store a second value when the literal value is not negated in the k-XOR-SAT clause.

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