A clock synchronization circuit and a clock synchronization method

Abstract

The application provides a clock synchronization circuit and a clock synchronization method, and the circuit comprises a voltage-controlled oscillation module, an input equal-width pulse module, an output equal-width pulse module, a synchronization feedback module and a phase discrimination module; the input equal-width pulse module is used for converting a first input signal into a first equal-width pulse signal; the output equal-width pulse module is used for converting an output signal into a second equal-width pulse signal; the synchronization feedback module is used for comparing the frequency of the second equal-width pulse signal with that of a preset signal, and sending a comparison result to the voltage-controlled oscillation module; the voltage-controlled oscillation module is used for adjusting the frequency of the second equal-width pulse signal according to the comparison result, and sending an adjusted first output signal to the phase discrimination module and the output equal-width pulse module; and the phase discrimination module performs frequency locking and phase locking based on the frequency comparison result of the first output signal and the first input signal. The application can improve the high-frequency stability and fast adaptability of the clock synchronization circuit.

Description

Technical Field

[0001] This invention relates to the field of digital signal processing technology, and in particular to a clock synchronization circuit and a clock synchronization method. Background Technology

[0002] A clock synchronization circuit is used to coordinate the clock signals of multiple circuits or systems to the same frequency and phase. Its main function is to ensure synchronization between different components, preventing data loss or errors due to clock signal asynchrony. It plays a crucial role in modern electronic systems and is fundamental to ensuring the normal operation of various applications. When the frequency of the output signal is equal to the frequency of the input signal, and the rising and falling edges of the output signal are spaced out, the clock synchronization circuit can output a relatively stable 50% duty cycle clock signal at the same frequency. While the clock signal at the same frequency has the same frequency as the reference clock signal, there may be a slight phase shift.

[0003] When the reference clock signal undergoes significant changes or abrupt shifts, the phase-locked loop (PLL) in the clock synchronization circuit requires time to adjust its output to match the new input frequency. Therefore, the frequency divider and PLL cannot adapt to rapid or large-scale frequency changes. The synchronization clock circuit may lose synchronization with the reference clock, resulting in an inaccurate output clock at the same frequency. The phase of the output clock may also deviate significantly, affecting signal integrity. Achieving high frequency stability and rapid adaptability is a major challenge in designing clock synchronization circuits. Summary of the Invention

[0004] The present invention aims to provide a clock synchronization circuit and a clock synchronization method to solve the above-mentioned technical problems and improve the high-frequency stability and rapid adaptability of the clock synchronization circuit.

[0005] To solve the above-mentioned technical problems, the present invention provides a clock synchronization circuit, including: a voltage-controlled oscillator module, an input equal pulse width module, an output equal pulse width module, a synchronization feedback module, and a phase detection module; The output terminal of the voltage-controlled oscillator module and the preset first input signal are respectively connected to the input terminal of the phase detector module; The output terminal of the voltage-controlled oscillation module is also connected to the input terminal of the output equal pulse width module; The output terminals of the output equal pulse width module, the phase detection module, and the input equal pulse width module are also connected to the input terminal of the synchronization feedback module. The output of the synchronous feedback module is connected to the input of the voltage-controlled oscillation module; The input equal-width pulse module is used to convert the received first input signal into a first equal-width pulse signal; The output equal pulse width module is used to convert the output signal into a second equal pulse width signal; The synchronous feedback module is used to compare the frequency of the second equal-width pulse signal with a preset signal and send the frequency comparison result to the voltage-controlled oscillation module; wherein, the preset signal includes the first equal-width pulse signal and a preset reference signal; The voltage-controlled oscillator module is used to adjust the frequency of the second equal-width pulse signal according to the frequency comparison result, and send the adjusted first output signal to the phase detection module and the output equal-width module. The phase detection module performs frequency locking and phase locking based on the frequency comparison results of the first output signal and the first input signal.

[0006] In the above scheme, the input signal is converted into a standardized first equal-width pulse signal by the input equal-width pulse module. This signal is output to the phase detector module for comparison with the output signal of the voltage-controlled oscillator module. The output signal of the voltage-controlled oscillator module is simultaneously sent to the output equal-width pulse module and used as a feedback signal to the synchronization feedback module. The synchronization feedback module compares the received second equal-width pulse signal with a preset signal in terms of frequency. Based on the frequency comparison result, it quickly adjusts the input of the voltage-controlled oscillator module to change its output frequency, making it match the first input signal as quickly as possible. The phase detector module compares the first output signal with the first input signal in terms of frequency, and performs frequency locking and phase locking based on the comparison result, thereby quickly correcting the output signal and ensuring stable output at the new frequency. The input equal-width pulse module converts the received first input signal into a first equal-width pulse signal with a uniform pulse width, eliminating pulse width inhomogeneity in the input signal and improving the accuracy of subsequent processing. The output equal-width pulse module converts the circuit output signal into a second equal-width pulse signal with a uniform pulse width, ensuring that the entire circuit maintains consistency on the output clock. The synchronous feedback module compares the frequency of the second equal-width pulse signal with a preset signal and feeds the comparison result back to the voltage-controlled oscillator module, enabling frequency adjustment and stabilization. Frequency locking and phase locking are achieved based on the frequency comparison result of the first output signal and the first input signal, ensuring the system can quickly adjust to a new frequency state. The clock synchronization circuit enhances the synergy between modules through real-time feedback and dynamic adjustment mechanisms, thereby improving overall frequency stability and rapid adaptability. Due to the optimized design of each module, the efficiency of signal interaction is improved, and the error recognition rate is reduced, enabling the entire circuit to not only adjust quickly when faced with large frequency changes but also maintain signal integrity and accuracy. These improvements make this clock synchronization circuit more competitive and practical in high-frequency signal applications.

[0007] In one implementation, the input equal-width pulse module is used to convert the received first input signal into a first equal-width pulse signal, specifically including: The input equal pulse width module includes a first capacitor, a first resistor, a first NOT gate, and a second NOT gate; The first input signal is connected to the positive terminal of the first capacitor and the input terminal of the phase detection module; The negative terminal of the first capacitor is connected to the first terminal of the first resistor and the input terminal of the first NOT gate; The output of the first NOT gate is connected to the input of the second NOT gate; The output of the second NOT gate is connected to the input of the synchronous feedback module.

[0008] In one implementation, the output equal-pulse-width module is used to convert the output signal into a second equal-width pulse signal, specifically including: The output equal pulse width module includes a second capacitor, a second resistor, a third NOT gate, and a fourth NOT gate; The input terminal of the third NOT gate is connected to the output terminal of the voltage-controlled oscillator module and the input terminal of the phase detector module; The output terminal of the third NOT gate is connected to the positive terminal of the second capacitor; The negative terminal of the second capacitor is connected to the first terminal of the second resistor and the input terminal of the fourth NOT gate; The second terminal of the second resistor is grounded; The output of the fourth NOT gate is connected to the input of the synchronous feedback module.

[0009] In one implementation, the synchronous feedback module is used to compare the frequency of the second equal-width pulse signal with a preset signal, and send the frequency comparison result to the voltage-controlled oscillator module, specifically including: The synchronous feedback module includes a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a third capacitor, a fourth capacitor, an operational amplifier, and a voltage source; The first end of the third resistor is connected to the output end of the output equal pulse width module; The first end of the fourth resistor is connected to the output end of the phase detection module; The first end of the fifth resistor is connected to the output end of the input equal pulse width module; The second terminal of the third resistor, the second terminal of the fourth resistor, and the second terminal of the fifth resistor are connected to the positive terminal of the third capacitor, the positive terminal of the fourth capacitor, the first terminal of the sixth resistor, and the negative input terminal of the operational amplifier. The negative terminal of the third capacitor is connected to the second terminal of the sixth resistor, the positive terminal of the voltage source, and the positive input terminal of the operational amplifier; The negative terminal of the voltage source is connected to the preset reference signal.

[0010] In one implementation, the voltage-controlled oscillator module is used to adjust the frequency of the second constant-width pulse signal according to the frequency comparison result, specifically including: The voltage-controlled oscillator module includes a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a fifth capacitor, a sixth capacitor, a first switch, a first voltage comparator, and a second voltage comparator; The first end of the seventh resistor is connected to the output end of the synchronous feedback module and the negative input end of the second voltage comparator. The second end of the seventh resistor is connected to the first end of the eighth resistor and the negative input end of the first voltage comparator; The output terminal of the first voltage comparator is connected to the input terminal of the output equal pulse width module and the input terminal of the phase detection module; The first end of the ninth resistor is connected to the power supply terminal; The second end of the ninth resistor is connected to the first end of the first switch, the positive input terminal of the first voltage comparator, the positive input terminal of the second voltage comparator, and the positive terminal of the fifth capacitor; wherein, when the first switch is closed, the second end of the first switch is connected to the negative terminal of the fifth capacitor; The positive terminal of the sixth capacitor is connected to the first terminal of the tenth resistor and the output terminal of the second voltage comparator; The second terminal of the eighth resistor, the negative terminal of the fifth capacitor, the negative terminal of the sixth capacitor, and the second terminal of the tenth resistor are grounded.

[0011] In one implementation, the phase detection module performs frequency locking and phase locking based on the frequency comparison result of the first output signal and the first input signal, specifically including: The phase detection module includes a seventh capacitor, an eighth capacitor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, and a trigger. The positive terminal of the seventh capacitor is connected to the output terminal of the voltage-controlled oscillator module; The negative terminal of the seventh capacitor is connected to the first terminal of the eleventh resistor, the first terminal of the twelfth resistor, and the reset input terminal of the trigger. The positive terminal of the eighth capacitor is connected to the first input signal; The negative terminal of the eighth capacitor is connected to the first terminal of the thirteenth resistor, the first terminal of the fourteenth resistor, and the setting input terminal of the trigger. The second end of the eleventh resistor and the second end of the thirteenth resistor are connected to the power supply terminal; The second terminal of the twelfth resistor and the second terminal of the fourteenth resistor are grounded.

[0012] In one implementation, the seventh and eighth capacitors are electrolytic capacitors, and the trigger is an RS trigger.

[0013] Secondly, this application also provides a clock synchronization method applicable to the clock synchronization circuit described above, comprising: The received first input signal is sent to the phase detection module and the input equal pulse width module is controlled to convert the first input signal into a first equal width pulse signal, and the first equal width pulse signal is sent to the synchronization feedback module. The control output equal pulse width module converts the first output signal output by the voltage-controlled oscillator module into a second equal pulse width signal and sends the second equal pulse width signal to the synchronous feedback module; The phase detection module is controlled to perform frequency locking and phase locking on the first input signal and the first output signal based on the trigger, and the output result of the phase detection module is sent to the synchronization feedback module; The synchronous feedback module is controlled to perform frequency comparisons on the second equal-width pulse signal, the first equal-width pulse signal, and the preset reference signal, and sends the frequency comparison results to the voltage-controlled oscillation module. The voltage-controlled oscillator module adjusts the frequency of the second equal-width pulse signal based on the frequency comparison result, and sends the frequency-adjusted first output signal to the output equal-width module and the phase detection module.

[0014] In the above scheme, the received first input signal is converted into a first equal-width pulse signal by the input equal-pulse-width module and quickly output to the synchronization feedback module. The phase detection module receives the first output signal (output from the output equal-pulse-width module) and the first input signal, performs phase locking based on the frequency difference, and quickly feeds back the frequency comparison result to the synchronization feedback module. The synchronization feedback module simultaneously compares the second equal-width pulse signal with preset signals (the first equal-width pulse signal and the reference signal) and adjusts the input of the voltage-controlled oscillator module accordingly, actively adjusting the control signal to maintain synchronization based on frequency changes. When a significant change in the reference signal is detected, the system quickly performs frequency adjustment and output update to ensure that the output signal is at the same frequency and stable, thereby reducing the impact of phase deviation of the output signal. Adaptive adjustment is implemented in the synchronization feedback module, adjusting the control voltage of the voltage-controlled oscillator module according to the real-time information of the frequency comparison, ensuring rapid response to frequency changes of the input signal and reducing the frequency locking time. By dynamically adjusting the feedback gain, the gain of the generated output signal is adjusted according to the rate and amplitude of the input signal change, which helps to quickly adapt to sudden frequency changes. By introducing a dynamic pulse width adjustment mechanism into the output pulse width module, the pulse width can be adjusted according to the actual changes in the input signal during circuit operation, thereby ensuring that an accurate clock signal is always provided in a rapidly changing environment. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the connection relationship of a clock synchronization circuit provided in one embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the connection relationship of an input equal pulse width module according to an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating the connection relationship of an output equal pulse width module provided in one embodiment of the present invention; Figure 4 This is a schematic diagram of the connection relationship of a synchronous feedback module provided in one embodiment of the present invention; Figure 5 This is a schematic diagram of the connection relationship of a voltage-controlled oscillation module provided in one embodiment of the present invention; Figure 6 This is a schematic diagram of the connection relationship of a phase detection module provided in one embodiment of the present invention; Figure 7 This is a flowchart illustrating a clock synchronization method provided in one embodiment of the present invention. Detailed Implementation

[0016] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and are not intended to limit the scope of the invention.

[0017] The terms "first" and "second," etc., in the specification, claims, and drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such processes, methods, products, or apparatus.

[0018] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0019] Example 1 See Figure 1 , Figure 1This is a schematic diagram of the connection relationship of a clock synchronization circuit provided in one embodiment of the present invention. The clock synchronization circuit includes: a voltage-controlled oscillator module 101, an input equal pulse width module 102, an output equal pulse width module 103, a synchronization feedback module 104, and a phase detector module 105; The output terminal of the voltage-controlled oscillation module 101 and the preset first input signal are respectively connected to the input terminal of the phase detection module 105; The output terminal of the voltage-controlled oscillation module 101 is also connected to the input terminal of the output equal pulse width module 103; The output terminals of the output equal pulse width module 103, the phase detection module 105, and the input equal pulse width module 102 are also connected to the input terminal of the synchronization feedback module 104. The output terminal of the synchronous feedback module 104 is connected to the input terminal of the voltage-controlled oscillation module 101; The input equal pulse width module 102 is used to convert the received first input signal into a first equal pulse width signal; The output equal pulse width module 103 is used to convert the output signal into a second equal pulse width signal; The synchronous feedback module 104 is used to compare the frequency of the second equal-width pulse signal with a preset signal and send the frequency comparison result to the voltage-controlled oscillation module 101; wherein, the preset signal includes the first equal-width pulse signal and a preset reference signal Vref; The voltage-controlled oscillator module 101 is used to adjust the frequency of the second equal-width pulse signal according to the frequency comparison result, and send the adjusted first output signal to the phase detection module 105 and the output equal-width module 103. The phase detection module 105 performs frequency locking and phase locking based on the frequency comparison results of the first output signal and the first input signal.

[0020] Figure 2 This is a schematic diagram of the connection relationship of an input equal pulse width module provided in one embodiment of the present invention.

[0021] In one embodiment, the input equal pulse width module 102 is used to convert the received first input signal into a first equal-width pulse signal, specifically including: the input equal pulse width module includes a first capacitor C3, a first resistor R5, a first NOT gate NOR1, and a second NOT gate NOR2; the first input signal Vi is connected to the positive terminal of the first capacitor C3 and the input terminal of the phase detection module; the negative terminal of the first capacitor C3 is connected to the first terminal of the first resistor R5 and the input terminal of the first NOT gate NOR1; the output terminal of the first NOT gate NOR1 is connected to the input terminal of the second NOT gate NOR2; and the output terminal of the second NOT gate NOR2 is connected to the input terminal of the synchronization feedback module.

[0022] In the input equal pulse width module 102 provided in this embodiment of the invention, an RC differentiating network is constructed using a first capacitor C3 and a first resistor R5. This RC differentiating network can be used as a differentiator. At the instant the input signal changes, capacitor C3 charges or discharges rapidly, generating an output voltage proportional to the rate of change of the input signal. This means that when the input signal rises or falls, a spike appears in the output signal, helping to identify the edge of the signal. By adjusting the values ​​of the first resistor R5 and the first capacitor C3, the width and shape of the output pulse can be changed. If the duty cycle of the input signal is 20%, the RC network can extend the pulse width through the discharge process, thereby outputting a signal with a duty cycle close to 50%. Through the design of the first resistor R5 and the first capacitor C3, the input equal pulse width module can convert input pulse signals of unequal width into a first equal pulse signal with unchanged phase via the RC differentiating network. The characteristic of a NOT gate is that the output is high only when all inputs are low. Furthermore, the first NOT gate (NOR1) performs logical processing based on the input signal and the output of the RC network. The output of NOR1 remains high for a period after the input signal goes low, thus lengthening the width of the output pulse and further adjusting the shape of the output pulse (the first constant-width pulse signal). The second NOT gate (NOR2) receives its input from the output of NOR1. This gate inverts the output signal of the first NOT gate, thereby generating a suitable clock signal output. The output of NOR2 is connected to a synchronous feedback module, allowing the circuit to dynamically adjust parameters according to the actual output conditions to better adapt to input signals with different duty cycles.

[0023] See Figure 3 , Figure 3 This is a schematic diagram illustrating the connection relationship of an output equal pulse width module according to an embodiment of the present invention. In one embodiment, the output equal pulse width module 103 is used to convert the output signal into a second equal-width pulse signal, specifically including: the output equal pulse width module includes a second capacitor C4, a second resistor R6, a third NOT gate NOR3, and a fourth NOT gate NOR4; the input terminal of the third NOT gate NOR3 is connected to the output terminal of the voltage-controlled oscillator module 101 and the input terminal of the phase detector module 105; the output terminal of the third NOT gate NOR3 is connected to the positive terminal of the second capacitor C4; the negative terminal of the second capacitor C4 is connected to the first terminal of the second resistor R6 and the input terminal of the fourth NOT gate NOR4; the second terminal of the second resistor R6 is grounded; the output terminal of the fourth NOT gate NOR4 is connected to the input terminal of the synchronous feedback module.

[0024] In an embodiment of the present invention, an output pulse width equalization module 103 is provided, in which the second capacitor C4 is used to store charge, forming a delay and pulse shaping function. It can adjust the width of the output pulse according to changes in the input signal. The charging and discharging characteristics of the second capacitor C4 can affect the duration of the output signal, keeping it at the required pulse width. The second resistor R6 and the second capacitor C4 form an RC network; the resistance value of the second resistor R6 determines the charging and discharging speed of the second capacitor C4, thereby affecting the width and shape of the output pulse. The third NOT gate NOR3 is used for logic integration, and its input is connected to the output signals of the voltage-controlled oscillator module 101 and the phase detector module 105. By logically processing the input signal, the third NOT gate NOR3 can identify changes in the state of the input signal and output a high-level signal at the appropriate time. The fourth NOT gate NOR4 is used to further process the output signal of the third NOT gate NOR3, inverting the output signal of NOR3 to ensure the generation of an appropriate output pulse. Simultaneously, the output of the fourth NOT gate NOR4 is also transmitted to the synchronous feedback module, providing feedback information for adjusting the circuit's operating state. Through the coordinated operation of the second capacitor C4, the second resistor R6, the third NOT gate NOR3, and the fourth NOT gate NOR4, the output equal pulse width module can effectively convert the input signal into an equal pulse width signal, thereby meeting the pulse width requirements of the clock synchronization circuit.

[0025] See Figure 4 , Figure 4 This is a schematic diagram of the connection relationship of a synchronous feedback module provided in one embodiment of the present invention. In one embodiment, the synchronous feedback module is used to compare the frequency of the second equal-width pulse signal with a preset signal and send the frequency comparison result to the voltage-controlled oscillator module. Specifically, the synchronous feedback module includes a third resistor R11, a fourth resistor R12, a fifth resistor R13, a sixth resistor R14, a third capacitor C9, a fourth capacitor C10, an operational amplifier OPA1, and a voltage source; the first end of the third resistor R11 is connected to the output end of the output equal-width pulse module; the first end of the fourth resistor R12 is connected to the output end of the phase detection module; the fifth resistor R13 is connected to the output end of the output equal-width pulse module; the fifth resistor R14 is connected to the output end of the output equal-width pulse module; the sixth resistor R15 is connected to the output end of the output equal-width pulse module; the sixth resistor R16 is connected to the output end of the output equal-width pulse module; the sixth resistor R17 is connected to the output end of the output equal-width pulse module; the sixth resistor R18 is connected to the output end of the output equal-width pulse module; the sixth resistor R19 is connected to the output end of the output equal-width pulse module; the sixth resistor R12 is connected to the output end of the output equal-width pulse module; the sixth resistor R13 is connected to the output end of the output equal-width pulse module; the sixth resistor R14 is connected to the output end of the output equal-width pulse module; the sixth resistor R15 is connected to the output end of the output equal-width pulse module; the sixth resistor R16 is connected to the output end of the output equal-width pulse module; the sixth resistor R17 ... The first terminal of resistor 13 is connected to the output terminal of the input equal pulse width module; the second terminals of the third resistor R11, the fourth resistor R12, and the fifth resistor R13 are connected to the positive terminal of the third capacitor C9, the positive terminal of the fourth capacitor C10, the first terminal of the sixth resistor R14, and the negative input terminal of the operational amplifier OPA1; the negative terminal of the third capacitor C9 is connected to the second terminal of the sixth resistor R14, the positive terminal of the voltage source, and the positive input terminal of the operational amplifier OPA1; the negative terminal of the voltage source is connected to the preset reference signal Vref.

[0026] In a synchronous feedback module 104 provided in this embodiment of the invention, a third resistor R11 is connected to a second equal-width pulse signal (from the output equal-width pulse module), a fourth resistor R12 is connected to the output signal of the phase detection module, and a fifth resistor R13 is connected to a first equal-width pulse signal (the output signal of the input equal-width pulse module). These resistors, together with the third capacitor C9, the fourth capacitor C10, and the sixth resistor R14, form a weighted averaging network that combines different signals. The third capacitor C9 and the fourth capacitor C10 are used to filter and smooth the signal, eliminate high-frequency noise, and ensure the stability of the input signal of the operational amplifier OPA1. The signals connected to resistors R11, R12, and R13 are filtered by C9 and C10 and then connected to the negative input terminal of OPA1. The positive input terminal of OPA1 is connected to a voltage source, and the negative terminal of the voltage source provides a preset reference signal Vref. The function of the operational amplifier OPA1 is to compare the voltage difference between the signal filtered by C9 and C10 and the preset reference signal Vref. The operational amplifier OPA1 generates an error signal representing the difference between the frequency of the output equal-width pulse signal and the frequency of the reference signal. The voltage value of this error signal is proportional to the frequency difference. Specifically, operational amplifier OPA1 compares the filtered signal with a preset reference signal Vref. The negative input of OPA1 is connected to the weighted signal, and the positive input is connected to the preset reference signal Vref. If the output signal frequency is lower than the preset reference signal Vref, the output of OPA1 will be positive; if it is higher than the preset reference signal Vref, the output will be negative. The error signal is transmitted to the voltage-controlled oscillator (VCO) module through the feedback path (i.e., the loop between the feedback module and the VCO module), which affects the control voltage of the VCO, thereby adjusting its output frequency. Specifically, when the output signal frequency is lower than the reference signal frequency: the feedback signal causes the control voltage of the VCO to increase, thereby increasing the oscillation frequency until the output signal frequency matches the reference signal frequency. When the output signal frequency is higher than the reference signal frequency: the feedback signal causes the control voltage of the VCO to decrease, thereby decreasing the oscillation frequency until the output signal frequency matches the reference signal frequency. Through the above configuration of the synchronous feedback module, a synchronous feedback system that automatically adjusts the output signal frequency can be realized. This system generates an error signal by comparing the frequency of the output signal with the frequency of a preset reference signal, and feeds it back to the voltage-controlled oscillator, thereby achieving automatic frequency adjustment.

[0027] See Figure 5 , Figure 5This is a schematic diagram of the connection relationship of a voltage-controlled oscillator module according to an embodiment of the present invention. In one embodiment, the voltage-controlled oscillator module 101 is used to adjust the frequency of the second equal-width pulse signal according to the frequency comparison result, specifically including: the voltage-controlled oscillator module 101 includes a seventh resistor R1, an eighth resistor R2, a ninth resistor R3, a tenth resistor R4, a fifth capacitor C1, a sixth capacitor C2, a first switch K1, a first voltage comparator COMP1, and a second voltage comparator COMP2; the first end of the seventh resistor R1 is connected to the output end of the synchronous feedback module and the negative input end of the second voltage comparator; the second end of the seventh resistor R1 is connected to the first end of the eighth resistor R2 and the negative input end of the first voltage comparator COMP1; the output end of the first voltage comparator COMP1 is connected to the output equal-width pulse module... The input terminal of the block is connected to the input terminal of the phase detection module; the first terminal of the ninth resistor R3 is connected to the power supply terminal; the second terminal of the ninth resistor R3 is connected to the first terminal of the first switch K1, the positive input terminal of the first voltage comparator COMP1, the positive input terminal of the second voltage comparator COMP2, and the positive terminal of the fifth capacitor C1; wherein, when the first switch K1 is closed, the second terminal of the first switch K1 is connected to the negative terminal of the fifth capacitor C1; the positive terminal of the sixth capacitor C2 is connected to the first terminal of the tenth resistor R4 and the output terminal of the second voltage comparator COMP2; the second terminal of the eighth resistor R2, the negative terminal of the fifth capacitor C1, the negative terminal of the sixth capacitor C2, and the second terminal of the tenth resistor R4 are grounded.

[0028] In a voltage-controlled oscillation module 101 provided in this embodiment of the invention, the seventh resistor R1, the eighth resistor R2, the tenth resistor R4, the fifth capacitor C1, and the sixth capacitor C2 constitute an RC circuit to form a sawtooth wave generator. When the sawtooth wave is charged, the capacitors charge through the resistors according to a fixed time constant, forming a rising slope. Preferably, the resistors can be replaced with constant current sources to obtain a more ideal linear slope, thereby accurately controlling the frequency. The first end of the seventh resistor R1 is connected to the output end of the synchronous feedback module, and the second end of the seventh resistor R1 is connected to the first end of the eighth resistor R2 and the negative input end of the first voltage comparator COMP1; the second end of the eighth resistor R2 is grounded. The positive input end of the first voltage comparator is connected to the charging sawtooth wave signal. When the sawtooth wave reaches V_{control} (determined by the feedback signal), the first voltage comparator COMP1 will flip its output, and its output end is connected to the input end of the output equal pulse width module and the input end of the phase detection module. The second voltage comparator COMP2 is used to set the duty cycle of the sawtooth wave, ensuring a 50% duty cycle for the final output signal and guaranteeing its stability. Driven by the output signal of COMP2, the sawtooth wave is reset. When the output voltage of the sawtooth wave is higher than V_{control}, the second voltage comparator COMP2 outputs a high level, opening the first switch K1 and connecting it to the negative terminal of the fifth capacitor C1, causing the sawtooth wave capacitor to discharge rapidly, completing one sawtooth wave cycle. By adjusting the output (error signal) from the synchronous feedback module, i.e., how it affects the magnitude of the V_{control} voltage, this voltage value determines the trigger point of the sawtooth wave. Increasing V_{control} will cause the time for the sawtooth wave to rise to that voltage to be longer for the same RC time constant, thus reducing the frequency; conversely, decreasing V_{control} will increase the output frequency. When V_{control} increases, the time required for the sawtooth wave to reach that voltage increases, resulting in a decrease in output frequency. Once the sawtooth wave voltage exceeds V_{control}, the second voltage comparator COMP2 flips, the first switch K1 opens, causing the fifth capacitor C1 to discharge, and the sawtooth wave begins to decline. When V_{control} decreases, the time to reach the comparison level shortens, and the output frequency increases.

[0029] See Figure 6 , Figure 6This is a schematic diagram of the connection relationship of a phase detection module provided in one embodiment of the present invention. In one embodiment, the phase detection module 105 performs frequency locking and phase locking based on the frequency comparison result of the first output signal and the first input signal, specifically including: the phase detection module includes a seventh capacitor C7, an eighth capacitor C8, an eleventh resistor R7, a twelfth resistor R8, a thirteenth resistor R9, a fourteenth resistor R10, and a trigger; the positive terminal of the seventh capacitor C7 is connected to the output terminal of the voltage-controlled oscillator module; the negative terminal of the seventh capacitor C7 is connected to the first terminal of the eleventh resistor R7, the first terminal of the twelfth resistor R8, and the reset input terminal of the trigger; the positive terminal of the eighth capacitor C8 is connected to the first input signal Vin; the negative terminal of the eighth capacitor C8 is connected to the first terminal of the thirteenth resistor R9, the first terminal of the fourteenth resistor R10, and the setting input terminal of the trigger; the second terminals of the eleventh resistor R7 and the thirteenth resistor R9 are connected to the power supply terminal Vcc; the second terminals of the twelfth resistor R8 and the fourteenth resistor R10 are grounded.

[0030] In a phase detection module provided in this embodiment of the invention, the seventh capacitor C7 is used to couple the first output signal of the voltage-controlled oscillator module and filter the signal; the eighth capacitor C8 is used to couple the first input signal Vin; the eleventh resistor R7, the twelfth resistor R8, the thirteenth resistor R9, and the fourteenth resistor R10 are used to set the time constant of the circuit and the gain of the signal; and the flip-flop is used for digital signal processing and frequency locking logic control. The flip-flop includes two control input terminals: a reset input terminal and a setting input terminal. The reset input terminal is connected to the combination of the seventh capacitor C7, the eleventh resistor R7, and the twelfth resistor R8. When the first output signal output by the voltage-controlled oscillator module is higher than a certain threshold, a reset is triggered, and the output of the flip-flop is cleared to zero. The setting input terminal is connected to the combination of the eighth capacitor C8, the thirteenth resistor R9, and the fourteenth resistor R10. When the first input signal Vin is offset to the setting input terminal of the flip-flop through the eighth capacitor C8, the flip-flop is set to a high-level state. When the first output signal of the voltage-controlled oscillator module 101 is higher than the first input signal Vin, the trigger will be frequently reset, thus maintaining a low output level, causing the phase-locked loop (PLL) process to be fed back to reduce the output frequency. Conversely, if the first input signal Vin is higher than the first output signal of the voltage-controlled oscillator module 101, the trigger will enter the setting state more often, maintaining a high output level, thus increasing the output frequency. As the frequencies of the first input signal Vin and the first output signal gradually approach each other, the state of the trigger becomes more stable, and the frequency of the output signal is finely adjusted to precisely match the frequency of the input signal. At this time, the phase detection module 105 is in a phase-locked state, improving the stability and anti-interference capability of the system. The phase detection module uses capacitors for signal coupling and resistors to adjust circuit parameters, and uses triggers for logic control to achieve locking of the output signal frequency with the input signal frequency. By comparing the frequencies of the output and input signals in real time, the module can adaptively adjust the output frequency, enabling the system to maintain the required accurate frequency under different conditions, thus achieving effective frequency-locking and phase-locking functions.

[0031] Preferably, the seventh capacitor C7 and the eighth capacitor C8 are electrolytic capacitors, and the trigger is an RS trigger. Electrolytic capacitors are suitable for coupling and filtering low-frequency signals, enabling smoothing and delay processing of specific stages. In the phase detection module, electrolytic capacitors help filter out high-frequency noise and smooth the input signal, thus providing more stable comparison conditions. RS triggers respond quickly to signal state changes (such as from reset to set or vice versa), making them suitable for immediate response to frequency changes and maintaining output stability. Compared to complex sequential circuits with multiple inputs and outputs, the simple logic structure of RS triggers is easier to design and implement, reducing circuit complexity and enhancing reliability. The combination of both achieves higher phase-locked loop accuracy and stability. RS triggers can quickly respond to frequency changes, while electrolytic capacitors can smooth the signal and reduce the impact of noise on the trigger.

[0032] This invention provides a clock synchronization circuit. The input signal is converted into a standardized first equal-width pulse signal by an input equal-pulse-width module, which is then compared with the output signal of a voltage-controlled oscillator (VCO) module. The output signal of the VCO module is simultaneously sent to an output equal-pulse-width module and used as a feedback signal to a synchronization feedback module. The synchronization feedback module compares the received second equal-width pulse signal with a preset signal in terms of frequency. Based on the frequency comparison result, it rapidly adjusts the input of the VCO module to change its output frequency, making it match the first input signal as quickly as possible. A phase detection module compares the first output signal with the first input signal in terms of frequency, and uses the comparison result to achieve frequency locking and phase locking, thereby quickly correcting the output signal and ensuring stable output at the new frequency. The input equal-pulse-width module converts the received first input signal into a first equal-width pulse signal with a uniform pulse width, eliminating pulse width inhomogeneity and improving the accuracy of subsequent processing. The output equal-pulse-width module converts the circuit output signal into a second equal-width pulse signal with a uniform pulse width, ensuring that the entire circuit maintains consistency in the output clock. The synchronous feedback module compares the frequency of the second equal-width pulse signal with a preset signal and feeds the comparison result back to the voltage-controlled oscillator module, enabling frequency adjustment and stabilization. Frequency locking and phase locking are achieved based on the frequency comparison result of the first output signal and the first input signal, ensuring the system can quickly adjust to a new frequency state. The clock synchronization circuit enhances the synergy between modules through real-time feedback and dynamic adjustment mechanisms, thereby improving overall frequency stability and rapid adaptability. Due to the optimized design of each module, the efficiency of signal interaction is improved, and the error recognition rate is reduced, enabling the entire circuit to not only adjust quickly when faced with large frequency changes but also maintain signal integrity and accuracy. These improvements make this clock synchronization circuit more competitive and practical in high-frequency signal applications.

[0033] Example 2 See Figure 7 , Figure 7 This is a flowchart illustrating a clock synchronization method provided in one embodiment of the present invention. The present invention provides a clock synchronization method applicable to the clock synchronization circuit described in Embodiment 1, comprising: Step 201: Send the received first input signal to the phase detection module and control the input equal pulse width module to convert the first input signal into a first equal width pulse signal, and send the first equal width pulse signal to the synchronization feedback module; Step 202: The control output equal pulse width module converts the first output signal output by the voltage-controlled oscillator module into a second equal pulse width signal and sends the second equal pulse width signal to the synchronization feedback module; Step 203: Control the phase detection module to perform frequency locking and phase locking on the first input signal and the first output signal based on the trigger, and send the output result of the phase detection module to the synchronization feedback module; Step 204: Control the synchronous feedback module to perform frequency comparison on the second equal-width pulse signal, the first equal-width pulse signal and the preset reference signal, and send the frequency comparison result to the voltage-controlled oscillation module; Step 205: Control the voltage-controlled oscillator module to adjust the frequency of the second equal-width pulse signal based on the frequency comparison result, and send the frequency-adjusted first output signal to the output equal-width module and the phase detection module.

[0034] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working process of the clock synchronization method described above can be referred to the corresponding process of the clock synchronization circuit in the foregoing embodiments, and will not be repeated here.

[0035] This invention provides a clock synchronization method. A received first input signal is converted into a first equal-width pulse signal by an input equal-pulse-width module and quickly output to a synchronization feedback module and a phase detection module. The phase detection module receives a second equal-width pulse signal (output from an output equal-pulse-width module) and the first input signal, performs phase-locking based on the frequency difference, and quickly feeds back the frequency comparison result to the synchronization feedback module. The synchronization feedback module simultaneously compares the second equal-width pulse signal with preset signals (the first equal-width pulse signal and a reference signal) and adjusts the input of the voltage-controlled oscillator module accordingly, actively adjusting the control signal based on frequency changes to maintain synchronization. When a significant change in the reference signal is detected, the system quickly performs frequency adjustment and output update to ensure the output signal is at the same frequency and stable, thereby reducing the impact of phase deviation in the output signal. Adaptive adjustment is implemented in the synchronization feedback module, adjusting the control voltage of the voltage-controlled oscillator module based on real-time frequency comparison information to ensure rapid response to frequency changes in the input signal and reduce frequency locking time. By dynamically adjusting the feedback gain, the gain of the generated output signal is adjusted according to the rate and amplitude of input signal changes, which helps to quickly adapt to sudden frequency changes. By introducing a dynamic pulse width adjustment mechanism into the output pulse width module, the pulse width can be adjusted according to the actual changes in the input signal during circuit operation, thereby ensuring that an accurate clock signal is always provided in a rapidly changing environment.

[0036] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make several improvements and substitutions without departing from the technical principles of the present invention, and these improvements and substitutions should also be considered within the scope of protection of the present invention.

Claims

1. A clock synchronization circuit, characterized in that, include: Voltage-controlled oscillator module, input equal pulse width module, output equal pulse width module, synchronous feedback module and phase detection module; The output terminal of the voltage-controlled oscillator module and the first input signal are respectively connected to the input terminal of the phase detector module; The output terminal of the voltage-controlled oscillation module is also connected to the input terminal of the output equal pulse width module; The output terminals of the output equal pulse width module, the phase detection module, and the input equal pulse width module are respectively connected to the input terminal of the synchronization feedback module. The output of the synchronous feedback module is connected to the input of the voltage-controlled oscillation module; The input equal-width pulse module is used to convert the received first input signal into a first equal-width pulse signal and send the first equal-width pulse signal to the synchronization feedback module; The output equal pulse width module is used to convert the first output signal output by the voltage-controlled oscillator module into a second equal pulse width signal, and send the second equal pulse width signal to the synchronization feedback module; The synchronous feedback module is used to perform a weighted average of the second equal-width pulse signal, the output signal of the phase detection module and the first equal-width pulse signal, compare the frequency with a preset reference signal, and send the frequency comparison result to the voltage-controlled oscillation module. The voltage-controlled oscillator module is used to adjust the frequency of its first output signal according to the frequency comparison result, and send the adjusted first output signal to the phase detection module and the output equal pulse width module; The phase detection module performs frequency locking and phase locking based on the frequency comparison results of the first output signal and the first input signal.

2. The clock synchronization circuit as described in claim 1, characterized in that, The input equal-width pulse module is used to convert the received first input signal into a first equal-width pulse signal and send the first equal-width pulse signal to the synchronization feedback module; the input equal-width pulse module includes a first capacitor, a first resistor, a first NOT gate, and a second NOT gate; The first input signal is connected to the positive terminal of the first capacitor and the input terminal of the phase detection module; The negative terminal of the first capacitor is connected to the first terminal of the first resistor and the input terminal of the first NOT gate; The output of the first NOT gate is connected to the input of the second NOT gate; The output of the second NOT gate is connected to the input of the synchronous feedback module.

3. A clock synchronization circuit as described in claim 1, characterized in that, The output equal pulse width module is used to convert the first output signal output by the voltage-controlled oscillator module into a second equal pulse width signal, and send the second equal pulse width signal to the synchronization feedback module; the output equal pulse width module includes a second capacitor, a second resistor, a third NOT gate, and a fourth NOT gate; The input terminal of the third NOT gate is connected to the output terminal of the voltage-controlled oscillator module and the input terminal of the phase detector module; The output terminal of the third NOT gate is connected to the positive terminal of the second capacitor; The negative terminal of the second capacitor is connected to the first terminal of the second resistor and the input terminal of the fourth NOT gate; The second terminal of the second resistor is grounded; The output of the fourth NOT gate is connected to the input of the synchronous feedback module.

4. A clock synchronization circuit as described in claim 1, characterized in that, The synchronous feedback module is used to perform a weighted average of the second equal-width pulse signal, the output signal of the phase detection module and the first equal-width pulse signal, compare the frequency with a preset reference signal, and send the frequency comparison result to the voltage-controlled oscillation module. The synchronous feedback module includes a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a third capacitor, a fourth capacitor, an operational amplifier, and a voltage source; The first end of the third resistor is connected to the output end of the output equal pulse width module; The first end of the fourth resistor is connected to the output end of the phase detection module; The first end of the fifth resistor is connected to the output end of the input equal pulse width module; The second terminal of the third resistor, the second terminal of the fourth resistor, and the second terminal of the fifth resistor are connected to the positive terminal of the third capacitor, the positive terminal of the fourth capacitor, the first terminal of the sixth resistor, and the negative input terminal of the operational amplifier. The negative terminal of the third capacitor is connected to the second terminal of the sixth resistor, the positive terminal of the voltage source, and the positive input terminal of the operational amplifier; The negative terminal of the voltage source is connected to the preset reference signal.

5. A clock synchronization circuit as described in claim 1, characterized in that, The voltage-controlled oscillator module is used to adjust the frequency of its first output signal according to the frequency comparison result, and send the adjusted first output signal to the phase detection module and the output equal pulse width module; the voltage-controlled oscillator module includes a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a fifth capacitor, a sixth capacitor, a first switch, a first voltage comparator and a second voltage comparator; The first end of the seventh resistor is connected to the output end of the synchronous feedback module and the negative input end of the second voltage comparator. The second end of the seventh resistor is connected to the first end of the eighth resistor and the negative input end of the first voltage comparator; The output terminal of the first voltage comparator is connected to the input terminal of the output equal pulse width module and the input terminal of the phase detection module; The first end of the ninth resistor is connected to the power supply terminal; The second end of the ninth resistor is connected to the first end of the first switch, the positive input terminal of the first voltage comparator, the positive input terminal of the second voltage comparator, and the positive terminal of the fifth capacitor; wherein, when the first switch is closed, the second end of the first switch is connected to the negative terminal of the fifth capacitor; The positive terminal of the sixth capacitor is connected to the first terminal of the tenth resistor and the output terminal of the second voltage comparator; The second terminal of the eighth resistor, the negative terminal of the fifth capacitor, the negative terminal of the sixth capacitor, and the second terminal of the tenth resistor are grounded.

6. A clock synchronization circuit as described in claim 1, characterized in that, The phase detection module performs frequency locking and phase locking based on the frequency comparison result of the first output signal and the first input signal; the phase detection module includes a seventh capacitor, an eighth capacitor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, and a trigger; The positive terminal of the seventh capacitor is connected to the output terminal of the voltage-controlled oscillator module; The negative terminal of the seventh capacitor is connected to the first terminal of the eleventh resistor, the first terminal of the twelfth resistor, and the reset input terminal of the trigger. The positive terminal of the eighth capacitor is connected to the first input signal; The negative terminal of the eighth capacitor is connected to the first terminal of the thirteenth resistor, the first terminal of the fourteenth resistor, and the setting input terminal of the trigger. The second end of the eleventh resistor and the second end of the thirteenth resistor are connected to the power supply terminal; The second terminal of the twelfth resistor and the second terminal of the fourteenth resistor are grounded.

7. A clock synchronization circuit as described in claim 6, characterized in that, The seventh and eighth capacitors are electrolytic capacitors, and the trigger is an RS trigger.

8. A clock synchronization method, characterized in that, Applicable to the clock synchronization circuit as described in any one of claims 1-7, comprising: The received first input signal is sent to the phase detection module and the input equal pulse width module is controlled to convert the first input signal into a first equal width pulse signal, and the first equal width pulse signal is sent to the synchronization feedback module. The control output equal pulse width module converts the first output signal output by the voltage-controlled oscillator module into a second equal pulse width signal and sends the second equal pulse width signal to the synchronous feedback module; The phase detection module is controlled to perform frequency locking and phase locking on the first input signal and the first output signal based on the trigger, and the output signal of the phase detection module is sent to the synchronization feedback module; The synchronous feedback module performs a weighted average of the second equal-width pulse signal, the output signal of the phase detection module, and the first equal-width pulse signal, compares the frequency with a preset reference signal, and sends the frequency comparison result to the voltage-controlled oscillation module. The voltage-controlled oscillator module adjusts the frequency of its first output signal based on the frequency comparison result, and sends the frequency-adjusted first output signal to the output equal pulse width module and the phase detection module.

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