Semiconductor devices and their manufacturing methods

Abstract

This application discloses a semiconductor device and its manufacturing method. The semiconductor device of this application uses body lines drawn from the body contact region inside the transistor as carrier channels to transport carriers induced by different vertical transistors. This results in extremely low off-state current over a wide gate control voltage range, effectively reducing the floating body effect of the semiconductor structure, preventing parasitic PN junction forward conduction, and significantly reducing leakage current. Furthermore, not only is part of the body line located within the body contact region inside the transistor, eliminating the need for additional area, but the bit lines, word lines, and body lines are all arranged in an overlapping manner within the channel region in the first direction, and the connection between them is blocked by an insulating material. This eliminates the inherent spacing between the bit lines, word lines, and body lines in the traditional DRAM array structure of a ring-gate transistor, which is beneficial for the miniaturization of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] In the field of DRAM (Dynamic Random Access Memory), the mainstream process development trend will adopt a vertical transistor structure with source, gate, and drain vertically distributed as the 4F structure, which has a higher storage density. 2 The architecture of DRAM memory cells aims to improve the integration density of DRAM. However, the floating body effect (FBE) and gate-induced drain leakage (GIDL) of traditional vertical channel transistors lead to an increase in the off-state current of the device, which to some extent hinders its further application in high-performance DRAM. Summary of the Invention

[0003] In view of this, this application provides a semiconductor device and a method for manufacturing the same, which, by leading out body lines through body contacts in the vertical channel region, achieves further miniaturization of DRAM memory cells while having extremely low off-state current over a wide range of gate control voltages.

[0004] According to one aspect of this application, a semiconductor device is provided, comprising:

[0005] Substrate;

[0006] A transistor is formed on a substrate, with a channel region formed between adjacent transistors. The transistor includes a surrounding gate layer, a source layer, a drain layer and a body contact layer. The surrounding gate layer is in contact with the source layer and the drain layer. There is a body contact cavity between the source layer and the drain layer. The opening of the body contact cavity is located on the side of the transistor away from the surrounding gate layer. The body contact layer is located inside the body contact cavity.

[0007] Bit lines are formed at the bottom of the channel region and extend along the second direction, and transistors are coupled to the bit lines;

[0008] Word lines, on the dielectric layer of the channel region, extend along a first direction and are perpendicular to the bit lines, wherein the dielectric layer covers the substrate and the bit lines;

[0009] A body line is formed in the body contact cavity and channel region. The body line is in contact with the body contact layer and isolated from the source layer, drain layer and word line. The body line extends along the second direction and is parallel to the bit line.

[0010] Optionally, the transistor also includes:

[0011] A channel layer is formed on the side of the transistor away from the opening of the body contact cavity. In the vertical direction of the semiconductor device, the doping concentration of the first part of the channel layer is higher than that of the second part of the channel layer. The first part of the channel layer is connected to the body contact layer, and the third part of the channel layer is connected to the source layer and the drain layer, respectively. The second part of the channel layer is located between the first part and the third part of the channel layer.

[0012] Optionally, in the vertical direction of the semiconductor device, the height of the first portion of the channel layer is greater than the height of the body contact layer, and the doping type of the channel layer is the same as the doping type of the source layer, drain layer or body contact layer it contacts.

[0013] Optionally, the trench area extends along a second direction.

[0014] Optionally, along the first direction, the spacing between the bit line and the transistor in the first direction is the same as the width of the transistor, and the spacing between the transistors is less than 50 nm.

[0015] According to another aspect of this application, a method for manufacturing a semiconductor device is provided, comprising:

[0016] A matrix of transistors is formed on a substrate, wherein a channel region is formed between adjacent transistors, and the transistor includes a surrounding gate layer, a source layer, a drain layer and a body contact layer. The surrounding gate layer is in contact with the source layer and the drain layer. A body contact cavity is formed between the source layer and the drain layer. The body contact cavity opens toward the side of the transistor away from the surrounding gate layer. The body contact layer is located inside the body contact cavity.

[0017] A bit line extending in a second direction is formed at the bottom of the channel region, and a dielectric layer is deposited thereon, wherein the dielectric layer covers the substrate and the bit line;

[0018] A word line is formed on the dielectric layer, extending along a first direction and perpendicular to the bit line;

[0019] A body line is formed in the body contact cavity and channel region, wherein the body line extends along the second direction and is parallel to the bit line, contacts the body contact layer, and is isolated from the source layer, drain layer, and word line.

[0020] Optionally, the formation of a matrix distribution of transistors on the substrate, with bit lines extending along a second direction formed at the bottom of the channel region, includes:

[0021] A device precursor is fabricated on a substrate, wherein the device precursor includes source / drain structures distributed along a first direction and a first etch sacrificial layer, and a first trench or a second trench extending to the substrate is formed between adjacent source / drain structures. The first etch sacrificial layer covers the source / drain structures and fills the first trench and the second trench. The source / drain structure includes a source layer, a drain layer, a body contact sacrificial layer, and a body contact layer. The body contact sacrificial layer is located between the source layer and the drain layer, and the body contact layer is sandwiched in the body contact sacrificial layer. A channel layer is formed on the inner wall of the first trench.

[0022] The first etch sacrificial layer and the source / drain structure located on the designated side of the second trench are etched according to the device region, and a portion of the source layer on the substrate is retained as a bit line;

[0023] The remaining first etch sacrificial layer is etched, and a dielectric layer is deposited on the substrate and bit lines to form a channel region;

[0024] Remove the body contact sacrificial layer in the source / drain structure to form a body contact cavity that opens toward the side of the source / drain structure away from the channel layer;

[0025] A high dielectric constant material and a metal gate material are deposited in the body contact cavity and on the surface of the source / drain structure. The high dielectric constant material and the metal gate material on the side of the source / drain structure near the opening of the body contact cavity are removed according to a predetermined width to form a gate-around layer to form a transistor, wherein the body contact layer is exposed outside the gate-around layer.

[0026] Optionally, fabricating a device precursor on a substrate includes:

[0027] Along the vertical direction of the semiconductor device, a source layer, a first body contact sacrificial layer, a body contact layer, a second body contact sacrificial layer, and a drain layer are sequentially grown on the substrate to form a stacked structure.

[0028] A patterned structure is formed on a stacked structure using a patterning process, and sidewalls are made on both sides of the patterned structure. The patterned structure includes a core mold sacrificial layer and a second etched sacrificial layer that are grown sequentially.

[0029] The stacked structure is etched using the boundaries of the sidewalls as barriers to form a first trench that extends deep into the substrate.

[0030] A channel layer is grown on the outer side of the inner wall of the first trench;

[0031] Polish the second etched sacrificial layer to expose the core mold sacrificial layer, and then remove the core mold sacrificial layer;

[0032] The stacked structure is etched using the boundary of the sidewalls generated after removing the core mold sacrificial layer as a mask to form a second trench and source / drain structure that extends deep into the substrate.

[0033] A first etch sacrificial layer is deposited on the first trench, the second trench, and the source / drain structure to form a device precursor.

[0034] Optionally, a channel layer is grown epitaxially on the inner wall of the first trench, comprising:

[0035] A single-crystal channel is epitaxially grown on the inner wall of the first trench;

[0036] The single-crystal channel is thermally annealed to drive the stacked structure doping into the single-crystal channel and form a channel layer.

[0037] Optionally, the angle between the device region and the second direction is 55° to 65°.

[0038] Optionally, along the first direction, the width of the die sacrificial layer is equal to the spacing of the transistors, the width of the transistors is the sum of the width of the sidewalls and the thickness of the channel layer, the width of the first trench is the sum of the width of the die sacrificial layer and twice the thickness of the channel layer, and the spacing of the transistors or the width of the transistors is less than 50 nm.

[0039] Optionally, a word line extending along a first direction and perpendicular to the bit line is formed on the dielectric layer in the channel region, including:

[0040] A high dielectric constant material and a metal gate material are sequentially deposited on the dielectric layer;

[0041] Word lines are formed by etching high dielectric constant material and metal gate material on the dielectric layer in the word line region.

[0042] Optionally, a body line is formed in the body contact cavity and channel region, including:

[0043] Etch stop layers are grown on word lines and the surrounding gate layer;

[0044] Remove part of the etching stop layer covering the letter lines to create gaps that expose the letter lines;

[0045] An insulating layer is filled into the cavity and gap of the body contact, while keeping the body contact layer exposed outside the insulating layer;

[0046] Deposit conductive materials on transistor and channel regions;

[0047] The conductive material in contact with the transistor, as well as a portion of the conductive material covering the etch stop layer, is removed to form a body line.

[0048] By employing the aforementioned technical solution, a body line is led out from the body contact region inside the transistor, ensuring that the body line can connect to the transistor. The body line serves as a carrier channel for transporting carriers induced by different vertical transistors. On one hand, this avoids the problem of unstable threshold voltage in vertical transistors due to the presence of excess carriers, resulting in extremely low off-state current over a wide gate control voltage range. This effectively reduces the floating body effect of the semiconductor structure, prevents parasitic PN junctions from forward conducting, and significantly reduces leakage current. On the other hand, the source, gate, and drain are arranged vertically perpendicular to the substrate surface, and part of the body line is located within the body contact region inside the transistor, requiring no additional area. Furthermore, the bit line, word line, and body line are all arranged overlappingly within the channel region in the first direction, and the connection between them is blocked by an insulating material. This eliminates the inherent spacing between the bit line, word line, and body line in the traditional DRAM array structure of a ring-gate transistor, which is beneficial for the miniaturization of semiconductor devices.

[0049] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0050] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0051] Figure 1 A partial cross-sectional view of a semiconductor device provided in an embodiment of this application is shown in a first direction;

[0052] Figure 2 A cross-sectional view of the stacked structure provided in an embodiment of this application is shown in a first direction;

[0053] Figure 3 This application provides a cross-sectional view of the structure along a first direction after the sidewalls have been fabricated.

[0054] Figure 4 A cross-sectional view of the structure along a first direction after the formation of the first trench is shown in an embodiment of this application;

[0055] Figure 5 This shows a cross-sectional view of the structure along the first direction after epitaxial growth of a single crystal channel according to an embodiment of this application;

[0056] Figure 6 This shows a cross-sectional view of the structure along the first direction after the growth channel layer provided in an embodiment of this application;

[0057] Figure 7 A partial cross-sectional view of a device precursor provided in an embodiment of this application is shown in a first direction;

[0058] Figure 8 A top view of the device precursor provided in an embodiment of this application is shown;

[0059] Figure 9 A cross-sectional view of the structure along a first direction after the formation of the channel region is provided in an embodiment of this application is shown;

[0060] Figure 10 This paper shows a cross-sectional view of the structure along the photoresist angle after removing the body contact sacrificial layer according to an embodiment of this application.

[0061] Figure 11 This illustration shows a cross-sectional view along a first direction of a structure provided in an embodiment of this application after sequentially depositing a high dielectric constant material and a conductive material on a dielectric layer;

[0062] Figure 12 A cross-sectional view of the structure along a first direction after forming transistors and word lines, provided in an embodiment of this application, is shown.

[0063] Figure 13 A cross-sectional view of the structure along the first direction after the filling of the isolation layer is provided in an embodiment of this application is shown;

[0064] Figure 14 A cross-sectional view of the structure along a first direction after the deposition line provided in an embodiment of this application is shown.

[0065] Figure label:

[0066] 110 Substrate, 121 Source / Drain Structure, 122 Channel Layer, 123 Single Crystal Channel, 124 Patterned Structure, 125 Sidewall, 126 Gate All-Around Layer, 130 Bit Line, 140 Word Line, 150 Body Line, 160 First Etching Sacrificial Layer, 170 Third Etching Sacrificial Layer, 180 Fourth Etching Sacrificial Layer, 190 Channel Region, 210 First Trench, 221 Dielectric Layer, 220 Second Trench, 230 Etching Stop Layer, 240 Photoresist, 250 Isolation Layer, 1212 Source Layer, 1213 Drain Layer, 1214 Body Contact Layer, 1215 First Body Contact Sacrificial Layer, 1216 Second Body Contact Sacrificial Layer, 1221 First Part of Channel Layer, 1222 Second Part of Channel Layer, 1223 Third Part of Channel Layer, 1241 Oxide Layer, 1242 Mold Sacrificial Layer, 1243 Second Etching Sacrificial Layer. Detailed Implementation

[0067] The present application will be described in detail below with reference to the accompanying drawings and embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in the embodiments of the present application can be combined with each other.

[0068] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0069] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “and,” and “the” used herein may also include the plural forms. It should be further understood that the word “comprising” as used in the specification of this application means the presence of features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Furthermore, the term “and / or” as used herein includes all or any unit and all combinations of one or more associated listed items. The terms “first,” “second,” “third,” etc., used herein are for descriptive purposes only and should not be construed as indicating or implying relative importance; the term “multiple” as used herein refers to two or more unless otherwise expressly defined. The terms “installed,” “connected,” “joined,” “fixed,” etc., as used herein should be interpreted broadly. For example, “connected” can be a fixed connection, a detachable connection, or an integral connection; “joined” can be a direct connection or an indirect connection through an intermediate medium. When we say that an element is “connected” or “attached” to another element, it can be directly connected or connected to other elements, or there may be an intermediate element. For those skilled in the art, the specific meaning of the above terms in the embodiments of the invention can be understood according to the specific circumstances. The terms "upper," "lower," "left," "right," "front," "rear," etc., used herein indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the invention and simplifying the description, and are not intended to indicate or imply that the device or unit referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of the invention.

[0070] Exemplary embodiments according to this application will now be described in more detail with reference to the accompanying drawings. However, these exemplary embodiments may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of this application is thorough and complete, and that the concept of these exemplary embodiments is fully conveyed to those skilled in the art.

[0071] This embodiment provides a semiconductor device, such as Figure 1As shown, taking a DRAM transistor array as an example, the semiconductor device includes: a substrate 110, transistors (not shown in the figure), bit lines 130, word lines 140, and body lines 150.

[0072] Among them, such as Figure 1 and Figure 9 As shown, transistors are formed on substrate 110 and arranged in a matrix, with channel regions 190 between adjacent transistors, such that the channel regions 190 can extend along a second direction.

[0073] The transistor includes a gate surrounding layer 126, a source layer 1212, a drain layer 1213, and a body contact layer 1214. The gate surrounding layer 126 is connected to the source layer 1212 and the drain layer 1213. A body contact cavity is formed between the source layer 1212 and the drain layer 1213. The opening of the body contact cavity is located on the transistor side away from the gate surrounding layer 126. The body contact layer 1214 is located within the body contact cavity and extends along a second direction.

[0074] Bit line 130 is formed at the bottom of channel region 190 and extends along a second direction. Transistor is coupled to bit line 130.

[0075] A word line 140 is formed on a dielectric layer 221 in a channel region 190. The word line 140 extends along a first direction and is perpendicular to the bit line 130. The dielectric layer 221 covers the substrate 110 and the bit line 130 to isolate the word line 140 from the substrate 110 and the bit line 130.

[0076] Body line 150 is formed in the body contact cavity and channel region 190. Body line 150 is in contact with body contact layer 1214 and isolated from source layer 1212, drain layer 1213 and word line 140. Body line 150 extends along the second direction and is parallel to bit line 130.

[0077] In this embodiment, a body line is led out from the body contact region inside the transistor, ensuring that the body line can connect to the transistor. The body line serves as a carrier channel to transport carriers induced by different vertical transistors. On one hand, this avoids the problem of unstable threshold voltage of vertical transistors due to the presence of excess carriers, resulting in extremely low off-state current over a wide gate control voltage range. This effectively reduces the floating body effect of the semiconductor structure, prevents parasitic PN junctions from forward conducting, and significantly reduces leakage current. On the other hand, the source, gate, and drain are arranged vertically perpendicular to the substrate surface, and part of the body line is located in the body contact region inside the transistor, requiring no additional area. At the same time, the bit line, word line, and body line are all arranged in an overlapping manner in the channel region in the first direction, and the connection between the three is blocked by an isolation material. This eliminates the inherent spacing between the bit line, word line, and body line in the traditional DRAM array structure of a ring-gate transistor, which is beneficial for the miniaturization of semiconductor devices.

[0078] It is understandable that, along the first direction, the spacing between the bit line and the transistor in the first direction is the same as the width of the transistor. The spacing between the transistors is less than 50nm, such as 10nm, 15nm, 26nm, etc., which helps to reduce the size of semiconductor devices.

[0079] Specifically, the substrate can be formed from silicon-containing semiconductor materials, such as silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, or a combination or multiple layers thereof. Taking a P-well / NMOS device as an example, a P-type well region is implanted on monocrystalline silicon to form a substrate with a P-type well region.

[0080] The body contact layer can be a conductive material such as a metal, metal nitride, or metal silicide, for example, heavily doped p-type silicon (P+Si). The bit line can be a semiconductor material, a metal-based material, or a combination thereof, for example, heavily doped n-type silicon. The word line, body line, and gate surround layer can include silicon oxide, silicon nitride, silicon oxide nitride, high-dielectric materials, or a combination thereof. The source and drain layers can be semiconductor materials doped with p-type or n-type impurities. For example, for p-type devices, the source and drain layers can be p-type doped silicon or germanium-silicon; for n-type devices, the source and drain layers can be n-type doped silicon or germanium-silicon.

[0081] In one embodiment, such as Figure 1 As shown, a channel layer 122 is provided on the side of the transistor surrounding the gate layer 126 (the side of the transistor away from the opening of the body contact cavity). The channel layer 122 can be connected to the source layer 1212, the drain layer 1213 and the body contact layer 1214, thereby forming a sidewall of the body contact cavity away from the opening. At least a portion of the channel layer 122 is located between the gate layer 126 and at least one of the source layer 1212, the drain layer 1213 and the body contact layer 1214.

[0082] Specifically, such as Figure 6 As shown, in the vertical direction of the semiconductor device, the doping concentration of the first portion 1221 of the channel layer is higher than that of the second portion 1222 of the channel layer. The first portion 1221 of the channel layer is connected to the body contact layer 1214, and the third portion 1223 of the channel layer is connected to the source layer 1212 and the drain layer 1213, respectively. The second portion 1222 of the channel layer is located between the first portion 1221 and the third portion 1223 of the channel layer. The thickness of the channel layer 122 is between 3nm and 20nm, for example, 5nm, 8nm, 10nm, 15nm, etc., and can be reasonably set according to the transistor size.

[0083] Understandably, the channel layer can be formed through epitaxial growth.

[0084] In this embodiment, due to the high doping concentration of the first part of the channel layer and the low doping concentration of the second part of the channel layer, the low doping concentration of the second part of the channel layer can reduce the energy band barrier along the channel direction, obtain a more stable electric field and energy band, thereby suppressing interband tunneling and reducing gate-induced drain leakage.

[0085] It is worth mentioning that, such as Figure 6 As shown, in the vertical direction of the semiconductor device, the height of the first portion 1221 of the channel layer is greater than the height of the body contact layer 1214. Thus, since the body contact layer 1214 is connected to the first portion 1221 with a high doping concentration, and at the same time ensuring that the first portion 1221 of the channel layer does not affect the region where gate-induced drain leakage occurs, a significant depletion region can exist, thereby enabling the body contact layer bias voltage to control the off-state current of the semiconductor device.

[0086] Furthermore, the channel layer can be symmetrical or asymmetrical with respect to the body contact layer, that is, the extension height of the first, second and third portions of the channel layer above the body contact layer is the same as or different from the extension height of the corresponding first, second and third portions below the body contact layer.

[0087] This embodiment provides a method for manufacturing a semiconductor device, the method comprising:

[0088] Step 301: Form a matrix distribution of transistors on the substrate.

[0089] In this transistor, a channel region is formed between adjacent transistors. The transistor includes a surrounding gate layer, a source layer, a drain layer, and a body contact layer. The surrounding gate layer is in contact with the source and drain layers for isolation. There is a body contact cavity between the source and drain layers. The body contact cavity opens toward the transistor side away from the surrounding gate layer. The body contact layer is located in the body contact cavity to form a body-contacted vertical channel transistor (BCVCT).

[0090] Step 302: A bit line extending in the second direction is formed at the bottom of the channel region, and a dielectric layer is deposited.

[0091] The dielectric layer covers the substrate and bit lines.

[0092] In this embodiment, bit lines are first fabricated at the bottom of the channel region between transistors. This ensures connectivity between transistors and bit lines while combining the bit line layout with a matrix-distributed transistor structure. This allows bit lines to connect multiple transistors in a regular manner, reducing the space occupied by bit lines on the chip and optimizing space utilization in the semiconductor device. Next, a dielectric layer is deposited in the channel region to cover the substrate and bit lines within the channel region. This effectively isolates the transistors and bit lines from other conductive structures, helping to reduce parasitic capacitance and resistance, and preventing electromagnetic interference and signal crosstalk, thereby improving the operating efficiency and response speed of the semiconductor device.

[0093] Furthermore, as a refinement and extension of the specific implementation of the above embodiments, in order to fully illustrate the specific implementation process of this embodiment, steps 301 and 302, namely forming a matrix distribution of transistors on the substrate and forming a bit line extending along the second direction at the bottom of the channel region, specifically include:

[0094] A device precursor is fabricated on a substrate; a first etch sacrificial layer and a source / drain structure located on a designated side of a second trench are etched according to the device region, while retaining a portion of the source layer on the substrate as a bit line; the remaining first etch sacrificial layer is etched, and a dielectric layer is deposited on the substrate and the bit line to form a channel region; the body contact sacrificial layer in the source / drain structure is removed to form a body contact cavity opening towards the side of the source / drain structure away from the channel layer; a high dielectric constant material and a metal gate material are deposited in the body contact cavity and on the surface of the source / drain structure, and the high dielectric constant material and the metal gate material on the side of the source / drain structure near the opening of the body contact cavity are removed according to a preset width to form a gate-around layer to form a transistor.

[0095] The body contact layer is exposed outside the surrounding gate layer to facilitate subsequent connection with the body wire. For example... Figure 7 , Figure 8 and Figure 9 As shown, the device precursor includes source / drain structures 121 distributed along a first direction and a first etched sacrificial layer 160. Adjacent source / drain structures 121 have a first trench 210 or a second trench 220 extending to the substrate 110. The first etched sacrificial layer 160 covers the source / drain structures 121 and fills the first trench 210 and the second trench 220. The source / drain structure 121 includes a source layer 1212, a drain layer 1213, a body contact sacrificial layer, and a body contact layer 1214. The body contact sacrificial layer is located between the source layer 1212 and the drain layer 1213, and the body contact layer 1214 is sandwiched within the body contact sacrificial layer. A channel layer 122 is formed on the inner wall of the first trench 210. Specifically, the angle α between the device region and the second direction is 55° to 65°. This angle can be flexibly determined according to process conditions and product requirements; this embodiment does not impose a specific limitation.

[0096] Further, the fabrication of the device precursor on the substrate specifically includes: sequentially growing a source layer, a first body contact sacrificial layer, a body contact layer, a second body contact sacrificial layer, and a drain layer on the substrate along the vertical direction of the semiconductor device to form a stacked structure; forming a patterned structure on the stacked structure using a patterning process, and fabricating sidewalls on both sides of the patterned structure, wherein the patterned structure includes a core mold sacrificial layer and a second etched sacrificial layer grown sequentially; etching the stacked structure using the boundary of the sidewall as a barrier to form a first trench extending into the substrate; epitaxially growing a channel layer on the inner wall of the first trench; polishing the second etched sacrificial layer to expose the core mold sacrificial layer, and removing the core mold sacrificial layer; etching the stacked structure using the boundary of the sidewall generated after removing the core mold sacrificial layer as a mask to form a second trench extending into the substrate and a source / drain structure; depositing a first etched sacrificial layer on the first trench, the second trench, and the source / drain structure to form the device precursor.

[0097] The patterning process includes steps such as deposition, exposure, and etching.

[0098] In this embodiment, after completing one etching using the core mold sacrificial layer, the remaining spacer layer is used as a mask to continue etching the stacked structure, thereby achieving spatial frequency multiplication of the pattern and avoiding edge placement errors that may occur when cutting separately at two locations.

[0099] Furthermore, a channel layer is epitaxially grown on the inner wall of the first trench, specifically including: epitaxially growing a single crystal channel on the inner wall of the first trench; and performing thermal annealing on the single crystal channel to drive the stacked structure doping into the single crystal channel to form a channel layer.

[0100] For example, such as Figure 2 As shown, N-type or P-type well regions are implanted on a suitable substrate 110 to serve as the corresponding regions for subsequent P-type or N-type transistor devices, respectively. Specifically, for P-wells...

[0101] For P-type / NMOS devices, P-type implantation is used, while for N-well / NMOS devices, N-type implantation is used. The doping concentration can be adjusted according to the type of dopant. Taking a P-well / NMOS device as an example, in the well region (P-Si) of the substrate 110, the following materials are stacked and epitaxially layered from bottom to top along the vertical direction of the semiconductor device to form a stacked structure: heavily doped N-type silicon (N+Si), intrinsic silicon (i-Si), intrinsic germanium silicon (i-SiGe), thin heavily doped P-type germanium silicon (P+SiGe), thin heavily doped P-type silicon (P+Si), thin heavily doped P-type germanium silicon (P+SiGe), intrinsic germanium silicon (i-SiGe), intrinsic silicon (i-Si), and heavily doped N-type silicon (N+Si). The first layer of heavily doped N-type silicon and the first layer of intrinsic silicon are used to fabricate the source layer 1212. After thermal annealing, the first layer of intrinsic silicon is also heavily doped by diffusion through the heavily doped N-type silicon to prevent the N-type heavy dopant from diffusing into the intrinsic channel during thermal annealing, thus preventing channel shortening and avoiding short-channel effects. The intrinsic germanium silicon and the thin layer of heavily doped P-type germanium silicon on the source layer 1212 are used to fabricate the first body contact sacrificial layer 1215 of the source layer 1212. The thin layer of heavily doped P-type silicon is used to fabricate the body contact layer 1214. The intrinsic germanium silicon and the thin layer of heavily doped P-type germanium silicon on the body contact layer 1214 are used to fabricate the second body contact sacrificial layer 1216. The last layer of intrinsic silicon and the last layer of heavily doped N-type silicon are used to fabricate the drain layer 1213. Specifically, the thickness of the thin layer can be adjusted according to the specific device performance requirements to facilitate the formation of a low-doped region corresponding to the channel layer through thermal annealing. The heavy doping concentration is approximately 1e19cm-3 to 1e20cm-3, which can be adjusted according to the specific device performance requirements.

[0102] like Figure 3 As shown, a thin oxide layer 1241, a core mold sacrificial layer 1242 (which can be made of amorphous silicon), and a second etch sacrificial layer 1243 (which can be made of silicon oxide) are deposited on the stacked structure to form a patterned structure 124. Then, using patterning and silicon oxide sidewall 125 processes, sidewalls 125 are fabricated on both sides of the patterned structure 124 to define the source / drain regions below the sidewall 125 structure. Wherein, as... Figure 4As shown, the width of the die sacrificial layer 1242 is the spacing (a) of the transistors to be fabricated. For an array of equally spaced, equal-width devices, the spacing between transistors is the same as the width of the transistors. Therefore, the width (a) of the transistors is the sum of the width of the sidewall 125 and the thickness (b) of the channel layer 122. Thus, after the channel layer 122 is deposited in the first trench 210, the remaining space width within the first trench 210 can be the same as the width of the transistors, thereby ensuring the formation of an equally spaced, equal-width device array. An equally spaced, equal-width device array means that the device spacing and device width are equal to each other. The device spacing and device width can be set to any value as needed; they can be the same or different. In this embodiment, the device spacing and device width are the same. For example, the spacing or width of the transistors is approximately 15 nm.

[0103] like Figure 3 and Figure 4 As shown, the sidewall 125 is etched as a barrier layer to transfer the pattern of the underlying stacked structure, forming the first trench 210. Figure 4 and Figure 5 As shown, a single-crystal channel 123 is formed by epitaxial single-crystal Si on the inner surface of the newly formed first trench 210. The width of the first trench 210 is the sum of the width (a) of the core mold sacrificial layer 1242 and twice the thickness of the channel layer 122 (2b), to ensure that the spacing between the two epitaxial single-crystal channels 123 is also the width (a) of the core mold sacrificial layer 1242. Figure 6 As shown, through appropriate heat annealing... Figure 2 The formed stacked structure is doped into the epitaxially formed single-crystal channel 123 to form a channel layer 122 with low doping at both ends and uniformly high doping in the middle. After filling with the first etched sacrificial layer 160 and planarizing with chemical mechanical polishing to expose the surface of the core mold sacrificial layer 1242, and after wet removal of the core mold sacrificial layer 1242, the Si layer and SiGe layer in the stacked structure are etched using the sidewalls formed by removing the core mold sacrificial layer 1242 as a mask, exposing all the SiGe layers on the sides, forming a second trench 220 extending to the substrate 110 and a source / drain structure 121. After the sacrificial layer is filled, the structure is formed as follows: Figure 7 and Figure 8 The device precursor shown.

[0104] like Figure 8 As shown, a single device region is defined on the device precursor by photolithography. The photoresist pattern 240 forms an angle α of approximately 60° with the vertical direction (the second direction extending from bit line 130) in the figure. For ease of understanding, Figure 8 Only two photoresist lines 240 are shown; in reality, they should be evenly spaced and cover the entire plane. Furthermore, to facilitate understanding of the positional relationship between the source / drain structure 121 and the trench, the first etch sacrificial layer 160 above the source / drain structure 121 is hidden. This is actually to protect the source / drain structure 121. Figure 7The first etched sacrificial layer 160 shown can cover the source / drain structure 121. The area covered by the photoresist 240 is designated as the desired device cell region. The etched sacrificial layer outside the photoresist 240 is opened, leaving only a portion of the bottom source layer 1212 connected as a bitline 130. Figure 9 As shown, after removing the photoresist 240, the first etch sacrificial layer 160 is filled and etched back to remove the remaining first etch sacrificial layer 160, and a dielectric layer 221 is deposited on the substrate 110 and bit line 130 in the second trench 220, thereby forming a channel region 190 between the source and drain structures 121. Figure 10 As shown, SiGe, i.e. the bulk contact sacrificial layer, is removed by selective dry or wet etching, thereby forming a device structure with a thin bulk contact layer 1214, a wide channel with uniform doping at the center and low doping on both sides of the channel.

[0105] Step 303: Form word lines on the dielectric layer that extend along the first direction and are perpendicular to the bit lines.

[0106] In this embodiment, word lines extending along a first direction are formed on the dielectric layer covering the bit lines. This achieves an isolated and vertically intersecting bit-word line layout, resulting in a relatively small overlap area between the bit lines and word lines, effectively reducing parasitic capacitance between them, and minimizing electric field scattering and leakage. Furthermore, it allows for accommodating more transistors on a given substrate area, facilitating the positioning and operation of each transistor via corresponding bit lines and word lines, thus achieving higher storage density.

[0107] Furthermore, as a refinement and extension of the specific implementation of the above embodiments, in order to fully illustrate the specific implementation process of this embodiment, step 303 specifically includes: sequentially depositing a high dielectric constant material and a metal gate material on the dielectric layer; etching the high dielectric constant material and the metal gate material on the dielectric layer according to the word line region to form word lines.

[0108] Step 304: Form body lines in the body contact cavity and channel region.

[0109] The body line extends along the second direction and is parallel to the bit line, contacts the body contact layer, and is isolated from the source layer, drain layer, and word line.

[0110] In this embodiment, a body line is led out from the body contact region inside the transistor, ensuring that the body line can connect to the transistor. The body line serves as a carrier channel to transport carriers induced by different vertical transistors. On the one hand, this avoids the problem of unstable threshold voltage of vertical transistors due to the presence of excess carriers, resulting in extremely low off-state current over a wide gate control voltage range. This effectively reduces the floating body effect of the semiconductor structure, prevents parasitic PN junctions from forward conducting, and significantly reduces leakage current. On the other hand, the source, gate, and drain are arranged vertically perpendicular to the substrate surface, and part of the body line is located in the body contact region inside the transistor, eliminating the need for additional area. Furthermore, the bit line, word line, and body line are all arranged overlappingly in the channel region in the first direction, and the connection between them is blocked by an insulating material. This eliminates the inherent spacing between the bit line, word line, and body line in the traditional DRAM array structure of a ring-gate transistor, which is beneficial for the miniaturization of semiconductor devices.

[0111] Furthermore, as a refinement and extension of the specific implementation of the above embodiments, in order to fully illustrate the specific implementation process of this embodiment, step 304 specifically includes: growing an etch stop layer on the word line and the surrounding gate layer; removing a portion of the etch stop layer covering the word line to form a gap exposing the word line; filling the body contact cavity and gap with an isolation layer, while keeping the body contact layer exposed outside the isolation layer; depositing conductive material on the transistor and channel region; removing the conductive material in contact with the transistor, as well as a portion of the conductive material covering the etch stop layer, to form a body line.

[0112] For example, such as Figure 11 As shown, HKMG ALD (High-kMetal Gate Atomic Layer Deposition) is performed on the dielectric layer 221 and the source / drain structure 121, thus forming the VGAA (Vertical Gate-All-Around) structure of the device. Subsequently, the word line region 140 is defined by photolithography. Anisotropic etching is performed on the word line region to remove the resist and grow an etch stop layer 230 on the VGAA structure. The etch stop layer 230 can be made of silicon nitride (SiN). A third etch sacrificial layer 170 is filled to protect the device, and chemical mechanical polishing is performed for planarization.

[0113] like Figure 12As shown, the third etch sacrificial layer 170 on one side of the channel layer 122 is protected by photoresist 240, and the exposed third etch sacrificial layer 170 is removed to a certain depth. After photoresist removal, isotropic etching is performed again to sequentially remove the metal gate and high-dielectric material, exposing the word line 140, source layer 1212, drain layer 1213, and body contact layer 1214. At this time, the remaining high-dielectric material and metal gate connected to the source / drain structure 121 and the channel layer 122 constitute the gate-around layer 126 of the transistor, and the remaining high-dielectric material and metal gate in the channel region 190 constitute the word line 140. The metal gate can be composed of a layer that modulates the work function (such as AlO) and a conductive material (such as W, Al).

[0114] like Figure 13 As shown, after HK-ALD is performed again, anisotropic high-dielectric material etching and a small amount of isotropic etching are performed sequentially to expose the contact layer 1214, forming the isolation layer 250. Finally, the exposed third etched sacrificial layer 170 is removed by wet etching.

[0115] like Figure 14 As shown, conductive material, such as tungsten, is deposited within the channel region 190 to form the baseline 150, and the fourth etch sacrificial layer 180 is etched back to protect the subsequent shaping of the baseline 150. The etch stop layer 230 and the fourth etch sacrificial layer 180 are used as stop layers for the etch back. After removing the exposed fourth etch sacrificial layer 180, the remaining tungsten on the etch stop layer 230, which can connect to the body contact layer 1214, constitutes the baseline 150. The baseline 150 is parallel to the bit line 130, and photolithographic etching defines the baseline 150, thus forming the baseline 150. Figure 1 The entire electrical structure of the front and middle sections is shown. Among them, the word line 140 extends along the first direction and is perpendicular to the position line 130 and the body line 150, and the position line 130 and the body line 150 are parallel to each other and extend along the second direction perpendicular to the first direction.

[0116] Optionally, the top n-Si can be removed anisotropically to ensure no short circuit. In this embodiment, the material for etching the sacrificial layer can be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, etc. The conductive material can also be a metal such as aluminum. Figure 1 and Figure 14 The example used is tungsten (W). Alternatively, a metal grid material can also be used to fabricate this body line.

[0117] It should be noted that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0118] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of a preferred embodiment, and the modules or processes shown in the drawings are not necessarily essential for implementing this application.

[0119] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0120] The serial numbers in this application are for descriptive purposes only and do not represent the superiority or inferiority of any particular implementation scenario. The above disclosures are merely a few specific implementation scenarios of this application; however, this application is not limited thereto, and any variations conceived by those skilled in the art should fall within the protection scope of this application.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A transistor is formed on the substrate, with a channel region formed between adjacent transistors. The transistor includes a surrounding gate layer, a source layer, a drain layer, and a body contact layer. The surrounding gate layer is in contact with the source layer and the drain layer. A body contact cavity is formed between the source layer and the drain layer. The opening of the body contact cavity is located on the side of the transistor away from the surrounding gate layer. The body contact layer is located within the body contact cavity. Bit lines are formed at the bottom of the channel region and extend along a second direction, and the transistor is coupled to the bit lines; A word line is formed on a dielectric layer in the channel region, the word line extending along a first direction and perpendicular to the bit line, wherein the dielectric layer covers the substrate and the bit line; A body line is formed in the body contact cavity and the channel region, the body line is in contact with the body contact layer and isolated from the source layer, the drain layer and the word line, wherein the body line extends along a second direction and is parallel to the bit line.

2. The semiconductor device according to claim 1, characterized in that, The transistor also includes: A channel layer is formed on the side of the transistor away from the opening of the body contact cavity. In the vertical direction of the semiconductor device, the doping concentration of the first portion of the channel layer is higher than that of the second portion of the channel layer. The first portion of the channel layer is connected to the body contact layer. The third portion of the channel layer is connected to the source layer and the drain layer, respectively. The second portion of the channel layer is located between the first portion and the third portion of the channel layer. In the vertical direction of the semiconductor device, the height of the first portion of the channel layer is greater than the height of the body contact layer, and the doping type of the channel layer is the same as the doping type of the source layer, the drain layer or the body contact layer it contacts.

3. The semiconductor device according to claim 1, characterized in that, The trench area extends along the second direction; Along the first direction, the spacing between the bit line and the transistor in the first direction is the same as the width of the transistor, and the spacing between the transistors is less than 50 nm.

4. A method for manufacturing a semiconductor device, characterized in that, The method includes: A matrix of transistors is formed on a substrate, wherein a channel region is formed between adjacent transistors, and each transistor includes a surrounding gate layer, a source layer, a drain layer and a body contact layer. The surrounding gate layer is in contact with the source layer and the drain layer, and a body contact cavity is formed between the source layer and the drain layer. The body contact cavity opens toward the side of the transistor away from the surrounding gate layer, and the body contact layer is located within the body contact cavity. A bit line extending in a second direction is formed at the bottom of the channel region, and a dielectric layer is deposited thereon, wherein the dielectric layer covers the substrate and the bit line; A word line is formed on the dielectric layer, extending in a first direction and perpendicular to the bit line; A body line is formed in the body contact cavity and the channel region, wherein the body line extends along a second direction and is parallel to the bit line, contacts the body contact layer, and is isolated from the source layer, the drain layer, and the word line.

5. The method for manufacturing a semiconductor device according to claim 4, characterized in that, The transistors formed in a matrix distribution on the substrate, wherein bit lines extending along a second direction are formed at the bottom of the channel region, include: A device precursor is fabricated on the substrate, wherein the device precursor includes source / drain structures distributed along a first direction and a first etch sacrificial layer, and a first trench or a second trench extending to the substrate is formed between adjacent source / drain structures. The first etch sacrificial layer covers the source / drain structures and fills the first trench and the second trench. The source / drain structure includes a source layer, a drain layer, a body contact sacrificial layer, and a body contact layer. The body contact sacrificial layer is located between the source layer and the drain layer, and the body contact layer is sandwiched in the body contact sacrificial layer. The channel layer is formed on the inner wall of the first trench. The first etch sacrificial layer and the source / drain structure located on the designated side of the second trench are etched according to the device region, and a portion of the source layer on the substrate is retained as the bit line; The remaining first etch sacrificial layer is etched, and a dielectric layer is deposited on the substrate and the bit line to form the channel region; Remove the body contact sacrificial layer in the source / drain structure to form the body contact cavity that opens toward the side of the source / drain structure away from the channel layer; A high dielectric constant material and a metal gate material are deposited in the body contact cavity and on the surface of the source / drain structure. The high dielectric constant material and the metal gate material on the source / drain structure near the opening of the body contact cavity are removed according to a preset width to form the surrounding gate layer to form the transistor, wherein the body contact layer is exposed outside the surrounding gate layer.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that, The fabrication of the device precursor on the substrate includes: The source layer, the first body contact sacrificial layer, the body contact layer, the second body contact sacrificial layer, and the drain layer are sequentially grown on the substrate along the vertical direction of the semiconductor device to form a stacked structure. A patterned structure is formed on the stacked structure using a patterning process, and sidewalls are fabricated on both sides of the patterned structure. The patterned structure includes a core mold sacrificial layer and a second etched sacrificial layer that are grown sequentially. The stacked structure is etched using the boundary of the sidewall as a barrier to form the first trench that extends deep into the substrate; The channel layer is grown epitaxially on the inner wall of the first trench; Polish the second etched sacrificial layer to expose the core mold sacrificial layer, and remove the core mold sacrificial layer; Using the boundary of the sidewalls generated after removing the core mold sacrificial layer as a mask, the stacked structure is etched to form the second trench extending into the substrate and the source / drain structure; The first etch sacrificial layer is deposited on the first trench, the second trench, and the source / drain structure to form the device precursor.

7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The step of growing the channel layer on the outer side of the inner wall of the first trench includes: A single-crystal channel is epitaxially grown on the inner wall of the first trench; The single-crystal channel is subjected to thermal annealing to drive the stacked structure into the single-crystal channel, forming the channel layer.

8. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The angle between the device region and the second direction is 55°~65°; Along the first direction, the width of the die sacrificial layer is equal to the spacing of the transistors, the width of the transistors is the sum of the width of the sidewall and the thickness of the channel layer, the width of the first trench is the sum of the width of the die sacrificial layer and twice the thickness of the channel layer, and the spacing of the transistors is less than 50 nm.

9. The method for manufacturing a semiconductor device according to claim 4, characterized in that, The formation of a word line extending in a first direction and perpendicular to the bit line on the dielectric layer in the channel region includes: A high dielectric constant material and a metal gate material are sequentially deposited on the dielectric layer; The word lines are formed by etching the high dielectric constant material and the metal gate material on the dielectric layer according to the word line region.

10. The method for manufacturing a semiconductor device according to claim 4, characterized in that, The formation of a body line in the body contact cavity and the channel region includes: An etch stop layer is grown on the word line and the surrounding gate layer; Remove a portion of the etch stop layer covering the word lines to create gaps that expose the word lines; An insulating layer is filled into the body contact cavity and gap, while keeping the body contact layer exposed outside the insulating layer; Conductive material is deposited on the transistor and the channel region; The conductive material in contact with the transistor, as well as a portion of the conductive material covering the etch stop layer, is removed to form the body line.

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