Semiconductor device and method for manufacturing the same

Abstract

The present invention discloses a semiconductor device and a manufacturing method thereof, belonging to the field of semiconductor technology, the manufacturing method comprising: providing a substrate, forming a shielding gate lead groove and a shielding gate groove in the substrate, the opening width of the shielding gate lead groove being less than half of the opening width of the shielding gate groove; depositing a shielding gate dielectric layer in the substrate and the groove; depositing a first gate material layer on the shielding gate dielectric layer, the surface of which is flush with the surface of the substrate; forming a protective layer on the first gate material layer, the surface of which is flush with the surface of the shielding gate dielectric layer; removing the protective layer in the shielding gate groove by oblique etching on both sides; removing part of the first gate material layer in the shielding gate groove to form a shielding gate and a lead gate; forming an inter-gate dielectric layer with a flat surface on the shielding gate; forming a control gate on the inter-gate dielectric layer. The semiconductor device and the manufacturing method thereof provided by the present invention can improve the performance of the semiconductor device and reduce the production cost.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a semiconductor device and a manufacturing method thereof. Background Art

[0002] The shielded gate trench (SGT) structure has a charge coupling effect. It introduces horizontal depletion on the basis of the vertical depletion of the traditional trench metal oxide semiconductor field effect transistor (MOSFET), which can enable semiconductor devices to obtain higher breakdown voltages. This structure is widely used in the field of medium and low voltage power devices. However, during the manufacturing process, the controllability of the manufacturing process is low. For example, when forming a shielded gate, it is necessary to add a photolithography process to protect the shielded gate lead area as a subsequent shielded gate metal connection, and to etch the shielded gate in other areas. The added photolithography process greatly increases the cost of SGT. In addition, during the manufacturing process, the dielectric layer on both sides of the shielded gate is removed too much, which is easy to form grooves on both sides of the shielded gate. When the subsequent shielded gate is formed, it will be deposited in the pit to form a sharp corner, which makes the two gates prone to leakage problems. Summary of the invention

[0003] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same. The semiconductor device and the method for manufacturing the same provided by the present invention can improve the gate leakage problem, improve the performance of the semiconductor device, save a photolithography process, and reduce production costs.

[0004] In order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device, which at least comprises the following steps:

[0005] Providing a substrate, and sequentially forming a pad oxide layer and a pad nitride layer on the substrate;

[0006] forming a shielding gate lead groove and a shielding gate groove in the substrate, wherein the opening width of the shielding gate lead groove is less than half of the opening width of the shielding gate groove;

[0007] Depositing a shielding gate dielectric layer in the substrate, the shielding gate lead trench and the shielding gate trench;

[0008] forming a protective layer on the first gate material layer, wherein a surface of the protective layer is flush with a surface of the shielding gate dielectric layer;

[0009] forming a protective layer in the shielding gate lead groove and the shielding gate groove, wherein the surface of the protective layer is flush with the surface of the shielding gate dielectric layer;

[0010] Performing oblique etching from both sides of the substrate to remove the protective layer in the shield gate trench;

[0011] Etching and removing a portion of the first gate material layer in the shielding gate trench to form a shielding gate and a lead gate;

[0012] forming an inter-gate dielectric layer on the shielding gate, wherein the surface of the inter-gate dielectric layer is flat; and

[0013] A control gate is formed on the inter-gate dielectric layer.

[0014] In one embodiment of the present invention, the etching angles α of the inclined etching performed on both sides of the substrate are equal, and one inclined etching exposes half of the first gate material layer on the shielding gate trench. The etching angle α is the angle between the etching direction and the substrate normal.

[0015] In one embodiment of the present invention, the etching angle α is smaller than a preset angle β, and the preset angle β is obtained by the formula β=arctan(a / b), wherein a is the difference between half of the opening width of the shielding gate groove and the thickness of the shielding gate dielectric layer on the side wall of the shielding gate groove, and b is the thickness of the protective layer on the substrate.

[0016] In one embodiment of the present invention, the material of the protective layer and the shielding gate dielectric layer have an etching selectivity ratio, and the protective layer is removed by selective dry etching. After removing the protective layer in the shielding gate groove, a portion of the protective layer remains on the first gate material layer in the shielding gate lead groove.

[0017] In one embodiment of the present invention, the manufacturing method further includes:

[0018] After forming the shielding gate, forming a first dielectric layer on the shielding gate and the shielding gate dielectric layer, wherein the thickness of the first dielectric layer on the shielding gate is greater than the total thickness of the shielding gate dielectric layer and the first dielectric layer on the sidewall of the shielding gate trench;

[0019] planarizing and removing the shield gate dielectric layer and the first dielectric layer on the pad nitride layer; and

[0020] The shielding gate dielectric layer and the first dielectric layer on the sidewalls of the shielding gate trench are removed, and a portion of the first dielectric remains on the shielding gate, and the first dielectric layer is flush with the shielding gate dielectric layer on both sides.

[0021] In one embodiment of the present invention, the manufacturing method further includes: after removing the shield gate dielectric layer and the first dielectric layer on the sidewall of the shield gate trench, removing the pad nitride layer and the pad oxide layer, after removing the pad oxide layer, the remaining thickness of the first dielectric is 0~300nm.

[0022] In one embodiment of the present invention, an oxide layer is formed on the substrate and in the shielding gate trench.

[0023] In an embodiment of the present invention, the oxide layer is formed on the sidewalls of the shielding gate trench, and the oxide layer, the first dielectric and the shielding gate dielectric layers on both sides of the first dielectric are the inter-gate dielectric layers.

[0024] In one embodiment of the present invention, the oxide layer is formed on the sidewall and the bottom of the shield gate trench, and the oxide layer is the inter-gate dielectric layer.

[0025] The present invention also provides a semiconductor device, comprising at least:

[0026] substrate;

[0027] A shielding gate lead groove and a shielding gate groove are arranged in the substrate, and the opening width of the shielding gate lead groove is less than half of the opening width of the shielding gate groove;

[0028] A lead grid is arranged in the shield grid lead groove;

[0029] A shielding gate is arranged at the bottom of the shielding gate trench;

[0030] a shielding gate dielectric layer, disposed between the lead gate and the substrate and between the shielding gate and the substrate; and

[0031] A control gate is arranged on the shielding gate, an inter-gate dielectric layer is arranged between the control gate and the shielding gate, and the surface of the inter-gate dielectric layer is flat.

[0032] In summary, the present invention provides a semiconductor device and a method for manufacturing the same. The unexpected technical effect of the present application is that it can save a photolithography process and reduce production costs. During the manufacturing process, it is possible to reduce the defects of the semiconductor device, avoid the formation of sharp corners at the bottom of the control gate, avoid leakage between the control gate and the shielding gate, improve the gate leakage problem, and improve the performance of the semiconductor device. It is possible to ensure that no voids are formed in the shielding gate, improve the quality of the shielding gate, thereby ensuring the performance of the shielding gate, reduce the conduction resistance and switching loss of the semiconductor device, enable the semiconductor device to obtain a higher breakdown voltage, and improve the performance of the semiconductor device.

[0033] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0035] Figure 1 FIG. 1 is a schematic diagram of positioning a first opening and a second opening on a substrate in one embodiment.

[0036] Figure 2 FIG. 1 is a schematic diagram of forming a shielding gate lead trench and a shielding gate trench in a substrate in an embodiment.

[0037] Figure 3 FIG. 4 is a schematic diagram of forming a shielding gate dielectric layer in an embodiment.

[0038] Figure 4 FIG. 1 is a schematic diagram of an embodiment after forming a first gate material layer and performing etching back.

[0039] Figure 5 FIG. 1 is a schematic diagram of forming a protection layer on the first gate material layer in one embodiment.

[0040] Figure 6 This is a schematic diagram of the protective layer after the first oblique etching in one embodiment.

[0041] Figure 7 This is a schematic diagram of the protective layer after the second oblique etching in one embodiment.

[0042] Figure 8 FIG. 4 is a schematic diagram of forming a shielding gate in an embodiment.

[0043] Fig. 9 FIG. 4 is a schematic diagram of forming a first dielectric layer in an embodiment.

[0044] Fig.10 FIG. 4 is a schematic diagram of a first dielectric layer after planarization in an embodiment.

[0045] Fig.11 It is a schematic diagram of removing the shielding gate dielectric layer and the first dielectric layer on the shielding gate trench in one embodiment.

[0046] Fig.12 FIG. 1 is a schematic diagram of an embodiment after the pad nitride layer and the pad oxide layer are removed.

[0047] Fig.13 FIG. 4 is a schematic diagram of forming an oxide layer in one embodiment.

[0048] Fig.14 FIG. 4 is a schematic diagram of forming a second gate material layer in an embodiment.

[0049] Fig.15 FIG. 1 is a schematic diagram of forming a control gate and a doped region in an embodiment.

[0050] Fig.16 FIG. 4 is a schematic diagram of forming a conductive plug in an embodiment.

[0051] Fig.17 FIG. 4 is a schematic diagram of forming electrodes in one embodiment.

[0052] Description of labels:

[0053] 10. substrate; 101. base; 102. epitaxial layer; 11. pad oxide layer; 12. pad nitride layer; 13. patterned photoresist layer; 131. first opening; 132. second opening; 141. shielding gate lead groove; 142. shielding gate groove; 15. shielding gate dielectric layer; 16. first gate material layer; 161. lead gate; 162. shielding gate; 17. protective layer; 18. first dielectric layer; 19. oxide layer; 20. second gate material layer; 21. control gate; 22. doped region; 23. interlayer dielectric layer; 241. first conductive plug; 242. second conductive plug; 243. third conductive plug; 251. first electrode; 252. second electrode; 253. third electrode. DETAILED DESCRIPTION

[0054] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0055] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0056] In the present invention, it should be noted that, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, if the terms "first" and "second" appear, they are only used for description and distinction purposes, and cannot be understood as indicating or implying relative importance.

[0057] See also Figure 1 As shown, in one embodiment of the present invention, the substrate 10 provided by the present invention is any applicable semiconductor material, such as a substrate such as sapphire, silicon wafer, silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN) or silicon germanium (GeSi), and also includes a stacked structure composed of these semiconductors, or silicon on insulator, stacked silicon on insulator, stacked silicon germanium on insulator, silicon germanium on insulator, and germanium on insulator, etc., which can be selected according to the manufacturing requirements of the semiconductor device. In this embodiment, the substrate 10, for example, includes a base 101 and an epitaxial layer 102, the epitaxial layer 102 is arranged on the base 101, and the epitaxial layer 102 is, for example, homoepitaxial or heteroepitaxial of the base 101. Among them, the substrate 101 is, for example, a sapphire substrate or a silicon wafer, the epitaxial layer 102 is, for example, a silicon epitaxial layer, and the epitaxial layer 102 is, for example, N-type epitaxial or P-type epitaxial. The present application does not limit the thickness of the substrate 101 and the epitaxial layer 102, as long as the manufacturing requirements of the semiconductor device are met.

[0058] See also Figure 1As shown, in one embodiment of the present invention, a pad oxide layer 11 is formed on a substrate 10, and the pad oxide layer 11 is, for example, a material such as dense silicon oxide, and the pad oxide layer 11 is, for example, prepared by a thermal oxidation method or an in-situ steam growth method (ISSG). The thickness of the pad oxide layer 11 is, for example, 10 nm to 40 nm. A pad nitride layer 12 is formed on the pad oxide layer 11, and the pad nitride layer 12 is, for example, silicon nitride or a stack of silicon nitride and silicon oxide. The pad nitride layer 12 applies tensile stress to the substrate 10, and the pad oxide layer 11 as a buffer layer can improve the stress between the substrate 10 and the pad nitride layer 12. In the present invention, the pad nitride layer 12 can be formed, for example, by low pressure chemical vapor deposition (LPCVD). Specifically, for example, the substrate 10 with the pad oxide layer 11 is placed in a furnace tube filled with dichlorosilane and ammonia, and reacts at a pressure of, for example, 0.2T~10T and a temperature of, for example, 600°C~800°C to deposit the pad nitride layer 12, and the thickness of the pad nitride layer 12 can be adjusted by controlling the heating time. In this embodiment, the pad nitride layer 12 is, for example, silicon nitride, and the thickness of the pad nitride layer 12 is, for example, 20nm~120nm. Among them, the pad oxide layer 11 is used to buffer the stress in the pad nitride layer 12 to prevent the stress from causing defects to the substrate 10, and at the same time, it serves as a stop layer when etching and removing the pad nitride layer 12.

[0059] See also Figure 1 to Figure 2As shown, in one embodiment of the present invention, a photoresist layer is formed on the pad nitride layer 12, and after exposure and development processes, a patterned photoresist layer 13 is formed, and the patterned photoresist layer 13 includes at least one first opening 131 and a plurality of second openings 132, and the openings expose a portion of the pad nitride layer 12. Among them, the first opening 131 is located on one side of the plurality of second openings 132, and is used to define the position of the shielding gate lead groove, and the second opening 132 is used to define the position of the shielding gate groove, and the distances between adjacent second openings 132 are equal, and the opening size of the first opening 131 is smaller than the opening size of the second opening 132, and for example, is smaller than half of the opening size of the second opening 132. With the patterned photoresist layer 13 as a mask, for example, dry etching is used to etch in the direction of the substrate 10 to form the shielding gate lead groove 141 and the shielding gate groove 142, and the etching gas includes, for example, chlorine (Cl2), trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6) or hydrogen bromide (HBr), etc., or a mixture of several of them. After the shielding gate lead groove 141 and the shielding gate groove 142 are formed, the patterned photoresist layer 13 is removed by wet cleaning or ashing. In the present embodiment, the opening width of the shielding gate lead groove 141 is, for example, less than half of the opening width of the shielding gate groove 142, and the bottoms of the shielding gate lead groove 141 and the shielding gate groove 142 are, for example, arc-shaped and located in the epitaxial layer 102.

[0060] See also Figures 2 to 3 As shown, in one embodiment of the present invention, after forming the shielding gate lead trench 141 and the shielding gate trench 142, a shielding gate dielectric layer 15 is formed on the sidewalls and bottom of the trench and the pad nitride layer 12. In this embodiment, the shielding gate dielectric layer 15 is, for example, a silicon oxide layer, and the shielding gate dielectric layer 15 is obtained, for example, by chemical vapor deposition or atomic layer deposition (ALD) and the like, and the thickness of the formed shielding gate dielectric layer 15 is not specifically limited, so as to meet the use requirements of the shielding gate. The formation method of the shielding gate dielectric layer 15 is limited, and the obtained shielding gate dielectric layer 15 has good coverage and uniform thickness, thereby improving the performance of the device.

[0061] See also Figure 3 to Figure 4As shown, in one embodiment of the present invention, after forming the shielding gate dielectric layer 15, a first gate material layer 16 is deposited on the shielding gate dielectric layer 15 until the shielding gate lead trench 141 and the shielding gate trench 142 are completely filled. The first gate material layer 16 is, for example, polycrystalline silicon or amorphous silicon, and the first gate material layer 16 is, for example, obtained by methods such as sub-atmospheric pressure chemical vapor deposition (SACVD) or high-density plasma chemical vapor deposition (HDPCVD) to improve the quality of the first gate material layer 16 and avoid the occurrence of voids. The first gate material layer 16 is planarized, for example, by chemical mechanical polishing (Chemical Mechanical Polishing). The first gate material layer 16 is etched back by a planarization process such as CMP (Celer Optical Surface Polishing) to make the surface of the first gate material layer 16 flush with the shielding gate dielectric layer 15 on both sides of the trench, and then the first gate material layer 16 in the trench is etched back to make the surface of the first gate material layer 16 flush with the surface of the epitaxial layer 102. The first gate material layer 16 is etched back by, for example, dry etching or wet etching. By selecting the deposition method of the first gate material layer 16, it can be ensured that no voids are formed in the shielding gate, the quality of the shielding gate is improved, and thus the performance of the shielding gate is ensured.

[0062] See also Figures 4 to 5 As shown, in one embodiment of the present invention, after etching back the first gate material layer 16, a protective layer 17 is deposited on the first gate material layer 16 until the protective layer 17 on the first gate material layer 16 protrudes from the shielding gate dielectric layer 15 on the pad nitride layer 12. The protective layer 17 is, for example, a material having an etching selectivity ratio with silicon oxide, such as silicon nitride, and the protective layer 17 is deposited, for example, by low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD). The protective layer 17 is planarized, for example, by a planarization process such as chemical mechanical polishing, so that the surface of the protective layer 17 is flush with the surface of the shielding gate dielectric layer 15 on both sides of the groove.

[0063] See also Figures 5 to 7 As shown, in one embodiment of the present invention, after forming the protective layer 17, the protective layer 17 is etched twice obliquely from both sides of the substrate, and for example, selective dry etching is used to remove the protective layer 17 on the shielding gate trench 142. Figure 6 to Figure 7As shown, the arrow direction in the figure is the etching direction. Specifically, a substrate with a protective layer 17 is placed in an etching chamber, and the etching gas is introduced from one side of the substrate 10 to perform a first oblique etching on the protective layer 17, and the etching is stopped when the first gate material layer 16 in the shielding gate groove 142 is exposed to half. Then, the direction of the etching gas is changed, and the protective layer 17 is obliquely etched for a second time from the other side of the substrate 10, and the etching is stopped when the first gate material layer 16 in the shielding gate groove 142 is exposed to half. The etching angle is defined as the angle between the etching direction and the normal line of the substrate 10, and the etching angles α of the first oblique etching and the second oblique etching are equal. In this embodiment, the etching gas is, for example, a mixed gas of sulfur hexafluoride and oxygen or a mixed gas of carbon tetrafluoride and oxygen.

[0064] See also Figure 6 to Figure 7 As shown, in one embodiment of the present invention, when performing inclined etching, the etching angle α is, for example, less than the preset angle β, and the preset angle β is calculated by the formula β=arctan(a / b). Wherein, a is the difference between half of the opening width of the shielding gate trench 142 and the thickness of the shielding gate dielectric layer 15 on the side wall of the shielding gate trench 142, and b is the thickness of the protective layer 17 on the substrate 10. Since the opening width of the shielding gate lead groove 141 is smaller than half of the opening width of the shielding gate groove 142, the preset angle β is obtained by calculation according to the opening width of the shielding gate groove 142, the thickness of the shielding gate dielectric layer 15 on the side wall of the shielding gate groove 142 and the thickness of the protective layer 17 on the substrate. During the etching process, the etching angle α is controlled to be smaller than the preset angle β. During a single inclined etching process, when half of the first gate material layer 16 in the shielding gate groove 142 is exposed, the protective layer 17 in the shielding gate lead groove 141 does not expose the first gate material layer 16. When two inclined etchings completely remove the first gate material layer 16 in the shielding gate groove 142, a portion of the protective layer 17 remains on the first gate material layer 16 in the shielding gate lead groove 141. By making the opening width of the shielding gate lead groove 141 smaller than half of the opening width of the shielding gate groove 142 and controlling the oblique etching angle, it is possible to ensure that after the oblique etching, a protective layer 17 is provided on the shielding gate lead groove 141, and in the subsequent process of forming the shielding gate, it is possible to ensure that the first gate material layer 16 in the shielding gate lead groove 141 is not etched. Although the protective layer is deposited and the side etching is performed twice, the deposition and etching process does not require a mask process, and the overall manufacturing cost is still less than the cost of a photolithography process, thereby saving a photolithography process and reducing the production cost.

[0065] See also Figures 7 and 8As shown, in one embodiment of the present invention, after the protective layer 17 is etched obliquely twice, the first gate material layer 16 exposed in the shielding gate groove 142 is etched to remove part of the first gate material layer 16. In which, for example, wet etching or dry etching is used for selective etching, and only the first gate material layer 16 is etched. Since there is a protective layer 17 on the first gate material layer 16 in the shielding gate lead groove 141, after etching, the first gate material layer 16 in the shielding gate groove 142 is lower than the substrate surface, and the first gate material layer 16 in the shielding gate lead groove 141 is flush with the surface of the substrate 10. In this embodiment, the first gate material layer 16 in the shielding gate lead groove 141 is defined as a lead gate 161, and the first gate material layer 16 in the shielding gate groove 142 is defined as a shielding gate 162. By controlling the relationship between the sizes of the groove openings, and then forming a protective layer and etching at an angle, it is possible to protect the first gate material layer in the shield gate lead groove when forming the shield gate, forming a lead gate for subsequent metal connection, and during the preparation process, no photolithography process is required, thereby reducing production costs.

[0066] See also Figures 8 to 9 As shown, in one embodiment of the present invention, after forming the shielding gate 162, a first dielectric layer 18 is formed on the shielding gate 162, the protective layer 17 and the shielding gate dielectric layer 15. The first dielectric layer 18 is, for example, made of the same material as the shielding gate dielectric layer 15, and is, for example, a silicon oxide layer. The first dielectric layer 18 is obtained, for example, by methods such as high-density plasma chemical vapor deposition. When the silicon oxide layer is formed by high-density plasma chemical vapor deposition, the deposition rate on the plane is greater than the deposition rate on the sidewall of the trench, that is, the thickness of the first dielectric layer 18 on the shielding gate 162 and the shielding gate dielectric layer 15 is greater than the thickness of the first dielectric layer 18 on the sidewall of the shielding gate trench 142. In this embodiment, by controlling the deposition time of the first dielectric layer 18, the thickness H of the first dielectric layer 18 on the shielding gate 162 is greater than the total thickness D of the shielding gate dielectric layer 15 and the first dielectric layer 18 on the sidewall of the shielding gate trench 142.

[0067] See also Figures 9 and 10 As shown, in one embodiment of the present invention, after the first dielectric layer 18 is deposited, the first dielectric layer 18 is planarized to remove the shield gate dielectric layer 15 and the first dielectric layer 18 on the pad nitride layer 12. In this embodiment, the planarization process is performed, for example, by chemical mechanical polishing, with the pad nitride layer 12 as a polishing stop layer for planarization.

[0068] See also Figure 10 to Figure 11As shown, in one embodiment of the present invention, after the planarization process, the shielding gate dielectric layer 15 and the first dielectric layer 18 are etched to remove the shielding gate dielectric layer 15 and the first dielectric layer 18 on the sidewalls of the shielding gate trench 142. In this embodiment, for example, wet etching is used, and for example, hydrofluoric acid or buffered oxide etchant (BOE) is selected to etch the shielding gate dielectric layer 15 and the first dielectric layer 18. In the wet etching process, due to the isotropic nature of etching, after removing the shielding gate dielectric layer 15 and the first dielectric layer 18 on the sidewalls of the shielding gate trench 142, a portion of the first dielectric layer 18 remains on the shielding gate 162, and the first dielectric layer 18 is flush with the shielding gate dielectric layer 15 on both sides, and no groove is formed. During the etching process, the first dielectric layer 18 and part of the shielding gate dielectric layer 15 on the lead gate 161 are etched away. Since the top of the shielding gate dielectric layer 15 in the shielding gate lead groove 141 is in contact with the etching solution, the shielding gate dielectric layer 15 is etched in the direction of the substrate 10. Therefore, the thickness of the shielding gate dielectric layer 15 in the shielding gate lead groove 141 is similar to the total thickness of the shielding gate dielectric layer 15 and the first dielectric layer 18 on the side wall of the shielding gate groove 142. In this embodiment, the surface of the remaining shielding gate dielectric layer 15 in the shielding gate lead groove 141 is, for example, higher than the surface of the pad oxide layer 11. In other embodiments, the surface of the remaining shielding gate dielectric layer 15 is lower than or flush with the surface of the pad oxide layer 11, and the present invention does not make specific limitations.

[0069] See also Figure 11 to Figure 12As shown, in one embodiment of the present invention, after the first dielectric layer 18 is partially etched, the pad nitride layer 12 and the pad oxide layer 11 are removed. Etching is performed, for example, by dry etching or wet etching. In this embodiment, wet etching is used, for example. And the pad nitride layer 12 is etched by an acid solution, for example, phosphoric acid with a volume fraction of 85% to 88%, and the pad nitride layer 12 is etched at a temperature of 150°C to 165°C. Since the protective layer 17 is also silicon nitride, phosphoric acid removes the protective layer 17 located in the shielding gate lead groove 141 when etching the pad nitride layer 12. For example, hydrofluoric acid or a buffered oxide etchant is selected to etch the pad oxide layer 11. When etching the pad oxide layer 11, the shielding gate dielectric layer 15 and the first dielectric layer 18 are also partially etched, and the etching speed is equal. After removing the pad oxide layer, the remaining thickness of the first dielectric layer 18 is, for example, 0 to 300 nm, and the surface of the first dielectric layer 18 is flush with the surfaces of the shielding gate dielectric layer 15 on both sides, or when the first dielectric layer 18 is completely removed, the surface of the shielding gate 162 is flush with the surfaces of the shielding gate dielectric layer 15 on both sides, and there are no grooves on both sides of the shielding gate 162. In this embodiment, the remaining thickness of the first dielectric layer 18 is, for example, 5 nm to 20 nm, so as to serve as an inter-gate dielectric layer in subsequent processes. The shielding gate dielectric layer 15 on both sides of the lead gate 161 is, for example, higher than the surface of the substrate 10. In other embodiments, it may also be lower than or flush with the surface of the substrate 10.

[0070] See also Figure 12 to Figure 13 As shown, in one embodiment of the present invention, after removing the pad oxide layer, an oxide layer 19 is formed on the substrate 10 and in the shield gate trench 142 , wherein the oxide layer 19 is, for example, a silicon oxide layer. In the present embodiment, the oxide layer 19 is prepared, for example, by thermal oxidation or in-situ steam growth method (In-Situ Steam), and the thickness of the oxide layer 19 is, for example, 5 nm to 20 nm. The oxide layer 19 on the substrate 10 is, for example, flush with the shielding gate dielectric layer 15 on both sides of the lead gate 161. During the oxidation process, the oxide layer 19 is formed on the substrate 10 or the substrate 10 where the sidewalls of the shielding gate trench 142 are exposed. On the shielding gate 162, the first dielectric layer 18, the shielding gate dielectric layer 15 on both sides of the first dielectric layer 18, and the oxide layer 19 on the sidewalls of the shielding gate trench 142 are defined as an inter-gate dielectric layer. When the first dielectric layer 18 is completely removed during the process of removing the pad oxide layer, the oxide layer 19 is formed, for example, by atomic layer deposition, and the oxide layer 19 on the shielding gate 162 and the sidewalls of the shielding gate trench 142 are defined as an inter-gate dielectric layer.

[0071] See also Figures 13 to 15As shown, in one embodiment of the present invention, after the oxide layer 19 is formed, a second gate material layer 20 is deposited on the shielding gate trench 142 and the oxide layer, and the second gate material layer 20 is, for example, polycrystalline silicon or amorphous silicon. In this embodiment, the second gate material layer 20 is, for example, polycrystalline silicon, and the second gate material layer 20 is obtained, for example, by chemical vapor deposition or the like. The second gate material layer 20 is planarized so that the surface of the second gate material layer 20 is flush with the surface of the oxide layer 19, that is, only the second gate material layer 20 on the shielding gate 162 is retained to form a control gate 21. The second gate material layer 20 is planarized, for example, by chemical mechanical polishing. Since the surface of the inter-gate dielectric layer on the shielding gate 162 is flat, there is no sharp corner at the bottom of the formed control gate 21, which will not cause leakage between the control gate 21 and the shielding gate 162, thereby improving the gate leakage problem and improving the performance of the semiconductor device.

[0072] See also Fig.15 As shown, in one embodiment of the present invention, after forming the control gate 21, a doped region 22 is formed in the epitaxial layer 102 on both sides of the control gate 21 to serve as the source of the semiconductor device. The doped ions in the doped region 22 are formed, for example, by ion implantation, and the type of the implanted ions is the same as the type of ions in the epitaxial layer 102. In this embodiment, when the epitaxial layer 102 is N-type, the doped ions in the doped region 22 are, for example, N-type impurities such as phosphorus or arsenic, and when the epitaxial layer 102 is P-type, the doped ions in the doped region 22 are, for example, P-type impurities such as boron or gallium. Before forming the doped region 22, a well region (not shown in the figure) is also formed in the epitaxial layer 102, and the doping depth of the well region is greater than the doping depth of the doped region 22, and the doping type is opposite to that of the doped region 22.

[0073] See also Figure 15 to Figure 16As shown, in one embodiment of the present invention, after forming the doping region 22, an interlayer dielectric layer 23 is formed on the oxide layer 19 and the control gate 21, that is, the interlayer dielectric layer 23 covers the surface of the substrate 10 and the control gate 21. In this embodiment, the interlayer dielectric layer 23 can be formed on the substrate 10 by, for example, high-density plasma chemical vapor deposition, and the thickness of the interlayer dielectric layer 23 can be 300nm~800nm. The material of the interlayer dielectric layer 23 is, for example, silicon dioxide. A plurality of openings (not shown in the figure) are formed in the interlayer dielectric layer 23, the bottom of the opening is located in the substrate or the gate, and a conductive material is deposited in the opening, for example, a metal material is deposited in the opening by a deposition process, such as a titanium / titanium nitride barrier layer and metal tungsten, so as to form a conductive plug. The conductive plugs include a first conductive plug 241 , a second conductive plug 242 and a third conductive plug 243 , wherein the first conductive plug 241 is disposed on the lead gate 161 and connected to the lead gate 161 , the second conductive plug 242 is disposed on the control gate 21 , and the third conductive plug 243 is disposed on both sides of the control gate 21 and connected to the doped region 22 .

[0074] See also Figure 16 to Figure 17 As shown, in one embodiment of the present invention, after forming the conductive plug, a plurality of electrodes are formed on the conductive plug and the interlayer dielectric layer 23, and the material of the electrodes is, for example, metal copper, tungsten or aluminum. The electrodes include a first electrode 251, a second electrode 252 and a third electrode 253, wherein the first electrode 251 is connected to the first conductive plug 241 and covers the first conductive plug 241, so as to serve as a shielding electrode of the semiconductor device. The second electrode 252 is connected to the second conductive plug 242 and covers the second conductive plug 242, so as to serve as a gate electrode of the semiconductor device. The third electrode 253 is connected to the third conductive plug 243 and covers the third conductive plug 243, so as to serve as a source electrode of the semiconductor device. After forming the electrodes, the substrate 10 is turned over and thinned, and a metal layer (not shown in the figure) is deposited on the thinned substrate surface to serve as a drain electrode. By providing a plurality of conductive plugs and connecting them to the metal layer, a plurality of electrodes are formed, which facilitates the connection and operation of the semiconductor device with the subsequent circuits. By forming a shielded gate, the conduction resistance and switching loss of the semiconductor device can be reduced, so that the semiconductor device can obtain a higher breakdown voltage and improve the performance of the semiconductor device. In addition, during the manufacturing process, the leakage of the semiconductor device can be reduced to obtain a high-quality semiconductor device.

[0075] In summary, the present invention provides a semiconductor device and a method for manufacturing the same. By improving the method and structure for manufacturing the semiconductor device, the unexpected technical effect of the present application is that it can save a photolithography process and reduce production costs. During the manufacturing process, it can reduce the defects of the semiconductor device, avoid the formation of sharp corners at the bottom of the control gate, avoid leakage between the control gate and the shielding gate, improve the gate leakage problem, and improve the performance of the semiconductor device. It can ensure that no voids are formed in the shielding gate, improve the quality of the shielding gate, thereby ensuring the performance of the shielding gate, and can reduce the conduction resistance and switching loss of the semiconductor device, so that the semiconductor device can obtain a higher breakdown voltage and improve the performance of the semiconductor device.

[0076] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: At least the following steps are included: Providing a substrate, and sequentially forming a pad oxide layer and a pad nitride layer on the substrate; forming a shielding gate lead groove and a shielding gate groove in the substrate, wherein the opening width of the shielding gate lead groove is less than half of the opening width of the shielding gate groove; Depositing a shielding gate dielectric layer in the substrate, the shielding gate lead trench and the shielding gate trench; Depositing a first gate material layer on the shielding gate dielectric layer, wherein a surface of the first gate material layer is flush with a surface of the substrate; forming a protective layer on the first gate material layer, wherein a surface of the protective layer is flush with a surface of the shielding gate dielectric layer; Performing oblique etching from both sides of the substrate to remove the protection layer in the shield gate trench; Etching and removing a portion of the first gate material layer in the shielding gate trench to form a shielding gate and a lead gate; forming an inter-gate dielectric layer on the shielding gate, wherein the surface of the inter-gate dielectric layer is flat; as well as forming a control gate on the inter-gate dielectric layer; The etching angles α of the oblique etching performed on both sides of the substrate are equal, and one oblique etching exposes half of the first gate material layer in the shield gate trench, and the etching angle α is the angle between the etching direction and the substrate normal; The etching angle α is smaller than a preset angle β, and the preset angle β is obtained by the formula β=arctan(a / b), wherein a is the difference between half of the opening width of the shielding gate groove and the thickness of the shielding gate dielectric layer on the side wall of the shielding gate groove, and b is the thickness of the protective layer on the substrate.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the protective layer and the shielding gate dielectric layer have an etching selectivity ratio, and the protective layer is removed by selective dry etching. After removing the protective layer in the shielding gate groove, a portion of the protective layer remains on the first gate material layer in the shielding gate lead groove.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The production method further comprises: After forming the shielding gate, forming a first dielectric layer on the shielding gate and the shielding gate dielectric layer, wherein the thickness of the first dielectric layer on the shielding gate is greater than the total thickness of the shielding gate dielectric layer and the first dielectric layer on the sidewall of the shielding gate trench; planarizing and removing the shield gate dielectric layer and the first dielectric layer on the pad nitride layer; and The shielding gate dielectric layer and the first dielectric layer on the sidewalls of the shielding gate trench are removed, and a portion of the first dielectric remains on the shielding gate, and the first dielectric layer is flush with the shielding gate dielectric layer on both sides.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The manufacturing method further includes: after removing the shield gate dielectric layer and the first dielectric layer on the sidewall of the shield gate trench, removing the pad nitride layer and the pad oxide layer, after removing the pad oxide layer, the remaining thickness of the first dielectric is 0-300nm.

5. The method for manufacturing a semiconductor device according to claim 4, characterized in that: An oxide layer is formed on the substrate and in the shielding gate trench.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that: The oxide layer is formed on the sidewall of the shielding gate trench, and the oxide layer, the first dielectric and the shielding gate dielectric layer on both sides of the first dielectric are the inter-gate dielectric layer.

7. The method for manufacturing a semiconductor device according to claim 5, characterized in that: The oxide layer is formed on the sidewall and the bottom of the shielding gate trench, and the oxide layer is the inter-gate dielectric layer.

8. A semiconductor device, obtained by the manufacturing method according to any one of claims 1 to 7, characterized in that: At least: substrate; A shielding gate lead groove and a shielding gate groove are arranged in the substrate, and the opening width of the shielding gate lead groove is less than half of the opening width of the shielding gate groove; A lead grid is arranged in the shield grid lead groove; A shielding gate is arranged at the bottom of the shielding gate trench; A shielding gate dielectric layer is disposed between the lead gate and the substrate and between the shielding gate and the substrate; as well as A control gate is arranged on the shielding gate, an inter-gate dielectric layer is arranged between the control gate and the shielding gate, and the surface of the inter-gate dielectric layer is flat.

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