LDMOS device and method for manufacturing the same

Abstract

The present application discloses an LDMOS device and a preparation method thereof, the LDMOS device comprising: a semiconductor layer; a body region and a drift region located in the semiconductor layer; a source region located in the body region; a first isolation structure and a drain region located in the drift region, the drain region and the source region are arranged along a target direction, and the first isolation structure is on a side of the drain region close to the source region; a gate structure located between the source region and the drain region on the surface of the semiconductor layer; a field plate structure located on the surface of the first isolation structure, the field plate structure comprising a field plate dielectric layer covering the surface of the first isolation structure and a field plate electrode layer located on the surface of the field plate dielectric layer, the field plate electrode layer being connected to the gate structure; wherein the field plate electrode layer is at a central position on the surface of the first isolation structure along the target direction, and the length of the field plate electrode layer in the target direction is 1 / 2-3 / 4 of the length of the surface of the first isolation structure. The present application can achieve high withstand voltage of the device without significantly increasing the on-resistance and process cost of the device.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to an LDMOS device and a method for preparing the same. Background Art

[0002] The BCD (Bipolar-CMOS-DMOS) process combines bipolar junction transistor (Bipolar Junction Transistor), CMOS (Complementary Metal Oxide Semiconductor), and DMOS (Double-Diffused Metal-Oxide-Semiconductor) devices on the same chip. The DMOS device is the core device of the entire chip, with a high drain breakdown voltage (BV). The commonly used voltage range is 12V to 90V, or even ultra-high voltage 500V to 700V.

[0003] DMOS devices mainly include VDMOS (Vertical Double-Diffused MOS) and LDMOS (Lateral Double-diffused MOS). BCD process generally uses LDMOS devices. LDMOS devices usually improve horizontal withstand voltage by improving the drain design. One of the existing solutions is to set a reduced surface field oxide (ROX) layer on the surface of the semiconductor layer under the gate structure and increase the length and thickness of the reduced surface field oxide layer to improve the horizontal withstand voltage of the device. Another architecture is to set a shallow trench isolation (STI) structure at the drain end and increase the length and depth of the shallow trench isolation structure to improve the horizontal withstand voltage of the device.

[0004] As the operating voltage of LDMOS devices increases, the existing solution of increasing the length and depth of the shallow trench isolation structure to improve the horizontal withstand voltage of the device will increase the device size and the device on-resistance (Rsp); increasing the length and thickness of the oxide layer that reduces the surface electric field to improve the horizontal withstand voltage of the device will increase the difficulty of the device process and the device process cost. How to achieve high withstand voltage without significantly increasing the on-resistance of the device and controlling the device process cost has become a technical problem that needs to be solved urgently. Summary of the invention

[0005] In view of the above problems, the present application aims to provide an LDMOS device and a method for preparing the same, which can achieve high withstand voltage of the device without significantly increasing the on-resistance of the device and the process cost by reasonably setting the surface field plate structure of the drift region.

[0006] According to a first aspect of the present invention, there is provided an LDMOS device, comprising:

[0007] a semiconductor layer of a first doping type;

[0008] a body region and a drift region in the semiconductor layer, the body region having a first doping type, and the drift region having a second doping type opposite to the first doping type;

[0009] a source region of a second doping type located in the body region;

[0010] A first isolation structure and a drain region of a second doping type located in the drift region, the drain region and the source region are arranged along a target direction, and the first isolation structure is located on a side of the drain region close to the source region;

[0011] A gate structure located between the source region and the drain region on the surface of the semiconductor layer;

[0012] a field plate structure located on the surface of the first isolation structure, the field plate structure comprising a field plate dielectric layer covering the surface of the first isolation structure and a field plate electrode layer located on the surface of the field plate dielectric layer, the field plate electrode layer being connected to the gate structure;

[0013] The field plate electrode layer is located at the center of the surface of the first isolation structure along the target direction, and the length of the field plate electrode layer in the target direction is 1 / 2-3 / 4 of the length of the surface of the first isolation structure.

[0014] Optionally, a plurality of the first isolation structures are provided in the drift region, and the plurality of the first isolation structures are arranged in a mutually separated manner along the target direction;

[0015] The field plate electrode layers on the surfaces of two adjacent isolation structures are connected to each other, and the field plate electrode layer on the surface of the first isolation structure having the largest distance from the drain region among the plurality of first isolation structures is connected to the gate structure.

[0016] Optionally, the lengths of the plurality of first isolation structures in the target direction are different, and the length of the first isolation structure in the target direction is negatively correlated with the distance between the first isolation structure and the drain region.

[0017] Optionally, the depths of the first isolation structures are all 0.25 um.

[0018] Optionally, the depth of the first isolation structure is positively correlated with its length in the target direction.

[0019] Optionally, the LDMOS device further includes: a surface dielectric layer located on the surface of the drift region, the surface dielectric layer is at least partially covered by the gate structure, and the surface dielectric layer is disposed separately from the field plate dielectric layer.

[0020] Optionally, the LDMOS device further includes: a doped region of the first doping type located between two adjacent first isolation structures in the drift region, and a doped region of the first doping type located between the surface dielectric layer and the field plate dielectric layer closest to the surface dielectric layer in the drift region.

[0021] Optionally, the field plate dielectric layer and the surface dielectric layer are made of oxide, and the field plate electrode layer is made of polysilicon;

[0022] Alternatively, the field plate dielectric layer and the surface dielectric layer are made of dielectric materials with high dielectric constants, and the field plate electrode layer is made of metal.

[0023] Optionally, the semiconductor layer comprises a buried layer of a second doping type, and the body region and the drift region in the semiconductor layer are above the buried layer.

[0024] According to a second aspect of the present invention, there is provided a method for preparing an LDMOS device, comprising:

[0025] forming a body region and a drift region in a semiconductor layer of a first doping type, wherein the body region has a first doping type and the drift region has a second doping type opposite to the first doping type;

[0026] forming a source region of a second doping type in the body region, and forming a first isolation structure and a drain region of a second doping type in the drift region, wherein the drain region and the source region are arranged along a target direction, and the first isolation structure is located on a side of the drain region close to the source region;

[0027] forming a gate structure located between the source region and the drain region on the surface of the semiconductor layer;

[0028] forming a field plate structure on the surface of the first isolation structure, the field plate structure comprising a field plate dielectric layer covering the surface of the first isolation structure and a field plate electrode layer located on the surface of the field plate dielectric layer, the field plate electrode layer being connected to the gate structure;

[0029] The field plate electrode layer is located at the center of the surface of the first isolation structure along the target direction, and the length of the field plate electrode layer in the target direction is 1 / 2-3 / 4 of the length of the surface of the first isolation structure, and the target direction is the arrangement direction of the source region and the drain region.

[0030] The unexpected technical effects of this application are:

[0031] The LDMOS device provided by the present application includes: a semiconductor layer of a first doping type; a body region and a drift region located in the semiconductor layer, the body region has a first doping type, and the drift region has a second doping type opposite to the first doping type; a source region of the second doping type located in the body region; a first isolation structure and a drain region of the second doping type located in the drift region, the drain region and the source region are arranged along the target direction, and the first isolation structure is on the side of the drain region close to the source region; a gate structure located between the source region and the drain region on the surface of the semiconductor layer; a field plate structure located on the surface of the first isolation structure, the field plate structure includes a field plate dielectric layer covering the surface of the first isolation structure and a field plate electrode layer located on the surface of the field plate dielectric layer, and the field plate electrode layer is connected to the gate structure. Wherein, the field plate electrode layer is located at the center position of the surface of the first isolation structure along the target direction, and the length of the field plate electrode layer in the target direction is 1 / 2-3 / 4 of the length of the surface of the first isolation structure, so that the high impact ionization area below the drain region is effectively reduced by reasonably setting the position and size of the field plate electrode layer, and the high withstand voltage of the device is achieved without significantly increasing the on-resistance and process cost of the device, and basically no process defects are caused.

[0032] Furthermore, a plurality of first isolation structures are provided in the drift region, the plurality of first isolation structures are arranged in a mutually separated manner along the target direction, the field plate electrode layers on the surfaces of two adjacent first isolation structures are connected to each other, and the field plate electrode layer on the surface of the first isolation structure having the largest spacing from the drain region among the plurality of first isolation structures is connected to the gate structure. Since the bottom of the first isolation structure having the field plate structure on the surface can attract charges, the plurality of first isolation structures respectively provided with the field plate structure can fully disperse the charges in the drift region, thereby significantly reducing the electric field strength of the drift region below the drain region, and significantly improving the breakdown voltage of the LDMOS device.

[0033] Furthermore, the lengths of the multiple first isolation structures in the target direction are different, and the length of the first isolation structure in the target direction is negatively correlated with the distance between it and the drain region, so that the bottom of the first isolation structure in the drift region that is closer to the drain region will attract more charges, which is beneficial to the charges in the drift region to be gradually dispersed from the area closer to the drain region to the area farther from the drain region in a gradient manner.

[0034] Furthermore, the depth of the first isolation structure is positively correlated with its length in the target direction, so that the plurality of first isolation structures are arranged according to the etching load effect, and thus the plurality of first isolation structures can be easily manufactured through the same process.

[0035] Furthermore, the LDMOS device provided in the present application also includes: a doped region of the first doping type located between two adjacent first isolation structures in the drift region, and a doped region of the first doping type located between the surface dielectric layer and the field plate dielectric layer closest to the surface dielectric layer in the drift region. The setting of the doped region enables the LDMOS device to adopt a double surface electric field reduction process. In this process, after the semiconductor layer is fully depleted, the ionized acceptor or donor in the doped region (the ionized acceptor is negatively charged when the first doping type is P-type doping, and the ionized donor is positively charged when the first doping type is N-type doping) introduces a reverse electric field into the channel located below the gate structure in the drift region, so that the electric field peak in the channel is reduced, and the device breakdown voltage is increased accordingly. At the same time, the on-resistance is reduced while ensuring that the net doping in the drift region remains unchanged, and the electric field peak on the drain region side of the first isolation structure does not increase under the isolation effect of the first isolation structure on the reverse electric field. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0037] Figure 1 Shown is a cross-sectional view of an existing LDMOS device;

[0038] Figure 2 Shown are a top view and a cross-sectional view of an LDMOS device according to an embodiment of the present application;

[0039] Figure 3 Shown are distribution data of multiple collision generation rates obtained from multiple one-dimensional dimensions of the field plate electrode layer in the target direction according to an embodiment of the present application;

[0040] Figure 4 FIG. 4 is a cross-sectional view of another LDMOS device according to an embodiment of the present application;

[0041] Figure 5 Shown is a flow chart of a method for preparing an LDMOS device according to an embodiment of the present application;

[0042] Figure 6 Shown are device cross-sectional views at some stages during the execution of a method for preparing an LDMOS device according to an embodiment of the present application.

[0043] Explanation of the accompanying drawings: 100-LDMOS device; 101-semiconductor layer; 102-body region; 103-drift region; 104-source region; 105-shallow trench isolation structure; 106-drain region; 107-oxidation layer for reducing surface electric field; 108-gate structure; 200-LDMOS device; 201-semiconductor layer; 202-body region; 203-drift region; 204-source region; 205-first isolation structure; 206-drain region; 207-gate structure; 208-surface dielectric layer; 209-field plate structure; 209a-field plate dielectric layer; 209b-field plate electrode layer; 210-doped region; 211-second isolation structure; 212-buried layer. DETAILED DESCRIPTION

[0044] The present application will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0045] This application may be presented in a variety of forms, some examples of which are described below.

[0046] Figure 1 FIG. 4 shows a cross-sectional view of an existing LDMOS device. Figure 1 As shown, the LDMOS device 100 includes: a semiconductor layer 101, a body region 102 and a drift region 103 located in the semiconductor layer 101, a source region 104 located in the body region 102, a shallow trench isolation structure 105 and a drain region 106 located in the drift region 103, and a reduced surface electric field oxide layer 107 and a gate structure 108 located on the surface of the semiconductor layer 101. At present, the horizontal direction withstand voltage of the LDMOS device 100 can be improved by increasing the length and thickness of the reduced surface electric field oxide layer 107, and the horizontal direction withstand voltage of the LDMOS device 100 can also be improved by increasing the length and depth of the shallow trench isolation structure 105. In the embodiment of the present application, the dimension of a certain structure included in the semiconductor device along the X-axis direction of the coordinate system in the figure is the length, and the dimension along the Y-axis direction of the coordinate system in the figure is the depth or thickness. Unless otherwise specified, the X-axis direction of the coordinate system in the embodiment of the present application is set to be parallel to the arrangement direction of the source region 104 and the drain region 106, and the source region 104 and the drain region 106 are arranged along the target direction; the Y-axis direction of the coordinate system is set to be perpendicular to the surface of the semiconductor layer 101.

[0047] In the above-mentioned solution for improving the horizontal withstand voltage of the LDMOS device 100, increasing the length and depth of the shallow trench isolation structure 105 will increase the overall size of the LDMOS device 100, and the on-resistance of the LDMOS device 100 will also increase accordingly; increasing the length and thickness of the surface electric field reducing oxide layer 107 will increase the difficulty of the device process, and the device process cost will increase accordingly. Therefore, the LDMOS device 100 cannot take into account the withstand voltage, on-resistance and process cost at the same time.

[0048] In view of this, an embodiment of the present application provides an LDMOS device. Figure 2 FIG. (a) is a top view of an LDMOS device provided in an embodiment of the present application; Figure 2 Figure (b) shows Figure 2 A cross-sectional view of the LDMOS device shown in FIG. 1 along line A1A2 is shown in FIG. Figure 2 Figures (a) and (b) show two LDMOS devices with the middle dotted line as the adjacent boundary. The following description refers to the LDMOS device on the right.

[0049] like Figure 2 As shown in (a) and (b) of the figure, the LDMOS device 200 includes: a semiconductor layer 201 of a first doping type; a body region 202 and a drift region 203 located in the semiconductor layer 201, the body region 202 has a first doping type, and the drift region 203 has a second doping type opposite to the first doping type; a source region 204 of the second doping type located in the body region 202; a first isolation structure 205 located in the drift region 203 and a drain region 206 of the second doping type, the drain region 206 and the source region 204 are arranged along the target direction, the first isolation structure 205 is on the side of the drain region 206 close to the source region 204; the gate structure 207 is located between the source region 204 and the drain region 206 on the surface of the semiconductor layer 201; the field plate structure 209 is located on the surface of the first isolation structure 205, the field plate structure 209 includes a field plate dielectric layer 209a covering the surface of the first isolation structure 205 and a field plate electrode layer 209b located on the surface of the field plate dielectric layer 209a, and the field plate electrode layer 209b is connected to the gate structure 207.

[0050] The first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type. Figure 2 In the examples shown in (a) and (b) of FIG. 1 , the first doping type is P-type doping, the second doping type is N-type doping, and the source region 204 and the drain region 206 are heavily N-type doped compared to the semiconductor layer 201 .

[0051] The semiconductor layer 201 may be made of silicon material and may be selected from any one of a semiconductor substrate, an epitaxial layer or a combination thereof. Figure 6As shown in FIG. 5( d ) , the semiconductor layer 201 includes a buried layer 212 of a second doping type, a semiconductor substrate located below the buried layer 212 , and an epitaxial layer located above the buried layer 212 . The body region 202 and the drift region 203 are located in the epitaxial layer above the buried layer 212 .

[0052] The first isolation structure 205 and the field plate structure 209 cooperate to reduce the voltage, so that the breakdown voltage of the LDMOS device 200 is improved. Specifically, during the operation of the LDMOS device, the field plate electrode layer 209b is energized by connecting to the gate structure 207, so that the bottom of the first isolation structure 205 induces and attracts charges, thereby increasing the conductivity of the drift region 203 in the on state, so that the area below the drain region 206 in the drift region 203 reduces the charge accumulation, and the high impact ionization area is reduced accordingly, so that the electric field strength in the area below the drain region 206 in the drift region 203 is reduced, thereby improving the horizontal withstand voltage of the LDMOS device 200, and the breakdown voltage of the LDMOS device 200 is improved.

[0053] Experiments have shown that the position of the field plate electrode layer 209b on the surface of the first isolation structure 205 affects the amount of charges attracted to the bottom of the first isolation structure 205 by affecting the distribution of potential lines, thereby indirectly affecting the horizontal withstand voltage of the LDMOS device 200. When the field plate electrode layer 209b is located at the center position of the surface of the first isolation structure 205 along the target direction, the horizontal withstand voltage of the LDMOS device 200 is the largest.

[0054] In addition, experiments have shown that the proportional relationship between the length of the field plate electrode layer 209b and the surface length of the first isolation structure 205 in the target direction will affect the amount of charges attracted to the bottom of the first isolation structure 205 by affecting the distribution of potential lines, thereby affecting the size of the high impact ionization region, and further affecting the horizontal withstand voltage of the LDMOS device 200.

[0055] Figure 3 The figure shows the distribution data of multiple collision generation rates obtained at multiple lengths of the field plate electrode layer 209b in the target direction. In semiconductor devices, since the kinetic energy of carriers (electrons or holes) is high enough that they can generate additional electron-hole pairs through impact ionization during movement, the impact generation rate (Impact Generation Rate) is used to represent the rate at which additional electron-hole pairs are generated through impact ionization. It is a parameter that characterizes the intensity of impact ionization, and the unit is usually per cubic centimeter per second (cm -3 ·s -1 ), which reflects the number of electron-hole pairs generated per second in one cubic centimeter. Reducing the area with high collision rate can improve device reliability and keep the device at a high withstand voltage.

[0056] Figure 3 In the figure, the field plate electrode layer 209b is located at the center of the surface of the first isolation structure 205 along the target direction. The length of the surface of the first isolation structure 205 in the target direction is 1.6 um, and the depth of the first isolation structure 205 is 0.25 um. Figure 3 In the figure (a), the length of the field plate electrode layer in the target direction is 0.2um, and the length of the region where the collision generation rate is greater than the threshold value, which is framed by the dotted line below the drain electrode, in the target direction is 0.634um; Figure 3 In (b), the length of the field plate electrode layer in the target direction is 0.5um, and the length of the region with a collision generation rate greater than the threshold value outlined by the dotted line frame under the drain electrode in the target direction is 0.535um; Figure 3 In (c), the length of the field plate electrode layer in the target direction is 0.8um, and the length of the region with a collision generation rate greater than the threshold value outlined by the dotted line frame under the drain electrode in the target direction is 0.501um; Figure 3 In Figure (d), the length of the field plate electrode layer in the target direction is 1.2 um, and the length of the area with a collision generation rate greater than the threshold value outlined by the dotted box under the drain electrode in the target direction is 0.493 um.

[0057] Depend on Figure 3 It can be seen that: in the process of increasing the length of the field plate electrode layer 209b from 1 / 2 to 3 / 4 of the surface length of the first isolation structure 205 in the target direction, or in the process of reducing the boundary spacing between the field plate electrode layer 209b and the first isolation structure 205 on the same side from 1 / 4 to 1 / 8 of the surface length of the first isolation structure 205 in the target direction, the length of the high impact ionization region in the drift region 203 below the drain region 206 in the target direction is only reduced by 0.008um, that is, the reduction in the high impact ionization region is no longer obvious. Considering that the continuous increase in the length of the field plate electrode layer 209b will lead to a continuous increase in process difficulty and thus bring about process defects, the length of the field plate electrode layer 209b in the target direction in the embodiment of the present application is set to 1 / 2-3 / 4 of the length of the surface of the first isolation structure 205 in the target direction.

[0058] The embodiment of the present application has reasonably optimized the position and size of the field plate electrode layer 209b based on a large number of experiments. By setting the field plate electrode layer 209b at the center position along the target direction of the surface of the first isolation structure 205 and setting the length of the field plate electrode layer 209b in the target direction to 1 / 2-3 / 4 of the length of the surface of the first isolation structure 205 in the target direction, the high impact ionization area in the drift region 203 in the area below the drain region 206 is reasonably reduced while considering the process difficulty, thereby effectively improving the horizontal withstand voltage of the LDMOS device 200, while not requiring an increase in on-resistance and process cost, and basically no process defects.

[0059] Furthermore, if Figure 2 As shown, a plurality of first isolation structures 205 may be provided in the drift region 203, and the plurality of first isolation structures 205 are arranged in a mutually separated manner along the target direction; the field plate electrode layers 209b on the surfaces of two adjacent isolation structures 205 are connected to each other, and the field plate electrode layer 209b on the surface of the first isolation structure with the largest spacing from the drain region 206 among the plurality of first isolation structures 205 is connected to the gate structure 207, so that when the LDMOS device 200 is working, the field plate electrode layers 209b on the surfaces of each isolation structure 205 can be energized based on the energization of the gate structure 207. The plurality of field plate electrode layers 209b may be as follows Figure 2 As shown in the middle (a), they are connected to form a mesh structure. Since the bottom of the first isolation structure 205 with a field plate structure 209 on the surface can attract charges, the multiple first isolation structures 205 respectively equipped with field plate structures 209 can better optimize the distribution of the electric field in the drift region 203, so that the charges in the drift region 203 are fully dispersed, thereby significantly reducing the electric field strength of the drift region 203 below the drain region 206, and significantly improving the breakdown voltage of the LDMOS device 200.

[0060] Furthermore, the lengths of the plurality of first isolation structures 205 in the target direction are different, and the length of the first isolation structure 205 in the target direction is negatively correlated with the distance between the first isolation structure 205 and the drain region 206, so that the bottom of the first isolation structure 205 in the drift region 203 that is closer to the drain region 206 will attract more charges, thereby facilitating the charges in the drift region 203 to be gradually dispersed in a gradient manner from the area closer to the drain region 206 to the area farther from the drain region 206. In some examples, the depth of each of the plurality of first isolation structures 205 can be as follows: Figure 3 The experiment shown is set to 0.25 um, so that the field plate structure 209 on the surface of the first isolation structure 205 can attract charges at the bottom of the first isolation structure 205 and will not be nearly short-circuited with the drift region 203 due to the small depth of the first isolation structure 205.

[0061] Figure 4FIG. 2 is a cross-sectional view of another LDMOS device provided in an embodiment of the present application. Figure 4 As shown, the depth of the first isolation structure 205 is positively correlated with its length in the target direction. It should be noted that the first isolation structure 205 is usually a shallow trench isolation structure (STI), which is formed by etching a shallow trench and filling the etched shallow trench with an isolation material, and the filled isolation material is, for example, any one of silicon oxide, silicon nitride and silicon oxynitride. Due to the etching loading effect (Loading Effect) during the shallow trench etching process, the etching depth of a trench with a smaller width will be smaller in the same process, while the etching depth of a trench with a larger width will be larger. Therefore, Figure 4 The multiple first isolation structures 205 shown are arranged according to the etching load effect, so that the multiple first isolation structures 205 can be easily manufactured by the same process.

[0062] Reference Figure 2 or Figure 4 In some examples, the LDMOS device 200 may further include a surface dielectric layer 208 located on the surface of the drift region 203, the surface dielectric layer 208 is at least partially covered by the gate structure 207, and the surface dielectric layer 208 is separated from the field plate dielectric layer 209a. Due to the above optimization of the position and size of the field plate electrode layer 209b, it is not necessary to significantly increase the length and thickness of the surface dielectric layer 208 in order to improve the horizontal withstand voltage of the device, so the surface dielectric layer 208 can further reduce the breakdown voltage of the LDMOS device 200 on the basis of the field plate structure 209 while taking into account the process cost.

[0063] Furthermore, the LDMOS device 200 can also be Figure 2 or Figure 4The figure includes: a doping region 210 of the first doping type located between two adjacent first isolation structures 205 in the drift region 203, and a doping region 210 of the first doping type located between the surface dielectric layer 208 and the field plate dielectric layer 209a closest to the surface dielectric layer 208 in the drift region 203. The function of the doping region 210 is to change the distribution of the potential lines in the drift region 203. Specifically, the setting of the doping region 210 enables the LDMOS device 200 to adopt a double reduced surface field (Double Reduced Surface Field, referred to as Double resurf) process, in which the ionized acceptors or donors in the doping region 210 (the ionized acceptors are negatively charged when the first doping type is P-type doping, and the ionized donors are positively charged when the first doping type is N-type doping) after the semiconductor layer 201 is fully depleted introduce a reverse electric field into the channel located below the gate structure 207 in the drift region 203, so that the peak value of the electric field in the channel is reduced, and the device breakdown voltage is increased accordingly. At the same time, the on-resistance is reduced while ensuring that the net doping of the drift region 203 remains unchanged, and the peak value of the electric field on the side of the drain region 206 of the first isolation structure 205 does not increase under the isolation effect of the first isolation structure 205 on the reverse electric field. Figure 2 or Figure 4 In the exemplary LDMOS device 200 shown, the first doping type is P-type doping, and the doping region 210 may be heavily P-type doped compared to the body region 202 . Figure 2 and Figure 4 The source regions 204 of the two LDMOS devices 200 shown respectively are arranged in the same body region 202, and a doped region of the first doping type is spaced between the source regions 204 of the two LDMOS devices 200 in the body region 202. Compared with the body region 202, the doped region spaced between the source regions 204 of the two LDMOS devices 200 is a heavily doped region of the first doping type. Figure 2 and Figure 4 The two LDMOS devices 200 shown are each isolated from other devices by a second isolation structure 211 .

[0064] In some examples, the material used for the field plate dielectric layer 209a and the surface dielectric layer 208 is an oxide, such as silicon dioxide; the material used for the field plate electrode layer 209b is polysilicon. In this example, the gate dielectric layer in the gate structure 207 can also be made of oxide like the field plate dielectric layer 209a and the surface dielectric layer 208, and the gate electrode layer in the gate structure 207 can also be made of polysilicon like the field plate electrode layer 209b. In the case where the field plate dielectric layer 209a and the surface dielectric layer 208 are made of silicon dioxide, silicon dioxide can be deposited by depositing tetraethyl orthosilicate (TEOS for short). Specifically, tetraethyl orthosilicate reacts with ozone to generate silicon dioxide, so depositing tetraethyl orthosilicate can deposit silicon dioxide.

[0065] In other examples, the field plate dielectric layer 209a and the surface dielectric layer 208 are made of a dielectric material with a high dielectric constant, such as hafnium dioxide; the field plate electrode layer 209b is made of a metal. In this example, the gate dielectric layer in the gate structure 207 can be made of a dielectric material with a high dielectric constant like the field plate dielectric layer 209a and the surface dielectric layer 208, and the gate electrode layer in the gate structure 207 can be made of a metal like the field plate electrode layer 209b.

[0066] Corresponding to the LDMOS device provided in the above embodiment, another embodiment of the present application provides a method for preparing the LDMOS device. Figure 5 FIG. 1 is a flow chart of a method for preparing an LDMOS device provided in an embodiment of the present application. Figure 5 As shown, the preparation method comprises:

[0067] Step S110, forming a body region and a drift region in a semiconductor layer of a first doping type, wherein the body region has a first doping type, and the drift region has a second doping type opposite to the first doping type;

[0068] Step S120, forming a source region of the second doping type in the body region, and forming a first isolation structure and a drain region of the second doping type in the drift region, wherein the drain region and the source region are arranged along a target direction, and the first isolation structure is located on a side of the drain region close to the source region;

[0069] Step S130, forming a gate structure located between the source region and the drain region on the surface of the semiconductor layer;

[0070] Step S140 , forming a field plate structure on the surface of the first isolation structure, the field plate structure comprising a field plate dielectric layer covering the surface of the first isolation structure and a field plate electrode layer located on the surface of the field plate dielectric layer, the field plate electrode layer being connected to the gate structure.

[0071] Among them, the field plate electrode layer is at the center position of the surface of the first isolation structure along the target direction, and the length of the field plate electrode layer in the target direction is 1 / 2-3 / 4 of the length of the surface of the first isolation structure. Therefore, by reasonably setting the position and size of the field plate electrode layer, the formed LDMOS device has a higher breakdown voltage, and at the same time, there is no need to increase the on-resistance and process cost, and basically no process defects will be caused.

[0072] Figure 6 The figure shows device cross-sectional views at some stages during the execution of a method for preparing an LDMOS device according to an embodiment of the present application, wherein: Figure 6 FIG. 2 (a) shows that a buried layer 212 is formed in a semiconductor substrate by ion implantation (IMP for short); Figure 6 FIG. (b) shows that an epitaxial layer is formed on the buried layer 212 to obtain a semiconductor layer 201 including a semiconductor substrate, a buried layer 212 and an epitaxial layer. The thickness of the epitaxial layer is 3-10 um. The specific value of the thickness of the epitaxial layer is determined according to the device application voltage. Figure 6 FIG. (c) shows that a body region 202 and a drift region 203 are formed in the epitaxial layer, a first isolation structure 205 and a second isolation structure 211 are formed in the drift region 203, and a surface dielectric layer 208 and a field plate dielectric layer 209a are formed on the surface of the drift region 203; Figure 6 FIG. (d) shows that a source region 204 is formed in the body region 202, a drain region 206 and a doped region 210 are formed in the drift region 203 by ion implantation, a gate structure 207 is formed between the source region 204 and the drain region 206 on the surface of the semiconductor layer 201, and a field plate electrode layer 209b is formed on the surface of the field plate dielectric layer 209a according to the designed size. In the case where the material used for the field plate electrode layer 209b is polysilicon, the field plate electrode layer 209b can be formed using existing polysilicon related processes. It should be noted that the source region 204, the drain region 206 and the gate structure 207 need to be energized through their respective electrodes, and the electrodes are made of metals such as aluminum. Therefore, the existing contact hole (contact) formation process and metal deposition process are used to form the respective electrodes of the source region 204, the drain region 206 and the gate structure 207.

[0073] Finally, it should be noted that the terms "first", "second" and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. According to the embodiments of the present application as described above, these embodiments do not describe all the details in detail, nor do they limit the application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that technicians in the relevant technical field can make good use of the present application and the modified use based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. An LDMOS device, comprising: a semiconductor layer of a first doping type; a body region and a drift region in the semiconductor layer, the body region having a first doping type, and the drift region having a second doping type opposite to the first doping type; a source region of a second doping type located in the body region; A first isolation structure and a drain region of a second doping type located in the drift region, the drain region and the source region are arranged along a target direction, and the first isolation structure is located on a side of the drain region close to the source region; A gate structure located between the source region and the drain region on the surface of the semiconductor layer; a field plate structure located on the surface of the first isolation structure, the field plate structure comprising a field plate dielectric layer covering the surface of the first isolation structure and a field plate electrode layer located on the surface of the field plate dielectric layer, the field plate electrode layer being connected to the gate structure; The field plate electrode layer is located at the center of the surface of the first isolation structure along the target direction, and the length of the field plate electrode layer in the target direction is 1 / 2-3 / 4 of the length of the surface of the first isolation structure.

2. The LDMOS device according to claim 1, wherein: A plurality of the first isolation structures are provided in the drift region, and the plurality of the first isolation structures are arranged in a mutually separated manner along the target direction; The field plate electrode layers on the surfaces of two adjacent isolation structures are connected to each other, and the field plate electrode layer on the surface of the first isolation structure having the largest distance from the drain region among the plurality of first isolation structures is connected to the gate structure.

3. The LDMOS device according to claim 2, wherein: The lengths of the plurality of first isolation structures in the target direction are different, and the length of the first isolation structure in the target direction is negatively correlated to the distance between the first isolation structure and the drain region.

4. The LDMOS device according to claim 3, wherein: The depths of the first isolation structures are all 0.25 um.

5. The LDMOS device according to claim 3, wherein: The depth of the first isolation structure is positively correlated with its length in the target direction.

6. The LDMOS device according to claim 2, further comprising: A surface dielectric layer is located on the surface of the drift region, wherein the surface dielectric layer is at least partially covered by the gate structure, and the surface dielectric layer is disposed separately from the field plate dielectric layer.

7. The LDMOS device according to claim 6, further comprising: A doped region of the first doping type located between two adjacent first isolation structures in the drift region, and a doped region of the first doping type located between the surface dielectric layer and the field plate dielectric layer closest to the surface dielectric layer in the drift region.

8. The LDMOS device according to claim 6, wherein: The field plate dielectric layer and the surface dielectric layer are made of oxide, and the field plate electrode layer is made of polysilicon; Alternatively, the field plate dielectric layer and the surface dielectric layer are made of dielectric materials with high dielectric constants, and the field plate electrode layer is made of metal.

9. The LDMOS device according to claim 1, wherein: The semiconductor layer includes a buried layer of a second doping type, and the body region and the drift region located in the semiconductor layer are above the buried layer.

10. A method for preparing an LDMOS device, comprising: forming a body region and a drift region in a semiconductor layer of a first doping type, wherein the body region has a first doping type and the drift region has a second doping type opposite to the first doping type; forming a source region of a second doping type in the body region, forming a first isolation structure and a drain region of a second doping type in the drift region, wherein the drain region and the source region are arranged along a target direction, and the first isolation structure is located on a side of the drain region close to the source region; forming a gate structure located between the source region and the drain region on the surface of the semiconductor layer; forming a field plate structure on the surface of the first isolation structure, the field plate structure comprising a field plate dielectric layer covering the surface of the first isolation structure and a field plate electrode layer located on the surface of the field plate dielectric layer, the field plate electrode layer being connected to the gate structure; The field plate electrode layer is located at the center of the surface of the first isolation structure along the target direction, and the length of the field plate electrode layer in the target direction is 1 / 2-3 / 4 of the length of the surface of the first isolation structure.

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