A buried-gate asymmetric reconfigurable field-effect high-frequency transistor and a method for manufacturing the same

Abstract

The present invention discloses a buried-gate asymmetric reconfigurable field-effect high-frequency transistor and a preparation method thereof. The transistor of the present invention comprises a substrate, a channel layer, a first gate dielectric layer, a second gate dielectric layer, a control gate, a polarity gate, a protective layer, a source electrode region, and a drain electrode region; a groove is etched on one side above the channel layer, and a first gate dielectric layer is grown above the groove, and a second gate dielectric layer is directly grown on the other end; the control gate is located above the first gate dielectric layer and is surrounded by the channel layer; the polarity gate is located above the second gate dielectric layer. The present invention adopts a buried-gate structure to bury the control gate in the channel layer, reduce the overlap of the control gate and the polarity gate, and reduce the parasitic capacitance of the device. At the same time, the control gate controls the channel layer, and the optimization of the channel structure can increase the channel length, reduce the threshold voltage of the transistor turning on, and also omit the "side wall" and "side wall" parts, simplifying the process.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor manufacturing, and in particular relates to a buried-gate asymmetric reconfigurable field-effect high-frequency transistor and a preparation method thereof. Background Art

[0002] In the field of semiconductor technology, the structure and performance of transistors are key factors in determining the performance of integrated circuits. As an improved MOSFET, buried-gate transistors (Trench MOSFET) have shown significant advantages in improving device performance with their unique trench structure. This structure helps to reduce the effective area between the gate and the source and drain, enhance the electric field control capability, and reduce parasitic capacitance, thereby improving the overall performance of the device.

[0003] The main feature of the buried-gate transistor is that the structure between the gate and the drain is trench-shaped. This design is beneficial to improving the thermal characteristics of the device, reducing parasitic capacitance, and increasing conductivity, especially in high-frequency applications.

[0004] Reconfigurable Field-Effect Transistor (RFET) is a special field-effect transistor with additional programmable or adjustable characteristics. It can switch between two or more steady-state operating states to adapt to different functional or performance requirements. The structure of RFET usually includes: (1) Control gate: used to adjust the shape and electrical characteristics of the RFET channel and affect the current flow. Its function is more flexible than the gate in traditional FET. (2) Polarity gate: used to control the polarity of the RFET channel (N-type or P-type), changing the polarity of the channel to affect the working state and performance of the RFET.

[0005] Although RFET and Trench MOSFET offer many advantages, there are still some challenges and shortcomings in the existing technology, such as (1) RFET is difficult to manufacture: Due to the short development time of RFET structure, the overall process size in the industry is large, the manufacturing difficulty is high, and many products are still in the simulation stage. (2) Poor stability problem: The reconfigurable nature of RFET may lead to stability problems during long-term use, especially the reconstruction of the channel may affect the stability of device performance. (3) The channel turn-on threshold voltage of RFET is high and the channel conductivity is poor. (4) Parasitic capacitance problem: The overlap of the control gate and the polarity gate is prone to parasitic capacitance, which affects the high-frequency characteristics of the transistor and reduces the switching speed and response time. (5) The buried gate transistor has high process requirements: The trench structure requires precise lithography and etching processes, and has high requirements for process accuracy and complexity. (6) Alignment and overlap problems: The buried gate structure requires precise alignment of the source, drain and gate positions, and there is an overlap between the gate and the source and drain, which is prone to breakdown and other problems.

[0006] In summary, although buried-gate transistors and RFETs offer performance improvements in theory, they still face many challenges in practical manufacturing and application. Summary of the invention

[0007] The purpose of the present invention is at least to solve these problems in the prior art and to provide a buried-gate asymmetric reconfigurable field-effect high-frequency transistor and a preparation method thereof, so as to improve the performance and reliability of the device.

[0008] The present invention is implemented as follows. In a first aspect, the present invention provides a buried-gate asymmetric reconfigurable field-effect high-frequency transistor, comprising a substrate, a channel layer, a first gate dielectric layer, a second gate dielectric layer, a control gate, a polarity gate, a protective layer, a source electrode region, and a drain electrode region;

[0009] The channel layer is located above the substrate;

[0010] The source electrode region and the drain electrode region are respectively located at two ends of the channel layer;

[0011] A groove is etched on one side above the channel layer, and a first gate dielectric layer is grown on the groove, and a second gate dielectric layer is directly grown on the other end;

[0012] The control gate is arranged above the first gate dielectric layer and is surrounded by the channel layer;

[0013] The polarity gate is disposed above the second gate dielectric layer.

[0014] Preferably, there is a gap between the control gate and the polarity gate.

[0015] Preferably, the length ratio of the control gate to the polarity gate is 1:1.

[0016] More preferably, the distance between the control gate and the polarity gate, and the length ratio of the control gate to the polarity gate are 1:1:1.

[0017] Preferably, the polarity gate is located at an end of the channel layer close to the drain electrode region, and the control gate is located at an end of the channel layer close to the source electrode region.

[0018] Preferably, the end of the polarity gate close to the drain electrode region is flush with the end of the second gate dielectric layer close to the drain electrode region and the end of the channel layer in contact with the drain electrode region.

[0019] Preferably, the control gate is isolated from the source electrode by a partial channel layer.

[0020] Preferably, the protection layer is located above the control gate, the polarity gate, the source electrode region, the drain electrode region, and the exposed channel layer.

[0021] Preferably, the length of the channel layer is 100-115 nm, the thickness of the first gate dielectric layer and the second gate dielectric layer is 1.5-1.6 nm; the thickness of the polarity gate is 90-110 nm, and the thickness of the control gate is 20-30 nm.

[0022] In a second aspect, the present invention provides a method for preparing the above-mentioned buried-gate asymmetric reconfigurable field-effect high-frequency transistor, the method comprising the following steps:

[0023] Step 1: forming a channel layer on a substrate;

[0024] Step 2: according to the designed size of the transistor device, a groove of a target size is etched at one end above the channel layer; then a first gate dielectric layer is grown in the groove, and a second gate dielectric layer is directly grown at the other end above the channel layer;

[0025] Step 3: forming a metal gate on the first gate dielectric layer and the second gate dielectric layer after etching, and forming a polarity gate control gate by etching;

[0026] Step 4: Form a source electrode region and a drain electrode region at both ends of the channel layer, and generate a protective layer above the device to isolate and protect the device.

[0027] Preferably, the channel layer in step 1 is also P-doped.

[0028] The beneficial effects of the present invention include at least:

[0029] The present invention adopts a buried gate transistor structure, buries the control gate CG in the channel layer, reduces the overlap between the control gate CG and the polarity gate PG, reduces the parasitic capacitance of the device, improves the electric field control capability and high frequency characteristics of the device, speeds up the switching speed, and reduces the energy loss.

[0030] The present invention buries the control gate CG of the device into the silicon channel, and can also enhance the control of CG over the channel layer. The channel structure optimization can increase the channel length, reduce the threshold voltage of transistor turn-on, improve the conductivity and electrical control ability of the device, improve the high-frequency electrical performance of the device, reduce power consumption and enhance circuit stability.

[0031] The present invention adopts a buried gate structure to eliminate the "side wall" and "side wall" parts, simplifies the process, reduces the difficulty of the alignment process of photolithography and etching, shortens the manufacturing cycle, improves product yield and reliability, reduces manufacturing costs, and lays a foundation for large-scale industrial production. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 It is a schematic diagram of the structure of a buried-gate asymmetric reconfigurable field-effect high-frequency transistor provided in an embodiment of the present invention.

[0034] Figure 2 It is a preparation flow chart of a buried-gate asymmetric reconfigurable field-effect high-frequency transistor provided by an embodiment of the present invention.

[0035] Markings in the figure: 1, substrate; 2, channel layer; 3, first gate dielectric layer; 4, second gate dielectric layer; 5, control gate; 6, polarity gate; 7, source electrode region; 8, drain electrode region; 9, insulating protection layer. DETAILED DESCRIPTION

[0036] As can be seen from the background technology, the RFET and Trench MOSFET in the prior art have at least the following problems: great manufacturing difficulty, low stability, limited electrical performance, easy generation of parasitic capacitance, and high process precision requirements.

[0037] In order to solve the technical problem, the present invention provides a new buried gate asymmetric reconfigurable field effect high frequency transistor, which is mainly composed of a substrate 1, a channel layer 2, a first gate dielectric layer 3, a second gate dielectric layer 4, a control gate 5, a polarity gate 6, a protective layer, a source electrode region 7 and a drain electrode region 8. Among them, the channel layer 2 is located above the substrate 1 as a channel for current conduction; the source electrode region 7 and the drain electrode region 8 are respectively arranged at both ends of the channel layer 2, which are used to connect with the external circuit to realize the input and output of current. Precise etching is performed on one side above the channel layer 2 to form a groove. The first gate dielectric layer 3 is grown above this groove, and the second gate dielectric layer 4 is directly grown at the other end above the channel layer 2. The control gate 5 is located above the first gate dielectric layer 3 and is completely surrounded by the channel layer 2. This buried structural design enables the control gate 5 to more effectively control the electric field distribution in the channel and enhance the control ability of the channel layer.

[0038] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] refer to Figure 1, showing a schematic structural diagram of an embodiment of a buried-gate asymmetric reconfigurable field-effect high-frequency transistor of the present invention, which specifically includes a substrate 1, a channel layer 2, a first gate dielectric layer 3, a second gate dielectric layer 4, a control gate 5CG, a polarity gate 6PG, a protective layer, a source electrode region 7, and a drain electrode region 8;

[0040] The channel layer 2 is located above the substrate 1; a groove is etched on one side above the channel layer 2, and a first gate dielectric layer 3 is grown above the groove, and a second gate dielectric layer 4 is directly grown on the other end; this asymmetric structural design lays the foundation for the subsequent gate layout and function realization.

[0041] In the semiconductor device structure, a channel layer 2 is arranged on the substrate 1, and the channel layer 2 is made of a specific crystal material (such as silicon) to provide a basic channel for subsequent current conduction. On one side above the channel layer 2, a groove with a specific size (depth, width, etc. need to be precisely controlled according to design requirements) is formed by a precise etching process (such as reactive ion etching, RIE). On this groove, the first gate dielectric layer 3 is grown by atomic layer deposition (ALD) technology. The dielectric layer material can be selected from oxides with high dielectric constants (such as HfO2, etc.) to ensure good insulation and capacitance characteristics. On the other side above the channel layer 2, a similar dielectric growth process is directly used to form a second gate dielectric layer 4, which together with the first gate dielectric layer 3 on the groove side constitutes the basis of the gate structure. The control gate 5 is located above the first gate dielectric layer 3 and is formed by a metal deposition (such as physical vapor deposition, PVD) process. It is completely surrounded by the channel layer 2. This buried structure enables the control gate 5 to effectively adjust the electric field distribution in the channel and enhance the control ability of the channel layer. The polarity gate 6 is arranged above the second gate dielectric layer 4, and its position is close to the end of the drain electrode area 8. The end of the polarity gate 6 close to the drain electrode area 8 is precisely flush with the end of the second gate dielectric layer 4 close to the drain electrode area 8 and the contact end of the channel layer 2 with the drain electrode area 8. This layout helps to minimize the parasitic capacitance coupling effect with the control gate 5 while realizing the polarity control function.

[0042] The control gate 5CG is arranged above the first gate dielectric layer 3 and surrounded by the channel layer 2; at the same time, there is a certain distance between the control gate 5 and the polarity gate 6, and the length ratio of the two is designed to be 1:1, and the distance between the control gate 5 and the polarity gate 6, and the length ratio of the control gate 5 and the polarity gate 6 are 1:1:1. This precise proportional relationship helps to optimize the electrical performance of the device and reduce the generation of parasitic capacitance.

[0043] The polarity gate 6PG is arranged above the second gate dielectric layer 4, and its position is close to the end of the drain electrode region 8, and the end of the polarity gate 6 close to the drain electrode region 8 is kept flush with the end of the second gate dielectric layer 4 close to the drain electrode region 8 and the end of the channel layer 2 that contacts the drain electrode region 8. This layout method is conducive to reducing mutual interference with the control gate 5 while realizing the polarity control function, and further reducing parasitic capacitance.

[0044] The overall channel length is 100~115nm, the thickness of the first gate dielectric layer 3 and the second gate dielectric layer 4 is 1.5~1.6nm; the polarity gate 6 is above the channel layer, and its process is relatively simple, and the thickness can be grown to 90~110nm; the control gate 5 is buried in the channel, and the process has certain difficulty, and its buried gate thickness is 20~30nm.

[0045] The protective layer covers the control gate 5, the polarity gate 6, the source electrode region 7, the drain electrode region 8 and the exposed channel layer 2, and plays a role of isolation and protection, preventing external factors from affecting the internal structure of the device, and improving the stability and reliability of the device.

[0046] refer to Figure 2 , showing the method of preparing the buried-gate asymmetric reconfigurable field-effect high-frequency transistor according to the present invention, the specific process flow is as follows:

[0047] Step 1: A layer of Si with a thickness of 50 nm to 80 nm is formed on the substrate 1 as the channel layer 2 of the device; the channel layer 2 may be doped with a small amount of P or may not be doped.

[0048] Step 2: according to the designed size of the transistor device, a groove of a target size is etched on one end above the channel layer 2; then a first gate dielectric layer 3 is grown in the groove, and a second gate dielectric layer 4 is directly grown on the other end above the channel layer 2;

[0049] Step 3: forming a metal gate on the first gate dielectric layer 3 and the second gate dielectric layer 4 after etching, and forming a polarity gate 6 to control the gate 5 by etching;

[0050] Step 4: Form a source electrode region 7 and a drain electrode region 8 on both sides of the channel layer 2, and generate a protection layer above the device to isolate and protect the device.

[0051] Specifically, step 1 is to select a suitable substrate 1 material (such as silicon wafer) and use chemical vapor deposition (CVD) technology to grow a channel layer 2 with a thickness of 50nm-80nm on the surface of the substrate 1. The growth process requires precise control of process parameters such as reaction temperature (for example, in the range of 600℃-800℃), gas flow (such as the ratio of silicon source gas to carrier gas, etc.) and reaction pressure to ensure the crystal quality and thickness uniformity of the channel layer 2. According to the specific device design requirements, a small amount of P doping can be selectively performed on the channel layer 2 (the doping concentration is generally controlled at range), phosphorus atoms are introduced into the channel layer 2 through an ion implantation process to adjust its electrical properties and increase the carrier concentration and mobility; if no additional doping is required, the channel layer 2 maintains its intrinsic properties.

[0052] Specifically, step 2 is to define the groove pattern at one end above the channel layer 2 based on the pre-designed size specifications of the transistor device (accurate layout and parameter setting through electronic design automation, EDA tools), and then use reactive ion etching (RIE) to transfer the pattern to the channel layer 2 to etch a groove of the target size (the depth is usually between 10nm-30nm, and the width is determined according to the design). The etching process requires strict control of parameters such as etching gas composition (such as fluorine-based gas, etc.), etching power (generally in the range of 100W-500W), and etching time to ensure that the dimensional accuracy of the groove (tolerance is controlled within ±1nm) meets the design requirements, while avoiding unnecessary damage to other areas of the channel layer 2.

[0053] In the groove after etching, the first gate dielectric layer 3 is grown by atomic layer deposition (ALD) process. The ALD process can achieve atomic-level thickness control, which has important advantages for forming high-quality and uniform dielectric layers. Taking the growth of aluminum oxide dielectric layer as an example, by precisely controlling the pulse time, purge time and reaction temperature (usually between 200°C-400°C) of precursors (such as trimethylaluminum, TMA and water), a first gate dielectric layer 3 with precise thickness (thickness error less than 0.1nm) and excellent quality can be grown, and its thickness is generally between 1nm-5nm. At the same time, at the other end above the channel layer 2, a similar ALD process is used to directly grow the second gate dielectric layer 4 to ensure the quality and thickness consistency of the two gate dielectric layers, providing a stable and reliable insulation foundation for the subsequent formation of the gate.

[0054] Specifically, step three is to deposit the metal gate material by physical vapor deposition (PVD) or chemical vapor deposition (CVD) on the structure where the growth of the first gate dielectric layer 3 and the second gate dielectric layer 4 has been completed. For the PVD process, sputtering deposition technology can be used. With a high-purity metal target (such as a polysilicon target or a metal silicide target) as the source, metal atoms are sputtered and deposited on the surface of the dielectric layer in an argon or other inert gas plasma environment to form a uniform metal film with a thickness generally between 50nm and 200nm. For the CVD process, the metal gate material is grown on the dielectric layer by chemically reacting the gaseous precursor at high temperature (such as 400°C-600°C).

[0055] Subsequently, the metal gate material is precisely etched into the desired polarity gate 6 and control gate 5 shapes using photolithography and etching processes. The photolithography process first spins photoresist on the surface of the metal gate material, transfers the pre-designed gate pattern to the photoresist by electron beam exposure or ultraviolet light exposure (selected according to the type of photoresist), and then performs a development process to remove the unexposed or exposed part of the photoresist to form a photoresist mask. The etching process selectively removes the metal gate material according to the pattern of the photoresist mask to form the polarity gate 6 and control gate 5. The etching process requires precise control of parameters such as the type of etching gas (such as chlorine, bromine, etc.), etching rate (controlled by adjusting parameters such as power and gas flow, generally in the range of 10nm / min-100nm / min), etching direction (isotropic or anisotropic etching, selected according to design requirements) and etching selectivity (ensuring that the etching rate of the metal gate material is much greater than the etching rate of the dielectric layer, and the selectivity is generally greater than 10:1) to ensure the dimensional accuracy (dimensional tolerance is controlled within ±5nm), shape integrity and position accuracy of the polarity gate 6 and the control gate 5, avoid problems such as short circuit, open circuit or dimensional deviation, thereby ensuring the electrical performance and reliability of the gate.

[0056] Specifically, step 4 is to form source electrode region 7 and drain electrode region 8 on both sides of channel layer 2 by ion implantation process. According to the conductivity type requirement of the device (N-type or P-type), select appropriate ion species (such as phosphorus ions for N-type doping and boron ions for P-type doping), and precisely control the ion implantation energy (generally in the range of 10keV - 100keV) and dose (in the range of 10keV - 100keV). The ions are implanted into a specific area of ​​the channel layer 2, and a layer of Ni is grown on the doped area. The first annealing temperature is about 300°C, and the annealing time is 10-300s to generate NiSi silicide. After washing away the excess Ni, another annealing is performed at about 400°C for 100-300s to achieve phase change and form the target structure, that is, the source and drain regions with the required doping concentration and distribution.

[0057] Finally, plasma enhanced chemical vapor deposition (PECVD) technology is used to generate a protective layer on the entire device surface. The PECVD process is carried out at low temperatures (generally 200℃-400℃), and can quickly grow high-quality insulating films without affecting the performance of other parts of the device. Silicon dioxide (SiO2) or silicon nitride (Si3N4) is selected as the protective layer material, and a protective layer with a thickness of 100nm-500nm is grown by precisely controlling parameters such as the reaction gas flow rate (such as the ratio of gases such as silane, ammonia, and oxygen), RF power (100W-500W range) and reaction pressure. This protective layer can effectively prevent external impurities (such as dust, metal ions, etc.), moisture, and mechanical stress from eroding and damaging the internal structure of the device, improving the long-term stability and reliability of the device, and ensuring the normal operation of the transistor in various complex environments.

[0058] Therefore, the present invention buries the control gate 5 in the channel layer 2 through a buried gate structure design, effectively reducing the overlap area between the control gate 5 and the polarity gate 6. According to the capacitance calculation formula (C = εA / d, where C is capacitance, ε is dielectric constant, A is plate area, and d is plate spacing), the reduction in the overlap area means a reduction in the effective plate area A, thereby significantly reducing the parasitic capacitance C. Lower parasitic capacitance shows outstanding advantages in high-frequency application scenarios. For example, in radio frequency communication circuits, the reduction of parasitic capacitance can greatly increase the switching speed of transistors (theoretically it can be increased by 20%-50%, the specific value depends on the circuit design and operating frequency). The faster switching speed enables the transistor to respond to changes in high-frequency signals more quickly, reduce signal distortion, improve the accuracy and efficiency of signal transmission, and thus improve the high-frequency performance of the entire circuit. At the same time, smaller parasitic capacitance also reduces energy loss during signal transmission and improves the power efficiency of the circuit.

[0059] The unique design of the control gate 5 buried in the silicon channel makes it closer to the channel layer 2. According to the electric field strength formula (E = V / d, where E is the electric field strength, V is the voltage, and d is the distance), at the same voltage, the reduction in distance d leads to an increase in the electric field strength E, thereby enhancing the control ability of the channel layer. In addition, the groove-shaped conductive channel effectively extends the channel length. According to the threshold voltage formula in semiconductor physics, the increase in channel length helps to reduce the threshold voltage for transistor turn-on. In practical applications, the reduction in threshold voltage means that the transistor can be turned on at a lower driving voltage, which not only reduces the power consumption of the circuit, but also improves the device's tolerance to power supply voltage fluctuations and enhances the stability of the circuit.

[0060] As mentioned above, the enhanced electric field control capability and the extended channel length work together to increase the mobility and concentration of carriers in the channel. In applications that require high current drive, such as power amplifiers, this increase in conductivity can provide a larger output current, increase the power gain (theoretically 50% - 100%), and ensure efficient operation of the circuit.

[0061] In addition, the buried gate structure of the present invention cleverly removes the "sidewall" and "sidewall" parts in the common RFET structure. In the traditional semiconductor manufacturing process, the formation of the "sidewall" and "sidewall" requires additional lithography, etching and deposition process steps, and the alignment accuracy of these processes is extremely high (the alignment error needs to be controlled within ±5nm). After omitting these parts, the present invention not only reduces the process steps (can reduce 2-3 key process steps), reduces the process complexity, but also reduces the risk of device performance degradation or failure caused by alignment errors. At the same time, reducing the process steps means shortening the manufacturing cycle, improving production efficiency, and reducing manufacturing costs, thereby improving the yield and reliability of the product, which is conducive to large-scale industrial production.

[0062] In summary, the buried-gate asymmetric reconfigurable field-effect high-frequency transistor and its preparation method of the present invention effectively solve many problems existing in the prior art, have significant advantages in improving device performance, simplifying processes, reducing costs and improving reliability, and provide a valuable solution for the development of semiconductor technology, and are expected to be widely used in future integrated circuit design and manufacturing.

[0063] The above is a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A buried-gate asymmetric reconfigurable field-effect high-frequency transistor, comprising a substrate (1), a channel layer (2), a first gate dielectric layer (3), a second gate dielectric layer (4), a control gate (5), a polarity gate (6), a protective layer, a source electrode region (7), and a drain electrode region (8); The channel layer (2) is located above the substrate (1); The source electrode region (7) and the drain electrode region (8) are respectively located at two ends of the channel layer (2); Features: A groove is etched on one side above the channel layer (2), and a first gate dielectric layer (3) is grown above the groove; the other side has no groove, and a second gate dielectric layer (4) is formed on the upper surface of the channel layer (2) without the groove; The control gate (5) is arranged above the first gate dielectric layer (3) and is surrounded by the channel layer (2); The polarity gate (6) is arranged above the second gate dielectric layer (4).

2. A buried-gate asymmetric reconfigurable field-effect high-frequency transistor according to claim 1, characterized in that: There is a gap between the control grid (5) and the polarity grid (6).

3. The buried-gate asymmetric reconfigurable field-effect high-frequency transistor according to claim 1, characterized in that: The length ratio of the control gate (5) and the polarity gate (6) is 1:

1.

4. The buried-gate asymmetric reconfigurable field-effect high-frequency transistor according to claim 1, characterized in that: The spacing between the control grid (5) and the polarity grid (6), and the length ratio of the control grid (5) and the polarity grid (6) are 1:1:

1.

5. The buried-gate asymmetric reconfigurable field-effect high-frequency transistor according to claim 1, characterized in that: The polarity gate (6) is located at the end of the channel layer (2) close to the drain electrode region (8), and the control gate (5) is located at the end of the channel layer (2) close to the source electrode region (7).

6. A buried-gate asymmetric reconfigurable field-effect high-frequency transistor according to claim 5, characterized in that: The end of the polarity gate (6) close to the drain electrode region (8) is flush with the end of the second gate dielectric layer (4) close to the drain electrode region (8) and the end of the channel layer (2) in contact with the drain electrode region (8).

7. The buried-gate asymmetric reconfigurable field-effect high-frequency transistor according to claim 5, characterized in that: The control gate (5) and the source electrode region (7) are isolated by a portion of the channel layer (2).

8. The buried-gate asymmetric reconfigurable field-effect high-frequency transistor according to claim 1, characterized in that: The protective layer is located above the control gate (5), the polarity gate (6), the source electrode region (7), the drain electrode region (8), and the exposed channel layer (2).

9. A method for preparing a buried-gate asymmetric reconfigurable field-effect high-frequency transistor according to any one of claims 1 to 8, characterized in that: The method comprises the following steps: Step 1: forming a channel layer (2) on a substrate (1); Step 2: etching a groove of a target size at one end above the channel layer (2) according to the designed size of the transistor device; then growing a first gate dielectric layer (3) in the groove, and directly growing a second gate dielectric layer (4) at the other end above the channel layer (2); Step three: forming a metal gate on the first gate dielectric layer (3) and the second gate dielectric layer (4) after etching, and forming a polarity gate (6) and a control gate (5) by etching; Step 4: forming a source electrode region (7) and a drain electrode region (8) at both ends of the channel layer (2), and generating a protective layer above the device to isolate and protect the device.

10. The method for preparing a buried-gate asymmetric reconfigurable field-effect high-frequency transistor according to claim 9, characterized in that: In step 1, the channel layer (2) is also doped with P.

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