Light emitting drive circuit and display panel

Abstract

The application relates to the field of display panels, and provides a light-emitting driving circuit and a display panel, wherein the light-emitting driving circuit comprises multiple-stage light-emitting driving units and a timing controller, each light-emitting driving unit comprises 10 transistors, 3 capacitors, a signal input end, a signal output end and two timing control ends, and the timing controller comprises a first timing control signal line and a second timing control signal line. The light-emitting driving circuit and the display panel of the application provide a new 10T3C light-emitting driving unit circuit, so that the switching between high and low levels of the output signal is pulled down in a stepless manner, the intermediate voltage is prevented from being affected by the threshold voltage of the transistor or process fluctuation, the falling edge time is reduced, the opening speed of the transistor is accelerated, and the response time of the circuit is reduced; the number of components of the circuit is reduced by reducing the use of the timing control signal line and the transistor, so that the frame width of the display panel is reduced, and the narrow-frame trend of the display panel is adapted.

Description

Technical Field

[0001] This invention relates to the field of display panels, and more specifically, to a light-emitting driving circuit and a display panel. Background Technology

[0002] The display panel includes a pixel array and scanning and light-emitting driving circuits that control the pixel array. The display panel uses a progressive scan display method. The scanning driving circuit generates scanning signals to sequentially activate each row of pixels, while the light-emitting driving circuit provides data signals to each activated pixel to achieve pixel display. The light-emitting driving circuit includes multiple cascaded light-emitting driving units. Each stage of the light-emitting driving unit typically consists of several transistors and capacitors. By inputting a clock signal and a start pulse signal to the light-emitting driving unit, a level signal is output at the output terminal.

[0003] In current LED driving circuits, the process of pulling the output from a high level to a low level requires a "step" approach, meaning a complete transition from high to low level in two steps. This "step" transition results in a longer fall time, or "falling edge (Tf)," which slows down the turn-on speed of the transistor (TFT) and increases the circuit's response time.

[0004] Figure 1 This diagram illustrates a circuit diagram of a prior art light-emitting driving unit. (For example...) Figure 1 As shown, Chinese patent CN105741749A discloses a light-emitting driving circuit. The reason for the "step" in this circuit is that when the potential of the clock signal c1 goes from high to low, the potential of the gate N4 node of transistor M2 is pulled down to the same potential as the power supply VEE by the low-level input signal, and M2 is turned on. However, it is limited by the threshold voltage Vth, and the output voltage Vout-V(N4) = Vth < 0. It is necessary for the potential of c2 to go from high to low, and to pull down the gate N4 of M2 to a value lower than VEE by capacitive coupling, so that Vout can be pulled down to the VEE voltage.

[0005] Figure 2 A circuit diagram of another prior art light-emitting driving unit is shown. (e.g.) Figure 2 As shown, US Patent US9548026B2 discloses a light-emitting driving circuit. The reason for the "step" in this circuit is that when the potential of the clock signal CLK1 goes from high to low, the potential of the gate N1 node of the M10 transistor is pulled down to the same potential as the power supply VGL by the low-level input signal, and M10 is turned on. However, it is limited by the threshold voltage Vth, and the output voltage Vout-V(N1) = Vth < 0. It is necessary for the potential of CLK2 to go from high to low, and to pull down the gate N1 of M10 to a value lower than VGL by capacitive coupling, so that Vout can be pulled down to the VGL voltage.

[0006] This "step" transition requires two sets of clock signals to pull down the output signal level. When the level of one clock signal decreases from high to low, the output signal En steps from high to the middle level; when the level of the next clock signal decreases from high to low, the output signal En steps from the middle level to low. The middle level is affected by the TFT threshold voltage and is significantly influenced by fluctuations in the manufacturing process.

[0007] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0008] In view of this, the present invention provides a light-emitting driving circuit and a display panel. The light-emitting driving circuit and display panel of the present invention, by providing a new 10T3C light-emitting driving unit circuit, enable stepless pull-down switching between high and low levels of the output signal, avoiding the influence of transistor threshold voltage or process fluctuations on the intermediate voltage, reducing fall time, accelerating transistor turn-on speed, and reducing circuit response time. Furthermore, the present invention reduces the number of components in the light-emitting driving circuit by reducing the use of timing control signal lines and transistors, thereby reducing the bezel width of the display panel and adapting to the trend of narrow bezels in display panels.

[0009] One aspect of the present invention provides a light-emitting driving circuit, including a multi-stage light-emitting driving unit, wherein the light-emitting driving unit includes:

[0010] The first transistor has its first terminal connected to a first power supply, its second terminal connected to a third node, and its gate connected to a signal input terminal.

[0011] The second transistor has a first terminal connected to the first node, a second terminal connected to the fourth node, and a gate connected to the third node;

[0012] The third transistor has its first terminal connected to the third node, its second terminal connected to the second power supply, and its gate connected to the first timing control terminal.

[0013] The fourth transistor has its first terminal connected to the fourth node, its second terminal connected to the second timing control terminal, and its gate connected to the second timing control terminal.

[0014] The fifth transistor has its first terminal connected to the first power supply, its second terminal connected to the second node, and its gate connected to the first node;

[0015] The sixth transistor has its first terminal connected to the first power supply, its second terminal connected to the first node, and its gate connected to the second node;

[0016] The seventh transistor has its first terminal connected to the first power supply, its second terminal connected to the signal output terminal, and its gate connected to the first node;

[0017] The eighth transistor has its first terminal connected to the signal output terminal, its second terminal connected to the second power supply, and its gate connected to the fifth node;

[0018] The ninth transistor has its first terminal connected to the second node, its second terminal connected to the fifth node, and its gate connected to the second power supply.

[0019] The tenth transistor has its first terminal connected to the second node, its second terminal connected to the signal input terminal, and its gate connected to the second timing control terminal.

[0020] A first capacitor, wherein the first terminal of the first capacitor is connected to the fifth node, and the second terminal is connected to the signal output terminal;

[0021] The second capacitor has its first terminal connected to the first power source and its second terminal connected to the first node;

[0022] The third capacitor has its first terminal connected to the fourth node and its second terminal connected to the third node.

[0023] In some embodiments, a timing controller is further included, the timing controller including a first timing control signal line and a second timing control signal line.

[0024] In some embodiments, the first timing control signal line is used to output a first timing control signal; the second timing control signal line is used to output a second timing control signal.

[0025] In some embodiments, the first timing control signal and the second timing control signal are square wave signals with the same output frequency and a phase difference of 180°.

[0026] In some embodiments, the light-emitting driving unit is used to perform delay processing on the signal received from the signal input terminal under the control of the first timing control signal and the second timing control signal, and the processed signal is output by the signal output terminal.

[0027] In some embodiments, the previous stage light-emitting driving unit outputs a light-emitting driving signal to the next stage light-emitting driving unit, and the last stage light-emitting driving unit outputs a light-emitting driving signal.

[0028] In some embodiments, in the odd-numbered light-emitting driving units, the first timing control terminal is connected to the first timing control signal line, and the second timing control terminal is connected to the second timing control signal line.

[0029] In some embodiments, in the even-numbered light-emitting driving units, the first timing control terminal is connected to the second timing control signal line, and the second timing control terminal is connected to the first timing control signal line.

[0030] In some embodiments, the first transistor to the tenth transistor are all P-type MOS transistors.

[0031] Another aspect of the present invention provides a display panel, characterized in that it includes the light-emitting driving circuit described in any one of the preceding claims.

[0032] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0033] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0034] Figure 1 A circuit diagram of a prior art light-emitting driving unit is shown;

[0035] Figure 2 A circuit diagram of another light-emitting driving unit in the prior art is shown;

[0036] Figure 3 A schematic diagram of the display panel of the present invention is shown;

[0037] Figure 4 A schematic diagram of the cascaded light-emitting driving circuit of the present invention is shown;

[0038] Figure 5 A circuit diagram of the light-emitting driving unit of the present invention is shown;

[0039] Figure 6 Show Figure 5 The waveform diagram shown is of the light-emitting driving unit in operation.

[0040] Figure label:

[0041] 10 Display Panel

[0042] 11 Display Area

[0043] 20. Timing Controller

[0044] 30 Light-emitting driving circuit

[0045] CKE1 First Timing Control Signal Line

[0046] CKE2 Second Timing Control Signal Line

[0047] c1 First timing control terminal

[0048] c2 Second timing control terminal

[0049] IN signal input terminal

[0050] Eout signal output terminal

[0051] T1 First Transistor

[0052] T2 second transistor

[0053] T3 Third Transistor

[0054] T4 fourth transistor

[0055] T5 fifth transistor

[0056] T6 sixth transistor

[0057] T7 Seventh Transistor

[0058] T8 Eighth Transistor

[0059] T9 Ninth Transistor

[0060] T10, the tenth transistor

[0061] C1 First capacitor

[0062] C2, the second capacitor

[0063] C3 Third capacitor

[0064] VDD First Power Supply

[0065] VEE Second Power Supply

[0066] n1 First node

[0067] n2 Second node

[0068] n3 Third node

[0069] n4 Fourth node

[0070] n5 Fifth Node Detailed Implementation

[0071] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore repeated descriptions of them will be omitted.

[0072] The use of terms such as "first," "second," and similar terms in the specific description does not indicate any order, quantity, or importance, but is merely used to distinguish different components. Furthermore, in the description of this invention, terms such as "upper," "lower," etc., indicate orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings. These are merely for ease of description and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on the invention.

[0073] It should be noted that, unless otherwise specified, the embodiments of the present invention and the features in different embodiments can be combined with each other.

[0074] Through meticulous and in-depth research, the inventors in this case have provided a solution to the problems existing in the prior art. Figure 3 A schematic diagram of the display panel of the present invention is shown; Figure 4 A schematic diagram of the cascaded light-emitting driving circuit of the present invention is shown; Figure 5 A circuit diagram of the light-emitting driving unit of the present invention is shown. (As shown) Figures 3 to 5 As shown, this invention discloses a light-emitting driving circuit 30 and a display panel 10. The light-emitting driving circuit 30 includes a multi-stage light-emitting driving unit and a timing controller 20. Each stage of the light-emitting driving unit specifically includes 10 transistors, 3 capacitors, a signal input terminal, a signal output terminal, and two timing control terminals. The timing controller 20 includes two timing control signal lines. The light-emitting driving circuit and display panel of this invention, by providing a new 10T3C light-emitting driving unit circuit, enable stepless pull-down switching between high and low levels of the output signal, avoiding the influence of transistor threshold voltage or process fluctuations on the intermediate voltage, reducing the fall edge time, accelerating the transistor turn-on speed, and reducing the circuit response time. Furthermore, by reducing the use of timing control signal lines and transistors, this invention reduces the number of components in the light-emitting driving circuit, thereby reducing the bezel width of the display panel and adapting to the trend of narrow bezels in display panels.

[0075] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0076] like Figure 3As shown, the present invention provides a display panel 10, which includes a display area 11 and a non-display area. A light-emitting driving circuit 30, a data driver, and a scan driving circuit are located in the non-display area of ​​the display panel 10. The display area 11 includes an array of light-emitting pixels and pixel circuits. The light-emitting pixels emit light under the combined action of the light-emitting driving circuit 30, the data driver, the scan driving circuit, and the pixel circuits.

[0077] like Figure 3 and 4 As shown, the present invention also provides a light-emitting driving circuit 30, which includes a multi-level light-emitting driving unit and a timing controller 20.

[0078] In some embodiments, such as Figure 5 As shown, the light-emitting driving unit includes 10 transistors, 3 capacitors, a signal input terminal IN, a signal output terminal Eout, a first timing control terminal c1, and a second timing control terminal c2. Each stage of the light-emitting driving unit outputs a light-emitting driving signal, which is input to a row of pixel circuits in the display area 11 of the display panel 10 to drive that row of pixels to emit light. The previous stage of the light-emitting driving unit also outputs its light-emitting driving signal to the signal input terminal IN of the next stage of the light-emitting driving unit as a start signal. Since the last stage of the light-emitting driving unit does not have a next stage, its output light-emitting driving signal is only input to the pixel circuit of that row.

[0079] Specifically, Figure 4 Taking a cascaded array of five LED driving units as an example, the first-stage LED driving unit E1 receives a start pulse signal STE at its input terminal IN1. The first-stage LED driving unit E1 outputs an LED driving signal at its output terminal Eout1, which serves as the input signal for the second-stage LED driving unit E2. Eout1 is connected to the second-stage LED driving unit E2's input terminal IN2. The second-stage LED driving unit E2 outputs an LED driving signal at its output terminal Eout2, which serves as the input signal for the third-stage LED driving unit E3. Eout2 is connected to the third-stage LED driving unit E3's input terminal IN3. The third-stage LED driving unit E3 outputs an LED driving signal at its output terminal Eout3, which serves as the input signal for the fourth-stage LED driving unit E4. Eout3 is connected to the fourth-stage LED driving unit E4's input terminal IN4. The signal output terminal Eout4 of the fourth-stage light-emitting driving unit E4 outputs a light-emitting driving signal as the input signal of the fifth-stage light-emitting driving unit E5. The signal output terminal Eout4 of the fourth-stage light-emitting driving unit E4 is connected to the signal input terminal IN5 of the fifth-stage light-emitting driving unit E5... Subsequent light-emitting driving units repeat this process to form the light-emitting driving circuit 30.

[0080] Figure 6 Show Figure 5 The waveform diagram shown illustrates the operation of the light-emitting driving unit. In some embodiments, such as... Figures 3 to 6 As shown, the timing controller 20 includes a first timing control signal line CKE1 and a second timing control signal line CKE2. The first timing control signal line CKE1 is used to output a first timing control signal. The second timing control signal line CKE2 is used to output a second timing control signal. The first and second timing control signals are square wave signals with the same output frequency and a phase difference of 180°.

[0081] In some embodiments, such as Figure 4 As shown, in the first-stage light-emitting driving unit, the first timing control terminal c1 is connected to the first timing control signal line CKE1 to receive the first timing control signal. The second timing control terminal c2 is connected to the second timing control signal line CKE2 to receive the second timing control signal. In the second-stage light-emitting driving unit, the first timing control terminal c1 is connected to the second timing control signal line CKE2 to receive the second timing control signal. The second timing control terminal c2 is connected to the first timing control signal line CKE1 to receive the first timing control signal. In the third-stage light-emitting driving unit, the first timing control terminal c1 is connected to the first timing control signal line CKE1 to receive the first timing control signal. The second timing control terminal c2 is connected to the second timing control signal line CKE2 to receive the second timing control signal. In the fourth-stage light-emitting driving unit, the first timing control terminal c1 is connected to the second timing control signal line CKE2 to receive the second timing control signal. The second timing control terminal c2 is connected to the first timing control signal line CKE1 and is used to receive the first timing control signal. In the fifth-level light-emitting driving unit, the first timing control terminal c1 is connected to the first timing control signal line CKE1 and is used to receive the first timing control signal. The second timing control terminal c2 is connected to the second timing control signal line CKE2 and is used to receive the second timing control signal... and so on, resulting in: In odd-numbered-level light-emitting driving units, the first timing control terminal c1 is connected to the first timing control signal line CKE1 and is used to receive the first timing control signal, and the second timing control terminal c2 is connected to the second timing control signal line CKE2 and is used to receive the second timing control signal. In even-numbered-level light-emitting driving units, the first timing control terminal c1 is connected to the second timing control signal line CKE2 and is used to receive the second timing control signal, and the second timing control terminal c2 is connected to the first timing control signal line CKE1 and is used to receive the first timing control signal.

[0082] In some embodiments of the present invention, such as Figure 5As shown, each stage of the light-emitting driving unit specifically includes 10 transistors, 3 capacitors, a signal input terminal IN, a signal output terminal Eout, a first timing control terminal c1, and a second timing control terminal c2.

[0083] In this embodiment, specifically, the light-emitting driving unit includes: a first transistor T1 to a tenth transistor T10. The first transistor T1 has its first terminal connected to a first power supply VDD, its second terminal connected to a third node n3, and its gate connected to a signal input terminal IN. The second transistor T2 has its first terminal connected to a first node n1, its second terminal connected to a fourth node n4, and its gate connected to a third node n3. The third transistor T3 has its first terminal connected to a third node n3, its second terminal connected to a second power supply VEE, and its gate connected to a first timing control terminal c1. The fourth transistor T4 has its first terminal connected to a fourth node n4, its second terminal connected to a second timing control terminal c2, and its gate connected to a second timing control terminal c2. The fifth transistor T5 has its first terminal connected to a first power supply VDD, its second terminal connected to a second node n2, and its gate connected to a first node n1. The sixth transistor T6 has its first terminal connected to a first power supply VDD, its second terminal connected to a first node n1, and its gate connected to a second node n2. The seventh transistor T7 has its first terminal connected to the first power supply VDD, its second terminal connected to the signal output terminal Eout, and its gate connected to the first node n1. The eighth transistor T8 has its first terminal connected to the signal output terminal Eout, its second terminal connected to the second power supply VEE, and its gate connected to the fifth node n5. The ninth transistor T9 has its first terminal connected to the second node n2, its second terminal connected to the fifth node n5, and its gate connected to the second power supply VEE. The tenth transistor T10 has its first terminal connected to the second node n2, its second terminal connected to the signal input terminal IN, and its gate connected to the second timing control terminal c2.

[0084] In this embodiment, the light-emitting driving unit further includes a first capacitor C1, a second capacitor C2, and a third capacitor C3. The first terminal of the first capacitor C1 is connected to the fifth node n5, and the second terminal is connected to the signal output terminal Eout. The first terminal of the second capacitor C2 is connected to the first power supply VDD, and the second terminal is connected to the first node n1. The first terminal of the third capacitor C3 is connected to the fourth node n4, and the second terminal is connected to the third node n3.

[0085] In this embodiment, the first transistor T1 to the tenth transistor T10 are all P-type MOS transistors. The control terminal of the PMOS transistor is the gate, and its first terminal is the source and its second terminal is the drain, or vice versa. The PMOS transistor's on-state level is low, and its off-state level is high. In other embodiments, those skilled in the art will readily recognize that the light-emitting driving unit provided by this invention can be easily modified to consist entirely of N-type MOS transistors. Furthermore, the light-emitting driving unit provided by this invention can also be easily modified to use CMOS transistors, etc.

[0086] In some embodiments of the present invention, reference is made to Figures 3 to 6 , Figure 6 The waveforms of each stage of two cycles during the operation of the light-emitting driving unit of the present invention are specifically shown, with the t1 to t6 processes within one cycle marked. During these stages, the output signal of the signal output terminal Eout of the aforementioned light-emitting driving unit completes one process from set to reset. The following is in conjunction with... Figure 6 waveform diagram and Figure 5 The circuit diagram is used to analyze the relationship between the input and output of the light-emitting driving unit in the above six processes:

[0087] In this embodiment, refer to Figure 5 and 6 During process t1, the signal input terminal IN is at a high level, the first timing control signal line CKE1 is at a low level, and the second timing control signal line CKE2 is at a high level. Consequently, the fourth node n4 is written with a high potential, and the third node n3 is written with an intermediate potential. Then, the first node n1 is written with a high potential, and the fifth node n5 is written with a low potential. Only the third node n3 and the fifth node n5 have three states: high potential, intermediate potential, and low potential. The same applies to the following stages, and will not be elaborated further. Finally, the signal output terminal Eout outputs a low potential.

[0088] In this embodiment, refer to Figure 5 and 6 During process t2, the signal input terminal IN is high, the first timing control signal line CKE1 is high, and the second timing control signal line CKE2 is low. Consequently, the fourth node n4 is written to a low potential, and the third node n3 is written to a low potential. Then, the first node n1 is written to a low potential, and the fifth node n5 is written to a high potential. Finally, the signal output terminal Eout outputs a high potential.

[0089] In this embodiment, refer to Figure 5 and 6During process t3, the signal input terminal IN is high, the first timing control signal line CKE1 is low, and the second timing control signal line CKE2 is high. Consequently, the fourth node n4 is written to a low potential, and the third node n3 is written to a low potential. Then, the first node n1 is written to a low potential, and the fifth node n5 is written to a high potential. Finally, the signal output terminal Eout outputs a high potential.

[0090] In this embodiment, refer to Figure 5 and 6 During process t4, the signal input terminal IN is set to a high level, the first timing control signal line CKE1 is set to a high level, and the second timing control signal line CKE2 is set to a low level. Consequently, the fourth node n4 is written to a low level, and the third node n3 is written to a low level. Then, the first node n1 is written to a low level, and the fifth node n5 is written to a high level. Finally, the signal output terminal Eout outputs a high level.

[0091] In this embodiment, refer to Figure 5 and 6 During process t5, the signal input terminal IN is low, the first timing control signal line CKE1 is low, and the second timing control signal line CKE2 is high. Consequently, the fourth node n4 is written to a low potential, and the third node n3 is written to an intermediate potential. Then, the first node n1 is written to a low potential, and the fifth node n5 is written to a high potential. Finally, the signal output terminal Eout outputs a high potential.

[0092] In this embodiment, refer to Figure 5 and 6 During process t6, the signal input terminal IN is low, the first timing control signal line CKE1 is high, and the second timing control signal line CKE2 is low. Consequently, the fourth node n4 is written to a low potential, and the third node n3 is written to a high potential. Then, the first node n1 is written to a high potential, and the fifth node n5 is written to a low potential. Finally, the signal output terminal Eout outputs a low potential.

[0093] In this embodiment, after process t6, the light-emitting driving unit will start displaying the next frame by inputting a high potential at the starting pulse signal STE or the signal input terminal IN, and then re-enter the next round of process t1.

[0094] In this embodiment, the relationship between the input and output of the light-emitting driving unit is as follows: when the start pulse signal STE or the signal input terminal IN inputs a high-level signal at the beginning of a certain process, the signal output terminal Eout outputs a high-level signal at the start of the next process; when the start pulse signal STE or the signal input terminal IN inputs a low-level signal during a certain process, the signal output terminal Eout outputs a low-level signal at the end of this process and the start of the next process. At other times, the signal output terminal Eout and the signal input to the start pulse signal STE or the signal input terminal IN are both low-level signals.

[0095] In this embodiment, the light-emitting driving circuit of the present invention provides a novel 10T3C light-emitting driving unit circuit, enabling the third node n3 and the fifth node n5 to exist in three states: high potential, intermediate potential, and low potential. This allows the step-like pull-down transition between high and low levels to be completed at the third node n3, thereby eliminating the step-like pull-down transition between high and low levels of the output signal at the signal output terminal Eout. This avoids the intermediate voltage being affected by transistor threshold voltage or process fluctuations, reduces fall time, accelerates transistor turn-on speed, and reduces circuit response time. Furthermore, by reducing the use of timing control signal lines and transistors, the present invention reduces the number of components in the light-emitting driving circuit, thereby reducing the bezel width of the display panel and adapting to the trend of narrow bezels in display panels.

[0096] Based on the same inventive concept, embodiments of the present invention also provide a display device, including the display panel 10 described above in the embodiments of the present invention. This display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Implementation of this display device can refer to the embodiments of the display panel 10 described above; repeated technical solutions and effects will not be repeated here.

[0097] In summary, the light-emitting driving circuit and display panel of the present invention, by providing a new 10T3C light-emitting driving unit circuit, enable stepless pull-down switching between high and low levels of the output signal, avoiding the influence of transistor threshold voltage or process fluctuations on the intermediate voltage, reducing fall time, accelerating transistor turn-on speed, and reducing circuit response time. In addition, the present invention reduces the number of components in the light-emitting driving circuit by reducing the use of timing control signal lines and transistors, thereby reducing the bezel width of the display panel and adapting to the trend of narrow bezels in display panels.

[0098] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A light-emitting driving circuit, characterized in that, It includes a multi-level light-emitting driving unit, wherein the light-emitting driving unit includes: The first transistor has its first terminal connected to a first power supply, its second terminal connected to a third node, and its gate connected to a signal input terminal. The second transistor has a first terminal connected to the first node, a second terminal connected to the fourth node, and a gate connected to the third node; The third transistor has its first terminal connected to the third node, its second terminal connected to the second power supply, and its gate connected to the first timing control terminal. The fourth transistor has its first terminal connected to the fourth node, its second terminal connected to the second timing control terminal, and its gate connected to the second timing control terminal. The fifth transistor has its first terminal connected to the first power supply, its second terminal connected to the second node, and its gate connected to the first node; The sixth transistor has its first terminal connected to the first power supply, its second terminal connected to the first node, and its gate connected to the second node; The seventh transistor has its first terminal connected to the first power supply, its second terminal connected to the signal output terminal, and its gate connected to the first node; The eighth transistor has its first terminal connected to the signal output terminal, its second terminal connected to the second power supply, and its gate connected to the fifth node; The ninth transistor has its first terminal connected to the second node, its second terminal connected to the fifth node, and its gate connected to the second power supply. The tenth transistor has its first terminal connected to the second node, its second terminal connected to the signal input terminal, and its gate connected to the second timing control terminal. A first capacitor, with its first terminal connected to the fifth node and its second terminal connected to the signal output terminal; the first capacitor is used to enable a stepless pull-down switching between high and low levels of the output signal at the signal output terminal. The second capacitor has its first terminal connected to the first power source and its second terminal connected to the first node; The third capacitor has its first terminal connected to the fourth node and its second terminal connected to the third node. A timing controller, the timing controller including a first timing control signal line and a second timing control signal line; In the odd-numbered stage light-emitting driving unit, the first timing control terminal is connected to the first timing control signal line, and the second timing control terminal is connected to the second timing control signal line. In the even-numbered stage light-emitting driving unit, the first timing control terminal is connected to the second timing control signal line, and the second timing control terminal is connected to the first timing control signal line. The first transistor to the tenth transistor are all P-type MOS transistors.

2. The light-emitting driving circuit according to claim 1, characterized in that, The first timing control signal line is used to output a first timing control signal; the second timing control signal line is used to output a second timing control signal.

3. The light-emitting driving circuit according to claim 2, characterized in that, The first timing control signal and the second timing control signal are square wave signals with the same output frequency and a phase difference of 180°.

4. The light-emitting driving circuit according to claim 2, characterized in that, The light-emitting driving unit is used to perform delay processing on the signal received from the signal input terminal under the control of the first timing control signal and the second timing control signal, and the processed signal is output by the signal output terminal.

5. The light-emitting driving circuit according to claim 1, characterized in that, The previous stage light-emitting driving unit outputs a light-emitting driving signal to the next stage light-emitting driving unit, and the last stage light-emitting driving unit outputs a light-emitting driving signal.

6. A display panel, characterized in that, Includes the light-emitting driving circuit according to any one of claims 1 to 5.

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