Memory and method for manufacturing the same, electronic device

Abstract

A memory, a manufacturing method thereof and an electronic device, the memory comprising: a substrate, an inner electrode, an outer electrode and a dielectric layer on the substrate, the dielectric layer being located between the inner electrode and the outer electrode for insulation; the inner electrode comprising oppositely arranged first and second sub-electrodes, the first sub-electrode having first and second surfaces opposite to each other, and the second sub-electrode having third and fourth surfaces opposite to each other; the first and second surfaces of the first sub-electrode being at least partially covered by the outer electrode, and the third and fourth surfaces of the second sub-electrode being at least partially covered by the outer electrode. The inner electrode of the memory according to the embodiments of the present application has a larger area and can store more charges.

Description

Technical Field

[0001] The embodiments of this application relate to, but are not limited to, the design and manufacture of semiconductor devices, and particularly to a memory and its manufacturing method and an electronic device. Background Technology

[0002] Semiconductor memory can be categorized by application into volatile memory (RAM) and non-volatile memory. RAM includes Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM), among others. Non-volatile memory includes Read-Only Memory (ROM) and non-ROM types.

[0003] Taking DRAM as an example, traditional DRAM has multiple repeating "memory cells," each containing a capacitor and a transistor. A capacitor can store one bit of data; after charging and discharging, the amount of charge stored in the capacitor corresponds to binary data "1" and "0," respectively. The transistor acts as a switch to control the charging and discharging of the capacitor.

[0004] To minimize product costs, the goal is to fabricate as many memory cells as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimization schemes to meet current product demands. Summary of the Invention

[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0006] This application provides a memory, a method for manufacturing the same, and an electronic device. The memory has a large internal electrode area, which allows it to store more charge.

[0007] This application provides a memory, which includes: a substrate and an inner electrode, an outer electrode, and a dielectric layer located on the substrate, wherein the dielectric layer is located between the inner electrode and the outer electrode for insulation;

[0008] The inner electrode includes a first sub-electrode and a second sub-electrode disposed opposite to each other. The first sub-electrode has a first surface and a second surface facing away from each other, and the second sub-electrode has a third surface and a fourth surface facing away from each other.

[0009] The first and second surfaces of the first sub-electrode are at least partially covered by the outer electrode, and the third and fourth surfaces of the second sub-electrode are at least partially covered by the outer electrode.

[0010] For example, the first sub-electrode and the second sub-electrode can be connected together to form a first annular body, and the inner and outer peripheral surfaces of the first annular body are at least partially covered by the outer electrode.

[0011] For example, the outer electrode covering the first sub-electrode and the outer electrode covering the second sub-electrode can be an integral structure.

[0012] For example, the outer electrode forms a second ring body within the first ring body of the inner electrode, and the second ring body has a conductive material inside.

[0013] For example, the memory further includes: a plurality of memory cells distributed in different layers, stacked and periodically distributed along a direction perpendicular to the substrate; each layer includes multiple rows of memory cells, the memory cells including transistors;

[0014] For example, the channel region of the transistor may extend along a first direction parallel to the substrate;

[0015] The cross-sectional profile of the internal electrode on a plane perpendicular to the substrate and parallel to the first direction is annular.

[0016] For example, the memory may further include word lines that extend in a direction perpendicular to the substrate and penetrate the memory cells of different layers.

[0017] For example, the memory may further include bit lines extending along a second direction parallel to the substrate.

[0018] For example, transistors in two columns of memory cells located on the same layer and adjacent in the first direction can be connected to the same bit line, the direction of the columns being the same as the second direction.

[0019] For example, the semiconductor layer of the transistor is electrically connected to the internal electrode through a conductive layer, the material of which is the same as the material of the bit line.

[0020] For example, the semiconductor layer includes a bottom, a middle and a top in sequence along a direction away from the substrate, and the dimensions of the top and bottom in a direction parallel to the substrate are greater than the dimensions of the middle in a direction parallel to the substrate.

[0021] For example, the word lines have protrusions at locations near the semiconductor layer of each transistor, the protrusions extending in a direction parallel to the substrate.

[0022] This application also provides a method for manufacturing a memory, the memory comprising: a plurality of memory cells distributed on different layers, stacked and periodically distributed along a direction perpendicular to the substrate, the memory cells comprising transistors and capacitors;

[0023] The manufacturing method includes:

[0024] A stacked structure is obtained by sequentially and alternately depositing a first insulating layer and a first conductive layer on a substrate.

[0025] The stacked structure is patterned and etched. Each patterned first conductive layer includes bit lines and a plurality of conductive portions spaced apart on at least one side of the bit lines. The conductive portions include the first electrode and the second electrode of the transistor.

[0026] Etching removes a portion of the conductive portion away from the bit line, exposing the side of the first insulating layer at a set depth in the patterned stacked structure;

[0027] A first sub-electrode and a second sub-electrode, disposed opposite to each other, are deposited on the exposed side of the first insulating layer in the patterned stacked structure. The first sub-electrode and the second sub-electrode constitute the internal electrode of the capacitor. Both the first sub-electrode and the second sub-electrode have two opposing surfaces.

[0028] A dielectric layer and an outer electrode are sequentially deposited on two opposing surfaces of the first sub-electrode and the second sub-electrode, respectively, and the inner electrode, the outer electrode, and the dielectric layer constitute the capacitor.

[0029] For example, the memory may further include multiple bit lines distributed in different layers and extending along a second direction parallel to the substrate, and the same bit line is connected to two adjacent columns of memory cells located in the same layer. The two adjacent columns of memory cells in different layers connected by the multiple bit lines stacked along a direction perpendicular to the substrate constitute a memory repeating unit.

[0030] Patterning etching of the stacked structure may include:

[0031] The stacked structure is patterned and etched along a direction toward the substrate, such that a first trench extending along a first direction parallel to the substrate and a second trench extending along a second direction are formed in the stacked structure; the first trench spaced each of the first conductive layers as bit lines and a plurality of conductive portions spaced apart on at least one side of the bit lines; the second trench spaced two adjacent memory repeating cells in the first direction; and two spaced first trenches are provided between two adjacent second trenches in the first direction.

[0032] Exemplarily, depositing and forming opposing first and second sub-electrodes on the exposed side of the first insulating layer in the patterned stacked structure may include:

[0033] A second conductive layer is deposited on the exposed side of the first insulating layer and on the inner wall of the first trench in the patterned stacked structure, and the second conductive layers located between two adjacent first insulating layers in the patterned stacked structure are connected together to form a ring.

[0034] The first insulating layer is used to fill each of the first trenches and to fill the gaps between each of the second conductive layers;

[0035] The first insulating layer and the second conductive layer on the inner wall of the first trench are removed by etching in a portion of the first trench near the second trench. The remaining second conductive layer is located in an annular shape between two adjacent first insulating layers. The second conductive layers located on opposite sides of the two adjacent first insulating layers serve as the first sub-electrode and the second sub-electrode, respectively. The first sub-electrode and the second sub-electrode are connected together to form a first annular body.

[0036] Exemplarily, depositing a dielectric layer and an external electrode sequentially on two opposing surfaces of the first sub-electrode and the second sub-electrode may include:

[0037] A dielectric layer and an external electrode are sequentially deposited on the inner and outer circumferential surfaces of the first annular body, such that the inner and outer circumferential surfaces of the first annular body are at least partially covered by the external electrode.

[0038] Exemplarily, the manufacturing method may further include, after patterning the stacked structure and before etching away a portion of the conductive portion away from the bit line, performing the following process:

[0039] A second insulating layer is deposited on the inner wall of the first trench;

[0040] The first trench is filled with the first insulating layer, and the second trench exposes the first insulating layer in the patterned stacked structure.

[0041] Laterally etch the first insulating layer exposed in the patterned stacked structure in the second trench to expose the side of the first conductive layer at a certain depth in the patterned stacked structure.

[0042] The second insulating layer is deposited on the inner wall of the second trench, and the first insulating layer is filled into the second trench;

[0043] The first and second insulating layers in a portion of the first trench near the second trench are etched away, exposing the first conductive layer in the patterned stacked structure.

[0044] Exemplarily, depositing a second insulating layer on the inner wall of the first trench, and filling the first insulating layer within the first trench, exposing the first insulating layer in the patterned stacked structure in the second trench, may include:

[0045] A second insulating layer is deposited on the inner walls of the first trench and the second trench, and the first insulating layer is filled into the first trench and the second trench.

[0046] Etching removes the first insulating layer within the second trench;

[0047] The second insulating layer on the inner wall of the second trench is etched away to expose the first insulating layer in the patterned stacked structure.

[0048] For example, etching away a portion of the first and second insulating layers in the first trench near the second trench, exposing a first conductive layer in a patterned stacked structure, may include:

[0049] The first insulating layer in a portion of the first trench near the second trench is etched away, exposing the second insulating layer on a portion of the inner wall of the first trench, and exposing the second insulating layer in the second trench near the bit line side;

[0050] The second insulating layer exposed on the inner wall of the first trench and the second insulating layer exposed in the second trench are etched away, so that a portion of the sidewall of the first trench exposes the first conductive layer in a patterned stacked structure.

[0051] This application also provides an electronic device, which includes the memory provided in the above embodiments of this application.

[0052] The memory in this embodiment uses a bipolar plate internal electrode structure, which increases the area of ​​the internal electrode, allowing it to store more charge and thus improve the memory's performance.

[0053] The memory manufacturing method of this application embodiment first removes the first conductive layer located in the capacitor region (i.e., the region subsequently used to form a capacitor), exposing the side surface of a patterned first insulating layer at a predetermined depth. Then, a second conductive layer is deposited on the exposed side surface of two adjacent patterned first insulating layers as a first sub-electrode and a second sub-electrode, respectively, to obtain an internal electrode with a bipolar plate structure (i.e., the internal electrode includes the first sub-electrode and the second sub-electrode). The first sub-electrode has a first surface and a second surface facing away from each other, and the second sub-electrode has a third surface and a fourth surface facing away from each other. Furthermore, the first surface, the second surface, the third surface, and the fourth surface can all store charge. Therefore, compared to an internal electrode with a single-plate structure, the internal electrode obtained by the manufacturing method of this application embodiment can have more area to store charge, thereby improving the performance of the memory.

[0054] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and advantages of this application may be realized and obtained by means of the structures particularly pointed out in the description and the accompanying drawings. Attached Figure Description

[0055] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0056] Figure 1A A longitudinal cross-sectional schematic diagram of a memory provided for an exemplary embodiment of this application;

[0057] Figure 1B for Figure 1A A schematic diagram of the longitudinal section of the memory at another angle;

[0058] Figure 2A A cross-sectional schematic diagram of a memory provided for an exemplary embodiment of this application;

[0059] Figure 2B for Figure 2A The diagram shows a longitudinal cross-section of the memory along the a-a' direction;

[0060] Figure 2C for Figure 2A The diagram shows a longitudinal cross-section of the memory along the b-b' direction;

[0061] Figure 2D for Figure 2A The diagram shows a longitudinal cross-section of the memory along the c-c' direction;

[0062] Figure 2E for Figure 2AThe diagram shows a longitudinal cross-section of the memory along the d-d' direction;

[0063] Figure 3 A process flow diagram of a method for manufacturing a memory provided for an exemplary embodiment of this application;

[0064] Figure 4A A schematic longitudinal section in the a-a' direction of a method for manufacturing a memory according to an exemplary embodiment of this application after forming a stacked structure;

[0065] Figure 4B for Figure 4A The diagram shows a longitudinal cross-section of the memory along the b-b' direction;

[0066] Figure 4C for Figure 4A The diagram shows a longitudinal cross-section of the memory along the c-c' direction;

[0067] Figure 4D for Figure 4A The diagram shows a longitudinal cross-section of the memory along the d-d' direction;

[0068] Figure 5A A schematic longitudinal section in the a-a' direction of a method for manufacturing a memory, which is an exemplary embodiment of this application, after forming a first trench and a second trench;

[0069] Figure 5B for Figure 5A The diagram shows a longitudinal cross-section of the memory along the b-b' direction;

[0070] Figure 5C for Figure 5A The diagram shows a longitudinal cross-section of the memory along the c-c' direction;

[0071] Figure 5D for Figure 5A The diagram shows a longitudinal cross-section of the memory along the d-d' direction;

[0072] Figure 6A A schematic longitudinal section in the a-a' direction of a method for manufacturing a memory, which is an exemplary embodiment of this application, after the first insulating layer is filled in the first trench and the second trench;

[0073] Figure 6B for Figure 6A The diagram shows a longitudinal cross-section of the memory along the b-b' direction;

[0074] Figure 6C for Figure 6A The diagram shows a longitudinal cross-section of the memory along the c-c' direction;

[0075] Figure 6D for Figure 6A The diagram shows a longitudinal cross-section of the memory along the d-d' direction;

[0076] Figure 7A A schematic longitudinal section in the a-a' direction of a method for manufacturing a memory, which is an exemplary embodiment of this application, after removing the second insulating layer in the second trench;

[0077] Figure 7B for Figure 7A The diagram shows a longitudinal cross-section of the memory along the b-b' direction;

[0078] Figure 7C for Figure 7A The diagram shows a longitudinal cross-section of the memory along the c-c' direction;

[0079] Figure 7D for Figure 7A The diagram shows a longitudinal cross-section of the memory along the d-d' direction;

[0080] Figure 8A A schematic longitudinal section in the a-a' direction of a method for manufacturing a memory, which is an exemplary embodiment of this application, after removing a first insulating layer of a certain depth in a patterned stacked structure;

[0081] Figure 8B for Figure 8A The diagram shows a longitudinal cross-section of the memory along the b-b' direction;

[0082] Figure 8C for Figure 8A The diagram shows a longitudinal cross-section of the memory along the c-c' direction;

[0083] Figure 8D for Figure 8A The diagram shows a longitudinal cross-section of the memory along the d-d' direction;

[0084] Figure 9A A schematic longitudinal section in the a-a' direction of a method for manufacturing a memory, which is an exemplary embodiment of this application, after removing a first insulating layer of a certain depth in a patterned stacked structure;

[0085] Figure 9B for Figure 9A The diagram shows a longitudinal cross-section of the memory along the b-b' direction;

[0086] Figure 9C for Figure 9A The diagram shows a longitudinal cross-section of the memory along the c-c' direction;

[0087] Figure 9D for Figure 9A The diagram shows a longitudinal cross-section of the memory along the d-d' direction;

[0088] Figure 10A A schematic longitudinal section in the a-a' direction of a method for manufacturing a memory, which is an exemplary embodiment of this application, after removing a portion of the first insulating layer in a first trench near a second trench;

[0089] Figure 10B for Figure 10A The diagram shows a longitudinal cross-section of the memory along the b-b' direction;

[0090] Figure 10C for Figure 10A The diagram shows a longitudinal cross-section of the memory along the c-c' direction;

[0091] Figure 10D for Figure 10A The diagram shows a longitudinal cross-section of the memory along the d-d' direction;

[0092] Figure 11A A schematic longitudinal section in the a-a' direction of a method for manufacturing a memory, which is an exemplary embodiment of this application, after removing the second insulating layer exposed by the first trench and the second trench;

[0093] Figure 11B for Figure 11A The diagram shows a longitudinal cross-section of the memory along the b-b' direction;

[0094] Figure 11C for Figure 11A The diagram shows a longitudinal cross-section of the memory along the c-c' direction;

[0095] Figure 11D for Figure 11A The diagram shows a longitudinal cross-section of the memory along the d-d' direction;

[0096] Figure 12A A schematic longitudinal cross-section in the a-a' direction of a method for manufacturing a memory, which is an exemplary embodiment of this application, after the formation of a second conductive layer;

[0097] Figure 12B for Figure 12A The diagram shows a longitudinal cross-section of the memory along the b-b' direction;

[0098] Figure 12C for Figure 12A The diagram shows a longitudinal cross-section of the memory along the c-c' direction;

[0099] Figure 12D for Figure 12A The diagram shows a longitudinal cross-section of the memory along the d-d' direction;

[0100] Figure 13AA schematic longitudinal section in the a-a' direction of a method for manufacturing a memory, which is an exemplary embodiment of this application, after removing the second conductive layer exposed on the inner wall of a first trench;

[0101] Figure 13B for Figure 13A The diagram shows a longitudinal cross-section of the memory along the b-b' direction;

[0102] Figure 13C for Figure 13A The diagram shows a longitudinal cross-section of the memory along the c-c' direction;

[0103] Figure 13D for Figure 13A The diagram shows a longitudinal cross-section of the memory along the d-d' direction;

[0104] Figure 14A A schematic longitudinal section in the a-a' direction of a method for manufacturing a memory, which is an exemplary embodiment of this application, after forming the third electrode of a capacitor;

[0105] Figure 14B for Figure 14A The diagram shows a longitudinal cross-section of the memory along the b-b' direction;

[0106] Figure 14C for Figure 14A The diagram shows a longitudinal cross-section of the memory along the c-c' direction;

[0107] Figure 14D for Figure 14A The diagram shows a longitudinal cross-section of the memory along the d-d' direction;

[0108] Figure 15A A schematic longitudinal section in the a-a' direction of a method for manufacturing a memory according to an exemplary embodiment of this application, after forming a capacitor;

[0109] Figure 15B for Figure 15A The diagram shows a longitudinal cross-section of the memory along the b-b' direction;

[0110] Figure 15C for Figure 15A The diagram shows a longitudinal cross-section of the memory along the c-c' direction;

[0111] Figure 15D for Figure 15A The diagram shows a longitudinal cross-section of the memory along the d-d' direction;

[0112] Figure 16A A schematic longitudinal section in the a-a' direction of a method for manufacturing a memory according to an exemplary embodiment of this application after forming a through hole K;

[0113] Figure 16B for Figure 16A The diagram shows a longitudinal cross-section of the memory along the b-b' direction;

[0114] Figure 16C for Figure 16A The diagram shows a longitudinal cross-section of the memory along the c-c' direction;

[0115] Figure 16D for Figure 16A The diagram shows a longitudinal cross-section of the memory along the d-d' direction;

[0116] Figure 17A A schematic longitudinal section in the a-a' direction after depositing a semiconductor layer in a via K, which is an exemplary embodiment of this application, is shown in the figure below.

[0117] Figure 17B for Figure 17A The diagram shows a longitudinal cross-section of the memory along the b-b' direction;

[0118] Figure 17C for Figure 17A The diagram shows a longitudinal cross-section of the memory along the c-c' direction;

[0119] Figure 17D for Figure 17A The diagram shows a longitudinal cross-section of the memory along the d-d' direction;

[0120] Figure 18A A schematic longitudinal section in the a-a' direction of a method for manufacturing a memory, which is an exemplary embodiment of this application, after removing the semiconductor layer of the parasitic MOS region;

[0121] Figure 18B for Figure 18A A magnified view of a portion of the image;

[0122] Figure 18C for Figure 18A The diagram shows a longitudinal cross-section of the memory along the b-b' direction;

[0123] Figure 18D for Figure 18A The diagram shows a longitudinal cross-section of the memory along the c-c' direction;

[0124] Figure 18E for Figure 18A The diagram shows a longitudinal cross-section of the memory along the d-d' direction. Detailed Implementation

[0125] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0126] The embodiments described in this application are not necessarily limited to the dimensions shown in the accompanying drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments described in this application are not limited to the shapes or values ​​shown in the drawings.

[0127] The ordinal numbers such as "first" and "second" in this application are used to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0128] In this application, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of this specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this application. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the application is not limited to the terms described in the disclosure and may be appropriately replaced as appropriate.

[0129] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0130] In this application, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, the channel region refers to the region through which current primarily flows.

[0131] In this application, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this application, unless otherwise specified, the "source electrode" and "drain electrode" can be interchanged.

[0132] In this disclosure, "electrical connection" or "connection" includes situations where constituent elements are connected together by a component having some electrical function, such as an electrical signal connection (coupled connection, e.g., coupled to), or a physical direct connection. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0133] In this application, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0134] In some embodiments of this application, the terms "film" and "layer" can be interchanged. For example, sometimes "first conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0135] In this application's embodiments, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected layers on a single film layer. For example, A and B may be formed using the same material to create a single film layer and simultaneously formed with interconnected structures through the same patterning process, or B may be directly grown on A via epitaxy, and the materials of the two may not be exactly the same.

[0136] In this application, the spacing can be understood as separate or independent. It can be achieved through a physical structural break or through electrical characteristics. For example, the semiconductor layer between the effective channels of two transistors is modified to achieve insulation, thereby creating an electrical spacing between the two channels.

[0137] In this application, "aperture" refers to the average aperture obtained after measurements at multiple locations.

[0138] In typical DRAM devices, the capacitor structure consists of two conductive plates sandwiching a dielectric layer. The lower plates of different capacitors are designed independently, each connected to the drain electrode of a transistor device. The upper plates of different capacitors are continuous and are typically used for grounding. A larger plate area in the capacitor structure can store more charge, resulting in better device performance. Therefore, it is desirable to maximize the plate area of ​​capacitors.

[0139] This application provides a memory. Figure 1A A longitudinal cross-sectional schematic diagram of a memory provided for an exemplary embodiment of this application; Figure 1B for Figure 1A A schematic diagram of the longitudinal section of the memory from another angle.

[0140] like Figure 1A and Figure 1B As shown, exemplarily, the memory includes: a substrate and an inner electrode 43, an outer electrode 44, and a dielectric layer 45 located on the substrate, the dielectric layer 45 being located between the inner electrode 43 and the outer electrode 44 for insulation;

[0141] The inner electrode 43 includes a first sub-electrode 431 and a second sub-electrode 432 disposed opposite to each other. The first sub-electrode 431 has a first surface 4311 and a second surface 4312 facing away from each other, and the second sub-electrode 432 has a third surface 4321 and a fourth surface 4322 facing away from each other.

[0142] The first surface 4311 and the second surface 4312 of the first sub-electrode 431 are at least partially covered by the outer electrode 44, and the third surface 4321 and the fourth surface 4322 of the second sub-electrode 432 are at least partially covered by the outer electrode 44.

[0143] For example, "at least partially covered" includes full or partial coverage. Figure 1A From the viewpoint shown, the first surface 4311, the second surface 4312, the third surface 4321, and the fourth surface 4322 are all partially covered by the external electrode 44; Figure 1B From the viewpoint shown, the first surface 4311, the second surface 4312, the third surface 4321 and the fourth surface 4322 are all completely covered by the external electrode 44.

[0144] The memory in this embodiment uses a bipolar plate internal electrode structure, which increases the area of ​​the internal electrode, allowing it to store more charge and thus improve the memory's performance.

[0145] For example, such as Figure 1AAs shown, the first sub-electrode 431 and the second sub-electrode 432 are connected together to form a first annular body 46, and the inner and outer peripheral surfaces of the first annular body 46 are covered by the outer electrode 44.

[0146] When the first sub-electrode and the second sub-electrode of the internal electrode are connected together to form the first ring body, the internal electrode can have more area to store charge, and the area occupied by the internal electrode of the same area can be reduced, so that more storage cells can be formed in a limited area, thereby improving the integration of the memory.

[0147] For example, such as Figure 1A and Figure 1B As shown, the outer electrode 44 covering the first sub-electrode 431 and the outer electrode 44 covering the second sub-electrode 432 can be an integral structure.

[0148] For example, such as Figure 1A As shown, the outer electrode 44 forms a second annular body 441 within the first annular body 46 of the inner electrode 43. The second annular body 441 contains a conductive material 442, and the second annular body 441 and the conductive material 442 constitute the outer electrode 44. Exemplarily, the dielectric layer material can be silicon oxide or a High-K dielectric material, i.e., a dielectric material with a dielectric constant K ≥ 3.9. The High-K dielectric material can include, but is not limited to, at least one of the following: aluminum oxide (Al2O3) and hafnium oxide.

[0149] For example, the stored material can be a capacitor.

[0150] Figure 2A A cross-sectional schematic diagram of a memory provided for an exemplary embodiment of this application; Figure 2B for Figure 2A The diagram shows a longitudinal cross-section of the memory along the a-a' direction; Figure 2C for Figure 2A The diagram shows a longitudinal cross-section of the memory along the b-b' direction; Figure 2D for Figure 2A The diagram shows a longitudinal cross-section of the memory along the c-c' direction; Figure 2E for Figure 2A The diagram shows a longitudinal cross-section of the memory along the d-d' direction.

[0151] like Figures 2A to 2E As shown, the memory may further include multiple storage units 60;

[0152] The memory cells 60 are distributed in different layers, stacked along a direction perpendicular to the substrate 10, and periodically distributed; each layer includes multiple rows of memory cells 60, and each memory cell 60 includes a transistor 61 and a capacitor 62. The capacitor 62 may include an inner electrode 43, an outer electrode 44, and a dielectric layer 45 as described above.

[0153] For example, such as Figures 2A to 2E As shown, the cross-sectional profile of the inner electrode 43 on a plane perpendicular to the substrate 10 and parallel to the first direction is annular.

[0154] For example, such as Figures 2A to 2E As shown, transistor 61 includes a first electrode 41, a second electrode 42, a semiconductor layer 80 located between the first electrode 41 and the second electrode 42, and a gate electrode 71. The semiconductor layer 80 and the gate electrode 71 are insulated from each other by a gate insulating layer 72 and a first insulating layer 11.

[0155] For example, such as Figure 2B and Figure 2D As shown, the semiconductor layers 80 of the transistors located in different layers are spaced apart.

[0156] For example, such as Figures 2A to 2E As shown, the channel region of transistor 61 extends along a first direction parallel to substrate 10, that is, the channel between the first electrode 41 and the second electrode 42 can be a horizontal channel.

[0157] A horizontal channel is defined as a channel in which the carrier transport direction lies in a plane parallel to the substrate, but this direction is not limited to a single direction. In practical applications, the carrier transport direction generally extends in one direction, but locally it depends on the shape of the semiconductor layer. In other words, a horizontal channel does not necessarily mean that it must extend in one direction within a horizontal plane; it may extend in different directions. For example, when the semiconductor layer is ring-shaped, the source and drain contact regions on the ring-shaped semiconductor layer are part of the ring. In this case, the carriers generally extend in one direction from the source contact region to the drain contact region, but locally it may not be in a single direction. Of course, the carrier transport direction lying in a plane parallel to the substrate is a macroscopic concept and is not limited to absolute parallelism to the substrate. This application protects the channel between the first and second electrodes as a channel that is not perpendicular to the substrate.

[0158] For example, such as Figure 2A As shown, the semiconductor layer 80 of the same transistor can surround its gate electrode 71.

[0159] Here, "encircling" can be understood as partially encircling or completely encircling. In some embodiments, such as... Figure 2AAs shown, the surrounding can be a complete surrounding, meaning that at least the entire sidewall of the gate electrode 71 is surrounded by the semiconductor layer 80, and the cross-section of the semiconductor layer 80 after surrounding is a closed ring. The cross-section is taken along a direction perpendicular to the substrate and parallel to the first direction. In some embodiments, the surrounding can be a partial surrounding, meaning that a portion of the sidewall of the gate electrode 71 is surrounded by the semiconductor layer 80, and the cross-section after surrounding is not closed, but presents a ring shape. For example, a ring with openings or two separate semiconductor layers. For example, opposite side surfaces of the gate electrode 71 are surrounded by the semiconductor layer 80, in which case the cross-section of the semiconductor layer 80 is a ring with two openings.

[0160] For example, such as Figure 2A As shown, the memory may further include a word line 70; the word line 70 extends in a direction perpendicular to the substrate 10. Stacked memory cells 60 of different layers may share a single word line 70 extending in a direction perpendicular to the substrate 10, that is, the word line 70 may penetrate the memory cells 60 of different layers.

[0161] For example, such as Figure 2B and Figure 2D As shown, the semiconductor layers 80 corresponding to transistors of different layers can be located on the sidewalls of word lines 70 and in different regions extending in a direction perpendicular to the substrate 10.

[0162] For example, such as Figure 2B and Figure 2D As shown, the gate electrode 71 of transistors in different layers can be part of word line 70, and word line 70 is exposed between the spaced semiconductor layers 80.

[0163] For example, such as Figure 2A and Figure 2B As shown, the memory may further include: bit line 31; bit line 31 extends along a second direction parallel to the substrate 10, the second direction intersecting the first direction.

[0164] For example, the first direction and the second direction can be perpendicular to each other. For instance, the first direction can be as follows: Figure 2A The direction shown is either a-a' or b-b', and the second direction can be as follows: Figure 2A The c-c' direction or d-d' direction is shown.

[0165] For example, such as Figure 2A and Figure 2B As shown, transistors 61 of two adjacent columns of memory cells 60 located on the same layer and in the second direction are connected to the same bit line 31, and the direction of the columns is the same as the second direction.

[0166] For example, such as Figure 2A and Figure 2B As shown, bit line 31 is connected to the first electrode 41 of two adjacent columns of transistors located on the same layer. The first electrode 41 and bit line 31 of the two adjacent columns of transistors located on the same layer can be an integral structure, or it can be understood that the first electrode 41 and bit line 31 can be shared.

[0167] For example, such as Figure 2A As shown, the external electrodes 44 of capacitors located in the same column on the same layer can be a single integrated structure. Alternatively, the external electrodes 44 of capacitors located in the same column on different layers can also be a single integrated structure.

[0168] Exemplarily, the dielectric layers of the capacitors located in the same column of different layers can be a single, integral structure. Exemplarily, the semiconductor layer of the transistor and the internal electrode can be electrically connected via a conductive layer, the material of which is the same as the material of the bit line. For example, as... Figure 2A and Figure 2B As shown, the semiconductor layer 80 and the inner electrode 43 are electrically connected through the first conductive layer where the second electrode 42 is located. The first conductive layer also includes a bit line 31, that is, the second electrode 42 and the bit line 31 are located in the same conductive layer and they are made of the same material.

[0169] For example, such as Figure 2D As shown, the semiconductor layer 80 includes a bottom 81, a middle 82 and a top 83 in sequence along the direction away from the substrate 10. The dimensions of the top 83 and the bottom 81 in the direction parallel to the substrate 10 are greater than the dimensions of the middle 82 in the direction parallel to the substrate 10. That is, the orthogonal projection of the middle 82 on the substrate 10 falls within the range of the orthogonal projections of the top 83 and the bottom 81 on the substrate 10.

[0170] For example, the word line 70 has a protrusion 74 at a location near the semiconductor layer 80 of each of the transistors, the protrusion 74 extending in a direction parallel to the substrate 10.

[0171] In this application, the semiconductor layer 80 can be understood as a semiconductor material; its shape and structure are not emphasized, only its function. For example, the material of the semiconductor layer can be silicon or polycrystalline silicon with a band gap of less than 1.65 eV, or it can be a wide band gap material, such as a metal oxide material with a band gap greater than 1.65 eV.

[0172] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.

[0173] In some embodiments, the material of the metal oxide semiconductor layer or channel may comprise any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InW). Materials such as O, IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) are all acceptable, as long as the leakage current of the transistor meets the requirements. Specific adjustments can be made based on the actual situation.

[0174] These materials have a wide band gap and low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10A to 15A, which can improve the performance of dynamic memory.

[0175] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.

[0176] For example, the material of the bit line can be selected from any one or more other metallic materials with similar properties, such as tungsten, molybdenum, and cobalt. The bit line can be a single-layer or multi-layer structure, for example, it can be a multi-layer structure formed of titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0177] For example, the electrode material of the gate electrode can be any one or more of the following different types of materials:

[0178] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can be a metal alloy containing these metals.

[0179] It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), and other metal oxide materials with high conductivity; such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), and other metal nitride materials.

[0180] Of course, it can also be polycrystalline silicon; it can also be a conductive material doped with a semiconductor material, such as conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.; and other materials that exhibit conductivity, etc.

[0181] Exemplarily, the gate insulating layer may comprise one or more Low-K and / or High-K dielectric materials, or comprise two or more regions with different dielectric constants K. The characteristics of the gate insulating layer of this application will be illustrated below by way of example.

[0182] Low-K materials, such as silicon oxide.

[0183] High-K materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, they may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, they may include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc.

[0184] The aforementioned storage unit may be a storage unit containing transistors, wherein the transistors may be access transistors, and the storage unit may also contain other components, such as read transistors and storage nodes in a 2TOC storage unit.

[0185] For example, the memory can be a 3D memory, such as 3D DRAM. The 3D memory can be a 1T1C or 2T1C structure.

[0186] This application also provides a method for manufacturing a memory, the memory comprising: a plurality of memory cells distributed on different layers, stacked and periodically distributed along a direction perpendicular to the substrate, the memory cells comprising transistors and capacitors. Figure 3 A process flow diagram of a method for manufacturing a memory provided for an exemplary embodiment of this application.

[0187] like Figure 3 As shown, the manufacturing method includes:

[0188] A stacked structure is obtained by sequentially and alternately depositing a first insulating layer and a first conductive layer on a substrate.

[0189] The stacked structure is patterned and etched. Each patterned first conductive layer includes bit lines and a plurality of conductive portions spaced apart on at least one side of the bit lines. The conductive portions include the first electrode and the second electrode of the transistor.

[0190] Etching removes a portion of the conductive portion away from the bit line, exposing the side of the first insulating layer at a set depth in the patterned stacked structure;

[0191] A first sub-electrode and a second sub-electrode, disposed opposite to each other, are deposited on the exposed side of the first insulating layer in the patterned stacked structure. The first sub-electrode and the second sub-electrode constitute the internal electrode of the capacitor. Both the first sub-electrode and the second sub-electrode have two opposing surfaces.

[0192] A dielectric layer and an outer electrode are sequentially deposited on two opposing surfaces of the first sub-electrode and the second sub-electrode, respectively, and the inner electrode, the outer electrode, and the dielectric layer constitute the capacitor.

[0193] The memory manufacturing method of this application embodiment first removes the first conductive layer located in the capacitor region (i.e., the region subsequently used to form a capacitor), exposing the side surface of a patterned first insulating layer at a predetermined depth. Then, a second conductive layer is deposited on the exposed side surface of two adjacent patterned first insulating layers as a first sub-electrode and a second sub-electrode, respectively, to obtain an internal electrode with a bipolar plate structure (i.e., the internal electrode includes the first sub-electrode and the second sub-electrode). The first sub-electrode has a first surface and a second surface facing away from each other, and the second sub-electrode has a third surface and a fourth surface facing away from each other. Furthermore, the first surface, the second surface, the third surface, and the fourth surface can all store charge. Therefore, compared to an internal electrode with a single-plate structure, the internal electrode obtained by the manufacturing method of this application embodiment can have more area to store charge, thereby improving the performance of the memory.

[0194] For example, the memory may further include multiple bit lines distributed in different layers and extending along a second direction parallel to the substrate, and the same bit line is connected to two adjacent columns of memory cells located in the same layer. The two adjacent columns of memory cells in different layers connected by the multiple bit lines stacked along a direction perpendicular to the substrate constitute a memory repeating unit.

[0195] Patterning etching of the stacked structure may include:

[0196] The stacked structure is patterned and etched along a direction toward the substrate, such that a first trench extending along a first direction parallel to the substrate and a second trench extending along a second direction are formed in the stacked structure; the first trench spaced each of the first conductive layers as bit lines and a plurality of conductive portions spaced apart on at least one side of the bit lines; the second trench spaced two adjacent memory repeating cells in the first direction; and two spaced first trenches are provided between two adjacent second trenches in the first direction.

[0197] Exemplarily, depositing and forming opposing first and second sub-electrodes on the exposed side of the first insulating layer in the patterned stacked structure may include:

[0198] A second conductive layer is deposited on the exposed side of the first insulating layer and on the inner wall of the first trench in the patterned stacked structure, and the second conductive layers located between two adjacent first insulating layers in the patterned stacked structure are connected together to form a ring.

[0199] The first insulating layer is used to fill each of the first trenches and to fill the gaps between each of the second conductive layers;

[0200] The first insulating layer and the second conductive layer on the inner wall of the first trench are removed by etching in a portion of the first trench near the second trench. The remaining second conductive layer is located in an annular shape between two adjacent first insulating layers. The second conductive layers located on opposite sides of the two adjacent first insulating layers serve as the first sub-electrode and the second sub-electrode, respectively. The first sub-electrode and the second sub-electrode are connected together to form a first annular body.

[0201] Exemplarily, depositing a dielectric layer and an external electrode sequentially on two opposing surfaces of the first sub-electrode and the second sub-electrode may include:

[0202] A dielectric layer and an external electrode are sequentially deposited on the inner and outer circumferential surfaces of the first annular body, such that the inner and outer circumferential surfaces of the first annular body are at least partially covered by the external electrode.

[0203] When the first sub-electrode and the second sub-electrode of the inner electrode are connected together to form the first ring body, the inner electrode can have more area to store charge, and the area occupied by the inner electrode can be reduced within the same area, so that more storage cells can be formed in a limited area, thereby improving the integration of the memory.

[0204] Exemplarily, the manufacturing method may further include, after patterning the stacked structure and before etching away a portion of the conductive portion away from the bit line, performing the following process:

[0205] A second insulating layer is deposited on the inner wall of the first trench;

[0206] The first trench is filled with the first insulating layer, and the second trench exposes the first insulating layer in the patterned stacked structure.

[0207] Laterally etch the first insulating layer exposed in the patterned stacked structure in the second trench to expose the side of the first conductive layer at a certain depth in the patterned stacked structure.

[0208] The second insulating layer is deposited on the inner wall of the second trench, and the first insulating layer is filled into the second trench;

[0209] The first and second insulating layers in a portion of the first trench near the second trench are etched away, exposing the first conductive layer in the patterned stacked structure.

[0210] Exemplarily, depositing a second insulating layer on the inner wall of the first trench, and filling the first insulating layer within the first trench, exposing the first insulating layer in the patterned stacked structure in the second trench, may include:

[0211] A second insulating layer is deposited on the inner walls of the first trench and the second trench, and the first insulating layer is filled into the first trench and the second trench.

[0212] Etching removes the first insulating layer within the second trench;

[0213] The second insulating layer on the inner wall of the second trench is etched away to expose the first insulating layer in the patterned stacked structure.

[0214] For example, etching away a portion of the first and second insulating layers in the first trench near the second trench, exposing a first conductive layer in a patterned stacked structure, may include:

[0215] The first insulating layer in a portion of the first trench near the second trench is etched away, exposing the second insulating layer on a portion of the inner wall of the first trench, and exposing the second insulating layer in the second trench near the bit line side;

[0216] The second insulating layer exposed on the inner wall of the first trench and the second insulating layer exposed in the second trench are etched away, so that a portion of the sidewall of the first trench exposes the first conductive layer in a patterned stacked structure.

[0217] The memory provided in the above embodiments of this application can be obtained by the manufacturing method described above.

[0218] The technical solutions of the embodiments of this application are further illustrated below through an exemplary embodiment of the memory manufacturing process. The "patterned etching" mentioned in this embodiment includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography" process mentioned in this embodiment includes coating a film layer, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations here.

[0219] Figures 4A to 18E These are schematic longitudinal cross-sectional views and partial enlarged views of a device structure obtained during an intermediate process of a memory manufacturing method, which is an exemplary embodiment of this application, in different directions.

[0220] like Figures 4A to 18E As shown, by way of example, the method of manufacturing the memory may include the following process.

[0221] S10: A substrate 10 is provided, and a first insulating layer 11 and a first conductive layer 12 are sequentially and alternately deposited on the substrate 10 to obtain a stacked structure composed of the first insulating layer 11 and the first conductive layer 12, wherein the uppermost layer of the stacked structure is the first insulating layer 11, as shown below. Figures 4A to 4D As shown.

[0222] For example, the material of the first insulating layer can be a low-K dielectric material, that is, a dielectric material with a dielectric constant K < 3.9, including but not limited to silicon oxides, such as silicon dioxide (SiO2) or other silicon-containing films.

[0223] For example, the material of the first conductive layer can be any one or more of conductive metal, conductive metal nitride, and polycrystalline silicon; the conductive metal includes, but is not limited to, tungsten (W), cobalt (Co), titanium (Ti), etc.

[0224] Exemplarily, the first conductive layer can be a single-layer or multi-layer structure, for example, it can be a multi-layer structure formed of Ti, TiN, and W. For example, Ti, TiN, and W can be sequentially deposited on the side of the first insulating layer 11 away from the substrate 10 to form a multi-layer first conductive layer. Placing TiN between the side of W near the substrate 10 and the first insulating layer 11 can prevent W from being oxidized by the oxygen-containing first insulating layer 11; therefore, the TiN film can be called an anti-oxidation layer. Of course, the first insulating layer can be an oxygen-free film, in which case an anti-oxidation layer is not needed for the first conductive layer.

[0225] For example, Ti can be deposited using chemical vapor deposition (CVD); TiN can be deposited using atomic layer deposition (ALD); and W can be deposited using either CVD or ALD. After each tungsten layer deposition, the tungsten layer can be planarized and its thickness controlled using chemical mechanical polishing (CMP).

[0226] For example, the substrate 10 can be a support structure, such as a silicon substrate, or a support structure on which other films or functionalities or circuits are already distributed. The device involved in the inventive construction of the present application embodiment is disposed on the upper main surface of the support structure.

[0227] Figures 4A to 4D The stacked structure shown includes four first insulating layers 11 and three first conductive layers 12. This is merely an example. In other embodiments, the stacked structure may include more or fewer alternating layers of first insulating layers 11 and first conductive layers 12.

[0228] S20: Pattern the stacked structure by etching.

[0229] For example, step S20 may include: depositing a second insulating layer 13 on the surface of the stacked structure; defining a photolithographic pattern using photolithography; and patterning the second insulating layer 13 and the stacked structure along a direction toward the substrate 10, such that a plurality of first trenches 21 extending along a first direction and a plurality of second trenches 22 extending along a second direction are formed in the stacked structure; the plurality of first trenches 21 are spaced apart in the second direction, and there are two spaced first trenches 21 between two adjacent second trenches 22 in the first direction; the first direction intersects the second direction, and the patterned first insulating layer 11 and patterned first conductive layer 12 stacked alternately constitute a patterned stacked structure.

[0230] The first trench 21 divides the first conductive layer 12 into bit lines 31 to be formed, a plurality of spaced-apart first conductive parts 32, and a plurality of spaced-apart second conductive parts 33. That is, the patterned first conductive layer 12 includes bit lines 31, first conductive parts 32, and second conductive parts 33. Among them, the bit lines 31 connect the first conductive parts 32 and the second conductive parts 33. The plurality of spaced-apart first conductive parts 32 and the plurality of spaced-apart second conductive parts 33 are respectively located on both sides of the bit lines 31. The bit lines 31, the plurality of first conductive parts 32, and the plurality of second conductive parts 33 can form a structure like the Chinese character "丰" (abundant). The bit lines 31 serve as the main trunk of the "丰" - shaped structure, and the plurality of first conductive parts 32 and the plurality of second conductive parts 33 serve as the branches of the "丰" - shaped structure. The first conductive parts 32 can extend along the first direction, the second conductive parts 33 can extend along the first direction, and the bit lines 31 can extend along the second direction. The same bit line can be connected to adjacent two columns of memory cells in the same layer to be formed. The adjacent two columns of memory cells connected by multiple bit lines stacked in the direction perpendicular to the substrate constitute a memory repeating unit. The second trench 22 is used to separate adjacent two memory repeating units in the first direction. The pattern of the patterned first insulating layer 11 is the same as the pattern of the patterned first conductive layer 12, as Figures 5A to 5D shown.

[0231] One end of the first conductive part 32 connected to the bit line 31 serves as the first electrode of the transistor to be formed subsequently. That is, the bit line 31 and the first electrode of the transistor connected thereto are an integral structure, or the bit line 31 and the first electrode of the transistor connected thereto are shared. One end of the first conductive part 32 far from the bit line 31 forms a second electrode of a transistor by disconnecting from the bit line 31 subsequently. One end of the second conductive part 33 far from the bit line 31 forms a second electrode of an adjacent another transistor by disconnecting from the bit line 31 subsequently. One end of the second conductive part 33 connected to the bit line 31 serves as the first electrode of this transistor or the bit line 31 is shared as the first electrode of this transistor.

[0232] Exemplarily, the first direction and the second direction can both be parallel to the substrate 10. For example, the first direction can be the a - a' direction or the b - b' direction as Figure 2A shown, and the second direction can be the c - c' direction or the d - d' direction as Figure 2A shown.

[0233] Exemplarily, as Figures 5A to 5D shown, the depth of the first trench 21 can be greater than the depth of the second trench 22. For example, the first trench 21 can extend into the substrate 10, and the second trench 22 exposes the surface of the substrate 10.

[0234] For example, the material of the second insulating layer can be any one or more of silicon oxide (e.g., SiO2), silicon oxynitride (SiON), silicon nitride (SiN), and silicon carbonitride (SiCN), and the materials of the second insulating layer and the first insulating layer are different so that when one of the insulating layers is subsequently etched away, the first insulating layer and the second insulating layer can have different etching rates, thereby removing the desired insulating layer. For example, in this embodiment, the material of the first insulating layer can be silicon oxide, and the material of the second insulating layer can be silicon nitride.

[0235] S30: A second insulating layer 13 is deposited on the inner walls (including sidewalls and bottom walls) of the first trench 21 and the second trench 22 and on the top surface of the patterned stacked structure, and the first insulating layer 11 is filled into the first trench 21 and the second trench 22. Then, a CMP process is used to planarize the first insulating layer 11 on the top surface of the substrate 10 until the second insulating layer 13 on the top surface of the substrate 10 is exposed. Figures 6A to 6D As shown.

[0236] S40: Etching removes the first insulating layer 11 within the second trench 22, such as Figures 7A to 7D As shown.

[0237] For example, step S40 may employ dry etching to remove the first insulating layer 11 within the second trench 22.

[0238] S50: Etch away the second insulating layer 13 on the inner wall of the second trench 22, exposing the first insulating layer 11 in the patterned stacked structure and the first insulating layer 11 in the first trench 21; perform lateral etching on the exposed first insulating layer 11 in the second trench 22 to remove the first insulating layer 11 to a certain depth, thereby exposing the end face of the first conductive layer 12 at a corresponding depth in the patterned stacked structure, such as... Figures 8A to 8D As shown.

[0239] For example, in step S50, wet etching may be used to remove the second insulating layer 13 on the inner wall of the second trench 22, and / or wet etching may be used to remove the first insulating layer 11 of a certain depth in the patterned stacked structure.

[0240] S60: A second insulating layer 13 is deposited on the inner wall (including the sidewalls and bottom wall) of the second trench 22, such that the exposed end face of the first conductive layer 12 of the patterned stacked structure is covered by the second insulating layer 13, and the exposed side and top surfaces of the first insulating layer 11 in the first trench 21 are also covered by the second insulating layer 13, and the second trench 22 is filled with the first insulating layer 11. The second insulating layer 13 deposited in this step can subsequently serve as an isolation layer between storage repeating units and a support layer for the capacitor to be formed. The first insulating layer 11 deposited in this step can serve as a barrier layer when the second insulating layer 13 is subsequently etched, such as... Figures 9A to 9D As shown.

[0241] S70: Remove the first insulating layer 11 from a portion of the first trench 21 near the second trench 22, such as... Figures 10A to 10D As shown.

[0242] For example, step S70 may include: using dry etching to remove a portion of the first insulating layer 11 in the first trench 21 near the second trench 22, exposing a portion of the second insulating layer 13 on the inner wall of the first trench 21, and exposing the second insulating layer 13 in the second trench 22 near the bit line side, and the second insulating layer 13 on the bottom wall of the first trench 21 that was originally covered by the first insulating layer 11 is also completely or partially etched away; wherein, the length of the first insulating layer 11 etched away in the first trench 21 in the first direction is equal to the expected length of the inner electrode 43 of the capacitor to be formed.

[0243] S80: Etching removes the second insulating layer 13 exposed on the inner wall of the first trench 21 and the second insulating layer 13 exposed in the second trench 22, such as Figures 11A to 11D As shown.

[0244] For example, step S80 may include: using wet etching to remove the second insulating layer 13 exposed on the sidewall of the first trench 21 and the second insulating layer 13 exposed in the second trench 22, so that a portion of the sidewall of the first trench 21 exposes the first conductive layer 12 in the patterned stacked structure.

[0245] like Figure 11B As shown, due to the presence of the first insulating layer 11 on the sidewall of the second trench 22, the first insulating layer 11 can act as a barrier layer in S80 to protect the second insulating layer 13 on the sidewall of the second trench 22 away from the bit line from being etched away. It can then be used as a support layer to support the memory repeating cell, thereby improving the structural stability of the memory.

[0246] like Figure 11A , Figure 11C and Figure 11DAs shown, due to the presence of the first insulating layer 11 on the surface of the substrate 10, the second insulating layer 13 covered by the first insulating layer 11 on the surface of the substrate 10 will not be etched away and can serve as a support layer (or frame) to provide support for the memory cell, thereby improving the structural stability of the memory cell.

[0247] S90: Laterally etch the first conductive layer 12 exposed on the sidewall of the first trench 21 to expose the sidewall of the first insulating layer 11 in the patterned stacked structure at a predetermined depth away from the bit line end, the predetermined depth being the length of the inner electrode of the capacitor to be formed; deposit a second conductive layer 14 on the exposed sidewall of the first insulating layer 11 in the patterned stacked structure and on the inner wall of the first trench 21, and connect the second conductive layers 14 located between two adjacent first insulating layers 11 in the patterned stacked structure to form a ring, wherein the second conductive layer 14 located between two adjacent patterned first insulating layers 11 is connected to the first conductive layer 12, such as... Figures 12A to 12D As shown.

[0248] For example, step S90 can use wet etching to perform lateral etching on the exposed first conductive layer 12, and the etching reagent used in wet etching is SC1 solution (a mixed solution of ammonia and hydrogen peroxide).

[0249] For example, the material of the second conductive layer can be any one or more of a conductive metal, a conductive metal nitride, and polycrystalline silicon; the conductive metal includes, but is not limited to, tungsten (W), cobalt (Co), titanium (Ti), etc., and the material of the second conductive layer can be the same as or different from the material of the first conductive layer. The second conductive layer can be a single-layer or multi-layer structure. In this exemplary embodiment, the first conductive layer can be a three-layer structure composed of Ti, TiN, and W, and the second conductive layer can be a two-layer structure composed of Ti and TiN.

[0250] S100: The gaps between each first trench 21 and each second conductive layer 14 are filled with a first insulating layer 11; the first insulating layer 11 and the second conductive layer 14 on the inner wall of the first trench 21 are etched away in a portion of the first trench 21 near the second trench 22. Figures 13A to 13D As shown.

[0251] For example, step S100 may include:

[0252] S101: The gaps between each first trench 21 and each second conductive layer 14 are filled with a first insulating layer 11, and planarization is performed using CMP process;

[0253] S102: Dry etching is used to remove a portion of the first insulating layer 11 in the first trench 21 near the second trench 22, exposing the second conductive layer 14 on the inner wall of the first trench 21. That is, the removed first insulating layer 11 is the first insulating layer 11 deposited after the second conductive layer 14. Then, wet etching is used to remove the exposed second conductive layer 14 on the inner wall of the first trench 21, leaving an annular second conductive layer 14 between two adjacent first insulating layers 11. The second conductive layers 14 on the opposite sides of the two adjacent first insulating layers 11 serve as the first sub-electrode 431 and the second sub-electrode 432, respectively. The first sub-electrode 431 and the second sub-electrode 432 are connected together to form an annular inner electrode 43. After the second conductive layer 14 on the sidewall of the first trench 21 is etched, the sidewall of the first trench 21 exposes the first insulating layer 11, as shown below. Figures 13A to 13D As shown.

[0254] S110: Laterally etch the first insulating layer 11 exposed on the sidewall of the first trench 21, so as to remove the first insulating layer 11 between the second conductive layers 14 spaced apart along the direction perpendicular to the substrate 10. After removing the first insulating layer 11, the two opposing surfaces of the first sub-electrode 431 and the second sub-electrode 432 of the inner electrode 43 are exposed. The exposed surfaces of the first sub-electrode 431 and the second sub-electrode 432 are connected together to form the annular inner and outer peripheral surfaces of the annular inner electrode 43. Figures 14A to 14D As shown.

[0255] like Figure 14A As shown, the longitudinal cross-sectional profile of the inner electrode 43 of the capacitor in the first direction can be annular.

[0256] S120: A dielectric layer 45 and a conductive film layer are sequentially deposited on the substrate 10, covering the exposed inner and outer peripheral surfaces of the annular inner electrode 43. The conductive film layer covering the inner and outer peripheral surfaces of the annular inner electrode 43 forms the outer electrode 44. The inner electrode 43, the outer electrode 44, and the dielectric layer 45 located between the inner electrode 43 and the outer electrode 44 constitute a capacitor. A third conductive layer 15 is filled into the empty space of the first trench 21 and the gaps in the capacitor. Figures 15A to 15D As shown.

[0257] For example, the material of the outer electrode 44 can be any one or more of a conductive metal, a conductive metal nitride, and polycrystalline silicon; the conductive metal includes, but is not limited to, tungsten (W), cobalt (Co), titanium (Ti), etc., and the materials of the outer electrode 44 and the inner electrode can be the same or different. The outer electrode 44 can be a single-layer or multi-layer structure, for example, it can include a second ring body formed by a Ti and TiN bilayer structure and polycrystalline silicon as the conductive material within the second ring body.

[0258] For example, the material of the third conductive layer can be any one or more of a conductive metal, a conductive metal nitride, and polysilicon; the conductive metal includes, but is not limited to, tungsten (W), cobalt (Co), and titanium (Ti), and the material of the third conductive layer can be the same as or different from the material of the first conductive layer. The third conductive layer can be a single-layer or multi-layer structure. In this exemplary embodiment, the first conductive layer can be a three-layer structure composed of Ti, TiN, and W, and the third conductive layer can be a single-layer structure formed of polysilicon.

[0259] S130: The patterned stacked structure is etched along the direction toward the substrate 10 to form a via K through each patterned first conductive layer 12.

[0260] For example, step S130 may include:

[0261] S131: Disconnect the dielectric layer 45 and conductive film layer (including the conductive film layer and the third conductive layer deposited when forming the external electrode) covering the patterned stacked structure on the top surface of the substrate 10 to prevent the capacitor from being connected to the word line formed subsequently. Then, deposit the first insulating layer 11 and the second insulating layer 13 sequentially on the surface of the substrate 10.

[0262] S132: The patterned stacked structure is etched along the direction toward the substrate 10 to form vias K penetrating each patterned first conductive layer 12, such as... Figures 16A to 16D As shown.

[0263] For example, step S132 can be performed using photolithography and dry etching to form the via K. The via K obtained in step S132 can have approximately the same aperture in the first conductive layer and the first insulating layer of the patterned stacked structure. The via K can extend along a direction perpendicular to the substrate 10 and expose the substrate 10.

[0264] S133: The through hole K is laterally expanded so that the first conductive part 32 and the second conductive part 33 are respectively disconnected by the through hole K to form the first electrode 41 and the second electrode 42 of the transistor.

[0265] For example, step S133 may include: laterally etching the first conductive layer 12 in the patterned stacked structure within the via K, such that the via K penetrates the first conductive portion 32 and the second conductive portion 33 in the second direction, but does not penetrate the first conductive portion 32 and the second conductive portion 33 in the first direction, thereby spacing the first conductive portion 32 into the first electrode 41 and the second electrode 42 of a transistor, and spacing the second conductive portion 33 into the first electrode 41 and the second electrode 42 of another adjacent transistor. After expansion, the aperture of the via K in the first conductive layer 12 is larger than the aperture of the via K in the first insulating layer 11, and the orthogonal projection of the via K in the first insulating layer 11 onto the substrate 10 falls within the range of the orthogonal projection of the via K in the first conductive layer 12 onto the substrate 10.

[0266] S140: A semiconductor layer 80 and a gate insulating layer 72 covering the inner wall of the via K are sequentially deposited on the substrate 10. A gate electrode layer 73 is formed by filling the via K with gate electrode material. Figures 17A to 17D As shown.

[0267] In this embodiment, the semiconductor layer 80 can be made of IGZO, the gate insulating layer 72 can be made of Al2O3, and the gate electrode layer 73 can be made of ITO.

[0268] S150: Remove the semiconductor layer 80 from the parasitic MOS region 200.

[0269] The connection between two transistors stacked in a direction perpendicular to the substrate 10 due to the presence of a semiconductor layer 80 will form a parasitic MOS transistor (referred to as parasitic MOS), which will affect the performance of the memory. Therefore, the semiconductor layer 80 located in the parasitic MOS region 200 should be removed, and only the semiconductor layer 80 located in the channel region 300 should be retained.

[0270] For example, step S150 may include: using wet etching to remove the gate electrode layer 73, gate insulating layer 72, and semiconductor layer 80 on a portion of the inner wall of the via K, leaving only the gate electrode layer 73, gate insulating layer 72, and semiconductor layer 80 on the sidewall of the portion of the via extending into the first electrode 41 and the second electrode 42; for example, oxalic acid may be used as an etching agent to etch the ITO gate electrode layer 73, and hydrochloric acid may be used as an etching agent to etch the Al2O3 gate insulating layer 72 and the IGZO semiconductor layer 80; hydrochloric acid has a low etching rate for ITO, which can prevent the ITO gate electrode layer 73 from being over-etched.

[0271] S160: Forms word line 70 in through hole K.

[0272] For example, step S160 may include:

[0273] S161: A first insulating layer 11 is deposited on the substrate 10 to fill the via K, covering the exposed semiconductor layer 80 and gate insulating layer 72 in the channel region 300; then, the first insulating layer 11 is wet-etched to expose at least a portion of the gate electrode layer 73, while the first insulating layer 11 covering the semiconductor layer 80 and gate insulating layer 72 remains. Figures 18A to 18E As shown;

[0274] S162: The via K is filled with the gate electrode material, and the gate electrode material in each via K forms a word line 70 that runs through each patterned first conductive layer; the region of the word line 70 between the first electrode 41 and the second electrode 42 serves as the gate electrode 71 of the transistor, and the semiconductor layer 80 in the channel region between the first electrode 41 and the second electrode 42 is used to form the channel of the transistor. The semiconductor layer 80 surrounds the gate electrode 71. The first electrode 41, the second electrode 42, the semiconductor layer 80 between the first electrode 41 and the second electrode 42, and the gate electrode 71 constitute the transistor.

[0275] S163: Then, the gate electrode material on the surface of the substrate 10 is planarized using a CMP process until the second insulating layer 13 on the surface of the substrate 10 is exposed, resulting in the following: Figures 2A to 2E The memory shown.

[0276] This application also provides an electronic device, which includes the memory provided in the above embodiments of this application.

[0277] For example, the electronic device may be a storage device, a smartphone, a computer, a tablet, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited here.

[0278] While the embodiments disclosed in this application are as described above, the content is merely for the purpose of facilitating understanding of this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A memory, characterized in that, include: Substrate and multiple memory cells located on the substrate; The plurality of memory cells are distributed in different layers, stacked along a direction perpendicular to the substrate, and periodically distributed. Each layer includes multiple rows of memory cells, each memory cell including a transistor and a capacitor; each transistor includes a second electrode; each capacitor includes an inner electrode, an outer electrode, and a dielectric layer located between the inner electrode and the outer electrode for insulation; the second electrode is connected to the inner electrode. The inner electrode includes a first sub-electrode and a second sub-electrode disposed opposite to each other. The first sub-electrode has a first surface and a second surface facing away from each other, and the second sub-electrode has a third surface and a fourth surface facing away from each other. The first and second surfaces of the first sub-electrode are at least partially covered by the outer electrode, and the third and fourth surfaces of the second sub-electrode are at least partially covered by the outer electrode.

2. The memory according to claim 1, characterized in that, The first sub-electrode and the second sub-electrode are connected together to form a first ring body, and the inner and outer peripheral surfaces of the first ring body are at least partially covered by the outer electrode.

3. The memory according to claim 2, characterized in that, The outer electrode covering the first sub-electrode and the outer electrode covering the second sub-electrode are an integral structure.

4. The memory according to claim 2, characterized in that, The outer electrode forms a second ring within the first ring of the inner electrode, and the second ring contains a conductive material.

5. The memory according to any one of claims 1 to 4, characterized in that, The channel region of the transistor extends along a first direction parallel to the substrate; The cross-sectional profile of the internal electrode on a plane perpendicular to the substrate and parallel to the first direction is annular.

6. The memory according to claim 5, characterized in that, Also includes: Word lines extend in a direction perpendicular to the substrate and penetrate the memory cells of different layers; And / or, Bit lines extend along a second direction parallel to the substrate; transistors in two columns of memory cells located on the same layer and adjacent in the first direction are connected to the same bit line, the columns being oriented in the same direction as the second direction.

7. The memory according to claim 6, characterized in that, The semiconductor layer of the transistor is electrically connected to the inner electrode through a conductive layer, the material of which is the same as the material of the bit line.

8. The memory according to claim 7, characterized in that, The semiconductor layer comprises a bottom, a middle, and a top in sequence along a direction away from the substrate, and the dimensions of the top and bottom in a direction parallel to the substrate are greater than the dimensions of the middle in a direction parallel to the substrate.

9. The memory according to claim 6, characterized in that, The word lines have protrusions near the semiconductor layer of each transistor, and the protrusions extend in a direction parallel to the substrate.

10. A method for manufacturing a memory, characterized in that, The memory includes: a plurality of memory cells distributed in different layers, stacked and periodically distributed along a direction perpendicular to the substrate; each memory cell includes a transistor and a capacitor; each transistor includes a second electrode; each capacitor includes an inner electrode, an outer electrode, and a dielectric layer located between the inner electrode and the outer electrode; the second electrode is connected to the inner electrode. The manufacturing method includes: A stacked structure is obtained by sequentially and alternately depositing a first insulating layer and a first conductive layer on a substrate. The stacked structure is patterned and etched. Each patterned first conductive layer includes bit lines and a plurality of conductive portions spaced apart on at least one side of the bit lines. The conductive portions include the first electrode and the second electrode of the transistor. Etching removes a portion of the conductive portion away from the bit line, exposing the side of the first insulating layer at a set depth in the patterned stacked structure; A first sub-electrode and a second sub-electrode, disposed opposite to each other, are deposited on the exposed side of the first insulating layer in the patterned stacked structure. The first sub-electrode and the second sub-electrode constitute the internal electrode of the capacitor. Both the first sub-electrode and the second sub-electrode have two opposing surfaces. Remove the first insulating layer covering the surface of the first sub-electrode and the surface of the second sub-electrode to expose the two opposite surfaces of the first sub-electrode and the two opposite surfaces of the second sub-electrode. A dielectric layer and an outer electrode are sequentially deposited on two opposing surfaces of the first sub-electrode and the second sub-electrode, respectively, and the inner electrode, the outer electrode, and the dielectric layer constitute the capacitor.

11. The manufacturing method according to claim 10, characterized in that, The memory also includes multiple bit lines distributed in different layers and extending along a second direction parallel to the substrate. Each bit line is connected to two adjacent columns of memory cells located in the same layer. The multiple bit lines stacked along a direction perpendicular to the substrate connect two adjacent columns of memory cells in different layers to form a memory repeating unit. Patterning etching of the stacked structure includes: The stacked structure is patterned and etched along a direction toward the substrate, such that a first trench extending along a first direction parallel to the substrate and a second trench extending along a second direction are formed in the stacked structure; The first trench separates each of the first conductive layers into bit lines and a plurality of conductive portions spaced apart on at least one side of the bit lines. The second trench is used to space two adjacent memory repeating cells apart in the first direction. There are two spaced first trenches between two adjacent second trenches in the first direction.

12. The manufacturing method according to claim 11, characterized in that, A first sub-electrode and a second sub-electrode, disposed opposite to each other, are deposited on the exposed side of the first insulating layer in the patterned stacked structure, including: A second conductive layer is deposited on the exposed side of the first insulating layer and on the inner wall of the first trench in the patterned stacked structure, and the second conductive layers located between two adjacent first insulating layers in the patterned stacked structure are connected together to form a ring. The first insulating layer is used to fill each of the first trenches and to fill the gaps between each of the second conductive layers; The first insulating layer and the second conductive layer on the inner wall of the first trench are removed by etching in a portion of the first trench near the second trench. The remaining second conductive layer is located in an annular shape between two adjacent first insulating layers. The second conductive layers located on opposite sides of the two adjacent first insulating layers serve as the first sub-electrode and the second sub-electrode, respectively. The first sub-electrode and the second sub-electrode are connected together to form a first annular body.

13. The manufacturing method according to claim 12, characterized in that, A dielectric layer and an outer electrode are sequentially deposited on two opposing surfaces of the first sub-electrode and the second sub-electrode, respectively, including: A dielectric layer and an external electrode are sequentially deposited on the inner and outer circumferential surfaces of the first annular body, such that the inner and outer circumferential surfaces of the first annular body are at least partially covered by the external electrode.

14. The manufacturing method according to any one of claims 11 to 13, characterized in that, This also includes performing the following process after patterning the stacked structure and before etching away a portion of the conductive portion away from the bit line: A second insulating layer is deposited on the inner wall of the first trench; The first trench is filled with the first insulating layer, and the second trench exposes the first insulating layer in the patterned stacked structure. Laterally etch the first insulating layer exposed in the patterned stacked structure in the second trench to expose the side of the first conductive layer at a certain depth in the patterned stacked structure. The second insulating layer is deposited on the inner wall of the second trench, and the first insulating layer is filled into the second trench; The first and second insulating layers in a portion of the first trench near the second trench are etched away, exposing the first conductive layer in the patterned stacked structure.

15. The manufacturing method according to claim 14, characterized in that, Depositing a second insulating layer on the inner wall of the first trench, and filling the first trench with the first insulating layer, and exposing the first insulating layer in the patterned stacked structure in the second trench, includes: A second insulating layer is deposited on the inner walls of the first trench and the second trench, and the first insulating layer is filled into the first trench and the second trench. Etching removes the first insulating layer within the second trench; Etching removes the second insulating layer on the inner wall of the second trench, exposing the first insulating layer in the patterned stacked structure; and / or, Etching removes a portion of the first and second insulating layers in the first trench near the second trench, exposing a first conductive layer in a patterned stacked structure in the first trench, including: The first insulating layer in a portion of the first trench near the second trench is etched away, exposing the second insulating layer on a portion of the inner wall of the first trench, and exposing the second insulating layer in the second trench near the bit line side; The second insulating layer exposed on the inner wall of the first trench and the second insulating layer exposed in the second trench are etched away, so that a portion of the sidewall of the first trench exposes the first conductive layer in a patterned stacked structure.

16. An electronic device, characterized in that, Includes the memory according to any one of claims 1 to 9.

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