Semiconductor device and method for manufacturing the same

Abstract

The present application relates to a semiconductor device and a method for preparing the same, comprising: a semiconductor material layer; a first groove, located in the semiconductor material layer, the side wall and the bottom wall of the first groove are connected by an arc angle, and the angle between the plane where the side wall is located and the plane where the bottom wall is located is an obtuse angle; a drain region, located in the semiconductor material layer outside the first groove, and its depth is less than the depth of the first groove; a well region, located in the semiconductor material layer below the bottom wall; a field oxide layer, extending on the bottom wall and the side wall between the well region and the drain region; a gate dielectric layer, connected to the field oxide layer, covering part of the well region; a field plate, located on the field oxide layer; a gate, located on the gate dielectric layer; a source region, located on the surface of the well region; and a current conduction path of the semiconductor device, including a first current conduction path located in the semiconductor material layer and extending adjacent to the bottom wall and a second current conduction path extending adjacent to the side wall. In this way, the device's on-resistance is reduced while the device's withstand voltage performance is guaranteed.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] The BCD (Bipolar-CMOS-DMOS) process is a monolithic integration process technology that can produce Bipolar, CMOS (Complementary Metal Oxide Semiconductor) and DMOS (Double-diffused Metal Oxide Semiconductor) devices on the same chip. The BCD process combines the advantages of the above three devices and has become the mainstream process technology for integrated circuits, achieving the requirements of low power consumption, high integration, high speed and high driving capability of the entire circuit, and has better reliability.

[0003] In addition to combining the high transconductance and strong load driving capability of bipolar devices, and the high integration and low power consumption of CMOS devices, the BCD process also combines the high voltage and high current driving capability of DMOS devices. DMOS devices usually occupy about half of the area in the chip. The BCD process can integrate a variety of DMOS power devices, such as lateral double-diffused MOSFET (LDMOS) devices, vertical double-diffused MOSFET (VDMOS) devices and trench DMOS devices. Among them, LDMOS high-voltage power devices are one of the core devices in product design. Therefore, how to optimize the structure and process of LDMOS devices to obtain higher withstand voltage has become an urgent problem to be solved. Summary of the invention

[0004] In view of this, an embodiment of the present application provides a semiconductor device and a method for manufacturing the same in order to solve at least one problem existing in the background technology.

[0005] In a first aspect, an embodiment of the present application provides a semiconductor device, including:

[0006] a semiconductor material layer;

[0007] A first groove is located in the semiconductor material layer, the first groove extends from the surface of the semiconductor material layer to the inside, the side wall and the bottom wall of the first groove are connected by an arc angle, and the angle between the plane where the side wall is located and the plane where the bottom wall is located is an obtuse angle;

[0008] a drain region, located in the semiconductor material layer at the periphery of the first trench, wherein the depth of the drain region is less than the depth of the first trench;

[0009] a well region located in the semiconductor material layer below the bottom wall of the first trench;

[0010] a field oxide layer, located in the first trench and extending on portions of the bottom wall and the side wall located between the well region and the drain region;

[0011] a gate dielectric layer connected to the field oxide layer and covering a portion of the well region;

[0012] A field plate, located on the field oxide layer;

[0013] A gate, located on the gate dielectric layer;

[0014] A source region located at a surface layer of a portion of the well region not covered by the gate dielectric layer;

[0015] The current conducting path of the semiconductor device includes a first current conducting path located in the semiconductor material layer and extending adjacent to the bottom wall, and a second current conducting path extending adjacent to the side wall.

[0016] In combination with the first aspect of the present application, in an optional implementation manner, the field oxide layer is formed by a shallow trench isolation structure.

[0017] In combination with the first aspect of the present application, in an optional embodiment, the angle between the plane where the side wall of the first groove is located and the plane where the bottom wall is located is in a range of 100 degrees to 110 degrees.

[0018] In combination with the first aspect of the present application, in an optional implementation, in a direction along the thickness of the semiconductor material layer, the depth of the first groove ranges from 280 nm to 300 nm.

[0019] In combination with the first aspect of the present application, in an optional embodiment, the angle between the inner surface of the field oxide layer and the plane where the bottom wall is located ranges from 135 degrees to 140 degrees, and the inner surface of the field oxide layer is the side surface of the field oxide layer away from the side wall.

[0020] In a second aspect, an embodiment of the present application provides a method for preparing a semiconductor device, the method comprising:

[0021] providing a semiconductor material layer;

[0022] forming a first trench, wherein the first trench is located in the semiconductor material layer, the first trench extends from the surface of the semiconductor material layer to the inside, the side wall and the bottom wall of the first trench are connected by an arc angle, and the angle between the plane where the side wall is located and the plane where the bottom wall is located is an obtuse angle;

[0023] Filling a field oxide layer material in the first trench;

[0024] Removing part of the field oxide layer material to form a field oxide layer, wherein the field oxide layer extends on the side wall and the bottom wall;

[0025] forming a well region, the well region being located in the semiconductor material layer below the bottom wall of the first trench;

[0026] forming a gate dielectric layer, wherein the gate dielectric layer is connected to the field oxide layer and covers a portion of the well region;

[0027] forming a field plate, wherein the field plate is located on the field oxide layer;

[0028] forming a gate, wherein the gate is located on the gate dielectric layer;

[0029] forming a drain region in the semiconductor material layer at the periphery of the first trench, wherein the depth of the drain region is less than the depth of the first trench;

[0030] forming a source region, wherein the source region is located at a surface layer of a portion of the well region that is not covered by the gate dielectric layer;

[0031] The current conducting path of the semiconductor device includes a first current conducting path located in the semiconductor material layer and extending adjacent to the bottom wall, and a second current conducting path extending adjacent to the side wall.

[0032] In conjunction with the second aspect of the present application, in an optional implementation manner, the filling of the first trench with a field oxide layer material; and removing a portion of the field oxide layer material to form a field oxide layer include:

[0033] Filling the first trench with an isolation material to form a shallow trench isolation structure;

[0034] A portion of the shallow trench isolation structure is removed to form the field oxide layer.

[0035] In conjunction with the second aspect of the present application, in an optional embodiment, the angle between the plane where the side wall of the first groove is located and the plane where the bottom wall is located is in a range of 100 degrees to 110 degrees.

[0036] In combination with the second aspect of the present application, in an optional implementation, along the thickness direction of the semiconductor material layer, the depth of the first groove ranges from 280 nm to 300 nm.

[0037] In combination with the second aspect of the present application, in an optional embodiment, the angle between the inner surface of the field oxide layer and the plane where the bottom wall is located ranges from 135 degrees to 140 degrees, and the inner surface of the field oxide layer is the side surface of the field oxide layer away from the side wall.

[0038] The semiconductor device and preparation method provided in the embodiment of the present application utilize a field plate located on the field oxide layer to achieve modulation of the device electric field, thereby improving the breakdown voltage. The source region is located in the semiconductor material layer at the bottom of the first trench, and the current conduction path of the source end, that is, the first current conduction path, is parallel to the bottom of the first trench, so that the current conduction path of the source end is straightened, the current conduction path is shortened, and the on-resistance of the device is reduced. The drain region is located in the semiconductor material layer at the periphery of the first trench, and the depth of the drain region is less than the depth of the first trench. From the thickness direction of the semiconductor material layer, there is a height difference between the drain region and the source region, so that the voltage-resistant path of the drain end is longitudinal, which ensures the voltage-resistant effect of the device and avoids adjusting the length of the voltage-resistant path from the lateral direction, which can save device area and is conducive to device miniaturization. The angle between the plane where the side wall is located and the plane where the bottom wall is located is an obtuse angle, and the side wall and the bottom wall of the first trench are connected by an arc angle. After conduction, the electron flow path is smoother, which effectively reduces current congestion and further reduces the on-resistance. Thus, a semiconductor device having low on-resistance and high withstand voltage is obtained.

[0039] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0041] Figure 1 A schematic diagram of a cross-sectional structure of a semiconductor device provided for related technology;

[0042] Figure 2 A schematic diagram of a cross-sectional structure of a semiconductor device provided for related technology;

[0043] Figure 3 A schematic cross-sectional structure diagram of a semiconductor device provided in an embodiment of the present application;

[0044] Figure 4A schematic diagram of a process for preparing a semiconductor device according to an embodiment of the present application;

[0045] Figures 5 to 15 A schematic diagram of the cross-sectional structure of a semiconductor device during the preparation process provided in an embodiment of the present application.

[0046] Description of reference numerals:

[0047] 100, semiconductor material layer; 110, substrate; 120, buried layer; 130, epitaxial layer; 210, well region; 220, drift region; 230, source region; 240, well region contact region; 250, drain region; 300, shallow trench isolation structure; 301, field oxide layer material; 310, first trench; 311, bottom wall; 312, side wall; 320, second trench; 330, device isolation structure; 340, field oxide layer ; 341, inner surface; 350, gate dielectric layer; 400, gate structure; 401, gate; 402, field plate; 410, gate sidewall; 500, crystallization layer; 600, dielectric layer; 610, source region contact hole; 620, drain region contact hole; 630, well region contact hole; 710, source region contact plug; 720, drain region contact plug; 730, well region contact plug; 800, metal layer. DETAILED DESCRIPTION

[0048] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art.

[0049] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0050] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0051] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0052] Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0053] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0054] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0055] In the related art, in order to increase the breakdown voltage of the LDMOS device, a field plate (electric field control plate) is usually manufactured on the oxide layer (field oxide layer) above the drain liner PN junction termination region. The field plate can effectively suppress the surface electric field and prevent surface breakdown, thereby increasing the drain breakdown voltage of the transistor in the device.

[0056] Here, the field plate can effectively suppress the surface electric field because a structure similar to a MOS (Metal Oxide Semiconductor) capacitor is formed at the field plate. A part of the electric field lines starts from the source region, extends and terminates at the field plate, and adds additional charge to the surface of the PN junction. The direction of the additional electric field is opposite to the previous electric field direction, which weakens the electric field peak at the PN junction and divides part of the high voltage in the drain region, thereby reducing the avalanche breakdown voltage on the silicon surface of the device, increasing the drain breakdown voltage, and effectively improving the voltage resistance of the device.

[0057] Specifically, please refer to Figure 1 , the LDMOS device includes: a semiconductor material layer 100; a well region 210 and a drift region 220, which are located in the semiconductor material layer 100 and are adjacent to each other; a source region 230 and a drain region 250, which are respectively located in the well region 210 and the drift region 220; a shallow trench isolation structure 300, which is located in the drift region 220 between the source region 230 and the drain region 250; and a gate structure 400, which covers a portion of the top surface of the well region 210 and extends to a portion of the top surface of the shallow trench isolation structure 300. The shallow trench isolation (STI) structure 300 is used as a field oxide layer, and the gate structure 400 extending to a portion of the STI is used as a field plate to increase the breakdown voltage.

[0058] However, when turned on, the current flows along the STI edge, and the current conduction path ( Figure 1 The path shown by the arrow in the figure is long, the device on-resistance is large, and the field oxide layer is too thick, so the electric field regulation effect is not obvious. Based on this, an LDMOS device is proposed in the art, please refer to Figure 2, the LDMOS device includes: a semiconductor material layer 100; a well region 210 and a drift region 220, which are located in the semiconductor material layer 100 and are adjacent to each other; a source region 230 and a drain region 250, which are located in the well region 210 and the drift region 220 respectively; a field oxide layer 340, which is located on the top surface of the drift region 220 between the source region 230 and the drain region 250; and a gate structure 400, which covers a portion of the top surface of the well region 210 and extends to a portion of the top surface of the field oxide layer 340. In this device, the field oxide layer 340 is located on the surface of the semiconductor material layer 100, and the gate structure 400 extending to a portion of the field oxide layer 340 serves as a field plate, and the current conduction path ( Figure 2 The path shown by the arrow in the figure is basically straightened, the current conduction path is shortened, and the on-resistance loss can be reduced.

[0059] It can be understood that while the field plate weakens the electric field peak at the PN junction, the electric field peak at the edge of the field plate will be increased to a certain extent. Figure 2 As shown, the voltage-withstand path of the drain terminal is lateral, and the lateral distance between the end of the field plate and the drain region 250 determines the length of the voltage-withstand path. If the lateral distance between the end of the field plate and the drain region 250 is too short, the voltage-withstand path is too short, the voltage-withstand performance of the device is reduced, and avalanche breakdown is very likely to occur under high voltage. Therefore, in order to ensure that the voltage-withstand of the drain terminal is sufficient, it is necessary to ensure a safe distance between the end of the field plate and the drain region 250 to avoid breakdown. This can be achieved by reducing the length of the field plate, but it affects the electric field modulation effect; or by increasing the size of the device, but it is not conducive to device miniaturization.

[0060] Based on this, an embodiment of the present application provides a semiconductor device. Figure 3 This is a schematic diagram of the cross-sectional structure of a semiconductor device provided in an embodiment of the present application. Please refer to Figure 3 , semiconductor devices include:

[0061] Semiconductor material layer 100;

[0062] A first trench 310 is located in the semiconductor material layer 100. The first trench 310 extends from the surface of the semiconductor material layer 100 to the inside. The sidewall 312 and the bottom wall 311 of the first trench 310 are connected by an arc angle. The angle between the plane where the sidewall 312 is located and the plane where the bottom wall 311 is located is an obtuse angle.

[0063] The drain region 250 is located in the semiconductor material layer 100 at the periphery of the first trench 310 , and the depth of the drain region 250 is less than the depth of the first trench 310 ;

[0064] The well region 210 is located in the semiconductor material layer 100 below the bottom wall 311 of the first trench 310;

[0065] A field oxide layer 340 is located in the first trench 310 and extends on a portion of the bottom wall 311 and the side wall 312 located between the well region 210 and the drain region 250 ;

[0066] A gate dielectric layer 350 connected to the field oxide layer 340 and covering a portion of the well region 210;

[0067] A field plate 402 , located on the field oxide layer 340 ;

[0068] The gate 401 is located on the gate dielectric layer 350;

[0069] The source region 230 is located at the surface of the portion of the well region 210 that is not covered by the gate dielectric layer 350 ;

[0070] The current conducting path of the semiconductor device includes a first current conducting path located in the semiconductor material layer 100 and extending adjacent to the bottom wall 311 , and a second current conducting path extending adjacent to the side wall 312 .

[0071] It can be understood that the embodiment of the present application realizes modulation of the device electric field through the field plate 402 located on the field oxide layer 340, thereby improving the breakdown voltage, and the source region 230 is located in the semiconductor material layer 100 at the bottom of the first trench 310, and the current conduction path of the source end, that is, the first current conduction path is parallel to the bottom of the first trench 310, so that the current conduction path of the source end is straightened, the current conduction path is shortened, and the on-resistance of the device is reduced; the drain region 250 is located in the semiconductor material layer 100 at the periphery of the first trench 310, and the depth of the drain region 250 is less than the depth of the first trench 310. From the thickness direction of the semiconductor material layer 100, there is a height difference between the drain region 250 and the source region 230, so that the voltage-resistant path of the drain end is vertical, which ensures the voltage-resistant effect of the device and avoids adjusting the length of the voltage-resistant path from the horizontal direction, which can save device area and is conducive to device miniaturization. Thus, a semiconductor device with low on-resistance and high withstand voltage is obtained; the angle between the plane where the side wall 312 is located and the plane where the bottom wall 311 is located is an obtuse angle, and the side wall 312 and the bottom wall 311 are connected by an arc angle. After conduction, the electron flow path is smoother, effectively reducing current congestion and further reducing the on-resistance.

[0072] In some embodiments, please refer to Figure 2 The semiconductor material layer 100 may include a substrate 110 and a buried layer 120 and an epitaxial layer 130 formed on the substrate 110. The buried layer 120 and the epitaxial layer 130 are sequentially stacked from bottom to top on the substrate 110. The semiconductor material layer 100 may also be referred to as a "wafer".

[0073] The material of the substrate 110 may be a single-element semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), or a III-V compound semiconductor material (e.g., a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), or a II-VI compound semiconductor material, or an organic semiconductor material, or other semiconductor materials known in the art. In the embodiment of the present application, the substrate 110 may be a silicon substrate.

[0074] In some specific embodiments, please refer to Figure 2 , the buried layer 120 can be a first conductivity type buried layer, and the epitaxial layer 130 can be a second conductivity type epitaxial layer. It should be noted that the first conductivity type is P type and the second conductivity type is N type; or the first conductivity type is N type and the second conductivity type is P type. Specifically, the N type impurity ions include phosphorus ions, arsenic ions, and antimony ions, and the P type impurity ions include boron ions, gallium ions, and indium ions. The buried layer 120 and the epitaxial layer 130 have opposite conductivity types, and the buried layer 120 and the epitaxial layer 130 can be adjusted according to the actual device formed.

[0075] In actual preparation, the buried layer 120 may be formed by implanting ions of the first conductivity type into the top surface layer of the substrate 110. The epitaxial layer 130 may be formed by an epitaxial growth process or other suitable methods.

[0076] The semiconductor material layer 100 includes a drift region 220. Please refer to Figure 3 In the present embodiment, the drift region 220 is located in the epitaxial layer 130 , and the well region 210 , the source region 230 , the drain region 250 , the first trench 310 , and the field oxide layer 340 are all located in the drift region 220 .

[0077] It can be understood that the conductivity type of the epitaxial layer 130 is the same as the conductivity type of the drift region 220. The drift region 220 and the buried layer 120 located at the bottom of the drift region 220 have opposite conductivity types, which is beneficial to increase the impurity concentration at the bottom of the drift region 220, thereby improving the electric field distribution at the bottom of the drift region 220 and increasing the breakdown voltage of the device.

[0078] In some embodiments, please refer to Figure 2 A well region contact region 240 is also formed in the well region 210 . The well region contact region 240 is adjacent to the source region 230 , and the well region contact region 240 is located on a side of the source region 230 away from the drain region 250 .

[0079] The well region 210 may also be referred to as a “body region” or a “channel region”, and the well region contact region 240 may be referred to as a “channel lead-out implant region”.

[0080] In actual preparation, the well region 210, the source region 230, the drain region 250 and other ion implantation regions can all be formed by ion implantation. The well region 210 can also be formed by implantation in a self-aligned manner.

[0081] In some specific embodiments, the drift region 220 , the source region 230 , and the drain region 250 may have the same conductivity type; the well region 210 and the well region contact region 240 may have the same conductivity type; and the drift region 220 and the well region 210 may have different conductivity types.

[0082] Specifically, the epitaxial layer 130 may be an N-type epitaxial layer, the drift region is an N drift region (N well), and the source region 230 may be an N + Source region (N + source), the drain region 250 may be N + Drain region (N + drain); the well region 210 may be P - Well region (P - well), the well contact region 240 may be P + Well contact area (P + to P - Here, the drift region 220 may be a lightly doped region, which is beneficial to improving the withstand voltage level of the device; the source region 230 and the drain region 250 may be heavily doped regions, which is beneficial to reducing the contact resistance.

[0083] Please refer to Figure 3 , the drain region 250 is located in the semiconductor material layer 100 at the periphery of the first trench 310, and the depth of the drain region 250 is less than the depth of the first trench 310. As shown in the figure, when the depth of the drain region 250 is less than the depth of the first trench 310, there is a height difference between the drain region 250 and the source region 230, so that the voltage-withstanding path of the drain end is longitudinal (such as Figure 3 In some other embodiments, the length of the voltage-resistant path can be adjusted by adjusting the difference between the depth of the drain region 250 and the depth of the first trench 310, so as to avoid adjusting the length of the voltage-resistant path in the lateral direction, which can save device area and facilitate device miniaturization.

[0084] The sidewall 312 of the first trench 310 is tilted, and the angle between the plane where the sidewall 312 is located and the plane where the bottom wall 311 is located is an obtuse angle. The voltage-resistant path of the device drain terminal extends along the sidewall 312 of the first trench 310. The sidewall 312 is tilted, which can increase the length of the voltage-resistant path and ensure the voltage-resistant performance of the drain terminal; and the angle between the plane where the sidewall 312 is located and the plane where the bottom wall 311 is located is an obtuse angle, so the flow path of electrons from the source region 230 to the drain region 250 is smoother, and the current conduction path is shortened, which is conducive to reducing the on-resistance of the device.

[0085] Optionally, the angle between the plane where the sidewall 312 of the first trench is located and the plane where the bottom wall 311 is located is in the range of 100 degrees to 110 degrees. Thus, within this range, the withstand voltage performance of the device can be better improved and the on-resistance of the device can be reduced.

[0086] The side wall 312 and the bottom wall 311 of the first groove 310 are connected by a rounded corner. Figure 1 In the related art, the shallow trench isolation structure 300 has a sharp corner. After conduction, the current conduction path corresponding to this corner is narrow, and electrons are easily congested at this corner when flowing, which causes the electric field to concentrate, resulting in a large current effect and increasing the risk of leakage. In this embodiment, the angle between the side wall 312 of the first trench 310 and the bottom wall 311 of the first trench 310 is set to a rounded angle, so that after conduction, the electron flow path is smoother (such as Figure 3 As shown by the arrow in the middle, the current conduction path is widened, which can reduce current congestion and mitigate the high current effect, thereby increasing the safe operating area; it can also reduce the peak electric field, which is beneficial to increasing the breakdown voltage and improving the hot carrier effect.

[0087] Optionally, in the direction along the thickness of the semiconductor material layer 100, the depth of the first trench 310 ranges from 280nm to 300nm. Thus, by reducing the depth of the first trench 310, the current conduction path is shortened, which is conducive to reducing the on-resistance of the device. It can be understood that if the depth of the first trench 310 is too short, the length of the drain withstand voltage path may be too short, and the drain end cannot be guaranteed to have sufficient withstand voltage, affecting the breakdown voltage of the device; if the depth of the first trench 310 is too large, the length of the current conduction path may be too long, affecting the on-resistance of the device. It should be noted that for LDMOS devices, the trade-off between breakdown voltage and on-resistance is the most important. Simply sacrificing on-resistance to obtain higher withstand voltage will limit the development of high density, high power and high withstand voltage of LDMOS devices to a certain extent, and limit the application and performance of LDMOS devices. Therefore, within this range, the breakdown voltage and on-resistance can be better balanced to obtain a device with low on-resistance and high withstand voltage.

[0088] Optionally, refer to Figure 3 , the angle between the inner surface 341 of the field oxide layer 340 and the plane where the bottom wall 311 is located is an obtuse angle, and the inner surface 341 of the field oxide layer 340 is the side surface of the field oxide layer 340 away from the side wall 312. As a result, the thickness of the part of the field oxide layer 340 close to the source region 230 is less than the thickness of the part of the field oxide layer 340 close to the drain region 250. The closer to the drain region 250, the thicker the field oxide layer 340, and the stronger the withstand voltage; the closer to the source region 230, the thinner the field oxide, and the stronger the electric field regulation effect. Under the action of electric field modulation, the charge distribution on the surface of the semiconductor material layer 100 will change. With the enhancement of the electric field regulation effect, when the gate voltage is lower than the flat band voltage, positive charges are induced, so that the hole concentration near the interface between the field oxide layer 340 and the semiconductor material layer 100 is greater than the hole concentration inside the semiconductor material layer 100, forming an accumulation area, which can provide more conductive channels, thereby helping to reduce the on-resistance.

[0089] Please refer to Figure 2 In the related art, two parts of field oxide layer 340 with different thicknesses are prepared on the surface of semiconductor material layer 100 to achieve that the thickness of the part of field oxide layer 340 close to source region 230 is smaller than the thickness of the part of field oxide layer 340 close to drain region 250. However, the thickness of field oxide layer 340 is limited by the process. Too large thickness will lead to insufficient window of processes such as photolithography, and preparing field oxide with different thicknesses increases the complexity and cost of the process. In this embodiment, field oxide layer 340 is formed in the first trench 310 extending into the inside of semiconductor material layer 100, and the angle between the inner surface 341 of field oxide layer 340 and the plane where bottom wall 311 is located is an obtuse angle, which is compatible with the traditional shallow trench isolation process, reduces the process difficulty, and is conducive to device miniaturization.

[0090] Furthermore, the angle between the inner surface 341 of the field oxide layer 340 and the plane where the bottom wall 311 is located ranges from 135 degrees to 140 degrees.

[0091] Optionally, the field oxide layer 340 is formed by a shallow trench isolation structure, which can be adapted to a conventional shallow trench isolation process in the manufacturing process.

[0092] In this embodiment, the material of the field oxide layer 340 may be silicon oxide.

[0093] The gate dielectric layer 350 is connected to the field oxide layer 340 and covers a portion of the well region 210. In this embodiment, the material of the gate dielectric layer 350 can be the same as that of the field oxide layer 340.

[0094] In some other embodiments, the field plate 402 is made of the same material as the gate 401. In an actual manufacturing process, the field plate 402 and the gate 401 can be manufactured in the same process.

[0095] In some other embodiments, the device includes a gate structure 400 , wherein the portion located on the field oxide layer 340 is a field plate 402 , and the portion extending onto the gate dielectric layer 350 is a gate 401 .

[0096] Gate spacers 410 are formed on two sidewalls of the gate structure 400 .

[0097] Specifically, the materials of the field plate 402 and the gate 401 include but are not limited to polysilicon or metal materials; the materials of the gate dielectric layer 350 include but are not limited to oxides; the materials of the gate sidewall 410 include but are not limited to silicon oxide and silicon oxynitride.

[0098] Optionally, refer to Figure 3 The semiconductor device further includes a crystallization layer 500, which covers the top surface of the source region 230, the drain region 250, the well region contact region 240, the field plate 402, and the gate 401. The material of the crystallization layer 500 includes but is not limited to metal silicide. The crystallization layer 500 can reduce the contact resistance between the source region 230, the drain region 250, the well region contact region 240, the gate structure 400 and other conductive structures.

[0099] Optionally, refer to Figure 3 The semiconductor device further includes: a dielectric layer 600 covering the semiconductor material layer 100 .

[0100] The material of the dielectric layer 600 may be any suitable insulating dielectric material, thereby being able to insulate and isolate the devices, which is not limited in this embodiment.

[0101] In some specific embodiments, please refer to Figure 3 The semiconductor device further includes: a well region contact plug 730 , a source region contact plug 710 , a drain region contact plug 720 and a gate contact plug (not shown in the figure). The above contact plugs all penetrate the dielectric layer 600 and are located on the crystallized layer 500 .

[0102] Specifically, the well region contact plug 730, the source region contact plug 710, the drain region contact plug 720 and the gate contact plug (not shown in the figure) are electrically connected to the well region contact region 240, the source region 230, the drain region 250 and the gate structure 400 respectively. The materials of the well region contact plug 730, the source region contact plug 710, the drain region contact plug 720 and the gate contact plug (not shown in the figure) can be the same or different. Specifically, the material of the above-mentioned contact plugs can be metal, such as tungsten, titanium, aluminum or copper, etc.

[0103] It should be noted that the source region contact plug 710 may also be referred to as a “source contact hole”, and the drain region contact plug 720 may also be referred to as a “drain contact hole”.

[0104] Optionally, in a direction perpendicular to the thickness of the semiconductor material layer 100, the size of the source region contact plug 710 ranges from 0.22 μm to 0.23 μm. It can be understood that the source region 230 is located in the semiconductor material layer 100 at the bottom of the first trench 310, and a field oxide layer 340 and a gate structure 400 are also formed in the first trench 310. After forming the dielectric layer 600, it is necessary to first etch out a source terminal contact through hole to form a source region contact plug 710 in the through hole. During the etching process, when the overlay is poor, the source region 230 may not be accurately positioned, so that the formed source region contact plug 710 is poorly connected, and then the voltage cannot be input or output to the source terminal. Therefore, increasing the size of the source region contact plug 710 can reduce the process difficulty and improve the conductive connection.

[0105] In some specific embodiments, please refer to Figure 3 The semiconductor device further includes: a device isolation structure 330 extending from the top surface of the epitaxial layer 130 into the epitaxial layer 130 and located on a side of the drain region 250 away from the source region 230 .

[0106] Here, the device isolation structure 330 may be a shallow trench isolation structure for isolating a plurality of LDMOS devices.

[0107] Please refer to Figure 3 The semiconductor device further includes: a metal layer 800 conductively connected to the isolation plug.

[0108] Based on this, an embodiment of the present application further provides a method for preparing a semiconductor device. Figure 4 This is a flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application. Please refer to Figure 4 , a method for preparing a semiconductor device comprises:

[0109] Step S101: providing a semiconductor material layer;

[0110] Step S102: forming a first trench, the first trench being located in the semiconductor material layer, the first trench extending from the surface of the semiconductor material layer to the inside, the sidewall and the bottom wall of the first trench being connected by an arc angle, and the angle between the plane where the sidewall is located and the plane where the bottom wall is located is an obtuse angle;

[0111] Step S103: filling a field oxide layer material in the first trench;

[0112] Step S104: removing part of the field oxide layer material to form a field oxide layer, wherein the field oxide layer extends on the side wall and the bottom wall;

[0113] Step S105: forming a well region, the well region being located in the semiconductor material layer below the bottom wall of the first trench;

[0114] Step S106: forming a gate dielectric layer, wherein the gate dielectric layer is connected to the field oxide layer and covers a portion of the well region;

[0115] Step S107: forming a field plate, where the field plate is located on the field oxide layer;

[0116] Step S108: forming a gate, where the gate is located on the gate dielectric layer;

[0117] Step S109: forming a drain region in the semiconductor material layer around the first trench, wherein the depth of the drain region is less than the depth of the first trench;

[0118] Step S110: forming a source region, where the source region is located on the surface of the portion of the well region not covered by the gate dielectric layer.

[0119] The current conducting path of the semiconductor device includes a first current conducting path located in the semiconductor material layer and extending adjacent to the bottom wall, and a second current conducting path extending adjacent to the side wall. It can be understood that the present embodiment utilizes the field plate located on the surface of the field oxide layer to achieve modulation of the device electric field, thereby increasing the breakdown voltage, and forming a source region in the semiconductor material layer at the bottom of the first trench, and the current conduction path of the source end, that is, the first current conduction path is parallel to the bottom of the first trench, so that the current conduction path of the source end is straightened, the current conduction path is shortened, and the on-resistance of the device is reduced; the drain region is in the semiconductor material layer at the periphery of the first trench, and the depth of the drain region is less than the depth of the first trench. From the thickness direction of the semiconductor material layer, there is a height difference between the drain region and the source region, so that the withstand voltage path of the drain end is longitudinal, which ensures the withstand voltage effect of the device, and avoids adjusting the length of the withstand voltage path from the lateral direction, which can save the device area and is conducive to the miniaturization of the device; the angle between the plane where the side wall is located and the plane where the bottom wall is located is an obtuse angle, and the side wall and the bottom wall of the first trench are connected by an arc angle. After conduction, the electron flow path is smoother, which effectively reduces current congestion and further reduces the on-resistance. Thus, a semiconductor device with low on-resistance and high withstand voltage is obtained.

[0120] Please refer to Figure 5 , perform step S101: provide a semiconductor material layer 100.

[0121] Specifically, providing the semiconductor material layer 100 may include: providing a substrate 110 ; forming a buried layer 120 on the substrate 110 ; and epitaxially growing an epitaxial layer 130 on the buried layer 120 .

[0122] Please refer to Figure 4, step S102 is performed: forming a first trench 310, the first trench 310 is located in the semiconductor material layer 100, the first trench 310 extends from the surface of the semiconductor material layer 100 to the inside, the side wall 312 and the bottom wall 311 of the first trench 310 are connected by an arc angle, and the angle between the plane where the side wall 312 is located and the plane where the bottom wall 311 is located is an obtuse angle. Therefore, it is beneficial to improve the breakdown voltage of the device and reduce the on-resistance of the device.

[0123] In this embodiment, the first trench 310 may be formed by photolithography and etching processes.

[0124] Optionally, the angle between the plane where the side wall 312 of the first groove is located and the plane where the bottom wall 311 is located is in a range of 100 degrees to 110 degrees.

[0125] Optionally, the depth of the first trench 310 is in the range of 280 nm to 300 nm along the thickness direction of the semiconductor material layer 100. Within this range, the breakdown voltage and the on-resistance can be better balanced to obtain a device with low on-resistance and high withstand voltage.

[0126] Optionally, the preparation method further includes: forming a second trench 320 in the semiconductor material layer 100 at the periphery of the first trench 310 , wherein the second trench 320 extends from the surface of the semiconductor material layer 100 toward the inside.

[0127] Please refer to Figure 6 , step S103 is performed: filling the first trench 310 with a field oxide layer material 301. In this embodiment, the field oxide layer material 301 may be made of silicon oxide.

[0128] Optionally, filling the first trench 310 with a field oxide layer material 301 includes: filling the first trench 310 with an isolation material to form a shallow trench isolation structure. In subsequent processes, a field oxide layer may be formed by removing part of the shallow trench isolation structure, which is compatible with a conventional shallow trench isolation process and reduces process difficulty.

[0129] In some specific embodiments, a field oxide layer material 301 is filled in the first trench 310; wherein the angle between the plane where the sidewall 312 of the first trench is located and the plane where the bottom wall 311 is located is in the range of 100 degrees to 110 degrees; the sidewall 312 and the bottom wall 311 of the first trench 310 are connected by an arc angle; along the thickness direction of the semiconductor material layer 100, the depth of the first trench 310 is in the range of 280nm to 300nm. Thus, mini-STI is formed. Compared with conventional STI, mini-STI has a smaller depth, a rounded corner, and a sidewall inclination angle between 70 degrees and 80 degrees, which reduces the process difficulty.

[0130] Optionally, the preparation method further includes: forming a device isolation structure 330 in the second trench 320. In this embodiment, the field oxide layer material 301 is made of the same material as the device isolation structure 330, and the field oxide layer material 301 and the device isolation structure 330 can be formed in the same process.

[0131] Please refer to Figure 7 , step S104 is performed: removing part of the field oxide layer material 301 to form a field oxide layer 340, and the field oxide layer 340 extends on the sidewall 312 and the bottom wall 311. Thus, the field oxide layer 340 is formed by removing the field oxide layer material 301 in the first trench 310, which reduces the process difficulty.

[0132] In this embodiment, part of the field oxide layer material 301 may be removed by photolithography and etching processes.

[0133] Optionally, the angle between the inner surface 341 of the field oxide layer 340 and the plane where the bottom wall 311 is located is an obtuse angle, and the inner surface 341 of the field oxide layer 340 is the side surface of the field oxide layer 340 away from the side wall 312. Thus, the closer to the drain region 250, the thicker the field oxide layer 340 is, and the stronger the withstand voltage is; the closer to the source region 230, the thinner the field oxide is, the stronger the electric field regulation effect is, and the accumulation region is formed, which can provide more conductive channels, thereby facilitating the reduction of on-resistance.

[0134] Furthermore, the angle between the inner surface 341 of the field oxide layer 340 and the plane where the bottom wall 311 is located ranges from 135 degrees to 140 degrees.

[0135] Please refer to Figure 8 , executing step S105 : forming a well region 210 , where the well region 210 is located in the semiconductor material layer 100 below the bottom wall 311 of the first trench 310 .

[0136] Specifically, the well region 210 may be formed by photolithography and ion implantation processes.

[0137] Next, please refer to Fig. 9 , step S106 : forming a gate dielectric layer 350 , the gate dielectric layer 350 is connected to the field oxide layer 340 , and covers a portion of the well region 210 .

[0138] The material of the gate dielectric layer 350 includes, but is not limited to, oxide.

[0139] Please refer to Fig.10 , step S107 is performed: forming a field plate 402 , the field plate 402 being located on the field oxide layer 340 . Thus, electric field regulation is achieved through the field plate 402 .

[0140] Continue to refer Fig.10, executing step S108 : forming a gate 401 , where the gate 401 is located on the gate dielectric layer 350 .

[0141] In some other embodiments, the field plate 402 is made of the same material as the gate 401. In an actual manufacturing process, the field plate 402 and the gate 401 can be manufactured in the same process.

[0142] In some other embodiments, the device includes a gate structure 400 , wherein the portion located on the field oxide layer 340 is a field plate 402 , and the portion extending onto the gate dielectric layer 350 is a gate 401 .

[0143] The materials of the field plate 402 and the gate 401 include but are not limited to polysilicon or metal materials.

[0144] Optionally, the preparation method further includes: forming gate spacers 410 on two sidewalls of the gate structure 400 .

[0145] The material of the gate spacer 410 includes but is not limited to silicon oxide and silicon oxynitride.

[0146] Please refer to Fig.11 , executing step S109 : forming a drain region 250 in the semiconductor material layer 100 at the periphery of the first trench 310 , wherein the depth of the drain region 250 is less than the depth of the first trench 310 .

[0147] It can be understood that, as shown in the figure, when the depth of the drain region 250 is less than the depth of the first trench 310, there is a height difference between the drain region 250 and the source region 230, so that the voltage-withstanding path of the drain end is vertical (such as Figure 3 In other embodiments, the length of the voltage-resistant path can be adjusted by adjusting the difference between the depth of the drain region 250 and the depth of the first trench 310, so as to avoid adjusting the length of the voltage-resistant path from the lateral direction, which can save device area and facilitate device miniaturization. It can be understood that in actual processes, the depth of the drain region 250 in the semiconductor material can be controlled according to different requirements for the breakdown voltage of the device.

[0148] Specifically, the drain region 250 may be formed by photolithography and ion implantation processes.

[0149] Please continue to refer to Fig.11 , executing step S110 : forming a source region 230 , where the source region 230 is located on a surface layer of a portion of the well region 210 that is not covered by the gate dielectric layer 350 .

[0150] Specifically, the source region 230 may be formed by photolithography and ion implantation processes.

[0151] In actual preparation, the drain region 250 and the source region 230 can be prepared in the same process.

[0152] It can be understood that after being turned on, electrons flow from the source region 230 to the drain region 250, and the current conduction path at the source end, that is, the first current conduction path, is parallel to the bottom of the first trench 310 (eg Figure 3 As shown by the arrow in the middle, it is close to a straight line, the current conduction path is shortened, and the on-resistance of the device is reduced.

[0153] Optionally, the preparation method also includes: forming a well region contact region 240 in the surface layer of the portion of the well region 210 not covered by the gate dielectric layer 350 , the well region contact region 240 being adjacent to the source region 230 , and the well region contact region 240 being located on the side of the source region 230 away from the drain region 250 .

[0154] It can be understood that the source region 230 and the well contact region 240 can be formed in the same process.

[0155] Please refer to Fig.12 The preparation method further includes: forming a crystallization layer 500 , wherein the crystallization layer 500 covers the top surfaces of the source region 230 , the drain region 250 , the field plate 402 and the gate 401 .

[0156] The material of the crystallization layer 500 includes but is not limited to metal silicide. The crystallization layer 500 can reduce the contact resistance between the source region 230, the drain region 250, the field plate 402, the gate 401 and other conductive structures.

[0157] Optionally, the crystallization layer 500 also covers the top surface of the well region contact region.

[0158] Next reference Fig.13 The preparation method further includes: forming a dielectric layer 600 , wherein the dielectric layer 600 covers the semiconductor material layer 100 .

[0159] The material of the dielectric layer 600 may be any suitable insulating dielectric material, which is not limited in this embodiment.

[0160] Please refer to Fig.14 The preparation method also includes: forming a source region contact through hole 610, a drain region contact through hole 620 and a gate contact through hole (not shown in the figure); wherein the source region contact through hole 610 penetrates the dielectric layer 600 and exposes a portion of the crystallized layer 500, the drain region contact through hole 620 penetrates the dielectric layer 600 and exposes a portion of the crystallized layer 500, and the gate contact through hole penetrates the dielectric layer 600 and exposes a portion of the crystallized layer 500.

[0161] Optionally, in a direction perpendicular to the thickness of the semiconductor material layer 100, the size of the source region contact through hole 610 ranges from 0.22 μm to 0.23 μm. Thus, in order to avoid the possibility that the source region 230 may not be accurately positioned when overlay is poor, resulting in poor connection of the formed source region contact plug, the process difficulty can be reduced and the conductive connection can be improved by increasing the size of the source region contact through hole 610.

[0162] Continue to refer Fig.14 The preparation method further includes: forming a well region contact through hole 630 , wherein the well region contact through hole 630 penetrates the dielectric layer 600 and exposes a portion of the crystallized layer 500 .

[0163] Next, please refer to Fig.15 The preparation method further includes: forming a source region contact plug 710 in the source region contact through hole 610; forming a drain region contact plug 720 in the drain region contact through hole 620; and forming a gate contact plug (not shown in the figure) in the gate contact through hole. Thus, conductive connection is achieved.

[0164] The manufacturing method further includes: forming a well region contact plug 730 in the well region contact through hole 630 .

[0165] Please refer to Figure 3 The preparation method further includes: forming a metal layer 800 on the contact plug.

[0166] It should be noted that the semiconductor device embodiment provided in the present application and the semiconductor device preparation method embodiment belong to the same concept; the technical features in the technical solutions recorded in the embodiments can be arbitrarily combined without conflict. However, it should be further noted that the semiconductor device provided in the embodiment of the present application, the combination of its various technical features can already solve the technical problem to be solved by the present application; therefore, the semiconductor device provided in the embodiment of the present application may not be limited by the semiconductor device preparation method provided in the embodiment of the present application, and any semiconductor device prepared by the preparation method that can form the semiconductor device structure provided in the embodiment of the present application is within the scope of protection of the present application.

[0167] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations included in the claims. Various modifications and changes may be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may be arbitrarily combined to form other embodiments of the present application that may not be explicitly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.

Claims

1. A semiconductor device, characterized in that: include: a semiconductor material layer; A first trench is located in the semiconductor material layer, the first trench extends from the surface of the semiconductor material layer to the inside, the sidewall and the bottom wall of the first trench are connected by an arc angle, the angle between the plane where the sidewall is located and the plane where the bottom wall is located is an obtuse angle and ranges from 100 degrees to 110 degrees; in the direction along the thickness of the semiconductor material layer, the depth of the first trench ranges from 280nm to 300nm, and the first trench is used to form a mini-STI shallow trench isolation structure; a drain region, located in the semiconductor material layer at the periphery of the first trench, wherein the depth of the drain region is less than the depth of the first trench; a well region located in the semiconductor material layer below the bottom wall of the first trench; a field oxide layer, located in the first trench and extending on portions of the bottom wall and the side wall located between the well region and the drain region, the field oxide layer being formed by the mini-STI, the angle between the inner surface of the field oxide layer and the plane where the bottom wall is located being an obtuse angle, the inner surface of the field oxide layer being the side surface of the field oxide layer away from the side wall, and the thickness of a portion of the field oxide layer close to the source region being less than the thickness of a portion of the field oxide layer close to the drain region; a gate dielectric layer connected to the field oxide layer and covering a portion of the well region; A field plate, located on the field oxide layer; A gate, located on the gate dielectric layer; A source region located at a surface layer of a portion of the well region not covered by the gate dielectric layer; The current conducting path of the semiconductor device includes a first current conducting path located in the semiconductor material layer and extending adjacent to the bottom wall, and a second current conducting path extending adjacent to the side wall.

2. The semiconductor device according to claim 1, wherein: The angle between the inner surface of the field oxide layer and the plane where the bottom wall is located is in a range of 135 degrees to 140 degrees.

3. A method for preparing a semiconductor device, characterized in that: The preparation method comprises: providing a semiconductor material layer; forming a first trench, the first trench being located in the semiconductor material layer, the first trench extending from the surface of the semiconductor material layer to the inside, the sidewall and the bottom wall of the first trench being connected by an arc angle, the angle between the plane where the sidewall is located and the plane where the bottom wall is located is an obtuse angle and ranges from 100 degrees to 110 degrees; in the thickness direction of the semiconductor material layer, the depth of the first trench ranges from 280 nm to 300 nm; Filling a field oxide layer material in the first trench to form a mini-STI shallow trench isolation structure; Removing part of the mini-STI to form a field oxide layer, wherein the field oxide layer extends on the side wall and the bottom wall, an angle between an inner surface of the field oxide layer and a plane where the bottom wall is located is an obtuse angle, the inner surface of the field oxide layer is a side surface of the field oxide layer away from the side wall, and a thickness of a portion of the field oxide layer close to the source region is less than a thickness of a portion of the field oxide layer close to the drain region; forming a well region, the well region being located in the semiconductor material layer below the bottom wall of the first trench; forming a gate dielectric layer, wherein the gate dielectric layer is connected to the field oxide layer and covers a portion of the well region; forming a field plate, wherein the field plate is located on the field oxide layer; forming a gate, wherein the gate is located on the gate dielectric layer; forming a drain region in the semiconductor material layer at the periphery of the first trench, wherein the depth of the drain region is less than the depth of the first trench; forming a source region, wherein the source region is located at a surface layer of a portion of the well region that is not covered by the gate dielectric layer; The current conducting path of the semiconductor device includes a first current conducting path located in the semiconductor material layer and extending adjacent to the bottom wall, and a second current conducting path extending adjacent to the side wall.

4. The method for preparing a semiconductor device according to claim 3, characterized in that: The angle between the inner surface of the field oxide layer and the plane where the bottom wall is located is in a range of 135 degrees to 140 degrees.

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