A hardware testing method, system, device and storage medium

Abstract

The application discloses a hardware testing method, system, device and storage medium, the method comprises the following steps: generating a corresponding subgraph sequence of a computation graph according to a model or algorithm to be tested; the computation graph is used for representing the data structure of the model or algorithm; the computation graph is composed of nodes and edges, the nodes represent the calculation steps of the model or algorithm, and the edges represent the logical relationship between the calculation steps; the subgraph execution sequence and the execution position are determined based on the calling sequence between the subgraph sequence; according to the subgraph execution sequence, the subgraph is input into the corresponding execution position of the hardware to perform calculation, and the hardware performance index is obtained. By automatically generating the subgraph sequence of the computation graph from the model or algorithm, and determining the execution sequence and the position, the efficiency and the accuracy of the hardware performance test are improved, the test result is more reliable, and the use of the hardware resources can be comprehensively evaluated and optimized.

Description

Technical Field

[0001] This invention relates to the field of computers, and more specifically to a hardware testing method, system, device, and storage medium. Background Technology

[0002] With the development of hardware technology, new generations of GPUs are constantly emerging, and they are widely used in various artificial intelligence software. These intelligent hardware devices, especially GPUs, are designed specifically for artificial intelligence algorithms, enabling AI software to achieve computational speeds relative to traditional CPUs. GPUs support deep neural network computations through various hardware units, but their performance and compatibility vary depending on different designs and compilers.

[0003] Assessing a GPU's support for AI software requires considering not only its computational speed and accuracy but also its collaboration with the compiler. Different GPU designs lead to variations in computational power and compatibility, directly impacting their adaptability to upper-level AI software. While GPUs excel at performing AI computational tasks, their performance is not isolated but rather collaborative with the CPU, allocating computational tasks based on the compiler's decisions.

[0004] Therefore, to comprehensively evaluate the computing power of a GPU, one cannot rely solely on the computation results, but needs to delve into the hardware level and consider the collaborative working mechanism between the GPU and the CPU, as well as the compiler's task allocation strategy. Summary of the Invention

[0005] The main objective of this invention is to provide a hardware testing method, system, device, and storage medium that automatically generates a sequence of subgraphs of a computation graph from a model or algorithm and determines the execution sequence and location. This not only improves the efficiency and accuracy of hardware performance testing but also makes the test results more reliable, which helps to comprehensively evaluate and optimize the use of hardware resources.

[0006] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0007] According to a first aspect of the embodiments of this application, a hardware testing method is provided, the method comprising:

[0008] Receive hardware test instructions, which carry the model or algorithm to be tested;

[0009] A sequence of subgraphs of the corresponding computation graph is generated based on the model or algorithm to be tested; the computation graph is used to represent the data structure of the model or algorithm; the computation graph consists of several nodes and edges, the nodes represent the computation steps of the model or algorithm, and the edges represent the logical relationships between the computation steps;

[0010] The execution sequence and execution location of the subgraph are determined based on the calling order among the subgraph sequences;

[0011] According to the subgraph execution sequence, the subgraph is input into the corresponding execution location of the hardware for calculation to obtain hardware performance indicators.

[0012] Optionally, a sequence of subgraphs of the corresponding computation graph is generated based on the model or algorithm to be tested, including:

[0013] The model or algorithm to be tested generates an initial computation graph based on the computation graph compiler;

[0014] The initial computation graph is divided into a sequence of subgraphs according to the partitioning rules. Each subgraph in the sequence represents a set of computational steps that can be computed in parallel.

[0015] Optionally, generating an initial computation graph based on a computation graph compiler for the model or algorithm to be tested includes:

[0016] A deep neural network is constructed based on the model or algorithm to be tested, and each network layer of the deep neural network is defined as a node in the computation graph; the weights and biases between network layers are defined as edges between nodes in the computation graph.

[0017] The computation graph compiler integrates all computational steps in a model or algorithm into an initial computation graph, which represents all computational steps in the model or algorithm.

[0018] Optionally, the execution sequence and execution location of the subgraph are determined based on the calling order among the subgraph sequences, including:

[0019] The data dependencies between subgraphs are determined based on the calling order among the subgraph sequences;

[0020] The execution sequence and execution location of the subgraph are determined based on the subgraph attributes and the data dependencies between the subgraphs; the attributes include subgraphs with no data dependencies and subgraphs that are executed only on the CPU, and the execution locations include CPU and / or GPU.

[0021] Optionally, the hardware performance metrics include computational graph coverage;

[0022] The step of calculating hardware performance metrics by inputting the subgraph into the corresponding execution location of the hardware according to the subgraph execution sequence includes:

[0023] According to the subgraph execution sequence, the subgraph is input into the corresponding execution location of the hardware for calculation to obtain the number of GPU subgraphs and / or CPU subgraphs;

[0024] The computation graph coverage is obtained based on the proportion of the number of GPU subgraphs and / or the number of CPU subgraphs in the subgraph sequence of the initial computation graph. The computation graph coverage includes GPU coverage and CPU coverage.

[0025] Optionally, the hardware performance metrics include the percentage of computation time.

[0026] The step of calculating hardware performance metrics by inputting the subgraph into the corresponding execution location of the hardware according to the subgraph execution sequence includes:

[0027] According to the subgraph execution sequence, the subgraph is input into the corresponding execution location of the hardware for calculation, and the calculation time of all subgraphs is recorded; the calculation time includes GPU calculation time and / or CPU calculation time.

[0028] The computation time percentage is obtained by taking the proportion of GPU computation time and / or CPU computation time of all subgraphs to the total computation time. The computation time percentage includes the proportion of GPU computation time and the proportion of CPU computation time. The total computation time is the total computation time of all subgraphs at the execution location of the hardware.

[0029] Optionally, the hardware performance metrics include computing speed;

[0030] The step of calculating hardware performance metrics by inputting the subgraph into the corresponding execution location of the hardware according to the subgraph execution sequence includes:

[0031] According to the subgraph execution sequence, the subgraph is input into the corresponding execution location of the hardware for calculation, and the calculation time of all subgraphs is recorded; the calculation time includes GPU calculation time and / or CPU calculation time.

[0032] The computational speed is obtained based on the computational workload of all subgraphs and the GPU computation time and / or CPU computation time of all subgraphs. The computational speed includes both GPU computational speed and CPU computational speed.

[0033] According to a second aspect of the embodiments of this application, a hardware testing system is provided, the system comprising:

[0034] The message receiving module is used to receive hardware test instructions, which carry the model or algorithm to be tested.

[0035] The subgraph generation module is used to generate a sequence of subgraphs of the corresponding computation graph based on the model or algorithm to be tested; the computation graph is used to represent the data structure of the model or algorithm; the computation graph consists of several nodes and edges, the nodes represent the computation steps of the model or algorithm, and the edges represent the logical relationships between the computation steps;

[0036] The execution order module is used to determine the execution sequence and execution position of a subgraph based on the calling order between subgraph sequences.

[0037] The indicator calculation module is used to calculate the hardware performance indicators by inputting the subgraph into the corresponding execution position of the hardware according to the subgraph execution sequence.

[0038] According to a third aspect of the present application, an electronic device is provided, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method described in the first aspect above.

[0039] According to a fourth aspect of the embodiments of this application, a computer-readable storage medium is provided having computer-readable instructions stored thereon, the computer-readable instructions being executable by a processor to implement the method described in the first aspect above.

[0040] In summary, this application provides a hardware testing method, system, device, and storage medium. It receives hardware testing instructions carrying a model or algorithm to be tested; generates a subgraph sequence of a corresponding computation graph based on the model or algorithm; the computation graph represents the data structure of the model or algorithm; the computation graph consists of several nodes and edges, where nodes represent computation steps of the model or algorithm, and edges represent logical relationships between computation steps; the execution sequence and execution position of the subgraph are determined based on the calling order between the subgraph sequences; and the subgraph is input into the corresponding execution position of the hardware according to the subgraph execution sequence for calculation to obtain hardware performance indicators. By automatically generating subgraph sequences of computation graphs from models or algorithms and determining execution sequences and positions, not only is the efficiency and accuracy of hardware performance testing improved, but the test results are also made more reliable, facilitating a comprehensive evaluation and optimization of hardware resource utilization. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0042] The structures, proportions, sizes, etc. illustrated in this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention.

[0043] Figure 1 This is a schematic diagram of a hardware testing method provided in an embodiment of this application;

[0044] Figure 2 Hardware test logic diagram provided for embodiments of this application;

[0045] Figure 3 A block diagram of a hardware testing system provided in this application embodiment;

[0046] Figure 4 This paper shows a structural diagram of an electronic device provided in an embodiment of this application;

[0047] Figure 5 A diagram of a computer-readable storage medium provided in an embodiment of this application is shown.

[0048] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0049] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0050] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0051] Furthermore, in this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0052] In this invention, unless otherwise explicitly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0053] Furthermore, the technical solutions of the various embodiments of the present invention can be combined with each other, but only if they are feasible for those skilled in the art. If the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0054] Figure 1 This application illustrates a hardware testing method provided in an embodiment, the method comprising:

[0055] Step 101: Receive hardware test instructions, which carry the model or algorithm to be tested;

[0056] Step 102: Generate a sequence of subgraphs of the corresponding computation graph based on the model or algorithm to be tested; the computation graph is used to represent the data structure of the model or algorithm; the computation graph consists of several nodes and edges, the nodes represent the computation steps of the model or algorithm, and the edges represent the logical relationships between the computation steps;

[0057] Step 103: Determine the subgraph execution sequence and execution location based on the calling order between subgraph sequences;

[0058] Step 104: According to the subgraph execution sequence, input the subgraph into the corresponding execution position of the hardware for calculation to obtain hardware performance indicators.

[0059] In one possible implementation, step 102 involves generating a sequence of subgraphs of the corresponding computation graph based on the model or algorithm to be tested, including:

[0060] The model or algorithm to be tested generates an initial computation graph based on the computation graph compiler; the initial computation graph is then used to generate a corresponding sequence of subgraphs according to the partitioning rules, where each subgraph in the sequence represents a set of computational steps that can be computed in parallel.

[0061] In one possible implementation, generating an initial computation graph based on a computation graph compiler for the model or algorithm to be tested includes:

[0062] A deep neural network is constructed based on the model or algorithm to be tested, and each network layer of the deep neural network is determined as a node in the computation graph; the weights and biases between network layers are determined as edges between nodes in the computation graph; and all computation steps in the model or algorithm are integrated into an initial computation graph through the computation graph compiler, wherein the initial computation graph represents all computation steps in the model or algorithm.

[0063] This application aims to propose a method for evaluating the compatibility of smart hardware based on low-level representation, in order to accurately measure the support performance of smart hardware for upper-layer application software. The core low-level representation refers to the computation graph generated through the hardware compilation process. As a data structure, the computation graph can effectively describe complex computational processes or algorithms. In the computation graph, nodes (or "operations" or "operators") represent specific computational steps, while edges represent data flow or control flow, connecting different operations and revealing the dependencies between them. From a programming framework perspective, any computational task can be represented by a computation graph.

[0064] In one possible implementation, step 103, determining the subgraph execution sequence and execution position based on the calling order between subgraph sequences, includes:

[0065] The data dependencies between subgraphs are determined based on the calling order between the subgraph sequences; the execution sequence and execution location of the subgraphs are determined based on the subgraph attributes and the data dependencies between the subgraphs; the attributes include subgraphs with no data dependencies and subgraphs that are executed only on the CPU, and the execution location includes the CPU and / or GPU.

[0066] In one possible implementation, in step 104, the hardware performance metric includes computation graph coverage; the step of inputting the subgraph into the execution location corresponding to the hardware according to the subgraph execution sequence to obtain the hardware performance metric includes: inputting the subgraph into the execution location corresponding to the hardware according to the subgraph execution sequence to obtain the number of GPU subgraphs and / or the number of CPU subgraphs; obtaining the computation graph coverage based on the ratio of the number of GPU subgraphs and / or the number of CPU subgraphs in the subgraph sequence of the initial computation graph, wherein the computation graph coverage includes GPU coverage and CPU coverage.

[0067] In one possible implementation, in step 104, the hardware performance metric includes the computation time percentage; the step of inputting the subgraph into the execution location corresponding to the hardware according to the subgraph execution sequence to obtain the hardware performance metric includes: inputting the subgraph into the execution location corresponding to the hardware according to the subgraph execution sequence to perform the computation, and recording the computation time of all subgraphs; the computation time includes GPU computation time and / or CPU computation time; the computation time percentage is obtained according to the ratio of the GPU computation time and / or CPU computation time of all subgraphs to the total computation time, the computation time percentage includes the GPU computation time percentage and the CPU computation time percentage, and the total computation time is the total computation time of all subgraphs at the execution location of the hardware.

[0068] In one possible implementation, in step 104, the hardware performance metric includes computation speed; the step of inputting the subgraph into the execution position corresponding to the hardware according to the subgraph execution sequence to obtain the hardware performance metric includes: inputting the subgraph into the execution position corresponding to the hardware according to the subgraph execution sequence to perform computation, and recording the computation time of all subgraphs; the computation time includes GPU computation time and / or CPU computation time; the computation speed is obtained based on the computational workload of all subgraphs and the GPU computation time and / or CPU computation time of all subgraphs, and the computation speed includes GPU computation speed and CPU computation speed.

[0069] This application evaluates the compatibility of smart hardware with upper-layer software by examining the execution performance of the computation graph. A computation graph can be decomposed into multiple subgraphs based on computational relationships, and allocating these subgraphs to hardware for execution enables highly parallel processing. To quantify the hardware's execution capabilities, this application introduces two key metrics: coverage ratio and time ratio. Coverage ratio refers to the percentage of the entire computation graph executed on the hardware; a higher ratio indicates stronger overall hardware execution capabilities. Time ratio, on the other hand, refers to the ratio of GPU computation time to total computation time; a lower time ratio indicates stronger computational power.

[0070] In summary, this application provides a more accurate evaluation method for determining the actual support capability of hardware for upper-layer application software by analyzing the execution performance of smart hardware on the computation graph, including subgraph coverage and time ratio. This method helps developers and users select the smart hardware best suited to their needs, ensuring that software can run efficiently on the hardware.

[0071] Figure 2This diagram illustrates the overall process provided in an embodiment of this application. An initial computational graph is generated from the model. Based on this computational graph, a set of subgraphs corresponding to the initial computational graph is formed using a subgraph segmentation algorithm. According to the order in which the subgraphs are called, they are sent to the smart hardware for computation from smallest to largest to obtain the returned results. The coverage ratio is calculated based on the coverage ratio of the initial computational graph by the subgraphs that can be computed on the smart hardware. The computation speed of the smart hardware is calculated based on the time it takes for all subgraphs to be computed. Specifically, it includes the following stages:

[0072] Phase 1: The model first generates an initial computation graph, which represents the structure of the entire computation task.

[0073] The initial computation graph is a complete computation graph generated by a computation graph compiler. This computation graph, generated by the compiler, contains all the computational processes. The computation graph is a core concept in deep neural networks. When building a neural network, we abstract each layer into a node in the computation graph, and the weights and biases between layers represent the edges between nodes. In this way, the learning process of a neural network can be viewed as a series of computational steps on a computation graph. The computation graph is an intermediate representation of hardware computation; after being further interpreted by a hardware compiler, it can be executed on the hardware. In fact, in smart hardware, the computation graph is a unified representation. A computation graph can be formed from an algorithm or generated from a model. Through the computation graph compiler, we generate a complete computation graph from all the computations.

[0074] Step 1-1: Building a Neural Network: When building a deep neural network, each layer of the network is treated as a node in a computation graph.

[0075] Step 1-2: Define nodes and edges: Abstract the weights and biases between network layers into edges between nodes in the computation graph, representing the flow of data and parameters.

[0076] Steps 1-3: Generate the initial computation graph: The computation graph compiler converts the entire neural network construction process into a complete computation graph, which contains all the computational steps of the network.

[0077] Steps 1-4: Intermediate Representation of the Computation Graph: The computation graph serves as an intermediate representation of hardware computation, mapping the learning process of the neural network into a series of operations on the computation graph.

[0078] Steps 1-5: Computation graph compilation: The hardware compiler further interprets the computation graph, converting it into a form that can be executed on smart hardware.

[0079] The second stage involves processing the initial computation graph using a subgraph partitioning algorithm to generate a sequence of subgraphs corresponding to the initial computation graph. Each subgraph contains a set of operations that can be computed in parallel.

[0080] To enable parallel computation of a computation graph, a complete computation graph is often divided into several subgraphs, which are then batched and computed in parallel on intelligent hardware. Subgraph division is based on several criteria, including:

[0081] (1) Maximum Parallel Partitioning: This algorithm maximizes the parallelism of the partitioned subgraphs based on the dependencies between data and the time estimation of subgraph computation.

[0082] (2) Operator segmentation: Since the smart hardware does not support all operators, operators that are not supported by the smart hardware will be executed on the CPU, so this part of the graph is segmented.

[0083] A maximum parallel partitioning algorithm is applied to analyze data dependencies and subgraph computation time estimates to ensure that the partitioned subgraphs achieve their maximum parallel computing potential. For operators not supported by the smart hardware, they are partitioned into separate subgraphs that will be executed on the CPU, while other subgraphs will be executed on the smart hardware. The initial computation graph is processed by the partitioning algorithm to generate a sequence of subgraphs, each containing a set of operations that can be computed in parallel.

[0084] The third stage: using the subgraph dependency analysis algorithm, the calling sequence and execution order between subgraph sequences are determined.

[0085] Based on the relationship between the input and output of the subgraph, the computational subgraphs are sorted according to their execution order, and subgraphs that can be computed in parallel are grouped together and marked. Subgraphs that run on the CPU are also distinguished. Based on the execution order and location, subgraphs executed on the smart hardware and CPU are then transferred to the corresponding GPU or CPU for computation.

[0086] Step 3-1: Analyze the inputs and outputs of each subgraph to determine the data dependencies between them.

[0087] Step 3-2: Determine the execution order of subgraphs based on the dependencies between them.

[0088] Step 3-3: Identify and label subgraphs that can be computed in parallel without data dependencies.

[0089] Steps 3-4: Identify those subgraphs that can only be executed on the CPU, usually because the smart hardware does not support certain operators.

[0090] Fourth stage: Based on the results of subgraph dependency analysis, determine a subgraph execution sequence to ensure the correctness and order of computation.

[0091] Based on the execution order and location of the subgraph, the subgraph is assigned to the corresponding GPU or CPU.

[0092] Perform subgraph dependency analysis to determine which subgraphs can be computed on the GPU and which need to be executed on the CPU.

[0093] Based on the results of subgraph dependency analysis, it can be determined which subgraphs can be computed on the GPU. By comparing these subgraphs with the initial computation graph according to their coverage relationships, a computation graph coverage metric can be obtained.

[0094] Phase 5: Following the defined subgraph execution sequence, each subgraph is fed into the intelligent hardware for computation. The computation of each subgraph can be performed in parallel to improve overall computational efficiency.

[0095] Phase 6: Calculate the coverage ratio of the subgraph that can be executed on smart hardware to the initial computation graph.

[0096]

[0097] The subgraph that can be computed on the GPU is compared with the initial computation graph to calculate the coverage metric, which is the percentage of the initial computation graph that has been tested on the smart hardware; the same applies to the CPU. A higher coverage ratio indicates a stronger ability of the hardware to execute the computation graph.

[0098] Phase 7: Record the total time required to complete the calculation of all subgraphs, and calculate the computing speed of the smart hardware accordingly.

[0099]

[0100] The percentage of total computation time for all subgraphs scheduled to the smart hardware is used to assess the GPU's activity throughout the computation process. The same applies to the CPU.

[0101]

[0102] The average computation time required to complete the scheduling of all subgraphs onto the smart hardware is calculated to evaluate the computing speed of the GPU, and the same applies to the CPU.

[0103] During the computation process, the computation time of the subgraph on the CPU and GPU is recorded separately to obtain the CPU and GPU computation speeds. By executing the computation graph multiple times and recording the computation time for each run, the average computation time is calculated to obtain a more accurate performance indicator. The faster the computation speed, the stronger the hardware's computing power. Based on the coverage ratio and computation speed, the compatibility and computing power of the smart hardware are comprehensively evaluated.

[0104] Phase 8: Collect the computation results of all subgraphs, integrate them according to a predetermined order or dependency, and output the final computation results.

[0105] Based on the calculated metrics, evaluate the smart hardware's performance on the computation graph, including its computation speed and participation in the entire computation process. If the coverage or computation speed does not meet expectations, analyze possible reasons and propose optimization suggestions, such as improving the subgraph partitioning algorithm, adjusting hardware resource allocation, or optimizing the software scheduling strategy.

[0106] The method provided in this application utilizes a computation graph to evaluate hardware, comprehensively reflecting its ability to handle complex computational tasks. This method not only focuses on computational speed but also considers the hardware's compatibility and stability when executing the computation graph, thus providing a more accurate and comprehensive performance evaluation. By testing both the entire computation graph and its subgraphs separately, this application fully leverages the hardware's parallel processing capabilities. This method allows for the simultaneous testing of multiple subgraphs, simulating real-world scenarios where hardware processes multiple tasks, thereby more accurately evaluating the hardware's parallel computing capabilities and efficiency.

[0107] Traditional hardware performance evaluation often relies on test results from upper-layer application software. However, this application provides a method for directly evaluating hardware performance from the lower layers, avoiding potential biases and influences from upper-layer application software. This low-level evaluation method can reveal the true performance of the hardware when executing computational graphs, providing a more direct reference for hardware selection and optimization.

[0108] In summary, this application provides a hardware testing method. It involves receiving a hardware testing instruction carrying a model or algorithm to be tested; generating a subgraph sequence of a corresponding computation graph based on the model or algorithm; the computation graph representing the data structure of the model or algorithm; the computation graph consisting of nodes and edges, where nodes represent computation steps of the model or algorithm and edges represent logical relationships between computation steps; determining the subgraph execution sequence and execution position based on the calling order between the subgraph sequences; and inputting the subgraph into the corresponding execution position of the hardware according to the subgraph execution sequence for computation to obtain hardware performance indicators. By automatically generating subgraph sequences of computation graphs from models or algorithms and determining the execution sequence and position, not only is the efficiency and accuracy of hardware performance testing improved, but the test results are also made more reliable, facilitating a comprehensive evaluation and optimization of hardware resource utilization.

[0109] Based on the same technical concept, embodiments of this application also provide a hardware testing system, such as... Figure 3 As shown, the system includes:

[0110] The message receiving module 301 is used to receive hardware test instructions, which carry the model or algorithm to be tested.

[0111] The subgraph generation module 302 is used to generate a sequence of subgraphs of the corresponding computation graph based on the model or algorithm to be tested; the computation graph is used to represent the data structure of the model or algorithm; the computation graph consists of several nodes and edges, the nodes represent the computation steps of the model or algorithm, and the edges represent the logical relationships between the computation steps;

[0112] The execution order module 303 is used to determine the subgraph execution sequence and execution position based on the calling order between subgraph sequences;

[0113] The indicator calculation module 304 is used to calculate the hardware performance indicators by inputting the subgraph into the execution position corresponding to the hardware according to the subgraph execution sequence.

[0114] This application also provides an electronic device corresponding to the method provided in the foregoing embodiments. Please refer to... Figure 4 The diagram illustrates an electronic device provided by some embodiments of this application. The electronic device 20 may include: a processor 200, a memory 201, a bus 202, and a communication interface 203, wherein the processor 200, the communication interface 203, and the memory 201 are connected via the bus 202; the memory 201 stores a computer program that can run on the processor 200, and when the processor 200 runs the computer program, it executes the method provided by any of the foregoing embodiments of this application.

[0115] The memory 201 may include high-speed random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Communication between this system network element and at least one other network element is achieved through at least one physical port (which can be wired or wireless), such as the Internet, wide area network, local area network, or metropolitan area network.

[0116] Bus 202 can be an ISA bus, PCI bus, or EISA bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. The memory 201 is used to store programs. After receiving an execution instruction, the processor 200 executes the program. The method disclosed in any of the foregoing embodiments of this application can be applied to the processor 200, or implemented by the processor 200.

[0117] The processor 200 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of the processor 200 or by instructions in software form. The processor 200 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules may reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory 201. The processor 200 reads the information in memory 201 and, in conjunction with its hardware, completes the steps of the above method.

[0118] The electronic devices and methods provided in the embodiments of this application are based on the same inventive concept and have the same beneficial effects as the methods they employ, operate, or implement.

[0119] This application also provides a computer-readable storage medium corresponding to the method provided in the foregoing embodiments. Please refer to... Figure 5The computer-readable storage medium shown is an optical disc 30, on which a computer program (i.e., a program product) is stored, which, when run by a processor, executes the methods provided in any of the foregoing embodiments.

[0120] It should be noted that examples of the computer-readable storage medium may also include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical and magnetic storage media, which will not be elaborated here.

[0121] The computer-readable storage medium provided in the above embodiments of this application and the method provided in the embodiments of this application are based on the same inventive concept and have the same beneficial effects as the methods adopted, run or implemented by the application stored therein.

[0122] It should be noted that the above embodiments are illustrative of this application and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0123] The above description is merely a preferred embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0124] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. All equivalent structural transformations made under the concept of the present invention using the contents of the present invention specification and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A hardware testing method, characterized in that, The method includes: Receive hardware test instructions, which carry the model or algorithm to be tested; A sequence of subgraphs of the corresponding computation graph is generated based on the model or algorithm to be tested; the computation graph is used to represent the data structure of the model or algorithm; the computation graph consists of several nodes and edges, the nodes represent the computation steps of the model or algorithm, and the edges represent the logical relationships between the computation steps; The execution sequence and execution location of the subgraph are determined based on the calling order among the subgraph sequences; According to the subgraph execution sequence, the subgraph is input into the corresponding execution location of the hardware for calculation to obtain hardware performance indicators; the hardware performance indicators include computation graph coverage, computation time percentage and computation speed. The step of generating a subgraph sequence of the corresponding computation graph based on the model or algorithm to be tested includes: generating an initial computation graph based on the model or algorithm to be tested using a computation graph compiler; generating a corresponding subgraph sequence from the initial computation graph according to a partitioning rule, wherein each subgraph in the subgraph sequence represents a set of computation steps that can be computed in parallel. The segmentation rules include: performing maximum parallel segmentation based on the dependencies between data and the time estimate of subgraph computation, and / or, segmenting the parts corresponding to operators not supported by the smart hardware into independent subgraphs based on the support of the smart hardware for the operators. The step of generating an initial computation graph based on the model or algorithm to be tested using a computation graph compiler includes: constructing a deep neural network according to the model or algorithm to be tested, and determining each network layer of the deep neural network as a node in the computation graph; determining the weights and biases between network layers as edges between nodes in the computation graph; and integrating all computation steps in the model or algorithm into an initial computation graph through the computation graph compiler, wherein the initial computation graph represents all computation steps in the model or algorithm. Determining the subgraph execution sequence and execution location based on the calling order between subgraph sequences includes: determining the data dependencies between subgraphs based on the calling order between the subgraph sequences; determining the subgraph execution sequence and execution location based on subgraph attributes and the data dependencies between the subgraphs; the attributes include subgraphs with no data dependencies and subgraphs that execute only on the CPU, and the execution location includes the CPU and / or GPU.

2. The method as described in claim 1, characterized in that, The step of calculating hardware performance metrics by inputting the subgraph into the corresponding execution location of the hardware according to the subgraph execution sequence includes: According to the subgraph execution sequence, the subgraph is input into the corresponding execution location of the hardware for calculation to obtain the number of GPU subgraphs and / or CPU subgraphs; The computation graph coverage is obtained based on the proportion of the number of GPU subgraphs and / or the number of CPU subgraphs in the subgraph sequence of the initial computation graph. The computation graph coverage includes GPU coverage and CPU coverage.

3. The method as described in claim 1, characterized in that, The step of calculating hardware performance metrics by inputting the subgraph into the corresponding execution location of the hardware according to the subgraph execution sequence includes: According to the subgraph execution sequence, the subgraph is input into the corresponding execution location of the hardware for calculation, and the calculation time of all subgraphs is recorded; the calculation time includes GPU calculation time and / or CPU calculation time. The computation time percentage is obtained by taking the proportion of GPU computation time and / or CPU computation time of all subgraphs to the total computation time. The computation time percentage includes the proportion of GPU computation time and the proportion of CPU computation time. The total computation time is the total computation time of all subgraphs at the execution location of the hardware.

4. The method as described in claim 1, characterized in that, The step of calculating hardware performance metrics by inputting the subgraph into the corresponding execution location of the hardware according to the subgraph execution sequence includes: According to the subgraph execution sequence, the subgraph is input into the corresponding execution location of the hardware for calculation, and the calculation time of all subgraphs is recorded; the calculation time includes GPU calculation time and / or CPU calculation time. The computational speed is obtained based on the computational workload of all subgraphs and the GPU computation time and / or CPU computation time of all subgraphs. The computational speed includes both GPU computational speed and CPU computational speed.

5. A hardware testing system, characterized in that, The system includes: The message receiving module is used to receive hardware test instructions, which carry the model or algorithm to be tested. A subgraph generation module is used to generate a sequence of subgraphs of a computational graph corresponding to the model or algorithm to be tested. The computational graph represents the data structure of the model or algorithm. The computational graph consists of several nodes and edges, where nodes represent computational steps of the model or algorithm, and edges represent logical relationships between computational steps. Generating the sequence of subgraphs of the computational graph according to the model or algorithm to be tested includes: generating an initial computational graph based on the model or algorithm to be tested using a computational graph compiler; generating a corresponding sequence of subgraphs from the initial computational graph according to a partitioning rule, where each subgraph in the sequence represents a set of computational steps that can be computed in parallel; the partitioning rule includes: based on the relationships between data... The maximum parallel partitioning is performed by combining the dependency relationship with the time estimation of subgraph computation, and / or, the parts corresponding to operators not supported by the smart hardware are partitioned into independent subgraphs according to the support of the smart hardware for the operators; the step of generating an initial computation graph based on the computation graph compiler for the model or algorithm to be tested includes: constructing a deep neural network according to the model or algorithm to be tested, and determining each network layer of the deep neural network as a node in the computation graph; determining the weights and biases between network layers as edges between nodes in the computation graph; and integrating all computation steps in the model or algorithm into an initial computation graph through the computation graph compiler, wherein the initial computation graph represents all computation steps in the model or algorithm; An execution order module is used to determine the execution sequence and execution location of a subgraph based on the call order between subgraph sequences. Determining the execution sequence and execution location based on the call order between subgraph sequences includes: determining the data dependencies between subgraphs based on the call order between the subgraph sequences; and determining the execution sequence and execution location of the subgraph based on subgraph attributes and the data dependencies between the subgraphs. The attributes include subgraphs with no data dependencies and subgraphs that execute only on the CPU, and the execution location includes the CPU and / or GPU. The indicator calculation module is used to calculate the hardware performance indicators by inputting the subgraph into the corresponding execution position of the hardware according to the subgraph execution sequence; the hardware performance indicators include computation graph coverage, computation time percentage and computation speed.

6. An electronic device, comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that the processor executes the computer program to implement the method as claimed in any one of claims 1-4.

7. A computer-readable storage medium, characterized in that, It stores computer-readable instructions that can be executed by a processor to implement the method as described in any one of claims 1-4.

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