Video transcoding method and device, electronic equipment, storage medium and program product

Abstract

The present disclosure provides a video transcoding method and device, electronic equipment, storage medium and program product, and relates to the technical field of video transcoding. The method comprises: a video transcoding card receiving a transcoding request and a video to be transcoded sent by a server, the transcoding request comprising first video parameters and second video parameters, the first video parameters and the second video parameters being video parameters before and after the video to be transcoded is transcoded respectively; determining configuration parameters according to the first video parameters and the second video parameters, the configuration parameters being used to control the transcoding speed; transcoding the video to be transcoded according to the configuration parameters to obtain a target video; and sending the target video to the server. The present disclosure transcodes by using an external video transcoding card instead of a CPU of the server, so that the computing resources of the server are not occupied, and the GPU is not used for transcoding, thereby reducing power consumption and cost on the premise of improving transcoding speed.

Description

Technical Field

[0001] This disclosure relates to the field of video transcoding technology, and in particular to a video transcoding method, apparatus, electronic device, computer-readable storage medium, and computer program product. Background Technology

[0002] With the increasing prevalence of urban surveillance, live streaming, and video conferencing, massive amounts of video data are generated daily. The processing, distribution, and storage of this data place enormous pressure on data centers supporting video services, particularly in terms of computing, network, and storage resource consumption, posing a significant challenge.

[0003] In related technologies, using a CPU (Central Processing Unit) to transcode and compress video can meet certain requirements, but due to its low transcoding efficiency, it often consumes most of the server's computing resources, resulting in limited overall performance. While using a GPU (Graphics Processing Unit) for transcoding can significantly improve efficiency, it comes with higher hardware costs and power consumption, further increasing the burden of equipment investment and operation.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] This disclosure provides a video transcoding method, apparatus, electronic device, storage medium, and program product, which at least to some extent improves transcoding speed and reduces power consumption and cost.

[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0007] According to one aspect of this disclosure, a video transcoding method is provided, applied to a video transcoding card, comprising: receiving a transcoding request and a video to be transcoded sent by a server, the transcoding request including a first video parameter and a second video parameter, the first video parameter and the second video parameter being video parameters of the video to be transcoded before and after transcoding, respectively; determining configuration parameters based on the first video parameter and the second video parameter, the configuration parameters being used to control the transcoding speed; transcoding the video to be transcoded according to the configuration parameters to obtain a target video; and sending the target video to the server.

[0008] In one embodiment of this disclosure, the configuration parameters include decoder parameters, scaler parameters, and encoder parameters. The decoder parameters are configured through decoder instructions, the scaler parameters are configured through scaler instructions, and the encoder parameters are configured through encoder instructions. The decoder instructions, the scaler instructions, and the encoder instructions are all custom instructions.

[0009] In one embodiment of this disclosure, transcoding the video to be transcoded according to the configuration parameters to obtain a target video includes: decoding the video to be transcoded according to the decoder parameters; performing transformation processing on the decoded video to be transcoded according to the scaler parameters; and encoding the transformed video to be transcoded according to the encoder parameters to obtain the target video; wherein the transformation processing includes scaling processing and / or watermark overlay processing.

[0010] In one embodiment of this disclosure, encoding the transformed video to be transcoded according to encoder parameters to obtain the target video includes: inputting the video to be transcoded into a first model for feature extraction to obtain temporal and spatial features; inputting the temporal and spatial features into a second model for feature fusion to obtain complexity parameters and a control strategy; encoding the transformed video to be transcoded according to the encoder parameters, and dynamically adjusting the encoding parameters according to the complexity parameters and the control strategy to obtain the target video; wherein the encoding parameters include one or more of bitrate, quantization parameters, and frame type.

[0011] In one embodiment of this disclosure, the decoder parameters include inverse quantization calculation parameters, inverse discrete cosine transform parameters, and arithmetic decoding parameters; the scaler parameters include nearest neighbor interpolation parameters and hybrid algorithm parameters; and the encoder parameters include quantization calculation parameters, discrete cosine transform parameters, and arithmetic coding parameters.

[0012] In one embodiment of this disclosure, the custom instruction is a RISC-V fifth generation reduced instruction set instruction.

[0013] According to another aspect of this disclosure, a video transcoding apparatus is provided, applied to a video transcoding card, comprising: a receiving module, configured to receive a transcoding request and a video to be transcoded sent by a server, the transcoding request including a first video parameter and a second video parameter, the first video parameter and the second video parameter being video parameters of the video to be transcoded before and after transcoding, respectively; a determining module, configured to determine configuration parameters based on the first video parameter and the second video parameter, the configuration parameters being used to control the transcoding speed; a transcoding module, configured to transcode the video to be transcoded according to the configuration parameters to obtain a target video; and a sending module, configured to send the target video to the server.

[0014] According to another aspect of this disclosure, a video transcoding card is provided, comprising: multiple video transcoding units, an expansion interface, and a controller. The multiple video transcoding units are all connected to a server via the expansion interface, and each video transcoding unit is connected to the controller, which is used for out-of-band monitoring and management. Each video transcoding unit includes: a control unit for instruction expansion and transcoding control; the controller and the expansion interface are both connected to the control unit; a decoder for decoding the video to be transcoded according to decoder parameters; a scaler for transforming the decoded video to be transcoded according to scaler parameters; and an encoder for encoding the transformed video to be transcoded according to encoder parameters to obtain a target video. The transformation process includes scaling and / or watermark overlay processing.

[0015] According to another aspect of this disclosure, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform any of the video transcoding methods described above by executing the executable instructions.

[0016] According to another aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements any of the video transcoding methods described above.

[0017] According to another aspect of this disclosure, a computer program product is provided, the computer program product comprising a computer program or computer instructions, the computer program or computer instructions being loaded and executed by a processor to enable a computer to implement any of the video transcoding methods described above.

[0018] In embodiments of this disclosure, the video transcoding card receives a transcoding request and a video to be transcoded from a server. The transcoding request includes first video parameters and second video parameters, which are the video parameters of the video to be transcoded before and after transcoding, respectively. Configuration parameters are determined based on the first and second video parameters, and these configuration parameters are used to control the transcoding speed. The video to be transcoded is then transcoded according to the configuration parameters to obtain the target video. The target video is then sent to the server. This disclosure uses an external video transcoding card for transcoding, instead of performing it on the server's CPU, thus avoiding the use of server computing resources and GPU transcoding, thereby reducing power consumption and cost while increasing transcoding speed.

[0019] Furthermore, this disclosure increases the flexibility of transcoding speed control by configuring parameters to control the transcoding speed.

[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0022] Figure 1 A schematic diagram of a video transcoding card according to an embodiment of the present disclosure is shown.

[0023] Figure 2 A flowchart of a video transcoding method according to an embodiment of this disclosure is shown.

[0024] Figure 3 A flowchart of a video transcoding method according to another embodiment of this disclosure is shown.

[0025] Figure 4 A schematic diagram of decoder instructions according to an embodiment of this disclosure is shown.

[0026] Figure 5 A schematic diagram of a scaler instruction according to an embodiment of the present disclosure is shown.

[0027] Figure 6 A schematic diagram of encoder instructions according to an embodiment of this disclosure is shown.

[0028] Figure 7 A schematic diagram of a video transcoding apparatus according to an embodiment of the present disclosure is shown.

[0029] Figure 8 A structural block diagram of an electronic device according to an embodiment of the present disclosure is shown.

[0030] Figure 9 This illustration shows a schematic diagram of a computer-readable storage medium provided in an embodiment of the present disclosure. Detailed Implementation

[0031] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0032] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0033] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0034] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0035] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0036] To facilitate understanding, the following is an explanation of several terms used in this disclosure:

[0037] DCT (Discrete Cosine Transform): Similar to the Discrete Fourier Transform, but using only real numbers, it is commonly used in signal processing and image processing.

[0038] IDCT (Inverse Discrete Cosine Transform): The inverse operation of the discrete cosine transform.

[0039] BMC (Baseboard Management Controller): A dedicated service processor that uses sensors to monitor the status of a computer, network server, or other hardware driver.

[0040] ASIC (Application-Specific Integrated Circuit) refers to a device or system that uses this dedicated chip model for efficient task processing.

[0041] RISC-V (Reduced Instruction Set Computer Five) is an instruction set architecture.

[0042] A Baseboard Management Controller (BMC) is an embedded microcontroller used for managing server and computer hardware. It operates independently of the host operating system and is specifically designed for monitoring and managing server hardware, supporting remote management capabilities. It communicates with administrators via various management protocols, such as IPMI.

[0043] A PCIe switch (Peripheral Component Interconnect Express Switch) is a network device that can forward data between multiple ports.

[0044] Video services generate massive amounts of video data daily. If this data is not transcoded and compressed, it will consume a huge amount of network bandwidth and storage resources in the data center during video distribution and storage. If the CPU is used to transcode the video, it will cause the CPU to be under high load for a long time and the transcoding efficiency will be low.

[0045] The inventors discovered that hardware transcoding solutions in related technologies, such as the AMD Alveo MA35D transcoding card (a type of transcoding card), are ASIC-based, relying on AMD for both hardware and dedicated software libraries, resulting in low flexibility and scalability. Using a GPU for video transcoding, however, leads to higher hardware costs and greater power consumption during operation.

[0046] Based on this, this disclosure proposes a video transcoding method applicable to video transcoding scenarios, such as a scenario where the video transcoding card of this disclosure is connected to a server handling video services to implement video transcoding. The video transcoding card of this disclosure receives a transcoding request and a video to be transcoded from the server. The transcoding request includes first video parameters and second video parameters, which are the video parameters of the video to be transcoded before and after transcoding, respectively. Based on the first and second video parameters, configuration parameters are determined to control the transcoding speed. The video to be transcoded is then transcoded according to the configuration parameters to obtain the target video. The target video is then sent to the server. This disclosure performs transcoding using an external video transcoding card, rather than on the server's CPU, thus avoiding the use of server computing resources and GPUs for transcoding. This reduces power consumption and cost while increasing transcoding speed. In other words, it reduces the cost of video services.

[0047] It should be noted that, unless otherwise specified, the embodiments of this disclosure and the technical features thereof can be combined with each other.

[0048] The specific implementation methods of the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0049] Figure 1 This diagram illustrates a video transcoding card according to an embodiment of the present disclosure, which can be used to apply the video transcoding methods or devices described in various embodiments of the present disclosure. The video transcoding card 100 provided in this disclosure includes: multiple video transcoding units 110, an expansion interface 120, and a controller 130. All video transcoding units 110 are connected to a server via the expansion interface 120, and all video transcoding units 110 are connected to the controller 130, which is used for out-of-band monitoring and management. Each video transcoding unit 110 may include: a control unit for instruction expansion and transcoding control; the controller and the expansion interface are both connected to the control unit; a decoder for decoding the video to be transcoded according to decoder parameters; a scaler for transforming the decoded video to be transcoded according to scaler parameters; and an encoder for encoding the transformed video to be transcoded according to encoder parameters to obtain a target video. The transformation processing includes scaling and / or watermark overlay processing.

[0050] For example, the video transcoding card 100 can be a RISC-V video transcoding card, which is a hardware acceleration card based on the RISC-V architecture used to convert video files from one format to another; the expansion interface 120 can be a PCIe switch; the controller 130 can be a BMC, and this disclosure does not impose specific limitations. Figure 1 As shown, the RISC-V video transcoding card may include multiple video transcoding units 110, each controlled by the RISC-V instruction set. Each video transcoding unit 110 may include a control unit, decoder, scaler, and encoder. A single video transcoding unit 110 can transcode multiple video streams simultaneously, and different video transcoding units 110 do not interfere with each other. The BMC is used for out-of-band monitoring and management. The video transcoding card 100 is connected to the server via a PCIe switch. For example, the server's video service platform connects to the expansion interface 120 of the video transcoding card 100 sequentially through the interface library and hardware driver.

[0051] It should be noted that the control unit can implement standard RV64GC (an instruction set based on RISC-V architecture) instruction extensions and is used to control a single video transcoding unit 110. The control unit is connected to the BMC and also to a PCIe switch.

[0052] It should be noted that the decoder decodes the input video to be transcoded. During the decoding process, custom instructions (such as encoder instructions) can be used to accelerate high-frequency calculations such as inverse quantization and IDCT.

[0053] It should be noted that the scaler can provide hardware scaling, watermark overlay and other functions, and these processes can be accelerated using custom commands (such as scaler commands).

[0054] It should be noted that the encoder can encode and compress video streams, and its built-in neural networks (such as the first model, the second model, and the third model) can assist in video compression. Simultaneously, custom instructions (such as encoder instructions) can be used to accelerate high-frequency calculations such as quantization and DCT. For example, the decoder can decode the input video to be transcoded through circuitry, and during the calculation process, custom instructions can be used to accelerate inverse quantization, inverse discrete cosine transform (IDCT), and arithmetic decoding.

[0055] In addition, at the software level, hardware drivers and interface libraries for the video transcoding card 100 need to be implemented, and the video service platform can use the video transcoding card 100 to process video by calling the interface.

[0056] This disclosure proposes a RISC-V-based video transcoding method. A RISC-V-based hardware architecture and a software library are designed, providing interfaces for video service platforms to call and offload video transcoding tasks from the server. Furthermore, this disclosure defines custom RISC-V instruction extensions for video transcoding to improve transcoding efficiency.

[0057] The following detailed description of this exemplary implementation method is provided in conjunction with the accompanying drawings and embodiments.

[0058] First, this disclosure provides a video transcoding method that can be executed by a video transcoding card.

[0059] Figure 2 A flowchart of a video transcoding method according to an embodiment of this disclosure is shown, as follows: Figure 2 As shown, the video transcoding method provided in this embodiment includes the following steps S201 to S204.

[0060] S201, Receive a transcoding request and a video to be transcoded sent by the server. The transcoding request includes a first video parameter and a second video parameter, which are the video parameters of the video to be transcoded before and after transcoding, respectively.

[0061] In this embodiment of the disclosure, the video transcoding card receives a transcoding request and a video to be transcoded from a server. The transcoding request is a request for the video transcoding card to transcode the video. It should be noted that, in addition to the first and second video parameters, the transcoding request may also include selection information for the transcoding speed level. For example, the selection information for the transcoding speed level may include a first level, a second level, and a third level; a higher level indicates a faster transcoding speed. The transcoding request includes the selection information for the third level.

[0062] In this embodiment of the disclosure, the first video parameter is the video parameter of the video to be transcoded before transcoding, and the second video parameter is the video parameter of the video to be transcoded after transcoding. For example, the video parameter can be one or more of resolution, bitrate, and frame rate.

[0063] S202, Based on the first video parameters and the second video parameters, determine the configuration parameters, which are used to control the transcoding speed.

[0064] In this embodiment of the disclosure, the configuration parameters are parameters that can control the transcoding speed. For example, the configuration parameters may include decoder parameters, scaler parameters, and encoder parameters. The decoder parameters are configured through decoder instructions, the scaler parameters are configured through scaler instructions, and the encoder parameters are configured through encoder instructions. The decoder instructions, scaler instructions, and encoder instructions are all custom instructions.

[0065] It should be noted that the mathematical operation parameters during transcoding can be configured through decoder instructions, scaler instructions, and encoder instructions. By changing these parameters, the transcoding speed can be increased, thus providing greater flexibility in transcoding control.

[0066] For example, configuration parameters may include multiple levels of parameters for configuration, each level including decoder parameters, scaler parameters, and encoder parameters. The configuration parameters corresponding to the transcoding speed level can be selected. For instance, if the transcoding request includes selection information for level three, and the configuration parameters include three levels of parameters, the parameters corresponding to level three can be selected to control the transcoding speed.

[0067] In this embodiment, the method for determining the configuration parameters based on the first video parameter and the second video parameter is not limited. For example, the configuration parameter corresponding to the first video parameter and the second video parameter can be selected according to a preset relationship correspondence table. Another example is that the first video parameter and the second video parameter can be input into a machine learning model, and the configuration parameter can be output. It should be noted that if the transcoding request includes selection information, the configuration parameters corresponding to the first video parameter and the second video parameter also include multiple levels of parameters for configuration. After determining the configuration parameters based on the first video parameter and the second video parameter, the corresponding parameter for configuration is selected based on the selection information. This embodiment increases the flexibility of control by selecting the corresponding level of configuration parameters through selection information, and the configuration parameters are configured through custom instructions, which can improve video transcoding efficiency. In addition, the transcoding compression of the video to be transcoded can reduce the cost of data center networks and storage.

[0068] S203, transcode the video to be transcoded according to the configuration parameters to obtain the target video;

[0069] In this embodiment of the disclosure, the video to be transcoded is sequentially decoded, scaled, and encoded according to configuration parameters to obtain the target video. The target video is the transcoded video.

[0070] S204, Send the target video to the server.

[0071] This disclosure utilizes an external video transcoding card for transcoding, rather than performing it on the server's CPU. This avoids consuming server computing resources and eliminates the need for a GPU for transcoding, thereby reducing power consumption and cost while increasing transcoding speed. Furthermore, this disclosure allows for control of transcoding speed through configuration parameters, increasing the flexibility of transcoding speed control.

[0072] The present disclosure will now be described through two exemplary embodiments.

[0073] In one exemplary embodiment, such as Figure 3 As shown, the video transcoding method provided in this embodiment of the present disclosure transcodes the video to be transcoded according to the configuration parameters to obtain the target video, which may include S2031 to S2033.

[0074] S2031 decodes the video to be transcoded according to the decoder parameters.

[0075] In this embodiment of the disclosure, the decoder parameters may include inverse quantization calculation parameters, inverse discrete cosine transform parameters, and arithmetic decoding parameters.

[0076] For example, the decoder decodes the input video stream to be transcoded, and custom decoder instructions can be used during the calculation process to accelerate inverse quantization, inverse discrete cosine transform, and arithmetic decoding.

[0077] like Figure 4 As shown, the DEQUANT, MACC, COS, and ARITHDEC instructions are all decoder instructions. The DEQUANT instruction is used to configure the inverse quantization calculation parameters, the MACC and COS instructions are used to configure the inverse discrete cosine transform parameters, and the ARITHDEC instruction is used to configure the arithmetic decoding parameters.

[0078] In one embodiment, the custom instructions (such as decoder instructions) are RISC-V fifth generation reduced instruction set instructions.

[0079] The two source registers of the DEQUANT instruction are used to store the quantization value Q(u,v) and the quantization step size Q. Step The target register stores the calculation result C. ′ (u,v). For example, source register 1 is used to store the quantized value Q(u,v), and source register 2 is used to store the quantization step size Q. Step .

[0080] The inverse quantization formula is shown in Formula 1 below.

[0081] C ′ (u,v)=Q(u,v)·Q Step (1)

[0082] Among them, C ′ (u,v) represents the dequantized transform coefficients, where u is the row index and v is the column index in the transform coefficient matrix. Q(u,v) represents the quantized coefficients (quantized values). Step This is for quantization step size.

[0083] The MACC and COS instructions can be used in DCT and IDCT for two frequently used calculations: multiplication accumulation and cosine calculation. The source registers rs1 and rs2 of the MACC instruction store the numbers used for multiplication, and rs3 stores the numbers used for addition. The source register of the COS instruction stores the input value of the cosine function. For example, the assembly format of the MACC instruction is MACC rd, rs1, rs2, rs3. Using this instruction and its corresponding hardware circuitry, the multiplication accumulation rd = rs1 * rs2 + rs3 is implemented.

[0084] The IDCT formula is shown in Formula 2 below.

[0085]

[0086] Where f(x,y) is the output pixel value, x is the row coordinate, y is the column coordinate, N is the size of the image patch, α is the normalization coefficient, and F(k,l) is the value in the input transform coefficient matrix, where k is the row index and l is the column index.

[0087] For example, such as Figure 4 As shown, the source registers rs1 and rs2 of the COS instruction can store (x, k) and (y, l), respectively. In the MACC instruction, the increment starts from 0. The source register rs3 stores the result of the previous operation, and the source register rs1 can store the output values ​​of the two COS operations. The product of f(k,l) and f(x,y) can be stored in the source register rs2 and the destination register rd.

[0088] It should be noted that the MACC and COS instructions are part of the IDCT operation, and the formula cannot be calculated using only these two instructions. The source register rs1 of the MACC instruction can also store the output values ​​of the two COS instructions.

[0089] The ARITHDEC instruction is used for arithmetic decoding. Two source registers, rs1 and rs2, are used to store the memory address of the bitstream S and the probability model p(s). j The storage address of ).

[0090] The formulas involved in arithmetic decoding are shown below.

[0091] S = {s1, s2, s3, ..., s} n} (3)

[0092] Where S is the input symbol set (bit stream), s i Let be the i-th symbol in the symbol set, n be the total number of symbols in the symbol set, and i be a positive integer less than or equal to n.

[0093] Each symbol s i There is a corresponding probability p(s) i Define the cumulative probability C(s). i As shown in Formula 4 below.

[0094]

[0095] Wherein, C(s) i p(s) represents the cumulative probability. j Let be the probability model for the j-th symbol, where j is a positive integer less than i-1.

[0096] E is the encoded value, and the current symbol update interval is [L, U), where L is the minimum value of the encoded value and U is the maximum value of the encoded value. The conditions to be met are shown in Formula 5 below.

[0097]

[0098] Wherein, C(s) i p(s) represents the cumulative probability. i Let L be the probability model for the i-th symbol, where i is a positive integer less than or equal to n, L is the minimum value of the encoded value, and U is the maximum value of the encoded value.

[0099] Update value L of the minimum value of the encoded value new As shown in Formula 6, the updated value U of the maximum encoded value. new As shown in Formula 7.

[0100] L new =L+(UL)·C(s) i (6)

[0101] U new =L+(UL)·(C(s) i )+p(s i (7)

[0102] Among them, L new The updated value of U is the minimum value of the encoded value. new The updated value is the maximum value of the encoded value, C(s). i p(s) represents the cumulative probability. i Let L be the probability model for the i-th symbol, where i is a positive integer less than or equal to n, L is the minimum value of the encoded value, and U is the maximum value of the encoded value.

[0103] It should be noted that the decoder parameters can be configured in advance or during the decoding process, and this embodiment does not limit this.

[0104] S2032 performs transformation processing on the decoded video to be transcoded according to the scaler parameters.

[0105] In this embodiment of the disclosure, the scaler parameters include nearest neighbor interpolation parameters and hybrid algorithm parameters.

[0106] For example, the scaler is used to implement functions such as video scaling and watermark overlay. The NEAREST and ALPHA commands are both scaler commands. The NEAREST command is used to configure the nearest neighbor interpolation parameters, and the ALPHA command is used to configure the blending algorithm parameters, where the blending algorithm parameters are the parameters of the Alpha blending algorithm in watermark overlay.

[0107] In one embodiment, the custom instructions (such as scaler instructions) are RISC-V fifth generation reduced instruction set instructions.

[0108] The NEAREST command is used for nearest-neighbor interpolation and can be used to scale video frames of the decoded video to be transcoded. For example... Figure 5 As shown, source register rs1 stores the storage address of the original video frame, source register rs2 stores the scaling factor S, and source register rs3 stores the coordinates of the current pixel of the target frame.

[0109] The nearest neighbor interpolation formula is shown in Figure 8 below.

[0110]

[0111] Among them, (x out y out (x) represents the coordinates of a pixel in the target image. in y in S represents the coordinates of a pixel in the original image. x S is the scaling factor for the row coordinates. y is the scaling factor for the column coordinates.

[0112] The ALPHA directive is used in the Alpha blending algorithm for watermark overlay, such as... Figure 5 As shown, the source register rs1 stores the original video pixel value P. video The pixel value P of the watermark in the source register rs2 watermark The source register rs3 stores the transparency α, and the destination register stores the color value of the output pixel.

[0113] The formula for the Alpha hybrid algorithm is shown in Figure 9 below.

[0114] P out =α·P watermark +(1-α)·P video (9)

[0115] Among them, P out P is the color value of the output pixel. watermark P represents the color value of the watermark pixel. video α represents the color value of the original video frame pixel, and α represents the transparency of the watermark.

[0116] It should be noted that the scaler parameters can be configured in advance or during the scaling or watermark overlay process, and this embodiment does not limit this.

[0117] S2033: Encode the transformed video to be transcoded according to the encoder parameters to obtain the target video. The transformation process includes scaling and / or watermark overlay.

[0118] In this embodiment of the disclosure, the encoder parameters include quantization calculation parameters, discrete cosine transform parameters, and arithmetic coding parameters.

[0119] For example, the encoder encodes the transformed video to be transcoded, and custom encoder instructions can be used during the calculation process to accelerate quantization, discrete cosine transform, and arithmetic coding.

[0120] like Figure 6 As shown, both the QUANT and ARITHENC instructions are encoder instructions. The QUANT instruction is used to configure quantization calculation parameters, while the ARITHENC instruction is used to configure arithmetic coding parameters.

[0121] In one embodiment, the custom instructions (such as encoder instructions) are RISC-V fifth generation reduced instruction set instructions.

[0122] The QUANT instruction is used for quantization calculations. The source registers rs1 and rs2 are used to store the quantized value C(u,v) and the quantization step size Q, respectively. Step The target register stores the calculation result Q(u,v).

[0123] The quantification formula is shown in Formula 10 below.

[0124]

[0125] Where C(u,v) are the original transform coefficients, u is the row index in the transform coefficient matrix, v is the column index in the transform coefficient matrix, and Q(u,v) are the quantized coefficients (quantized values). Step This is for quantization step size.

[0126] The MACC and COS instructions defined in the decoder can also be used in the DCT calculation of the encoder.

[0127] The DCT formula is shown in Formula 11 below.

[0128]

[0129] Where f(x,y) is the input pixel value, x is the row coordinate, y is the column coordinate, N is the size of the image patch, α is the normalization coefficient, and F(k,l) is the value in the output transform coefficient matrix, where k is the row index and l is the column index.

[0130] The ARITHENC instruction is used for arithmetic encoding. Source registers rs1 and rs2 are used to store the memory address of the bitstream S and the probability model p(s). j The storage address of ).

[0131] The formulas involved in arithmetic coding are shown below.

[0132] S = {s1, s2, s3, ..., s} n}

[0133] Where S is the input symbol set (bit stream), s i Let be the i-th symbol in the symbol set, n be the total number of symbols in the symbol set, and i be a positive integer less than or equal to n.

[0134] Each symbol s i There is a corresponding probability p(s) i Define the cumulative probability C(s). i The formula is shown below.

[0135]

[0136] Wherein, C(s) i p(s) represents the cumulative probability. j Let be the probability model for the j-th symbol, where j is a positive integer less than i-1.

[0137] The current symbol update interval is [L, U), where L is the minimum value of the encoded value, U is the maximum value of the encoded value, and the update value of the minimum value is L. new The updated value U of the maximum value of the encoded value new As shown in the formula below.

[0138] L new =L+(UL)·C(s) i )

[0139] U new =L+(UL)·(C(s) i )+p(s i ))

[0140] Among them, L new The updated value of U is the minimum value of the encoded value. new The updated value is the maximum value of the encoded value, C(s). i p(s) represents the cumulative probability. i Let L be the probability model for the i-th symbol, where i is a positive integer less than or equal to n, L is the minimum value of the encoded value, and U is the maximum value of the encoded value.

[0141] The final encoded result is any small value within the final interval, usually taken as the midpoint of the interval, as shown in Formula 12 below.

[0142]

[0143] Wherein, Encoded Value is the encoding result, L is the minimum value of the encoded value, and U is the maximum value of the encoded value.

[0144] In another exemplary embodiment, the video transcoding method provided in this disclosure embodiment encodes the transformed video to be transcoded according to encoder parameters to obtain the target video, which may include the following steps A1 to A3.

[0145] Step A1: Input the video to be transcoded into the first model for feature extraction to obtain temporal and spatial features.

[0146] In this embodiment of the disclosure, the first model is used to extract features from the video frames of the video to be transcoded. The specific type of the first model is not limited in this embodiment. For example, the first model can be a CNN (Convolutional Neural Network) model.

[0147] In this embodiment, temporal and spatial features are two-dimensional features. Temporal features focus on dynamic changes and motion information in the video. For example, temporal features can be one or more of motion vectors (MV), optical flow, motion, temporal correlation, and sequential patterns. Spatial features focus on the spatial information of each frame of the video, especially the details and surface structure of the image. Texture is the visual representation of repetitive or regular patterns in an image. For example, spatial features can be one or more of local texture patterns, edge information, frequency domain features, and gray-level co-occurrence matrix (GLCM).

[0148] Step A2 involves inputting the temporal and spatial features into the second model for feature fusion to obtain complexity parameters and control strategies.

[0149] In this embodiment of the disclosure, the second model is used to fuse temporal and spatial features. The specific type of the second model is not limited in this embodiment. For example, the second model can be a CNN model or an adaptive model.

[0150] In this embodiment, the complexity parameter is a parameter that affects the computational complexity of the video encoding process. The complexity parameter can adjust the encoding strategy according to different video content to ensure optimal compression effect and video quality. For example, the complexity parameter can be parameters such as code block size, motion estimation accuracy, transform, and quantization. The control strategy is used to dynamically adjust various parameters in the encoding process, aiming to ensure optimal visual quality and encoding performance under different input video scenarios. Guided by a second model (such as a pre-trained network), the control strategy can achieve automated dynamic adjustment, thereby improving the overall efficiency of video compression.

[0151] This embodiment of the disclosure fuses temporal and spatial features through a second model, and obtains complexity parameters and control strategies based on the fused features. This results in higher accuracy in the dynamic adjustment of the control strategy and more precise complexity parameters, thereby ensuring optimal compression performance and video quality while maintaining encoding speed.

[0152] It should be noted that the first model and the second model are combined into a reference AI (artificial intelligence) model, which is used to obtain complexity parameters and control strategies. Based on the complexity parameters and control strategies, the encoding parameters are dynamically adjusted to generate a video stream with better compression efficiency.

[0153] Step A3: Encode the transformed video to be transcoded according to the encoder parameters, and dynamically adjust the encoding parameters according to the complexity parameters and control strategy to obtain the target video; wherein, the encoding parameters include one or more of the following: bitrate, quantization parameters and frame type.

[0154] In addition to the custom instruction-based acceleration encoding process described in the above embodiments, the encoder also includes a neural network accelerator (a first model and a second model). The first model performs preliminary feature extraction on the input video, including temporal features such as video volume (MV) and spatial features such as detail texture. Then, the second model fuses the temporal and spatial features to obtain complexity parameters and control strategies that conform to the visual model. During encoding, the encoder dynamically adjusts parameters such as bitrate and QP (quantization parameter) value according to the input video to generate a video stream with better compression efficiency.

[0155] The embodiments of this disclosure, by fusing temporal and spatial features, can significantly improve the performance of video processing tasks. By simultaneously capturing the dynamic changes (temporal features) and spatial details (spatial features) of the video, a more comprehensive understanding of the video content can be achieved, enhancing the ability to recognize complex actions and behaviors, improving robustness, and effectively capturing spatiotemporal dependencies, facilitating encoding according to a precise control encoder.

[0156] In summary, this disclosure leverages the customizability of RISC-V to offload video transcoding tasks from the CPU on a RISC-V-based hardware platform, accelerating the video transcoding process through custom instructions and corresponding hardware circuitry. This disclosure designs custom instructions for video decoding, accelerating inverse quantization, IDCT, and arithmetic decoding operations during the decoding process. Furthermore, this disclosure designs custom instructions to accelerate video scaling and watermark overlay functions. Custom instructions for video encoding are also designed to accelerate quantization, DCT, and arithmetic encoding operations during the encoding process, while providing a first module and a second model to assist the encoding process, generating a video stream with higher compression efficiency.

[0157] It should be noted that this disclosure is based on the open-source and free RISC-V instruction set, which has lower hardware costs compared to GPU-based solutions. Custom RISC-V instructions for video transcoding offer faster video transcoding capabilities compared to general-purpose CPUs.

[0158] The present disclosure will now be described in detail through examples.

[0159] In one embodiment, the video transcoding method provided in this disclosure includes the following steps B1 to B6.

[0160] In step B1, the video service platform begins processing the video transcoding request. For example, it transcodes the input H.264 format video to H.265 format video.

[0161] In step B2, the video service platform calls the interface library of the video transcoding card (such as a video transcoding card based on RISC-V architecture) to start scheduling the video to be transcoded to the video transcoding card for video transcoding.

[0162] In step B3, the video transcoding unit of the video transcoding card decodes the input video to be transcoded (H.264 video stream). During the decoding process, when performing IDCT calculation, the calculation circuit is called using the MACC instruction and COS command to accelerate the two processes of accumulation multiplication and cosine calculation according to the formula. When performing inverse quantization calculation, the DEQUANT instruction is used for acceleration. When performing arithmetic decoding, the ARITHDEC instruction is called for acceleration.

[0163] In step B4, when performing operations such as video scaling and watermark overlay on the decoded video stream, the computational circuit is accelerated by calling the NEAREST and ALPHA instructions.

[0164] Step B5: The scaled video stream is input into the encoder for encoding. The bit rate and QP parameters are dynamically adjusted in conjunction with the reference AI encoder in the encoder. Encoding is performed according to the above parameters. The quantization, DCT and arithmetic encoding processes are accelerated by using QUANT, MACC, COS and ARITHENC instructions and their circuits.

[0165] Step B6 involves returning the encoded H.265 video stream to the video service platform for subsequent storage or distribution.

[0166] Based on the same inventive concept, this disclosure also provides a video transcoding apparatus, as shown in the following embodiments. Since the principle by which this apparatus solves the problem is similar to that of the method embodiments described above, the implementation of this apparatus embodiment can refer to the implementation of the method embodiments described above, and repeated details will not be described again.

[0167] Figure 7 This diagram illustrates a video transcoding apparatus according to an embodiment of the present disclosure, such as... Figure 7 As shown, this video transcoding device, applied to a video transcoding card, includes a receiving module 71, a determining module 72, a transcoding module 73, and a sending module 74. The receiving module 71 receives a transcoding request and a video to be transcoded from a server. The transcoding request includes first video parameters and second video parameters, which are the video parameters of the video before and after transcoding, respectively. The determining module 72 determines configuration parameters based on the first and second video parameters. These configuration parameters control the transcoding speed. The transcoding module 73 transcodes the video to be transcoded according to the configuration parameters to obtain the target video. The sending module 74 sends the target video to the server.

[0168] In one embodiment, the configuration parameters include decoder parameters, scaler parameters, and encoder parameters. The decoder parameters are configured through decoder instructions, the scaler parameters are configured through scaler instructions, and the encoder parameters are configured through encoder instructions. The decoder instructions, scaler instructions, and encoder instructions are all custom instructions.

[0169] In one embodiment, the transcoding module 73 can also be used to decode the video to be transcoded according to the decoder parameters; perform transformation processing on the decoded video to be transcoded according to the scaler parameters; and encode the transformed video to be transcoded according to the encoder parameters to obtain the target video; wherein the transformation processing includes scaling processing and / or watermark overlay processing.

[0170] In one embodiment, the transcoding module 73 can also be used to input the video to be transcoded into a first model for feature extraction to obtain temporal and spatial features; input the temporal and spatial features into a second model for feature fusion to obtain complexity parameters and control strategies; encode the transformed video to be transcoded according to encoder parameters, and dynamically adjust the encoding parameters according to the complexity parameters and control strategies to obtain the target video; wherein, the encoding parameters include one or more of bitrate, quantization parameters, and frame type.

[0171] In one embodiment, the decoder parameters include inverse quantization calculation parameters, inverse discrete cosine transform parameters, and arithmetic decoding parameters; the scaler parameters include nearest neighbor interpolation parameters and hybrid algorithm parameters; and the encoder parameters include quantization calculation parameters, discrete cosine transform parameters, and arithmetic coding parameters.

[0172] In one embodiment, the custom instructions are RISC-V fifth generation reduced instruction set instructions.

[0173] The video transcoding device disclosed in this embodiment performs transcoding using an external video transcoding card, rather than on the server's CPU. This avoids consuming server computing resources and eliminates the need for a GPU for transcoding, thereby reducing power consumption and cost while increasing transcoding speed. Furthermore, this disclosure increases the flexibility of transcoding speed control by allowing configuration parameters to be used for speed control.

[0174] Those skilled in the art will understand that various aspects of this disclosure can be implemented as a system, method, or program product. Therefore, various aspects of this disclosure can be specifically implemented in the following forms: a completely hardware implementation, a completely software implementation (including firmware, microcode, etc.), or a combination of hardware and software aspects, collectively referred to herein as a "circuit," "module," or "system."

[0175] The following reference Figure 8 To describe an electronic device 800 according to such an embodiment of the present disclosure. Figure 8 The electronic device 800 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0176] like Figure 8 As shown, the electronic device 800 is manifested in the form of a general-purpose computing device. The components of the electronic device 800 may include, but are not limited to: at least one processing unit 810, at least one storage unit 820, and a bus 830 connecting different system components (including storage unit 820 and processing unit 810).

[0177] The storage unit stores program code that can be executed by the processing unit 810, causing the processing unit 810 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure. For example, the processing unit 810 can perform the following steps of the above method embodiments: receiving a transcoding request and a video to be transcoded from a server, the transcoding request including a first video parameter and a second video parameter, the first video parameter and the second video parameter being the video parameters before and after transcoding of the video to be transcoded, respectively; determining configuration parameters based on the first video parameter and the second video parameter, the configuration parameters being used to control the transcoding speed; transcoding the video to be transcoded according to the configuration parameters to obtain a target video; and sending the target video to the server.

[0178] Storage unit 820 may include a readable medium in the form of a volatile storage unit, such as random access memory (RAM) 8201 and / or cache memory 8202, and may further include a read-only memory (ROM) 8203.

[0179] The storage unit 820 may also include a program / utility 8204 having a set (at least one) of program modules 8205, including but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment.

[0180] Bus 830 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0181] Electronic device 800 can also communicate with one or more external devices 840 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 800, and / or with any device that enables electronic device 800 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 850. Furthermore, electronic device 800 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 860. As shown, network adapter 860 communicates with other modules of electronic device 800 via bus 830. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 800, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0182] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0183] In the disclosed exemplary embodiments, a computer-readable storage medium is also provided, which may be a readable signal medium or a readable storage medium. Figure 9 This illustration shows a schematic diagram of a computer-readable storage medium according to an embodiment of the present disclosure, such as... Figure 9 As shown, the computer-readable storage medium 900 stores a program product capable of implementing the methods described above.

[0184] In some possible implementations, various aspects of this disclosure may also be implemented as a program product comprising program code that, when run on a terminal device, causes the terminal device to perform the steps described in the foregoing “Detailed Description” section of this specification according to various exemplary embodiments of this disclosure.

[0185] More specific examples of computer-readable storage media in this disclosure may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0186] In this disclosure, a computer-readable storage medium may include a data signal propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of transmitting, propagating, or transmitting a program for use by or in connection with an instruction execution system, apparatus, or device.

[0187] Optionally, the program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0188] In practical implementation, program code for performing the operations of this disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0189] This disclosure provides a computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the video transcoding method provided in various alternative embodiments of this disclosure.

[0190] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0191] Furthermore, although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0192] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, mobile terminal, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0193] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope of this disclosure is indicated by the appended claims.

Claims

1. A video transcoding method, characterized in that, Applied to video transcoding cards, including: The system receives a transcoding request and a video to be transcoded from a server. The transcoding request includes a first video parameter, a second video parameter, and selection information for a corresponding transcoding speed level. The first video parameter and the second video parameter are the video parameters of the video to be transcoded before and after transcoding, respectively. Based on the first video parameters and the second video parameters, configuration parameters are determined, and configuration parameters of the corresponding level are selected according to the selection information. The configuration parameters are used to control the transcoding speed and include multiple levels of configurable parameters. Each level of configurable parameters includes decoder parameters, scaler parameters, and encoder parameters. The decoder parameters are configured through decoder instructions, the scaler parameters are configured through scaler instructions, and the encoder parameters are configured through encoder instructions. All decoder, scaler, and encoder instructions are custom instructions, which are RISC-V fifth-generation reduced instruction set instructions. The decoder parameters include inverse quantization calculation parameters, inverse discrete cosine transform parameters, and arithmetic decoding parameters. The scaler parameters include nearest neighbor interpolation parameters and hybrid algorithm parameters. The encoder parameters include quantization calculation parameters, discrete cosine transform parameters, and arithmetic coding parameters. The video to be transcoded is transcoded according to the configuration parameters of the corresponding level to obtain the target video; Send the target video to the server; The process of transcoding the video to be transcoded according to the configuration parameters of the corresponding level to obtain the target video includes: decoding the video to be transcoded according to the decoder parameters; transforming the decoded video to be transcoded according to the scaler parameters; and encoding the transformed video to be transcoded according to the encoder parameters to obtain the target video.

2. The method according to claim 1, characterized in that, The transformation process includes scaling and / or watermark overlay processing.

3. The method according to claim 1, characterized in that, The target video is obtained by encoding the transformed video according to the encoder parameters, including: The video to be transcoded is input into the first model for feature extraction to obtain temporal and spatial features; The temporal and spatial features are input into the second model for feature fusion to obtain complexity parameters and control strategies. The transformed video to be transcoded is encoded according to the encoder parameters, and the encoding parameters are dynamically adjusted according to the complexity parameters and the control strategy to obtain the target video; The encoding parameters include one or more of the following: bit rate, quantization parameters, and frame type.

4. A video transcoding device, characterized in that, Applied to video transcoding cards, including: The receiving module is used to receive a transcoding request and a video to be transcoded sent by the server. The transcoding request includes a first video parameter, a second video parameter, and selection information for a corresponding transcoding speed level. The first video parameter and the second video parameter are the video parameters of the video to be transcoded before and after transcoding, respectively. The determining module is used to determine configuration parameters based on the first video parameters and the second video parameters, and to select configuration parameters of the corresponding level based on the selection information. The configuration parameters are used to control the transcoding speed. The configuration parameters include multiple levels of parameters for configuration. Each level of parameters includes decoder parameters, scaler parameters, and encoder parameters. The decoder parameters are configured through decoder instructions, the scaler parameters are configured through scaler instructions, and the encoder parameters are configured through encoder instructions. The decoder instructions, scaler instructions, and encoder instructions are all custom instructions, which are RISC-V fifth-generation reduced instruction set instructions. The decoder parameters include inverse quantization calculation parameters, inverse discrete cosine transform parameters, and arithmetic decoding parameters. The scaler parameters include nearest neighbor interpolation parameters and hybrid algorithm parameters. The encoder parameters include quantization calculation parameters, discrete cosine transform parameters, and arithmetic coding parameters. The transcoding module is used to transcode the video to be transcoded according to the configuration parameters of the corresponding level to obtain the target video; The sending module is used to send the target video to the server; The transcoding module is further configured to decode the video to be transcoded according to the decoder parameters; transform the decoded video to be transcoded according to the scaler parameters; and encode the transformed video to be transcoded according to the encoder parameters to obtain the target video.

5. An electronic device, characterized in that, include: processor; as well as Memory for storing the executable instructions of the processor; The processor is configured to execute the video transcoding method of any one of claims 1-3 by executing the executable instructions.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the video transcoding method according to any one of claims 1-3.

7. A computer program product comprising computer instructions stored in a computer-readable storage medium, wherein the computer instructions, when executed by a processor, implement the operation instructions of the video transcoding method according to any one of claims 1-3.

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