Memory device, memory system, and manufacturing method of memory device

Abstract

Embodiments of the present application provide a memory device, a memory system, and a manufacturing method of the memory device. The memory device includes a first electrode layer; a first stack structure located at one side of the first electrode layer and including first dielectric layers and plate line layers alternately arranged; a storage pillar penetrating through the first stack structure and the first electrode layer and protruding from the first electrode layer, the storage pillar including storage functional layers and an inner electrode arranged successively from outside to inside; a first channel layer covering a portion of the storage functional layers protruding from the first electrode layer and the first electrode layer; and a second electrode located at a side of the first channel layer away from the first electrode layer and electrically connected with the first channel layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a memory device, a memory system, and a method for manufacturing the memory device. Background Technology

[0002] New types of memory (e.g., ferroelectric memory) are widely used in portable medical devices, wearable devices, IoT sensors, industrial and automotive applications due to their advantages such as high-speed interfaces, ultra-low power operation, instant non-volatile storage and unlimited read / write cycle endurance.

[0003] In novel memories, each memory cell may include a transistor and a capacitor. Currently, optimizing the structure and performance of transistors is one of the problems that the field is working to solve. Summary of the Invention

[0004] This application provides a memory device, a memory system, and a method for manufacturing the memory device that can at least partially solve the above-mentioned problems in related technologies or other problems in the art.

[0005] In a first aspect, some embodiments of this application provide a memory device. The memory device includes: a first electrode layer; a first stacked structure located on one side of the first electrode layer and including alternately disposed first dielectric layers and board line layers; a memory pillar penetrating the first stacked structure and the first electrode layer, and protruding beyond the first electrode layer, the memory pillar including a memory functional layer and an inner electrode disposed sequentially from the outside in; a first channel layer covering the portion of the memory functional layer protruding beyond the first electrode layer and the first electrode layer; and a second electrode located on the side of the first channel layer away from the first electrode layer and electrically connected to the first channel layer.

[0006] In some embodiments, the first electrode layer, the first channel layer, the second electrode, and the inner electrode and the storage function layer each protrude from the portion of the first stacked structure to form a transistor.

[0007] In some implementations, the storage function layer and the internal electrode are respectively located in portions corresponding to a board line layer, and the board line layer forms a capacitor unit.

[0008] In some implementations, multiple capacitor cells are arranged along the stacking direction of the first stack structure, and the multiple capacitor cells and transistors share the storage function layer and internal electrode.

[0009] In some embodiments, the memory device further includes a first insulating layer covering the first channel layer, wherein a second electrode extends through the first insulating layer to the first channel layer, and the second electrode is at least partially aligned with the axis of the memory pillar.

[0010] In some embodiments, the memory device further includes: a second stacked structure located on the side of the first stacked structure away from the first electrode layer, including a gate layer and a second dielectric layer located on the side of the gate layer away from the first stacked structure; and a channel structure extending through the second stacked structure to a memory pillar, including a gate dielectric layer and a second channel layer pillar disposed sequentially from the outside to the inside, the second channel layer being electrically connected to an inner electrode.

[0011] In some embodiments, the memory device further includes: a second insulating layer located on the side of the second stacked structure away from the first stacked structure; and a bit line connection structure penetrating the second insulating layer and electrically connected to the second channel layer.

[0012] In some embodiments, the memory device further includes a gate connection structure that penetrates the second insulating layer and extends to the gate layer.

[0013] In some embodiments, the material of the second channel layer includes a semiconductor with a first conductivity type dopant, the internal electrode includes a metal pillar and a semiconductor plug, the material of the semiconductor plug includes a semiconductor with a second conductivity type dopant, and the second channel layer is in contact with the semiconductor plug.

[0014] In some implementations, the materials used in the storage functional layer include ferroelectric and antiferroelectric materials.

[0015] Secondly, some embodiments of this application provide a memory system. The memory system includes: a memory device as mentioned in any of the embodiments described above; and a controller coupled to the memory device for controlling the memory device to store data.

[0016] Thirdly, some embodiments of this application provide a method for manufacturing a memory device. The method includes: sequentially forming a first electrode layer and a first stacked structure on a first side of a substrate, the first stacked structure including alternating first dielectric layers and line layers; forming a memory pillar extending through the first stacked structure and the first electrode layer toward the substrate, the memory pillar including a memory functional layer and an inner electrode sequentially disposed from the outside in; removing the substrate and exposing portions of the first electrode layer and the memory functional layer protruding from the first electrode layer; forming a first channel layer covering the portion of the memory functional layer protruding from the first electrode layer; and forming a second electrode electrically connected to the first channel layer.

[0017] In some embodiments, before forming the first electrode layer and the first stacked structure sequentially on the first side of the substrate, the method further includes: forming a stop layer and an insulating material layer sequentially on the first side of the substrate; wherein forming a memory pillar that penetrates the first stacked structure and the first electrode layer and extends toward the substrate includes: forming a memory pillar that sequentially penetrates the first stacked structure, the first electrode layer, the insulating material layer to the stop layer.

[0018] In some embodiments, forming a storage pillar that sequentially penetrates the first stacked structure, the first electrode layer, the insulating material layer to the stop layer includes: forming a storage hole that sequentially penetrates the first stacked structure, the first electrode layer, the insulating material layer to the stop layer; and sequentially forming a storage function layer and an inner electrode within the storage hole.

[0019] In some embodiments, removing the substrate and exposing portions of the first electrode layer and the storage function layer that protrude from the first electrode layer includes removing the substrate, the stop layer, and the insulating material layer to expose portions of the first electrode layer and the storage function layer that protrude from the first electrode layer.

[0020] In some embodiments, forming a second electrode electrically connected to the first channel layer includes: forming a first insulating layer covering the first channel layer; and forming a second electrode extending through the first insulating layer to the first channel layer, the second electrode being at least partially aligned with the axis of the storage column.

[0021] In some embodiments, the method further includes: forming a second stacked structure on the side of the first stacked structure away from the substrate, the second stacked structure including a gate layer and a second dielectric layer located on the side of the gate layer away from the first stacked structure; and forming a channel structure extending through the second stacked structure to a memory pillar, the channel structure including a gate dielectric layer and a second channel layer disposed sequentially from the outside to the inside, the second channel layer being electrically connected to an internal electrode.

[0022] In some embodiments, the method further includes: forming a second insulating layer on the side of the second stack structure away from the first stack structure; and forming a bit line connection structure through the second insulating layer to the second channel layer.

[0023] In some embodiments, the method further includes forming a gate connection structure that penetrates the second insulating layer and extends to the gate layer.

[0024] According to at least one embodiment of this application, the memory device, memory system, and method for manufacturing the memory device provided in this application can reduce the planar area occupied by forming a memory cell structure comprising multiple capacitor cells and CAA transistors. Simultaneously, since the CAA transistor is a closed-gate structure, the gate length and gate control capability of the transistor in the memory cell can be improved. Furthermore, a self-aligned process can be used to enable the CAA transistor and multiple capacitor cells to share the memory functional layer and internal electrode, thereby improving the uniformity and consistency of the corresponding structural dimensions in the transistor. Attached Figure Description

[0025] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0026] Figure 1This is a block diagram of a system with a memory system provided in an embodiment of this application;

[0027] Figure 2 This is a circuit diagram of a storage unit provided in an embodiment of this application;

[0028] Figure 3 This is a cross-sectional structural schematic diagram of the memory device provided in the embodiments of this application;

[0029] Figure 4 This is a schematic flowchart of a method for manufacturing a memory device according to an embodiment of this application; and

[0030] Figures 5A to 5D This is a cross-sectional structural diagram of the memory device provided in the embodiments of this application during the manufacturing process. Detailed Implementation

[0031] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0032] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first stacking structure discussed herein may also be referred to as the second stacking structure, and vice versa.

[0033] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0034] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0035] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0036] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0037] Furthermore, in this application, the use of "connection" or "linkage" may indicate direct or indirect contact between corresponding components, unless otherwise expressly defined or inferred from the context. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0038] Figure 1 This is a block diagram of a system with a memory system provided in an embodiment of this application. For example... Figure 1 As shown, system 11 can be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a memory system 12 located therein). Figure 1As shown, system 11 may include a host 18 and a memory system 12. The memory system 12 has one or more memory devices 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to and from the memory devices 14.

[0039] In some implementations, controller 16 is coupled to memory device 14 and host 18 and is configured to control memory device 14. For example, controller 16 may be configured to control memory device 14 for operations such as read, erase, and program. Controller 16 may also manage data stored in memory device 14 and communicate with host 18. For example, controller 16 may communicate with external devices (e.g., host 18) according to a specific communication protocol. For example, controller 16 and one or more memory devices 14 may be integrated into a single chip to form memory system 12. As another example, controller 16 and one or more memory devices 14 may be integrated into two separate chips to form memory system 12.

[0040] Figure 2 This is a circuit diagram of a memory cell provided in an embodiment of this application. For example, memory device 14 may include multiple memory cells. Figure 2 As shown, the memory cell 100 may include a first transistor T1 and a second transistor T2. For example, both the first transistor T1 and the second transistor T2 may be metal-oxide-semiconductor field-effect transistors (MOSFETs). For example, the first transistor T1 and / or the second transistor T2 may be NMOS (N-channel metal-oxide-semiconductor transistors). As another example, the first transistor T1 and / or the second transistor T2 may be PMOS (P-channel metal-oxide-semiconductor transistors). The memory cell 100 may also include at least two capacitor cells C. For example, the capacitor cells C may be implemented as ferroelectric capacitor cells. Figure 2 The storage cell 100 is shown as exemplarily comprising two capacitor cells C, but may also comprise three capacitor cells C or more capacitor cells C.

[0041] In the memory cell 100, the first terminal of the second transistor T2 is electrically connected to the second bit line BL2, and the control terminal of the second transistor T2 is electrically connected to the second word line WL2. The first terminals of multiple capacitor cells C are all electrically connected to the second terminal of the second transistor T2, and the first terminals of multiple capacitor cells C are also electrically connected to the control terminal of the first transistor T1. The second terminal of each capacitor cell C is electrically connected to the board line PL. The first terminal of the first transistor T1 is electrically connected to the first bit line BL1, and the second terminal of the first transistor T1 is electrically connected to the first word line WL1. For example, the first word line WL1 is a read word line, and the first bit line BL1 is a read bit line. The second word line WL2 is a write word line, and the second bit line BL2 is a write bit line. In this application, one of the drain or source terminals of the first transistor T1 and / or the second transistor T2 is called the first terminal, and the corresponding other terminal is called the second terminal. The control terminal of the first transistor T1 and / or the second transistor T2 is the gate.

[0042] In this embodiment, a storage cell 100 includes multiple capacitor cells C electrically connected to a first transistor T1 and a second transistor T2. Thus, a storage cell 100 can be used to store multiple bits of data, thereby increasing the storage capacity of each storage cell 100. Alternatively, since multiple capacitor cells C share two transistors T1 and T2, the storage density can be increased by reducing the number of transistors configured in each storage cell 100.

[0043] Will Figure 2 The storage cells 100 shown can be arranged in an array to form a storage cell array. Each storage cell 100 has the same circuit structure. Those skilled in the art can design the arrangement of storage cells 100 and the number of storage cells 100 in the storage cell array according to the storage capacity requirements of the memory devices in the memory system.

[0044] Figure 3 This is a cross-sectional structural schematic diagram of the memory device provided in an embodiment of this application. For example, the memory device may be memory device 14 in the memory system 12 described above (see reference). Figure 1 This is part of the description of the spatial relationships of the components in the memory device. It should be noted that, in the following figures, the x, y, and z directions illustrate the spatial relationships of the components. For example, the z direction is the stacking direction of the first stacked structure, and the x and y directions are two directions perpendicular to each other on a plane perpendicular to the stacking direction. The same concepts will be used throughout this application to describe the spatial relationships of the components in the memory device.

[0045] like Figure 3As shown, the memory device 200 includes a first electrode layer 211. For example, the first electrode layer 211 may extend laterally in a plane perpendicular to the z-direction. Exemplarily, the material of the first electrode layer 211 may be one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material.

[0046] The memory device 200 may further include a first stacked structure 221 located on one side (e.g., the surface) of the first electrode layer 211. The first stacked structure 221 includes alternating first dielectric layers 222 and line-on-line layers 223. Exemplarily, the material of the first dielectric layer 222 may be silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiO2). x N y The material of the board line layer 223 may be one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material. In the first stack structure 221, the thickness of each of the plurality of first dielectric layers 222 may be the same or different, and the thickness of each of the plurality of board line layers 223 may be the same or different. The thicknesses of the first dielectric layers 222 and the board line layers 223 can be selected according to actual needs. Additionally, Figure 3 An exemplary first stack structure 221 is shown to include two board line layers 223. In alternative embodiments, the first stack structure 221 may also include three board line layers 223 or more board line layers 223. This application does not impose any specific limitations on this.

[0047] The memory device 200 also includes a memory pillar 231. The memory pillar 231 penetrates the first stack structure 221 and the first electrode layer 211, and protrudes beyond the first electrode layer 211. For example, the memory pillar 231 may have a generally cylindrical outer contour, and, for example, sequentially penetrate the first stack structure 221 and the first electrode layer 211 along the z-direction, and extend from the first electrode layer 211. The memory pillar 231 includes a memory functional layer 232 and an inner electrode 233 sequentially disposed from the outside in. For example, the memory functional layer 232 may be a generally tubular structure closed at one end, and the closed end of the memory functional layer 232 may be the end extending from the first electrode layer 211. The inner electrode 233 may be embedded inside the memory functional layer 232 and contact the memory functional layer 232.

[0048] In some embodiments, the internal electrode 233 may include a metal pillar 2331 and a semiconductor plug 2332. Exemplarily, the metal pillar 2331 may extend in the z-direction, thereby occupying the inner space of the storage functional layer 232. The semiconductor plug 2332 may be located at the end of the metal pillar 2331 away from the first electrode layer 211. In some examples, the sidewall of the semiconductor plug 2332 contacts the metal layer 2331. In other examples, the sidewall of the semiconductor plug 2332 contacts the storage functional layer 232 (not shown). Exemplarily, the material of the metal pillar 2331 may be one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), or any other suitable metallic material. The material of the semiconductor plug 2332 may be one or more of polysilicon (poly-Si), indium gallium zinc oxide (IGZO), indium tin oxide (ITO), or any other suitable semiconductor material. Optionally, a dopant may be incorporated into the material of the semiconductor plug 2332. For example, the dopant may be of N-type or P-type conductivity, thereby making the semiconductor plug 2332 N-type or P-type conductive. In other embodiments, the internal electrode 233 may have other internal structures. For example, the internal electrode 233 may consist of a conductive layer in contact with the storage functional layer 232 and an insulating pillar located inside the conductive layer (not shown), and this application does not impose specific limitations on this.

[0049] In some embodiments, the material of the storage functional layer 232 may be a ferroelectric material. Ferroelectric materials may include zirconium oxide (ZrO2), hafnium oxide (HfO2), aluminum (Al)-doped HfO2, silicon (Si)-doped HfO2, zirconium (Zr)-doped HfO2, lanthanum (La)-doped HfO2, yttrium (Y)-doped HfO2, and one or more other elements doped with ferroelectric materials. When an electric field is applied to the ferroelectric material layer, the central atoms remain in a low-energy state along with the electric field; conversely, when the electric field is reversed and applied to the ferroelectric material layer, the central atoms move in the direction of the electric field within the crystal and remain in another low-energy state. A large number of central atoms move and couple within the crystal unit cell to form ferroelectric domains, which generate polarization charges under the influence of the electric field. The polarization charge formed when ferroelectric domains reverse under an electric field is high, while the polarization charge formed when ferroelectric domains do not reverse under an electric field is low. This binary stability of ferroelectric materials makes them suitable for use as storage functional layer 232 to store logic information. In other embodiments, the material of storage functional layer 232 can be an antiferroelectric material. Antiferroelectric materials may include lead zirconate (PbZrO3), lead hafnium oxide (PbHfO3), sodium niobate (NaNbO3), ammonium dihydrogen phosphate (NH4H2PO4), ammonium iodate (NH4IO3), tungsten trioxide (WO3), etc. Antiferroelectric materials have better stability, resulting in better data retention characteristics when applied to memory devices. For example, when the material of storage functional layer 232 is a ferroelectric or antiferroelectric material, the memory device 200 can be called a ferroelectric random access memory (FeRAM). It should be noted that the ferroelectric and antiferroelectric materials described above also have insulating properties.

[0050] Continue to refer to Figure 3 The memory device 200 further includes a first channel layer 241. The first channel layer 241 covers the portion of the storage functional layer 232 that protrudes from the first electrode layer 211 and the first electrode layer 211. The material of the first channel layer 241 may be one or more of polysilicon (poly-Si), indium gallium zinc oxide (IGZO), indium tin oxide (ITO), or any other suitable semiconductor material. The memory device 200 may also include a second electrode 242. The second electrode 242 is located on the side of the first channel layer 241 away from the first electrode layer 211 and is electrically connected to the first channel layer 241. For example, the second electrode 242 may have a generally columnar outer profile and contact the first channel layer 241. The material of the second electrode 242 may be one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material.

[0051] In some embodiments, the memory device 200 may further include a first insulating layer 243. The first insulating layer 243 covers the first channel layer 241. Exemplarily, the material of the first insulating layer 243 may be silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiO2). x N y One or more of the following: (or any other suitable insulating material). The second electrode 242 extends through the first insulating layer 243 to the first channel layer 241 to contact the first channel layer 241, thereby electrically connecting the second electrode 242 to the first channel layer 241. The second electrode 242 may be at least partially aligned with the axis of the storage post 231. For example, in the case where the second electrode 242 is generally columnar, the axis of the second electrode 242 generally coincides with the axis of the storage post 231.

[0052] In some embodiments, portions of the first electrode layer 211, the first channel layer 241, the second electrode 242, the inner electrode 233, and the storage function layer 232 protruding from the first stacked structure 221 form a first transistor T1. For example, a portion of the first electrode layer 211 in contact with the first channel layer 241 can serve as the second electrode (e.g., the source) of the first transistor T1, and other portions of the first electrode layer 211 can serve as the first word line WL1 (see reference). Figure 2 The portion of the inner electrode 233 protruding from the first stacked structure 221 can serve as the control terminal (e.g., gate) of the first transistor T1. The portion of the storage layer 232 protruding from the first stacked structure 221 can serve as the gate dielectric layer of the first transistor T1. The second electrode 242 can serve as the first electrode (e.g., drain) of the first transistor T1. In the first transistor T1, the first channel layer 241 surrounds the outer side of the portion of the inner electrode 233 protruding from the first stacked structure 221 to increase the gate length and gate control capability. The first transistor T1 can be a channel-all-around field-effect transistor (CAA FET).

[0053] In some embodiments, the portions of the storage functional layer 232 and the internal electrode 233 that are each surrounded by a board line layer 223, and the portion of the board line layer 223 that contacts the storage functional layer 232, constitute a capacitor cell C. The portion of the internal electrode 233 surrounded by the board line layer 223 serves as the first end of the capacitor cell C, the portion of the board line layer 223 that contacts the storage functional layer 232 serves as the second end of the capacitor cell C, and the remaining portion of the board line layer 223 serves as the board line PL (see reference). Figure 2 ).

[0054] In some embodiments, multiple (e.g., two) capacitor cells C are arranged along the z-direction. The first ends of these capacitor cells C share an internal electrode 233 to achieve electrical connection between them, and the first ends of these capacitor cells C also share an internal electrode 233 with the control terminal of the first transistor T1 to achieve electrical connection with the control terminal of the first transistor T1.

[0055] According to the above embodiments, this application provides a memory cell structure comprising multiple capacitor cells and CAA transistors. This memory cell can reduce the planar area occupied. Simultaneously, since the CAA transistor has a closed-gate structure, the gate length and gate control capability of the transistors in the memory cell can be improved. Furthermore, a self-aligned process can be used to enable the CAA transistor and multiple capacitor cells to share the memory functional layer and internal electrodes, thereby improving the uniformity and consistency of the corresponding structural dimensions in the transistor.

[0056] In some embodiments, the memory device 200 may further include a second stacked structure 251. The second stacked structure 251 may be located on the side of the first stacked structure 221 away from the first electrode layer 211, and includes a gate layer 253 and two second dielectric layers 252 located on opposite sides of the gate layer 253. For example, the two second dielectric layers 252 may include a second dielectric layer 252 on the side of the gate layer 253 away from the first stacked structure 221 and a second dielectric layer 252 on the side of the gate layer 253 close to the first stacked structure 221. Exemplarily, the material of the second dielectric layer 252 may be silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiO2). x N y The gate layer 253 may be one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material. If the second dielectric layer 252 and the first dielectric layer 222 are made of the same material, there may be no obvious interface between them.

[0057] In some embodiments, the memory device 200 further includes a channel structure 261. The channel structure 261 extends through the second stack structure 251 to the memory pillar 231 for connection to the memory pillar 231. The channel structure 261 may include a gate dielectric layer 262 and a second channel layer 263 disposed sequentially from the outside in. The second channel layer 263 is electrically connected to the inner electrode 233, for example, through contact with a semiconductor plug 2332. Exemplarily, the channel structure 261 may have a generally cylindrical outer contour. The gate dielectric layer 262 may be a generally tubular structure open at both ends, and the second channel layer 263 may be located inside the gate dielectric layer 262. In other words, the gate dielectric layer 262 surrounds the outer wall of the second channel layer 263. In some examples, the second channel layer 263 may be a generally columnar structure. In other examples, the second channel layer may be a generally tubular structure with an insulating pillar (not shown) disposed on its inner side. For example, the material of the gate dielectric layer 262 may be silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiO2). x N y The material of the second channel layer 263 may be one or more of polycrystalline silicon (Poly-Si), amorphous silicon (α-Si), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium tin oxide (ITO), or any other suitable insulating material. Optionally, the material of the second channel layer 263 may be doped with a dopant. For example, the dopant may be of N-type or P-type conductivity, thereby making the second channel layer 263 N-type or P-type conductive.

[0058] In some embodiments, the second channel layer 263, the gate dielectric layer 262, and a portion of the gate layer 253 in contact with the gate dielectric layer 262 can constitute a second transistor T2. The second transistor T2 can be a vertical channel transistor. For example, the end of the second channel layer 263 away from the memory pillar 231 can serve as the first electrode of the second transistor T2, the semiconductor plug 2332 can serve as the second electrode of the second transistor T2, a portion of the gate layer 253 in contact with the gate dielectric layer 262 can serve as the gate of the second transistor T2, and the remaining portion of the gate layer 253 serves as the second word line WL2. The second transistor T2, together with the first transistor T1 described above and a plurality of capacitor cells C, can constitute a memory cell.

[0059] In some embodiments, the dopant incorporated into the material of the second channel layer 263 may have a different conductivity type than the dopant incorporated into the material of the semiconductor plug 2332. For example, the material of the second channel layer 263 may be polysilicon with a first conductivity type dopant. The material of the semiconductor plug 2232 may be polysilicon with a second conductivity type dopant. Optionally, the first conductivity type dopant may include boron (B), and the second conductivity type dopant may include phosphorus (P), thereby enabling the second transistor T2 to be an NMOS transistor.

[0060] In some embodiments, the memory device 200 may further include a second insulating layer 271 and a bit line connection structure 272. The second insulating layer 271 may be located on the side of the second stacked structure 251 away from the first stacked structure 221 (e.g., a surface). The bit line connection structure 272 may extend through the second insulating layer 271 and be electrically connected (e.g., in contact) to the second channel layer 263. For example, the bit line connection structure 272 may be generally columnar. The bit line connection structure 272 may be used to extend the second channel layer 263 in the z-direction to connect to a second bit line (not shown). Exemplarily, the material of the bit line connection structure 272 may be one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material.

[0061] In some embodiments, the memory device 200 may further include a gate connection structure 273. The gate connection structure 273 may penetrate the second insulating layer 271 and extend to the gate layer 253. For example, the gate connection structure 273 may be generally columnar. The gate connection structure 273 may be used to lead the gate layer 253 out in the z-direction. Exemplarily, the material of the gate connection structure 273 may be one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material.

[0062] This application also provides a method for manufacturing a memory device. Figure 4 This is a schematic flowchart illustrating a method for manufacturing a memory device according to an embodiment of this application. Figure 4 As shown, the method for manufacturing a memory device 300 (hereinafter referred to as manufacturing method 300) may include the following steps.

[0063] S310, a first electrode layer and a first stacked structure are sequentially formed on a first side of the substrate. The first stacked structure includes an alternately arranged first dielectric layer and a board line layer.

[0064] S320, forming a memory pillar that penetrates the first stacked structure and the first electrode layer and extends toward the substrate, the memory pillar including a memory functional layer and an inner electrode arranged sequentially from the outside to the inside.

[0065] S330, remove the substrate and expose the portion of the first electrode layer and the storage function layer that protrudes from the first electrode layer.

[0066] S340, forming a first channel layer that covers the storage function layer and protrudes from the first electrode layer.

[0067] S350 forms a second electrode that is electrically connected to the first channel layer.

[0068] According to the method for manufacturing a memory device provided in this embodiment, by removing the substrate and exposing the portion of the first electrode layer and the storage functional layer protruding from the first electrode layer, and forming the first channel layer and the second electrode, a structure comprising a memory cell containing multiple capacitor cells and CAA transistors can be formed through a self-aligned process, thereby improving the uniformity and consistency of the corresponding structural dimensions in the transistor. Furthermore, the memory cell can reduce the planar area occupied. Simultaneously, since the CAA transistor is a closed-gate structure, the gate length and gate control capability of the transistors in the memory cell can be improved.

[0069] Figures 5A to 5D This is a cross-sectional structural diagram of the memory device provided in the embodiments of this application during the manufacturing process. For example, the intermediate structure of the memory device during the manufacturing process in this embodiment can be based on... Figure 4 The manufacturing method shown forms, and is used to form Figure 3 The memory device 200 is shown below. (The following is in conjunction with...) Figures 5A to 5D as well as Figure 3 The above steps S310 to S350 are explained.

[0070] In step S310, as Figure 5A As shown, a first dielectric layer 222 and a plate line layer 223 can be alternately formed on the first side of the substrate 212 using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, thereby forming a first stacked structure 221.

[0071] In some embodiments, substrate 212 may be used to support the first stacked structure 221. Exemplarily, substrate 212 may be a semiconductor substrate. For example, the material of substrate 212 may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). Exemplarily, substrate 212 may be a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) substrate, etc.

[0072] In some embodiments, before forming the first electrode layer 211 and the first stacked structure 221, the manufacturing method 200 may further include the step of sequentially forming a stop layer 213 and an insulating material layer 214 on a first side of the substrate 212. Exemplarily, the stop layer 213 and the insulating material layer 214 may be formed before the substrate 212 and the first stacked structure 221 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. For example, the stop layer 213 contacts the substrate 212 and the insulating material layer 214, respectively, and the insulating material layer 214 contacts the stop layer 213 and the first stacked structure 221 (e.g., the first dielectric layer 222), respectively. The materials of the stop layer 213 and the insulating material layer 214 are different from each other, thereby giving them different etch selectivity ratios relative to the same etch material. For example, the material of the insulating material layer 214 may be silicon oxide (SiO2), and the material of the stop layer 213 may be silicon nitride (Si3N4). Furthermore, the thickness of the insulating material layer 214 may be determined according to the second transistor T2 to be formed (reference). Figure 3 The gate length of the second transistor T2 can be adjusted according to the actual needs, and this application does not impose specific restrictions on the thickness of the insulating material layer 214. In other words, the gate length of the second transistor T2 can be controlled by controlling the thickness of the insulating material layer 214, and the process steps are simple.

[0073] In step S320, continue to refer to Figure 5A A memory pillar 231 can be formed by photolithography and etching processes as well as thin film deposition processes, extending through the first stacked structure 221 and the first electrode layer 211 and toward the substrate 212 in a direction (e.g., the z direction). The memory pillar 231 includes a memory functional layer 232 and an inner electrode 233 arranged sequentially from the outside to the inside.

[0074] In some embodiments, when an insulating material layer 214 with a stop layer 213 is formed on a first side of the substrate 212, the memory pillar 231 can sequentially penetrate the first stacked structure 221, the first electrode layer 211, the insulating material layer 214 to the stop layer 213. Exemplarily, the memory pillar 231 can be formed by the manufacturing method described below. First, a memory hole (corresponding to the outer contour of the memory pillar 231) sequentially penetrating the first stacked structure 221, the first electrode layer 211, the insulating material layer 214 to the stop layer 213 can be formed using photolithography and etching (e.g., dry etching or wet etching) processes. Next, a memory functional layer 232 can be formed on the inner wall of the memory hole using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, and an inner electrode 233 can be formed on the inner side of the memory functional layer 232. Optionally, during the formation of the internal electrode 233, a thin film deposition process, such as CVD, PVD, ALD, or any combination thereof, can first be used to fill the inner side of the storage functional layer 232 with metal material to form a metal pillar 2331. Then, a portion of the metal pillar 2331 away from the substrate 212 is etched back to form a semiconductor plug 2332 at the end of the metal pillar 2331 away from the substrate 212, thereby forming the internal electrode 233.

[0075] In some embodiments, a second stacked structure 251 may be formed on the side of the first stacked structure 221 away from the substrate 212 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The second stacked structure 251 may include a gate layer 253 and a second dielectric layer 252 located on the side of the gate layer 253 away from the first stacked structure 221. Exemplarily, a second dielectric layer 252, a gate layer 253, and another second dielectric layer 252 may be sequentially formed on the surface of the first stacked structure 221 away from the substrate 212, such that the second dielectric layers 252 are located on opposite sides of the gate layer 253.

[0076] In some embodiments, a channel structure 261 extending through the second stacked structure 251 to the memory pillar 231 can be formed using photolithography and etching processes as well as thin film deposition processes. The channel structure 261 may include a gate dielectric layer 262 and a second channel layer 263 sequentially disposed from the outside in, the second channel layer 263 being electrically connected (e.g., contacting) to an internal electrode 233 (e.g., a semiconductor plug 2332). Exemplarily, the channel structure 261 can be formed using the manufacturing method described below. First, a channel hole (corresponding to the outer contour of the channel structure 261) extending through the second stacked structure 251 to the memory pillar 231 can be formed using photolithography and etching processes (e.g., dry etching or wet etching). Next, a thin film deposition process, such as CVD, PVD, ALD, or any combination thereof, can be used to form the gate dielectric layer 262 on the sidewall of the channel hole, and the second channel layer 263 can be formed inside the gate dielectric layer 262. Alternatively, a second channel layer may be formed on the sidewall of the gate dielectric layer 262, and an insulating pillar (not shown) may be formed on the inner side of the second channel layer.

[0077] In some embodiments, a second insulating layer 271 may be formed on the side of the second stacked structure 251 away from the first stacked structure 221 using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. Further, a bit line interconnect structure 272 extending through the second insulating layer 271 to the second channel layer 263 may be formed using photolithography and etching processes as well as thin film deposition processes. Optionally, a gate interconnect structure 273 extending through the second insulating layer 271 and reaching the gate layer 253 may also be formed using photolithography and etching processes as well as thin film deposition processes.

[0078] In step S330, as Figure 5A and Figure 5B As shown, the substrate 212 can be removed by etching (e.g., wet etching and / or dry etching) processes, exposing the portion of the first electrode layer 211 and the storage functional layer 232 in the storage pillar 231 that protrudes from the first electrode layer 211.

[0079] In some embodiments, where an insulating material layer 214 of a stop layer 213 is formed on a first side of the substrate 212, after removing the substrate 212, the stop layer 213 and the insulating material layer 214 may be further removed by an etching process (e.g., wet etching and / or dry etching) to expose the portion of the first electrode layer 211 and the storage function layer 232 that protrudes from the first electrode layer 211.

[0080] In step S340, as Figure 5B and Figure 5CAs shown, a first channel layer 241, which covers the storage functional layer 232 and protrudes from the first electrode layer 211, can be formed using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. For example, the first channel layer 241 also covers the surface of the first electrode layer 211.

[0081] In step S350, as Figure 3 As shown, a second electrode 242 electrically connected (e.g., in contact) to the first channel layer 241 can be formed using photolithography and etching processes as well as thin film deposition processes. Exemplarily, the second electrode 242 can be formed by the manufacturing method described below. First, as... Figure 5C and Figure 5D As shown, a first insulating layer 243 covering the first channel layer 241 can be formed using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. Next, a contact hole (corresponding to the outer contour of the second electrode 242) extending through the first insulating layer 243 to the first channel layer 241 can be formed using photolithography and etching (e.g., dry etching or wet etching), wherein the contact hole is at least partially aligned with the axis of the memory pillar 231. For example, the axis of the contact hole substantially coincides with the axis of the memory pillar 231. Then, the contact hole is filled with one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material to form the second electrode 242.

[0082] It should be noted that the steps described above for forming the second stacked structure 251, the second insulating layer 271, the bit line connection structure 272, and the gate connection structure 273 can be formed after the second electrode 242 is formed, and this application does not impose any specific limitations on this.

[0083] In this embodiment, by removing the substrate and exposing the portion of the first electrode layer and the storage functional layer protruding from the first electrode layer, and forming the first channel layer and the second electrode, a structure comprising a storage cell containing multiple capacitor cells and CAA transistors can be formed through a self-aligned process, thereby improving the uniformity and consistency of the corresponding structural dimensions in the transistor. Furthermore, this storage cell can reduce the planar area occupied. Simultaneously, since the CAA transistor is a closed-gate structure, the gate length and gate control capability of the transistors in the storage cell can be improved.

[0084] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A memory device, characterized in that, include: First electrode layer; A first stacked structure is located on one side of the first electrode layer and includes alternating first dielectric layers and board line layers; A storage column penetrates the first stacked structure and the first electrode layer, and protrudes beyond the first electrode layer. The storage column includes a storage function layer and an inner electrode arranged sequentially from the outside to the inside. The first channel layer covers the portion of the storage function layer that protrudes from the first electrode layer and the first electrode layer; as well as The second electrode is located on the side of the first channel layer away from the first electrode layer and is electrically connected to the first channel layer.

2. The memory device according to claim 1, wherein, The first electrode layer, the first channel layer, the second electrode, the inner electrode, and the storage function layer each protrude from the portion of the first stacked structure to form a transistor.

3. The memory device according to claim 2, wherein, The storage function layer and the internal electrode are respectively associated with a portion of a board line layer, and the board line layer forms a capacitor unit.

4. The memory device according to claim 3, wherein, The plurality of capacitor cells are arranged along the stacking direction of the first stacked structure, and the plurality of capacitor cells and the transistor share the storage function layer and the internal electrode.

5. The memory device according to claim 1, wherein, It also includes a first insulating layer covering the first channel layer, wherein the second electrode passes through the first insulating layer to the first channel layer, and the second electrode is at least partially aligned with the axis of the storage column.

6. The memory device according to claim 1, wherein, Also includes: The second stacked structure is located on the side of the first stacked structure away from the first electrode layer, and includes a gate layer and a second dielectric layer located on the side of the gate layer away from the first stacked structure. as well as The channel structure extends through the second stack structure to the memory pillar and includes a gate dielectric layer and a second channel layer arranged sequentially from the outside to the inside, the second channel layer being electrically connected to the inner electrode.

7. The memory device according to claim 6, wherein, Also includes: The second insulating layer is located on the side of the second stacked structure away from the first stacked structure; as well as The bit line connection structure penetrates the second insulating layer and is electrically connected to the second channel layer.

8. The memory device according to claim 7, wherein, Also includes: A gate connection structure extends through the second insulating layer and into the gate layer.

9. The memory device according to claim 6, wherein, The material of the second channel layer includes a semiconductor with a first conductivity type dopant, the internal electrode includes a metal pillar and a semiconductor plug, the material of the semiconductor plug includes a semiconductor with a second conductivity type dopant, and the second channel layer is in contact with the semiconductor plug.

10. The memory device according to any one of claims 1 to 9, wherein, The materials used in the storage functional layer include ferroelectric materials and antiferroelectric materials.

11. A memory system, characterized in that, include: The memory device as described in any one of claims 1 to 10; as well as A controller, coupled to the memory device, is used to control the memory device to store data.

12. A method for manufacturing a memory device, characterized in that, include: A first electrode layer and a first stacked structure are sequentially formed on a first side of the substrate. The first stacked structure includes an alternately arranged first dielectric layer and a plate line layer. A memory pillar is formed that penetrates the first stacked structure and the first electrode layer and extends toward the substrate. The memory pillar includes a memory functional layer and an inner electrode arranged sequentially from the outside to the inside. as well as Remove the substrate and expose the portion of the first electrode layer and the storage function layer that protrudes from the first electrode layer; A first channel layer is formed that covers the storage function layer and protrudes from the first electrode layer; as well as A second electrode is formed that is electrically connected to the first channel layer.

13. The manufacturing method according to claim 12, wherein, Before sequentially forming a first electrode layer and a first stacked structure on a first side of the substrate, the method further includes: A stop layer and an insulating material layer are sequentially formed on the first side of the substrate; The storage pillars forming the first stacked structure and the first electrode layer and extending toward the substrate include: The storage column is formed sequentially through the first stacked structure, the first electrode layer, the insulating material layer to the stop layer.

14. The manufacturing method according to claim 13, wherein, The storage pillar, which sequentially extends through the first stacked structure, the first electrode layer, the insulating material layer, and the stop layer, comprises: A storage hole is formed that sequentially penetrates the first stacked structure, the first electrode layer, the insulating material layer, and the stop layer; The storage functional layer and the internal electrode are formed sequentially within the storage hole.

15. The manufacturing method according to claim 13, wherein, Removing the substrate and exposing the portion of the first electrode layer and the storage function layer protruding from the first electrode layer includes: Remove the substrate, the stop layer, and the insulating material layer to expose the portion of the first electrode layer and the storage function layer that protrudes from the first electrode layer.

16. The manufacturing method according to claim 12, wherein, The second electrode, which is electrically connected to the first channel layer, includes: Forming a first insulating layer covering the first channel layer; and A second electrode is formed extending through the first insulating layer to the first channel layer, and the second electrode is at least partially aligned with the axis of the storage column.

17. The manufacturing method according to claim 12, wherein, Also includes: A second stacked structure is formed on the side of the first stacked structure away from the substrate, the second stacked structure including a gate layer and a second dielectric layer located on the side of the gate layer away from the first stacked structure; as well as A channel structure is formed that extends through the second stack structure to the memory pillar. The channel structure includes a gate dielectric layer and a second channel layer arranged sequentially from the outside to the inside. The second channel layer is electrically connected to the internal electrode.

18. The manufacturing method according to claim 17, wherein, Also includes: A second insulating layer is formed on the side of the second stacked structure away from the first stacked structure; as well as A bit line connection structure is formed that extends from the second insulating layer to the second channel layer.

19. The manufacturing method according to claim 18, wherein, Also includes: A gate connection structure is formed that penetrates the second insulating layer and extends to the gate layer.

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