Semiconductor structure and method of forming the same, memory system

Abstract

The present disclosure provides a semiconductor structure, a method for forming the semiconductor structure, and a memory system, the semiconductor structure comprising an active layer, an electrostatic protection structure, and a pad on the active layer; wherein the electrostatic protection structure comprises at least one transistor structure, the transistor structure comprising a gate structure, and a first electrode region, a channel region, and a second electrode region in the active layer and arranged along a first direction, the gate structure being on the channel region; the first direction being perpendicular to a second direction; the second direction being a thickness direction of the active layer; and the pad being connected to the first electrode region or the second electrode region of the transistor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same, and a memory system. Background Technology

[0002] With the continuous development of semiconductor chip manufacturing processes and the increasing integration of circuits, the withstand voltage capability of electronic components is decreasing, making electrostatic discharge (ESD) increasingly harmful to chips. Therefore, it is necessary to protect chips from electrostatic discharge, and a common method is to incorporate ESD protection circuits into the chip.

[0003] However, as the requirements for the integration of semiconductor chips continue to increase, how to set up electrostatic discharge protection circuits to improve the damage of semiconductor chips caused by electrostatic discharge has become an urgent problem to be solved. Summary of the Invention

[0004] In view of the above, this disclosure provides a semiconductor structure and a method for forming the same, as well as a memory system, to solve at least one problem existing in the prior art.

[0005] To achieve the above objectives, the technical solution of this disclosure embodiment is implemented as follows:

[0006] In a first aspect, embodiments of this disclosure provide a semiconductor structure, including an active layer, an electrostatic discharge (ESD) protection structure, and pads located on the active layer; wherein...

[0007] The electrostatic protection structure includes at least one transistor structure, the transistor structure including a gate structure and a first electrode region, a channel region, and a second electrode region located in the active layer and arranged along a first direction, the gate structure being located on the channel region; the first direction is perpendicular to the second direction; the second direction is the thickness direction of the active layer;

[0008] The pad is connected to the first electrode region or the second electrode region of the transistor structure.

[0009] In one optional embodiment, the semiconductor structure further includes:

[0010] The power line and the ground line are located on the active layer, and the power line and the ground line are respectively located on opposite sides of the pad along the first direction.

[0011] In one alternative embodiment, the electrostatic protection structure includes one of the transistor structures;

[0012] The transistor structure is located between the power line and the pad, the first electrode region and the gate structure of the transistor structure are connected to the power line, and the second electrode region of the transistor structure is connected to the pad;

[0013] or,

[0014] The transistor structure is located between the pad and the ground line. The first electrode region and the gate structure of the transistor structure are connected to the pad, and the second electrode region of the transistor structure is connected to the ground line.

[0015] In one optional embodiment, the electrostatic discharge (ESD) protection structure includes a plurality of transistor structures connected in series and arranged along the first direction; the ESD protection structure includes a first end and a second end opposite to each other along the first direction, the first end being close to the power line and the second end being close to the ground line;

[0016] The electrostatic discharge (ESD) protection structure is located between the power line and the ground line; the first electrode region and gate structure of the transistor structure at the first end are connected to the power line; the second electrode region of the transistor structure at the second end is connected to the ground line; the pad is connected to the first electrode region and gate structure of the transistor structure closest to the ground line among the two transistor structures closest to the pad in the ESD protection structure, and the second electrode region of the other transistor structure is connected.

[0017] or,

[0018] The electrostatic protection structure is located between the pad and the grounding wire; the first electrode region and gate structure of the transistor structure located at the first end are connected to the pad; the second electrode region of the transistor structure located at the second end is connected to the grounding wire.

[0019] or,

[0020] The electrostatic protection structure is located between the power line and the pad; the first electrode region and gate structure of the transistor structure at the first end are connected to the power line; the second electrode region of the transistor structure at the second end is connected to the pad.

[0021] In one alternative implementation, the first electrode region of the transistor structure and the second electrode region of the transistor structure closer to the power line in one of the two adjacent transistor structures are shared.

[0022] The second electrode region of the transistor structure is shared with the first electrode region of the transistor structure closer to the ground wire in the two adjacent transistor structures.

[0023] In one optional embodiment, the semiconductor structure further includes:

[0024] A conductive line located on the active layer; the conductive line is located between the pad and the power line and / or between the pad and the ground line in the first direction; the conductive line is connected to a first electrode region and a gate structure of a transistor structure.

[0025] In one optional embodiment, the gate structure includes a gate layer and a dielectric layer, and the semiconductor structure further includes:

[0026] An isolation layer is located on the active layer; the dielectric layer is located between the isolation layer and the active layer; the gate layer is located in the isolation layer; the pads, the power lines, and the ground lines are all located on the isolation layer.

[0027] In one optional embodiment, the semiconductor structure further includes:

[0028] A plurality of first contact structures extending through the dielectric layer and the isolation layer along the second direction; one end of the first contact structure along the second direction is connected to the first electrode region or the second electrode region, and the other end of the first contact structure along the second direction is connected to one of the pad, the power line and the ground line.

[0029] In one alternative embodiment, the semiconductor structure includes a plurality of active layers, each of the active layers extending along the first direction;

[0030] The pads are located on the plurality of active layers; each active layer has at least one transistor structure.

[0031] In one optional embodiment, the semiconductor structure further includes:

[0032] A stacked structure located on the side of the active layer opposite each other along the second direction, away from the pad;

[0033] A plurality of channel structures extending along the second direction and penetrating the stacked structure; the channel structures are connected to the active layer.

[0034] In one optional embodiment, the semiconductor structure further includes:

[0035] The peripheral circuit portion is located on one side of the stacked structure opposite each other along the second direction, away from the pad.

[0036] In a second aspect, embodiments of this disclosure provide a memory system, including:

[0037] At least one semiconductor structure as described in any of the foregoing embodiments;

[0038] A controller is coupled to the semiconductor structure and configured to control the semiconductor structure.

[0039] Thirdly, embodiments of this disclosure provide a method for forming a semiconductor structure, including:

[0040] Provide an active layer;

[0041] A pad is formed on the active layer, and an electrostatic discharge (ESD) protection structure is formed thereon. The ESD protection structure includes at least one transistor structure, which includes a gate structure and a first electrode region, a channel region, and a second electrode region located in the active layer and arranged along a first direction. The gate structure is located on the channel region. The pad is connected to the first electrode region or the second electrode region of the transistor structure. The first direction is perpendicular to the second direction. The second direction is the thickness direction of the active layer.

[0042] In one optional embodiment, the method for forming the semiconductor structure further includes:

[0043] A power line and a ground line are formed on the active layer; the power line and the ground line are respectively located on opposite sides of the pad along the first direction.

[0044] In one optional embodiment, the method for forming the semiconductor structure further includes:

[0045] Conductive lines are formed on the active layer; the conductive lines are located between the pads and the power lines and / or between the pads and the ground lines in the first direction; each conductive line is connected to a first electrode region and a gate structure of a transistor structure.

[0046] In one alternative embodiment, forming the electrostatic protection structure includes:

[0047] A dielectric layer and an isolation layer are formed on the active layer; the dielectric layer is located between the isolation layer and the active layer;

[0048] A gate layer is formed in the isolation layer; the gate layer and the dielectric layer constitute the gate structure.

[0049] In one optional embodiment, the method for forming the semiconductor structure further includes:

[0050] A plurality of first contact structures are formed that penetrate the dielectric layer and the isolation layer along the second direction; one end of the first contact structure along the second direction is connected to the first electrode region or the second electrode region;

[0051] The process of forming pads, power lines, and ground lines on the active layer includes:

[0052] The pads, the power lines, and the ground lines are formed on the isolation layer; one end of the first contact structure along the second direction is connected to one of the pads, the power lines, and the ground lines.

[0053] In one optional embodiment, the method for forming the semiconductor structure further includes:

[0054] A stacked structure is formed along the second direction;

[0055] Forming a plurality of channel structures that penetrate the stacked structure along the second direction;

[0056] The active layer is formed on one of the two opposite sides of the stacked structure along the second direction; the active layer is connected to the channel structure.

[0057] In one optional embodiment, the method for forming the semiconductor structure further includes:

[0058] A peripheral circuit portion is formed on the other side of the two opposite sides of the stacked structure along the second direction.

[0059] In the technical solution provided in this disclosure, an electrostatic discharge (ESD) protection structure connected to the pads is provided in the semiconductor structure including the active layer. The ESD protection structure includes at least one transistor structure. The first electrode region, channel region, and second electrode region of the transistor structure are all disposed in the active layer. The gate structure of the transistor structure is disposed on the active layer. The two ends of the ESD protection structure are respectively connected to the power supply line and the ground line. Thus, the static electricity generated on the pads can be discharged to the power supply end or the ground end through the ESD protection structure, without entering the interior of the semiconductor structure. This can alleviate the damage caused by high voltage static electricity to the memory array structure and other circuit structures, and effectively improve the reliability and yield of the semiconductor structure. Attached Figure Description

[0060] Figure 1 Top view of the semiconductor structure provided in the embodiments of this disclosure Figure 1 ;

[0061] Figure 2 Cross-section of a semiconductor structure provided in an embodiment of this disclosure Figure 1 ;

[0062] Figure 3 This is a schematic diagram of the circuit structure provided in the embodiments of this disclosure;

[0063] Figure 4 Cross-section of a semiconductor structure provided in an embodiment of this disclosure Figure 2 ;

[0064] Figure 5 Cross-section of a semiconductor structure provided in an embodiment of this disclosure Figure 3 ;

[0065] Figure 6 Cross-section of a semiconductor structure provided in an embodiment of this disclosure Figure 4 ;

[0066] Figure 7 Cross-section of a semiconductor structure provided in an embodiment of this disclosure Figure 5 ;

[0067] Figure 8 Top view of the semiconductor structure provided in the embodiments of this disclosure Figure 2 ;

[0068] Figure 9 Cross-section of a semiconductor structure provided in an embodiment of this disclosure Figure 6 ;

[0069] Figure 10 A schematic diagram of a memory system provided in an embodiment of this disclosure;

[0070] Figure 11 A schematic flowchart illustrating a method for forming a semiconductor structure according to an embodiment of this disclosure;

[0071] Figure 12 Structural schematic diagram of the semiconductor structure formation process provided in the embodiments of this disclosure Figure 1 ;

[0072] Figure 13 Structural schematic diagram of the semiconductor structure formation process provided in the embodiments of this disclosure Figure 2 ;

[0073] Figure 14 Structural schematic diagram of the semiconductor structure formation process provided in the embodiments of this disclosure Figure 3 . Detailed Implementation

[0074] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0075] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0076] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0077] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0078] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0079] With the continuous development of semiconductor chip manufacturing processes and the increasing integration of circuits, the withstand voltage capability of electronic components is decreasing, making electrostatic discharge (ESD) increasingly harmful to chips. Therefore, ESD protection for chips is necessary, and a common method is to incorporate ESD protection circuits into the chip.

[0080] In some embodiments, for a three-dimensional memory comprising a vertically arranged peripheral circuit and a memory array structure, an electrostatic discharge (ESD) protection circuit is typically provided in the peripheral circuit. However, in a three-dimensional memory, the side of the memory array structure furthest from the peripheral circuit has lead-out pads. When performing electrical tests on the three-dimensional memory, a probe needs to be used to contact the lead-out pads to apply an electrical signal to the three-dimensional memory. When the tip of the probe contacts the lead-out pad, ESD is easily triggered. Since this location is far from the ESD protection circuit in the peripheral circuit, the static electricity cannot be discharged in time, which may enter the interior of the three-dimensional memory and damage the memory array structure and other circuit structures, potentially leading to product scrap and consequently reducing production efficiency and product yield.

[0081] Therefore, there is a need to further optimize the electrostatic discharge (ESD) protection architecture in three-dimensional memory. The present disclosure proposes the following implementation methods.

[0082] This disclosure provides a semiconductor structure including an active layer, an electrostatic discharge (ESD) protection structure, and pads located on the active layer; wherein the ESD protection structure includes at least one transistor structure, the transistor structure including a gate structure and a first electrode region, a channel region, and a second electrode region located in the active layer and arranged along a first direction, the gate structure being located on the channel region; the pads are connected to the first electrode region or the second electrode region of the transistor structure; the first direction is perpendicular to the second direction, the second direction being the thickness direction of the active layer.

[0083] In this embodiment of the disclosure, the active layer in the semiconductor structure is used as the setting area of ​​the channel region and electrode region of the transistor structure, and the gate structure of the transistor structure is set on the active layer to form an electrostatic discharge protection structure including at least one transistor structure. The electrostatic discharge protection structure is connected to the pad, thereby dissipating the static electricity generated at the pad, reducing the risk of static electricity generated at the pad entering the semiconductor structure and damaging the memory array structure and other circuit structures, and effectively improving the reliability and yield of the semiconductor structure.

[0084] Figure 1 This is a top view of a semiconductor structure provided in an embodiment of the present disclosure. Figure 2 for Figure 1 Cross-sectional view along line AA', in conjunction with reference Figure 1 and Figure 2The semiconductor structure includes an active layer 101, an electrostatic discharge (ESD) protection structure 100, and pads 301 located on the active layer 101. The ESD protection structure 100 includes a plurality of transistor structures 200, each transistor structure 200 including a gate structure 201 and a first electrode region 102, a channel region 103, and a second electrode region 104 located in the active layer 101 and arranged along a first direction. The gate structure 201 is located on the channel region 103. The pads 301 are connected to the first electrode region 102 or the second electrode region 104 of the transistor structure 200.

[0085] In this embodiment of the disclosure, the first direction is perpendicular to the second direction, and the second direction is the thickness direction of the active layer 101. Here, the first direction is the X direction, and the second direction is the Z direction.

[0086] In some embodiments, the semiconductor structure further includes a power line 302 and a ground line 303 located on the active layer 101, wherein the power line 302 and the ground line 303 are located on opposite sides of the pad 301 along a first direction.

[0087] In this embodiment of the disclosure, the power line 302 is a conductive line coupled to the power supply terminal and can provide a power supply voltage VCC to the circuit structure connected thereto; the ground line 303 is a conductive line coupled to the ground terminal and can provide a ground voltage VSS to the circuit structure connected thereto.

[0088] In a specific example, such as Figure 1 As shown, both the power line 302 and the ground line 303 extend along a third direction, which is the Y direction.

[0089] In this embodiment, the electrostatic discharge (ESD) protection structure 100 comprises a plurality of transistor structures 200 connected in series and arranged along a first direction. The first electrode region 102, channel region 103, and second electrode region 104 of each transistor structure 200 are located in the active layer 101, and adjacent transistor structures 200 share a single electrode region. Specifically, the first electrode region 102 of a transistor structure 200 is shared with the second electrode region 104 of the transistor structure 200 adjacent to it that is closer to the power line 302; the second electrode region 104 of a transistor structure 200 is shared with the first electrode region 102 of the transistor structure 200 adjacent to it that is closer to the ground line 303. Figure 2 As shown, a transistor structure 200 includes two electrode regions. The electrode region closer to the power line 302 is the first electrode region 102 of the transistor structure 200, and the electrode region closer to the ground line 303 is the second electrode region 104 of the transistor structure 200.

[0090] In some specific examples, the active layer 101 can be a heavily doped semiconductor material, such as N-type doped polysilicon. Therefore, the active layer 101 can be used as a high-voltage N-well of the transistor structure 200. P-type doping of the active layer 101 can form a first electrode region 102 and a second electrode region 104 in the active layer 101.

[0091] It should be noted that in this embodiment, the first electrode region 102 is the source region and the second electrode region 104 is the drain region.

[0092] In this embodiment of the disclosure, reference is made to Figure 2 The gate structure 201 of the transistor structure 200 includes a gate layer 202 and a dielectric layer 203 located on the active layer 101. The dielectric layer 203 is located between the active layer 101 and the gate layer 202. One gate structure 201 and two electrode regions located in the active layer 101 constitute a transistor structure 200. The active layer 101 located between the first electrode region 102 and the second electrode region 104 and directly below the gate structure 201 constitutes the channel region 103 of the transistor structure 200. Here, taking the electrostatic discharge protection structure 100 as an example, which includes six transistor structures 200 connected in series and arranged along a first direction.

[0093] In some embodiments, the semiconductor structure further includes: an isolation layer 204 located on the active layer 101, a dielectric layer 203 located between the isolation layer 204 and the active layer 101, a gate layer 202 located in the isolation layer 204, and pads 301, power lines 302 and ground lines 303 all located on the isolation layer 204.

[0094] In some embodiments, the semiconductor structure further includes a plurality of first contact structures 205 extending through the dielectric layer 203 and the isolation layer 204 along a second direction, wherein one end of the first contact structure 205 along the second direction is connected to the first electrode region 102 or the second electrode region 104, and the other end of the first contact structure 205 along the second direction is connected to one of the pad 301, the power line 302 and the ground line 303.

[0095] In some embodiments, the semiconductor structure further includes a plurality of second contact structures (not shown in the figure) extending through the dielectric layer 203 and the isolation layer 204 along a second direction, wherein the two ends of the second contact structures along the second direction are respectively connected to the pad 301 and the active layer 101 to enable the extraction of the active layer 101.

[0096] In some specific examples, the material of the gate layer 202 can be at least one of doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metallic materials (e.g., tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.); the material of the dielectric layer 203 can be silicon oxide, hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, etc. The material can be at least one of the following: strontium titanium, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate; the material of the isolation layer 204 can be at least one of the following: silicon nitride, silicon oxide, and silicon oxynitride; the material of the first contact structure 205 can be at least one of the following: doped semiconductor material (e.g., doped silicon, doped germanium, etc.), conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), metallic material (e.g., tungsten, titanium, tantalum, etc.), and metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0097] In one specific example, the gate layer 202 is made of titanium nitride, the dielectric layer 203 is made of silicon oxide, the isolation layer 204 is made of silicon nitride, and the first contact structure 205 is made of tungsten.

[0098] In this embodiment, the electrostatic discharge (ESD) protection structure 100 is located between the power line 302 and the ground line 303. The ESD protection structure 100 includes a first end and a second end opposite to each other along a first direction. The first electrode region 102 and gate structure 201 of the transistor structure 200 located at the first end are connected to the power line 302. The second electrode region 104 of the transistor structure 200 located at the second end is connected to the ground line 303. The pad 301 is connected to the first electrode region 102 and gate structure 201 of the two transistor structures 200 closest to the pad 301 in the ESD protection structure 100 that are closest to the ground line 303. The second electrode region 104 of the other transistor structure 200 is also connected. Here, the two transistor structures 200 closest to the pad 301 share a common electrode region; therefore, the electrode regions connected to the pad 301 are the first electrode region 102 of one transistor structure 200 and the second electrode region 104 of the other transistor structure 200.

[0099] In some embodiments, the semiconductor structure further includes a conductive line 304 located on the active layer 101. The conductive line 304 is located in a first direction between the pad 301 and the power line 302 or between the pad 301 and the ground line 303. The conductive line 304 is connected to the first electrode region 102 and the gate structure 201 of a transistor structure 200.

[0100] In this embodiment of the disclosure, the first electrode region 102 of the transistor structure 200 and the gate structure 201 are electrically connected, such as... Figure 2 As shown, for the transistor structure 200 located at the first end of the electrostatic protection structure 100, its first electrode region 102 and gate structure 201 are electrically connected through the power line 302 and the first contact structure 205. For the transistor structure 200 closest to the ground line 303 among the two transistor structures 200 closest to the pad 301, its first electrode region 102 and gate structure 201 are electrically connected through the pad 301 and the first contact structure 205. For the other transistor structures 200 in the electrostatic protection structure 100, their first electrode region 102 and gate structure 201 are electrically connected through the conductive line 304 and the first contact structure 205.

[0101] In some specific examples, the pads 301, power lines 302, ground lines 303, and conductive lines 304 have the same dimensions in the second direction. The materials of the pads 301, power lines 302, ground lines 303, and conductive lines 304 can also be the same, and can be at least one of the following metal materials: tungsten, copper, nickel, aluminum, silver, gold, titanium, etc.

[0102] In some embodiments, Figure 3 A schematic diagram of an electrostatic discharge (ESD) protection circuit corresponding to the semiconductor structure in the above embodiments is shown below. Figure 3 As shown, the electrostatic discharge (ESD) protection circuit includes multiple PMOS transistors connected in series between the power supply terminal and the ground terminal. One PMOS transistor corresponds to one transistor structure 200 in the above embodiment. Current I represents the current flowing from the pad 301 into the interior of the semiconductor structure. Taking the coupling point between current I and the ESD protection circuit as the dividing point, the ESD protection circuit can be divided into region A and region B. The coupling point between current I and the ESD protection circuit corresponds to the connection point between the pad 301 and the ESD protection structure 100 in the above embodiment.

[0103] In some specific examples, when static electricity is generated on the pad 301, a high voltage will be generated in the direction of the current I. When the high voltage is the positive voltage V1 and the difference between the power supply voltage VCC and V1 is less than the sum of the threshold voltages VA of the multiple PMOS transistors in region A, that is, VCC - V1 < VA, the multiple PMOS transistors in region A are turned on, and the static electricity charge can be discharged to the power supply terminal through the circuit in region A. At this time, the multiple PMOS transistors in region B remain in the off state; when the high voltage is the negative voltage V2 and the difference between V2 and the ground voltage VSS is less than the sum of the threshold voltages VB of the multiple PMOS transistors in region B, that is, V2 - VSS < VB, the multiple PMOS transistors in region B are turned on, and the static electricity charge can be discharged to the ground terminal through the circuit in region B. At this time, the multiple PMOS transistors in region A remain in the off state. That is to say, when the magnitude of the voltage V in the direction of the current I satisfies VSS + VB ≤ V ≤ VCC - VA, the electrostatic protection circuit will not be triggered. When static electricity is generated on the pad 301, causing the voltage in the direction of the current I to exceed this voltage range, the electrostatic protection circuit will be triggered and discharge the static electricity charge to the power supply terminal or the ground terminal to reduce the risk that high voltage enters the interior of the semiconductor structure and causes the circuit structure inside the semiconductor structure to fail due to the high voltage.

[0104] In the embodiments of the present disclosure, the number of transistor structures 200 in the electrostatic protection structure 100 or the threshold voltage of a single transistor structure 200 can be changed to change VA or VB, so that the voltage range for triggering the electrostatic protection circuit can be changed. For example, for Figure 1 and Figure 2 the semiconductor structure shown, without changing the threshold voltage of a single transistor structure 200, the voltage range for triggering the electrostatic protection circuit can be changed by increasing or decreasing the number of transistor structures 200, or, without changing the number of transistor structures 200, the voltage range for triggering the electrostatic protection circuit can be changed by changing the thickness of the dielectric layer 203 or the aspect ratio of the channel region 103 in the transistor structure 200. It can be understood that for multiple series-connected transistor structures 200, the more the number of transistor structures 200, the greater the sum of the threshold voltages of the multiple transistor structures 200. For a single transistor structure 200, the thicker its dielectric layer 203 or the smaller the aspect ratio of the channel region 103, the greater its threshold voltage. Here, the aspect ratio of the channel region 103 refers to the ratio of the dimension of the channel region in the Y direction to the dimension of the channel region in the X direction.

[0105] The above embodiments take the electrostatic protection structure 100 including multiple transistor structures 200 located between the power supply line 302 and the ground line 303 as an example. In other embodiments, in order to control the production cost and the area occupied by the electrostatic protection structure 100, the electrostatic protection structure 100 may also only include one transistor structure 200.

[0106] In a specific example, refer to Figure 4 The electrostatic discharge protection structure 100 includes a transistor structure 200 located between the power line 302 and the pad 301. The first electrode region 102 and the gate structure 201 of the transistor structure 200 are connected to the power line 302, and the second electrode region 104 of the transistor structure 200 is connected to the pad 301.

[0107] In another specific example, refer to Figure 5 The electrostatic discharge protection structure 100 includes a transistor structure 200 located between the ground line 303 and the pad 301. The first electrode region 102 and the gate structure 201 of the transistor structure 200 are connected to the pad 301, and the second electrode region 104 of the transistor structure 200 is connected to the ground line 303.

[0108] It should be noted that, in Figure 4 and Figure 5 In the figure, transistor structure 200 constitutes electrostatic discharge protection structure 100, and the markings for electrostatic discharge protection structure 100 are omitted.

[0109] In other embodiments, the electrostatic protection structure 100 includes a plurality of transistor structures 200 located between the pad 301 and the power line 302, or includes a plurality of transistor structures 200 located between the pad 301 and the ground line 303.

[0110] In a specific example, refer to Figure 6 The electrostatic protection structure 100 is located between the power line 302 and the pad 301; the first electrode region 102 and the gate structure 201 of the transistor structure 200 located at the first end are connected to the power line 302; the second electrode region 104 of the transistor structure 200 located at the second end is connected to the pad 301.

[0111] In another specific example, refer to Figure 7 The electrostatic protection structure 100 is located between the pad 301 and the ground line 303; the first electrode region 102 and the gate structure 201 of the transistor structure 200 located at the first end are connected to the pad 301; the second electrode region 104 of the transistor structure 200 located at the second end is connected to the ground line 303.

[0112] It should be noted that, Figures 4 to 7 The semiconductor structure shown can function as... Figure 1 and Figure 2 The semiconductor structures shown have similar functions, which will not be elaborated here.

[0113] In some embodiments, a pad 301 may be connected to multiple active layers 101, and an electrostatic discharge protection structure 100 is provided on each active layer 101.

[0114] In a specific example, refer to Figure 8 The pad 301 is connected to three active layers 101, and each active layer 101 is provided with at least one transistor structure 200. Thus, the static electricity generated on the pad 301 can be discharged through multiple electrostatic discharge protection structures 100, thereby increasing the reliability of electrostatic discharge protection.

[0115] In some embodiments, the semiconductor structure further includes: a stacked structure located on the side of the active layer 101 opposite each other along the second direction away from the pad 301; and a plurality of channel structures extending along the second direction and penetrating the stacked structure, wherein the channel structures are connected to the active layer.

[0116] In some embodiments, the semiconductor structure further includes a peripheral circuit portion located on the side of the stacked structure opposite each other along the second direction that is away from the pad 301.

[0117] In some specific examples, refer to Figure 9 The stacked structure 400 is located on the side of the active layer 101 opposite each other along the second direction, away from the pad 301. The channel structure 401 extends along the second direction and penetrates the stacked structure 400. The stacked structure 400 and the multiple channel structures 401 constitute a memory array structure. A portion of the film layer in the channel structure 401 extends into and connects to the active layer 101. The active layer 101 is further connected to the pad 301 to enable back-side routing of the channel structure 401.

[0118] The peripheral circuit portion 501 is located on the side of the stacked structure 400 opposite each other along the second direction, away from the pad 301. A first wiring layer 402 and a second wiring layer 502 are also provided between the peripheral circuit portion 501 and the stacked structure 400. In a specific example, a hybrid bonding layer is also formed between the first wiring layer 402 and the second wiring layer 502.

[0119] like Figure 9 As shown, the distance between the pad 301 and the peripheral circuit section 501 in the second direction is relatively large. As the storage density increases, the number of stacked layers in the stacked structure 400 needs to be further increased, and the distance between the pad 301 and the peripheral circuit section 501 in the second direction also increases. Therefore, when electrostatic discharge is triggered due to the contact between the tip of the test probe and the pad 301, the electrostatic protection circuit set in the peripheral circuit section 501 cannot discharge the static electricity in time.

[0120] In this embodiment, an electrostatic discharge (ESD) protection structure 100 connected to the pad 301 is provided around the pad 301. The ESD protection structure 100 includes at least one transistor structure 200. The first electrode region 102, channel region 103, and second electrode region 104 of the transistor structure 200 are disposed in the active layer 101. The gate structure 201 of the transistor structure 200 is disposed on the active layer 101. The first electrode region 102 and gate structure 201 of the transistor structure 200 located at the first end of the ESD protection structure 100 are connected to the power line 302. The second electrode region 104 of the transistor structure 200 located at the second end of the ESD protection structure 100 is connected to the ground line 303. The pad 301 is connected to the first electrode region 102 or the second electrode region 104 of the transistor structure 200. Thus, the static electricity generated on the pad 301 can be discharged to the power supply or ground terminal through the ESD protection structure 100 without entering the interior of the semiconductor structure. This reduces the risk of high voltage static electricity damaging the memory array structure and other circuit structures, effectively improving the reliability and yield of the semiconductor structure.

[0121] In some embodiments, since static electricity is usually generated when an external power supply applies an electrical signal to the inside of the semiconductor structure via the pad 301, after the semiconductor structure enters normal operating condition, the connection between the electrostatic protection structure 100 and the power supply terminal and the ground terminal can be disconnected, so that the electrostatic protection structure 100 is in a shielded state, so as to avoid additional power consumption caused by the electrostatic protection structure 100 being accidentally triggered during normal operating condition.

[0122] In some specific examples, the peripheral circuit section 501 may include circuit elements such as page buffer sense amplifiers, column decoders / bit line drivers, row decoders / word line drivers, voltage generators, control logic units, registers, interfaces, and data buses.

[0123] In other specific examples, the semiconductor structures provided in this disclosure may also include only memory array structures.

[0124] It should be noted that in the above embodiments, the memory array structure composed of the stacked structure 400 and the channel structure 401 is a NAND memory array structure, and the memory including the peripheral circuit part 501 is a 3D NAND memory as an example. However, this disclosure is not limited to this. Any other three-dimensional memory obtained by wafer bonding process can include the semiconductor structure including the electrostatic protection structure 100 provided in the embodiments of this disclosure.

[0125] Reference Figure 10This disclosure also provides a memory system 600, including: at least one semiconductor structure as described in any of the foregoing embodiments and a controller 602; the controller 602 is coupled to the at least one semiconductor structure and configured to control the semiconductor structure. Here, the semiconductor structure may be a memory 601.

[0126] In some embodiments, the controller 602 and one or more memories 601 can be integrated into various types of storage devices, that is, the memory system 600 can be implemented and packaged into different types of terminal electronic products.

[0127] In some specific examples, the memory system 600 may be one of the following: a Compact Flash Card (CFC), a Smart Media Card (SMC), a Memory Stick (MS), a Multi-Media Card (MMC) such as RS-MMC, MMCmicro, eMMC, etc., a Secure Digital Memory Card (SD card) such as Mini SD card, Micro SD card, SDHC card, etc., a Universal Flash Storage (UFS) card, and a Solid State Drive (SSD).

[0128] In other specific examples, the memory system 600 may be located in a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein.

[0129] Based on a concept similar to the semiconductor structure in the above embodiments, this disclosure also provides a method for forming a semiconductor structure. Figure 11 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure. The method for forming a semiconductor structure includes the following steps:

[0130] Step S10: Provide an active layer;

[0131] Step S20: A pad is formed on the active layer, and an electrostatic discharge (ESD) protection structure is formed; the ESD protection structure includes at least one transistor structure, the transistor structure includes a gate structure and a first electrode region, a channel region, and a second electrode region located in the active layer and arranged along a first direction, the gate structure being located on the channel region; the pad is connected to the first electrode region or the second electrode region of the transistor structure; the first direction is perpendicular to the second direction; the second direction is the thickness direction of the active layer.

[0132] Figures 12 to 14 This is a schematic diagram of the semiconductor structure formation process. Below, we will combine... Figures 12 to 14 The formation process of semiconductor structures is described.

[0133] Reference Figure 12 An active layer 101 is provided, and a plurality of first electrode regions 102, channel regions 103 and second electrode regions 104 arranged along a first direction are formed in the active layer 101.

[0134] In some embodiments, the active layer 101 can be a heavily doped semiconductor material, such as N-type doped polysilicon. Therefore, the active layer 101 can be used as a high-voltage N-well in a transistor structure. P-type doping of the active layer 101 can form a first electrode region 102 and a second electrode region 104 in the active layer 101.

[0135] In some specific examples, the active layer 101 can be doped using an ion implantation (IMP) process to form multiple first electrode regions 102 and second electrode regions 104 arranged along a first direction. The doping element for N-type doping can be phosphorus or arsenic, and the doping element for P-type doping can be boron or gallium.

[0136] Reference Figure 13 A dielectric layer 203 and an isolation layer 204 are sequentially formed on the active layer 101, and a gate layer 202 located in the isolation layer 204 and a first contact structure 205 penetrating the dielectric layer 203 and the isolation layer 204 along the second direction are formed. The gate layer 202 and the dielectric layer 203 constitute the gate structure 201 of the transistor structure 200. One end of the first contact structure 205 at opposite ends along the second direction is connected to the first electrode region 102 or the second electrode region 104.

[0137] In this embodiment of the disclosure, the first direction is perpendicular to the second direction, and the second direction is the thickness direction of the active layer 101. Here, the first direction is the X direction, and the second direction is the Z direction.

[0138] In some specific examples, a dielectric layer 203 and an isolation layer 204 can be formed by deposition, and an opening can be formed in the isolation layer 204 by photolithography and etching, followed by filling the opening with conductive material by deposition to form a gate layer 202. A via can be formed through the dielectric layer 203 and the isolation layer 204 by photolithography and etching, and the via can be filled with conductive material by deposition to form a first contact structure 205.

[0139] In the embodiments disclosed herein, the deposition processes include, but are not limited to, chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0140] In some specific examples, the material of the gate layer 202 can be at least one of doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metallic materials (e.g., tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.); the material of the dielectric layer 203 can be silicon oxide, hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, etc. The material can be at least one of the following: strontium titanium, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate; the material of the isolation layer 204 can be at least one of the following: silicon nitride, silicon oxide, and silicon oxynitride; the material of the first contact structure 205 can be at least one of the following: doped semiconductor material (e.g., doped silicon, doped germanium, etc.), conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), metallic material (e.g., tungsten, titanium, tantalum, etc.), and metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0141] In some embodiments, the method for forming a semiconductor structure further includes: forming a plurality of second contact structures penetrating the dielectric layer 203 and the isolation layer 204 along a second direction. The second contact structures serve to connect the pads 301 and the active layer 101 to enable the extraction of the active layer 101. Furthermore, the materials and dimensions of the second contact structures and the first contact structures 205 in the second direction can be the same, so the first contact structure 205 and the second contact structure can be formed simultaneously.

[0142] In some embodiments, in conjunction with reference Figure 13 and Figure 14 The method for forming a semiconductor structure further includes: forming a pad 301, a power line 302, a ground line 303, and a conductive line 304 on an isolation layer 204; the power line 302 and the ground line 303 are respectively located on opposite sides of the pad 301 along a first direction; the conductive line 304 is located between the pad 301 and the power line 302 and / or between the pad 301 and the ground line 303 in the first direction; each conductive line 304 is connected to a first electrode region 102 and a gate structure 201 of a transistor structure 200; the other end of the first contact structure 205 along a second direction is connected to one of the pad 301, the power line 302, the ground line 303, and the conductive line 304.

[0143] In some specific examples, the materials of pad 301, power line 302, ground line 303, and conductive line 304 can be the same, and can be at least one of the following metals: tungsten, copper, nickel, aluminum, silver, gold, and titanium. Furthermore, pad 301, power line 302, ground line 303, and conductive line 304 can be formed simultaneously. Specifically, an insulating layer (not shown in the figure) can be formed on the isolation layer 204 first, and then openings corresponding to pad 301, power line 302, ground line 303, and conductive line 304 can be formed in the insulating layer using photolithography and etching processes. Metal material is then filled into the openings to form pad 301, power line 302, ground line 303, and conductive line 304.

[0144] It should be noted that a method similar to the semiconductor structure formation method in the above embodiments can also be used to form... Figures 4 to 9 The semiconductor structures shown will not be described in detail here.

[0145] In some embodiments, return to reference Figure 9 The method for forming a semiconductor structure further includes: forming a stacked structure 400 stacked along a second direction; forming a plurality of channel structures 401 penetrating the stacked structure 400 along the second direction; forming an active layer 101 on one of the opposite sides of the stacked structure 400 along the second direction; and connecting the active layer 101 to the channel structure 401.

[0146] In some embodiments, the method of forming a semiconductor structure further includes forming a peripheral circuit portion 501 on the other side of two opposite sides of the stacked structure 400 along a second direction.

[0147] In this embodiment, the active layer 101, which serves as an N-well in the semiconductor structure, is used as the formation region of the first electrode region 102, the channel region 103, and the second electrode region 104 of the transistor structure 200. A gate structure 201 is formed on the active layer 101 to form an electrostatic discharge (ESD) protection structure 100, which includes at least one transistor structure 200, connected to the pad 301. Compared to the semiconductor structure formation process including the active layer 101 in related technologies, the semiconductor structure formation method provided in this disclosure only adds doping of the active layer 101 to form the first electrode region 102 and the second electrode region 104. The process of forming the gate structure 201 and the process of forming the first contact structure 205 can be integrated into the same process step as the process of forming the second contact structure located between the pad 301 and the active layer 101; the process of forming the power line 302, the ground line 303 and the conductive line 304 can be integrated into the same process step as the process of forming the pad 301. Thus, while improving the reliability of the semiconductor structure by adding the electrostatic protection structure 100, the additional process cost caused by adding the electrostatic protection structure 100 can also be reduced, and the size of the semiconductor structure in the second direction can be minimized.

[0148] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0149] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0150] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, It includes an active layer, an electrostatic discharge (ESD) protection structure, and pads located on the active layer; wherein, The electrostatic protection structure includes at least one transistor structure, the transistor structure including a gate structure and a first electrode region, a channel region, and a second electrode region located in the active layer and arranged along a first direction, the gate structure being located on the channel region; the first direction is perpendicular to the second direction; the second direction is the thickness direction of the active layer; The pad is connected to the first electrode region or the second electrode region of the transistor structure.

2. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: The power line and the ground line are located on the active layer, and the power line and the ground line are respectively located on opposite sides of the pad along the first direction.

3. The semiconductor structure according to claim 2, characterized in that, The electrostatic protection structure includes one of the transistor structures; The transistor structure is located between the power line and the pad, the first electrode region and the gate structure of the transistor structure are connected to the power line, and the second electrode region of the transistor structure is connected to the pad; or, The transistor structure is located between the pad and the ground line. The first electrode region and the gate structure of the transistor structure are connected to the pad, and the second electrode region of the transistor structure is connected to the ground line.

4. The semiconductor structure according to claim 2, characterized in that, The electrostatic protection structure includes a plurality of transistor structures connected in series and arranged along the first direction; the electrostatic protection structure includes a first end and a second end opposite to each other along the first direction, the first end being close to the power line and the second end being close to the ground line. The electrostatic protection structure is located between the power line and the grounding line; The first electrode region and gate structure of the transistor structure located at the first end are connected to the power line; The second electrode region of the transistor structure located at the second end is connected to the ground line; the pad is connected to the first electrode region and gate structure of the transistor structure closest to the ground line in the two transistor structures closest to the pad in the electrostatic protection structure, and the second electrode region of the other transistor structure is connected. or, The electrostatic protection structure is located between the pad and the grounding wire; the first electrode region and gate structure of the transistor structure located at the first end are connected to the pad; The second electrode region of the transistor structure located at the second end is connected to the ground wire; or, The electrostatic protection structure is located between the power line and the pad; the first electrode region and gate structure of the transistor structure located at the first end are connected to the power line; The second electrode region of the transistor structure located at the second end is connected to the pad.

5. The semiconductor structure according to claim 4, characterized in that, The first electrode region of the transistor structure is shared with the second electrode region of the transistor structure closer to the power line in one of the two adjacent transistor structures. The second electrode region of the transistor structure is shared with the first electrode region of the transistor structure closer to the ground wire in the two adjacent transistor structures.

6. The semiconductor structure according to claim 2, characterized in that, The semiconductor structure also includes: A conductive line located on the active layer; the conductive line is located between the pad and the power line and / or between the pad and the ground line in the first direction; the conductive line is connected to a first electrode region and a gate structure of a transistor structure.

7. The semiconductor structure according to claim 2, characterized in that, The gate structure includes a gate layer and a dielectric layer, and the semiconductor structure further includes: An isolation layer is located on the active layer; the dielectric layer is located between the isolation layer and the active layer; the gate layer is located in the isolation layer; the pads, the power lines, and the ground lines are all located on the isolation layer.

8. The semiconductor structure according to claim 7, characterized in that, The semiconductor structure also includes: A plurality of first contact structures extending through the dielectric layer and the isolation layer along the second direction; one end of the first contact structure along the second direction is connected to the first electrode region or the second electrode region, and the other end of the first contact structure along the second direction is connected to one of the pad, the power line and the ground line.

9. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure includes multiple active layers, each of which extends along the first direction; The pads are located on the plurality of active layers; each active layer has at least one transistor structure.

10. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: A stacked structure located on the side of the active layer opposite each other along the second direction, away from the pad; A plurality of channel structures extending along the second direction and penetrating the stacked structure; the channel structures are connected to the active layer.

11. The semiconductor structure according to claim 10, characterized in that, The semiconductor structure also includes: The peripheral circuit portion is located on one side of the stacked structure opposite each other along the second direction, away from the pad.

12. A memory system, characterized in that, include: At least one semiconductor structure as described in claim 10 or 11; A controller is coupled to the semiconductor structure and configured to control the semiconductor structure.

13. A method for forming a semiconductor structure, characterized in that, include: Provide an active layer; Pads are formed on the active layer, and an electrostatic protection structure is formed thereon. The electrostatic discharge protection structure includes at least one transistor structure, the transistor structure including a gate structure and a first electrode region, a channel region, and a second electrode region located in the active layer and arranged along a first direction, the gate structure being located on the channel region; the pad is connected to the first electrode region or the second electrode region of the transistor structure; the first direction is perpendicular to the second direction; the second direction is the thickness direction of the active layer.

14. The method for forming a semiconductor structure according to claim 13, characterized in that, The method for forming the semiconductor structure further includes: A power line and a ground line are formed on the active layer; the power line and the ground line are respectively located on opposite sides of the pad along the first direction.

15. The method for forming a semiconductor structure according to claim 14, characterized in that, The method for forming the semiconductor structure further includes: Conductive lines are formed on the active layer; the conductive lines are located between the pads and the power lines and / or between the pads and the ground lines in the first direction; each conductive line is connected to a first electrode region and a gate structure of a transistor structure.

16. The method for forming a semiconductor structure according to claim 14, characterized in that, The formation of the electrostatic protection structure includes: A dielectric layer and an isolation layer are formed on the active layer; the dielectric layer is located between the isolation layer and the active layer; A gate layer is formed in the isolation layer; the gate layer and the dielectric layer constitute the gate structure.

17. The method for forming a semiconductor structure according to claim 16, characterized in that, The method for forming the semiconductor structure further includes: A plurality of first contact structures are formed that penetrate the dielectric layer and the isolation layer along the second direction; one end of the first contact structure along the second direction is connected to the first electrode region or the second electrode region; The process of forming pads, power lines, and ground lines on the active layer includes: The pads, the power lines, and the ground lines are formed on the isolation layer; one end of the first contact structure along the second direction is connected to one of the pads, the power lines, and the ground lines.

18. The method for forming a semiconductor structure according to claim 13, characterized in that, The method for forming the semiconductor structure further includes: A stacked structure is formed along the second direction; Forming a plurality of channel structures that penetrate the stacked structure along the second direction; The active layer is formed on one of the two opposite sides of the stacked structure along the second direction; the active layer is connected to the channel structure.

19. The method for forming a semiconductor structure according to claim 18, characterized in that, The method for forming the semiconductor structure further includes: A peripheral circuit portion is formed on the other side of the two opposite sides of the stacked structure along the second direction.

Images