Chip, chip and chip core particle data transmission method and electronic equipment

Abstract

The application relates to a chip, a data transmission method between chip cores and an electronic device, and belongs to the field of integrated circuits. The chip comprises a plurality of cores and interconnection links, the plurality of cores are connected through the interconnection links, each core is connected with at least two interconnection links, and each interconnection link in the at least two interconnection links is connected to a different core; each core is used for transmitting data to a destination through a transmission path in which a first interconnection link in the at least two interconnection links is located, and when the first interconnection link is abnormal, a second interconnection link in the at least two interconnection links is automatically selected, and data transmission is carried out by replacing the first interconnection link with the second interconnection link, wherein the second interconnection link is a normal link, and there is a transmission path between the second interconnection link and the destination. The application can improve the problems of high cost and low utilization of the existing fault-tolerant design of the backup redundant link.

Description

Technical Field

[0001] This application belongs to the field of integrated circuits, specifically relating to a chip, a data transmission method between chip chips, and electronic devices. Background Technology

[0002] Integrating multiple functional modules (DIEs) into a single package not only improves chip performance and integration density but also shortens design cycles and reduces manufacturing costs. However, as chip system scale continues to increase, the number of integrated DIEs grows, and the interconnect links between DIEs become increasingly complex. This complexity increases the probability of inter-DIE link failures, directly impacting system startup and operational stability. Inter-DIE interconnect links refer to the data transmission channels between individual DIEs; they are responsible for transmitting various control signals and data information and are crucial for ensuring the normal operation of the entire chip system. However, these links are susceptible to various factors in complex operating environments, leading to link failures. To improve system reliability and stability, effective fault-tolerant methods must be employed to ensure the system can quickly recover and resume normal operation in the event of a link failure.

[0003] The current solution involves adding redundant backup links to each critical link in the chip system. These redundant backup links can automatically switch over via hardware multiplexing and switching switches. For example, each primary link has one or more redundant backup links. If the primary link fails, the system can automatically switch to a redundant backup link to maintain data transmission continuity. While this solution improves system reliability to some extent, it still has the following drawbacks: the design of redundant backup links requires additional hardware resources, thus increasing the cost of chip design and manufacturing; furthermore, the redundant backup links are idle under normal conditions, resulting in low utilization and wasted resources. Summary of the Invention

[0004] Therefore, the purpose of this application is to provide a chip and a data transmission method and electronic device between chip chips, so as to improve the problems of high cost and low utilization rate of existing backup redundant link fault-tolerant design.

[0005] The embodiments of this application are implemented as follows:

[0006] In a first aspect, embodiments of this application provide a chip, including: a plurality of chips and interconnect links, the plurality of chips being connected through the interconnect links, each chip being connected to at least two interconnect links, each of the at least two interconnect links being connected to a different chip; each chip being configured to automatically select a second interconnect link among the at least two interconnect links when data is to be transmitted to a destination via a transmission path containing a first interconnect link among the at least two interconnect links, and to use the second interconnect link to replace the first interconnect link for data transmission when the first interconnect link is abnormal, wherein the second interconnect link is a normal link and there is a transmission path between the second interconnect link and the destination.

[0007] In the above embodiments, since each chip is connected to at least two interconnect links, and each interconnect link is connected to a different chip, the chip can automatically select and switch interconnect links when an interconnect link fails. For example, if data is to be transmitted to the destination via the transmission path of the first interconnect link among the at least two interconnect links, and the first interconnect link is faulty, the second interconnect link (which is a normal link and has a transmission path with the destination) is used to replace the first interconnect link for data transmission, ensuring that the chip can still operate correctly. By using this method of mutual backup of at least two interconnect links, and through measures such as a fast fault switching mechanism, optimized resource utilization, and automated fault handling, the problems of high cost, resource waste, large latency, and system complexity in the prior art are effectively solved, thereby improving the reliability and stability of the chip system.

[0008] In one possible implementation of the first aspect embodiment, each of the cores is provided with an adaptive routing control module. The adaptive routing control module is used to obtain a cross-core backup routing table in a preset routing table when the first interconnecting link among the at least two interconnecting links is abnormal, and to automatically select the transmission path where the second interconnecting link among the at least two interconnecting links is located for data transmission according to the cross-core backup routing table. The cross-core backup routing table is used to determine a transmission path that bypasses the abnormal interconnecting link and includes the second interconnecting link. The destination of the transmission path where the second interconnecting link is located is the same as the destination of the transmission path where the first interconnecting link is located.

[0009] In the above embodiments, by adding an adaptive routing control module inside the chip (DIE), the chip can quickly select and switch transmission paths automatically according to the pre-configured cross-chip backup routing table (also known as cross-DIE backup routing table) when the interconnection link fails, ensuring that the chip can still operate correctly. This effectively solves the problems of high cost, waste of resources, large latency, and system complexity in the prior art, and improves the reliability and stability of the chip system.

[0010] In one possible implementation of the first aspect embodiment, the adaptive routing control module includes: a routing table lookup unit and a path switching control unit; the routing table lookup unit is used to look up a routing table built into the core, the routing table including the cross-core backup routing table; the path switching control unit is connected to the routing table lookup unit; the path switching control unit is used to look up the cross-core backup routing table through the routing table lookup unit when the first interconnection link is abnormal, and automatically select the transmission path where the second interconnection link is located for data transmission according to the found cross-core backup routing table.

[0011] In the above embodiments, the use of a routing lookup unit in conjunction with a path switching control unit ensures that the chip can still operate normally even when some links fail. For example, when the first interconnect link fails, the path switching control unit uses the routing lookup unit to search the routing table built into the chip, and automatically selects the second interconnect link based on the found cross-chip backup routing table, replacing the first interconnect link for data transmission. Breaking down complex modules into different small units helps reduce design complexity and increase design flexibility.

[0012] In one possible implementation of the first aspect embodiment, the adaptive routing control module further includes: a link status monitoring unit connected to the path switching control unit; the link status monitoring unit is used to monitor the status of interconnected links, and when an abnormality is detected in the first interconnected link, records the abnormal first interconnected link in an abnormal link table; the path switching control unit is also used to access the abnormal link table to learn about the abnormal interconnected links.

[0013] In the above embodiments, a link status monitoring unit is added to monitor the status of interconnect links. When an anomaly is detected, the first abnormal interconnect link is recorded in the abnormal link table. This ensures that the path switching control unit can promptly learn about the abnormal interconnect links and quickly switch to other paths, ensuring that the chip can still operate normally even when some links fail.

[0014] In one possible implementation of the first aspect embodiment, the preset routing table further includes a cross-core master routing table, which is used to determine the optimal transmission path for data transmission when the interconnection link is normal.

[0015] In the above embodiments, by combining the cross-chip primary routing table with the cross-chip backup routing table, data can be transmitted based on the optimal transmission path when the interconnection link is normal, and based on the alternative path when the interconnection link is abnormal, which is beneficial to improving the performance of the chip system.

[0016] In one possible implementation of the first aspect embodiment, the plurality of cores includes M*N cores, where M and N are both integers greater than or equal to 2; the at least two interconnection links include horizontal interconnection links and vertical interconnection links; the cross-core-level primary routing table follows a configuration rule of either the vertical interconnection link followed by the horizontal interconnection link or the horizontal interconnection link followed by the vertical interconnection link; the cross-core-level backup routing table follows a configuration rule of mutual backup between the horizontal interconnection link and the vertical interconnection link.

[0017] In the above embodiments, the configuration rules described above are followed when configuring the cross-chip primary routing table and the cross-chip backup routing table to ensure that the transmission path determined by the cross-chip primary routing table is the optimal transmission path when the interconnection link is normal, and that the transmission path determined by the cross-chip backup routing table can bypass the abnormal interconnection link when the interconnection link is abnormal, thereby ensuring the reliability and stability of the chip.

[0018] In one possible implementation of the first aspect embodiment, the chip further includes: a cache queue for temporarily caching data transmitted externally by the chip; the adaptive routing control module is further configured to utilize the second interconnection link to transmit the data transmitted externally by the chip in the cache queue.

[0019] In the above embodiments, setting up a cache queue to temporarily cache the data transmitted externally by the chip helps to improve the chip's concurrent processing capabilities, reduce network transmission latency, and improve the efficiency of data transmission and reception.

[0020] In one possible implementation of the first aspect embodiment, the core further includes: a master module, a slave module, a routing node, and at least two interconnect modules, wherein the at least two interconnect modules, the master module, and the slave module are all connected to the routing node; each of the interconnect modules, the master module, and the slave module in the core is provided with the adaptive routing control module; the adaptive routing control module in the interconnect module is further configured to report abnormal link information to the adaptive routing control modules in other modules of the core when an abnormality is detected in the first interconnect link.

[0021] In the above embodiments, since each interconnect module, master module, and slave module is equipped with an adaptive routing control module, the modules can transmit data in parallel, which can improve the efficiency of data transmission. At the same time, the adaptive routing control module in the interconnect module is also used to report the abnormal link information to the adaptive routing control modules in other modules in the core when an abnormality is detected in the first interconnect link. In this way, the adaptive routing control modules in other modules can be informed of the abnormal link information.

[0022] In one possible implementation of the first aspect embodiment, the chip is a server chip.

[0023] In the above embodiments, by adding an adaptive routing control module to the server chip, it is ensured that the chip can still operate normally in the event of partial link failure, so as to meet the high reliability and high stability requirements of high-performance computing and data centers.

[0024] Secondly, embodiments of this application also provide an electronic device, including: a chip provided as described in the first aspect embodiments and / or in any possible implementation of the first aspect embodiments.

[0025] Thirdly, embodiments of this application also provide a data transmission method between chip dies, wherein the chip includes multiple dies and interconnect links, the multiple dies are connected by interconnect links, each die is connected to at least two interconnect links, and each of the at least two interconnect links is connected to a different die; the method includes: when a die is about to transmit data to a destination through a transmission path containing a first interconnect link among the at least two interconnect links, and the first interconnect link is abnormal, it automatically selects a second interconnect link among the at least two interconnect links; the die uses the second interconnect link to replace the first interconnect link for data transmission; wherein the second interconnect link is a normal link, and there is a transmission path between the second interconnect link and the destination.

[0026] In one possible implementation of the third aspect embodiment, each core is provided with an adaptive routing control module that automatically selects the second interconnecting link among the at least two interconnecting links, including: the adaptive routing control module obtaining a preset cross-core backup routing table in the core, wherein the cross-core backup routing table is used to determine a transmission path that bypasses the abnormal interconnecting link and includes the second interconnecting link; the adaptive routing control module automatically selects the second interconnecting link among the at least two interconnecting links according to the cross-core backup routing table.

[0027] In one possible implementation of the third aspect embodiment, the method further includes: the adaptive routing control module monitoring the status of the interconnection link, and when the first interconnection link is detected to be abnormal, recording the abnormal first interconnection link in the abnormal link table.

[0028] Other features and advantages of this application will be set forth in the following description. The objectives and other advantages of this application can be realized and obtained through the structures specifically pointed out in the written description and the accompanying drawings. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. The above and other objects, features, and advantages of this application will become clearer through the accompanying drawings.

[0030] Figure 1 A schematic diagram of the structure of a chip provided in an embodiment of this application is shown.

[0031] Figure 2a This illustration shows a schematic diagram illustrating the principle of data transmission by a chip according to a cross-chip master routing table, as provided in an embodiment of this application.

[0032] Figure 2b This illustration shows a schematic diagram illustrating the principle of data transmission by a chip according to a cross-chip backup routing table, as provided in an embodiment of this application.

[0033] Figure 3 A schematic diagram of the structure of a core provided in an embodiment of this application is shown.

[0034] Figure 4a A schematic diagram of the structure of an adaptive routing control module provided in an embodiment of this application is shown.

[0035] Figure 4b A schematic diagram of the structure of another adaptive routing control module provided in an embodiment of this application is shown.

[0036] Figure 5 This illustration shows a data transmission diagram before and after an interconnect module enters backup routing mode, according to an embodiment of this application.

[0037] Figure 6 This illustration shows a schematic diagram of the principle of a fault-tolerant processing method for inter-chip routing provided in an embodiment of this application.

[0038] Figure 7 A schematic flowchart of a data transmission method between chip chips provided in an embodiment of this application is shown.

[0039] Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0040] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. The following embodiments are provided as examples to more clearly illustrate the technical solutions of this application, and should not be used to limit the scope of protection of this application. Those skilled in the art will understand that, without conflict, the following embodiments and features can be combined with each other.

[0041] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0042] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0043] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical term "connection" can be a direct connection or an indirect connection through an intermediate medium.

[0044] With the increase in interconnect links between chips (such as server chips), the frequency of interconnect link failures has risen significantly. Given the shortcomings of existing redundant link designs—for example, while redundant link designs provide fault tolerance, their high cost and resource waste remain—this application provides a fault-tolerant processing method for inter-chip routing. When an interconnect link between chips fails, the chip system can quickly switch to other paths, ensuring that the chip can still operate normally even with partial link failures. Through rapid fault switching mechanisms, optimized resource utilization, and automated fault handling, this method effectively solves the problems of high cost, resource waste, high latency, and system complexity in existing technologies, improving the reliability and stability of the chip system and meeting the high reliability and stability requirements of high-performance computing and data centers.

[0045] The following is combined with Figure 1 The chip provided in the embodiments of this application will be described, such as... Figure 1 As shown, the chip includes multiple dies and interconnects. The dies are connected via interconnects, and each die is connected to at least two interconnects (including a first interconnect and a second interconnect). Each of the at least two interconnects connects to a different die. For example, the multiple dies connected via interconnects form a mesh or a fully interconnected network. It is understood that... Figure 1 Only a schematic diagram is shown, illustrating multiple particles connected by interconnecting links to form a MESH network.

[0046] Each core is used to transmit data to the destination via the transmission path containing the first interconnect link out of at least two interconnect links (or planned to be passed, or prepared to be passed). If the first interconnect link is faulty, it automatically selects the second interconnect link out of at least two interconnect links and uses the second interconnect link to replace the first interconnect link for data transmission. The second interconnect link is a normal link, and a transmission path exists between the second interconnect link and the destination (the destination of the transmission path containing the first interconnect link). When transmitting data using a transmission path containing the second interconnect link, the destination of that transmission path must be the same as the destination of data transmitted using a transmission path containing the first interconnect link to ensure that the data is transmitted to the same destination.

[0047] Since there is a transmission path between the second interconnection link and the destination, when the first interconnection link fails, the core can transmit the data to be transmitted (i.e., the data to be transmitted through the transmission path of the first interconnection link) to the destination through the second interconnection link. For example, the data to be transmitted can be transmitted to the next core through the second interconnection link, and the next core can then continue to transmit the data to the next core according to the destination in the data to be transmitted, and so on, so that it can be transmitted to the destination.

[0048] It should be noted that the second interconnecting link and the first interconnecting link in this application provide mutual backup. The second interconnecting link in this application is not a backup redundant link specifically designed for the first interconnecting link. Under normal circumstances, the second interconnecting link is not idle, but serves as a link for data transmission with other core components. The reason why the second interconnecting link and the first interconnecting link in this application provide mutual backup is determined by the connection method of the core components. Since multiple core components are connected through interconnecting links to form a MESH or fully interconnected network, each of the at least two interconnecting links connected to each core component is connected to different core components, allowing for mutual backup.

[0049] Specifically, for MESH networks: nodes in a MESH network are only connected to their neighboring nodes, making it suitable for large-scale networks and easy to expand. For fully interconnected networks: each node in a fully interconnected network is directly connected to all other nodes, making it suitable for small-scale networks with a large number of connections.

[0050] In one possible implementation, the chip includes M*N chips, for example, it can be multiple chips including M*N chips, where M and N are both integers greater than or equal to 2. Each chip is connected to a horizontal interconnect link and a vertical interconnect link, that is, each chip has at least two interconnect links including a horizontal interconnect link and a vertical interconnect link, wherein the first interconnect link (or the second interconnect link) can be a horizontal interconnect link or a vertical interconnect link. Figure 1 In the example shown, the chip consists of 3*2 cores, each core connected to a horizontal interconnect link and a vertical interconnect link.

[0051] In one possible implementation, each chip is equipped with an Adaptive Routing Control Module (ARCM). When the first interconnection link among at least two interconnection links of the chip fails, the ARCM obtains a cross-chip backup routing table from a preset routing table and automatically selects the transmission path of the second interconnection link among the at least two interconnection links for data transmission based on the cross-chip backup routing table. The destination of the transmission path of the second interconnection link is the same as the destination of the transmission path of the first interconnection link. This ensures that the chip can still operate normally under partial link failure, thereby ensuring that the chip can still operate normally under partial link failure.

[0052] It is understandable that there can be many transmission paths that include the second interconnection link, and these multiple transmission paths may have different destinations. When selecting a transmission path that includes the second interconnection link, it is necessary to select a transmission path whose destination is the same as the destination of the transmission path containing the first interconnection link, and which includes the second interconnection link. Then, the transmission path that includes the second interconnection link is the transmission path containing the second interconnection link.

[0053] This application provides a novel chip that adds an adaptive routing control module inside the chip. This module enables the chip to monitor the status of interconnect links in real time and, when an interconnect link fails, quickly selects and switches transmission paths based on information in a pre-configured routing table (such as a cross-chip backup routing table, also known as a cross-DIE backup routing table), ensuring that the chip can still operate correctly.

[0054] The cross-core backup routing table is used to determine alternative transmission paths (alternative paths) that bypass faulty interconnect links, including second interconnect links. The cross-core backup routing table needs to be pre-configured, during which backup transmission paths are configured for each interconnect link in case of failure, thus bypassing the faulty interconnect link. Correspondingly, the preset routing table also includes a cross-core master routing table (also known as a cross-DIE master routing table), which is used to determine the optimal transmission path (e.g., the shortest transmission distance) when the interconnect link is normal. By combining the cross-core master routing table and the cross-core backup routing table, data can be transmitted based on the optimal transmission path when the interconnect link is normal, and based on alternative paths when the interconnect link is faulty.

[0055] In some possible implementations, when the chip comprises M*N chips, each chip is connected to a horizontal (e.g., X-axis) interconnect link and a vertical (e.g., Y-axis) interconnect link, the cross-chip primary routing table follows the configuration rule of either vertical interconnect link first and then horizontal interconnect link, or horizontal interconnect link first and then vertical interconnect link; the cross-chip backup routing table follows the configuration rule of mutual backup between horizontal interconnect link and vertical interconnect link.

[0056] For ease of understanding, combined with Figure 2a , Figure 2b The example shown illustrates this. When configuring the cross-core master routing table, you can follow the rule of "Y-axis routing first, then X-axis routing," for example, as follows: Figure 2a As shown, when a message is sent from MasterA of DIE0 to SlaveA of DIE5, the message will first travel along the Y-axis to the row containing the target DIE, and then travel along the X-axis to reach the target DIE. The transmission path is as follows: Figure 2a As shown by the dashed line. When configuring cross-core backup routing tables, the rule of "horizontal links and vertical links mutually backing up" can be followed. This means that when a horizontal link fails, the system will automatically switch to the corresponding vertical backup link, and vice versa. For example, when... Figure 2a When an anomaly occurs in the link between DIE3 and DIE4, such as Figure 2b As shown, DIE3 will forward the message to the backup horizontal link, and it will reach the target DIE via the path of DIE2. The transmission path is as follows: Figure 2b As shown by the dashed line.

[0057] Figure 2a The link between DIE3 and DIE4 can be considered the first interconnection link, and the link between DIE3 and DIE2 can be considered the second interconnection link. When DIE3 is about to pass through the transmission path of the first interconnection link ( Figure 2aWhen data is transmitted from the dashed line (DIE3-DIE4-DIE5 Slave A) to its destination (DIE5 Slave A), due to an anomaly in the first interconnection link, and since there is a transmission path between the second interconnection link and DIE5 Slave A, as shown in 2b, DIE3 can transmit the data to be transmitted to DIE2 via the second interconnection link. Then, DIE2 will transmit the data to be transmitted to DIE5 Slave A. Figure 2b The dashed line containing SlaveA in DIE3-DIE2-DIE5 is the transmission path of the second interconnection link.

[0058] The aforementioned routing table can be built into the adaptive routing control module. In one possible implementation, the routing table may not be built into the adaptive routing control module, but rather stored in the core's memory. The adaptive routing control module retrieves the routing table by accessing this memory. In this implementation, multiple adaptive routing control modules can share a single routing table.

[0059] Each die is a single integrated circuit chip unit, an independent chip cut from a wafer. Each die contains specific circuitry and functions and can function as a standalone chip or part of a chipplet. The functions implemented by each die can differ, and therefore, the internal structure of each die can vary. A chipplet, on the other hand, refers to a small integrated circuit module that can be part of a larger system-on-a-chip (SoC).

[0060] In one possible implementation, the chip also includes: a master module, a slave module, a crossbar, and at least two interconnect modules, such as... Figure 3 As shown, at least two interconnect modules, the master module, and the slave module are all connected to the routing node. The Crossbar can be an NxN routing node used to connect the Master, Slave, and interconnect modules. The Master refers to the main entity controlling data transmission in the system; it is typically the initiating control unit that decides how data is transferred between different modules or devices. The Slave refers to a responding entity controlled by the Master; it typically performs specific functions as a subordinate unit and returns the results to the Master. Since the functions implemented by each core may differ, the implementation methods of the Master and Slave in different cores may also differ.

[0061] In one possible implementation, such as Figure 3In the example shown, each interconnect module, master module, and slave module in the core is equipped with an adaptive routing control module. Because each interconnect module, master module, and slave module has an adaptive routing control module, the modules can transmit data in parallel, improving data transmission efficiency. In this implementation, the adaptive routing control module in the interconnect module is also used to report the abnormal link information to the adaptive routing control modules in other modules of the core when an anomaly is detected in the first interconnect link, so that the adaptive routing control modules in other modules can be aware of the abnormal link information.

[0062] exist Figure 3 In the illustrated implementation, any cross-DIE packet needs to be sent to the Crossbar via the adaptive routing control module, and then routed to the designated Link via the interconnect module. During normal operation, data (including packets) is transmitted according to the primary path in the routing table. When a Link fails, the interconnect module will detect it first and then enter backup routing mode. At this time, the data transmission in the interconnect module will change. The adaptive routing control module will take over the unsent packets and retrieve the backup path information from the routing table, quickly adjusting the signal flow so that the data transmission bypasses the faulty link and continues to be transmitted through the backup path. The entire process is completed within milliseconds, ensuring the real-time response of the system. After the interconnect module enters backup routing mode, it will report the abnormal link information to all Masters, Slaves, and interconnect modules within this DIE. Then, the adaptive routing control module will record the abnormal link information in the abnormal link table (abnormal link table). When it is detected that a packet is about to pass through an abnormal Link, the backup path in the routing table is retrieved, and the transmission path is adjusted so that the data transmission bypasses the faulty link, ensuring that the data can be seamlessly transferred to the backup path. Through the aforementioned improvements, the newly added Adaptive Routing Control Module (ARCM) can manage link states and path switching more efficiently within a DIE, ensuring a rapid response in the event of anomalies. Simultaneously, ARCM enables rapid path switching through its internally integrated cross-core routing table, allowing the system to achieve routing fault tolerance between DIEs in complex interconnect architectures.

[0063] In some implementations, each interconnect module, master module, and slave module in the core can share an adaptive routing control module. In this case, the adaptive routing control module is no longer located in each interconnect module, master module, and slave module in the core, but is connected to each interconnect module, master module, and slave module in the core through a routing node. Each interconnect module, master module, and slave module in the core will access the adaptive routing control module when sending data. When multiple modules need to access the adaptive routing control module, a serial access method can be used, requiring them to wait for the previous module to finish accessing before they can access the module.

[0064] In one possible implementation, the kernel further includes a buffer queue, which is used to temporarily buffer data transmitted externally by the kernel. An adaptive routing control module is also used to utilize a second interconnection link to transmit the data transmitted externally by the kernel in the buffer queue. In some implementations, the buffer queue may include an out queue, which refers to a buffer or queue used to temporarily store data that has been processed and is ready for transmission. In some possible implementations, the buffer queue may also include an in queue, which refers to a buffer or queue used to temporarily store data entering the system.

[0065] In one possible implementation, each interconnect module, master module, and slave module in the core may have a cache queue, for example, each may have an In Queue and an Out Queue.

[0066] In one implementation, such as Figure 4a As shown, the adaptive routing control module includes a routing table lookup unit and a path switching control unit. The routing table lookup unit is used to look up the routing table built into the core, which may include the aforementioned cross-core backup routing table and cross-core primary routing table. The path switching control unit is connected to the routing table lookup unit. When the first interconnection link fails, the path switching control unit uses the routing table lookup unit to look up the cross-core backup routing table, automatically selects a second interconnection link based on the found cross-core backup routing table, and uses the second interconnection link to replace the first interconnection link for data transmission.

[0067] In the example shown in 4a, both the cross-DIE primary routing table and the cross-DIE backup routing table are built into the adaptive routing control module, and the path switching control unit can look up the routing table through the routing table lookup unit.

[0068] In some possible implementations, such as Figure 4b As shown, the adaptive routing control module may further include a link status monitoring unit, connected to the path switching control unit. The link status monitoring unit monitors the status of interconnecting links, and when an anomaly is detected in the first interconnecting link, it records the anomaly in the anomaly link table (also called the anomaly link table). The path switching control unit also accesses the anomaly link table to obtain or become aware of the anomaly interconnecting links.

[0069] exist Figure 4bIn the example shown, the abnormal link table is built into the adaptive routing control module. In some possible implementations, the normal link table may not be built into the adaptive routing control module, but may be stored in the chip's memory. The adaptive routing control module can access the abnormal link table in this memory. In this implementation, multiple adaptive routing control modules can share a single abnormal link table. Link anomaly detection and monitoring are mainly achieved through two methods: 1. The link actively reports errors; 2. The interconnect module's timeout mechanism, i.e., if a packet is not successfully sent to the link and the buffer time exceeds a threshold, it is considered a link anomaly by default. After the link status monitoring unit in the interconnect module detects an anomaly in the connected link, the corresponding interconnect module will enter backup routing mode. After entering backup routing mode, the adaptive routing control module will take over the unsent packets in the In Queue and perform route parsing on these packets. Based on the destination and the cross-DIE backup routing table, a suitable backup link is selected, and the packet is sent to the Crossbar through the Out Queue and then forwarded to the backup link. The principle is as follows. Figure 5 As shown.

[0070] After the interconnect module enters backup routing mode, it sends a special message to notify all Masters, Slaves, and interconnect modules within this DIE of any abnormal links. Upon receiving the abnormal link information, the adaptive routing control modules in all Masters, Slaves, and interconnect modules within the DIE will switch packets passing through the abnormal link to the backup link.

[0071] In one possible implementation, after the link status monitoring unit detects an abnormality in the connection, it can also report the specific abnormal link information to the user and remind the user of the occurrence of the link abnormality.

[0072] In one possible implementation, the principle of the fault-tolerant processing method for inter-chip routing in this application can be as follows: Figure 6 As shown. After the interconnect module enters backup routing mode, it obtains the cross-DIE backup routing table from the preset routing table, and automatically selects the second interconnect link from at least two interconnect links based on the cross-DIE backup routing table, and uses the second interconnect link to replace the first interconnect link for data transmission. The cross-DIE routing table configuration can be configured once and used multiple times; for example, it can be configured during the first power-on startup and does not need to be reconfigured during subsequent power-on startups. The cross-DIE routing table configuration can include cross-DIE backup routing table and cross-DIE primary routing table configuration.

[0073] The aforementioned adaptive routing control module can be implemented in hardware or software, or in a hybrid hardware / software architecture. For example, the adaptive routing control module can be designed as a reconfigurable hardware accelerator, rather than being limited to fixed logic circuits. Through reconfigurable logic (such as FPGA), routing strategies and path switching logic can be dynamically adjusted under different application scenarios or fault modes, thereby achieving the effect of the adaptive routing control module of this application. A hybrid hardware / software architecture is adopted, where the core high-performance routing switching logic is implemented in hardware, while software handles more complex fault handling and path optimization, thus achieving the effect of the adaptive routing control module of this application.

[0074] The chips provided in this application embodiment include, but are not limited to, server chips. Additionally, they may be other chips comprising multiple cores. The chip may be a processor.

[0075] This application also provides a data transmission method between chip dies with fault-tolerant processing capabilities. This data transmission method is applied to the aforementioned chip, i.e., the chip includes multiple dies and interconnect links, the multiple dies are connected through interconnect links, each die is connected to at least two interconnect links, and each of the at least two interconnect links is connected to a different die. The following describes the method in conjunction with... Figure 7 The diagram shown illustrates this data transmission method.

[0076] S1: If data is to be transmitted to the destination via the transmission path of the first interconnection link among at least two interconnection links, and the first interconnection link is abnormal, the second interconnection link among the at least two interconnection links is automatically selected.

[0077] In one possible implementation, each core is equipped with an adaptive routing control module, and the above-mentioned S1 implementation process can be as follows: the adaptive routing control module obtains a preset cross-core backup routing table in the core; the adaptive routing control module automatically selects the second interconnection link from at least two interconnection links according to the cross-core backup routing table.

[0078] By adding an adaptive routing control module and a cross-core backup routing table within the core, when the first interconnecting link among at least two interconnecting links connected to the core fails, the adaptive routing control module can obtain the preset cross-core backup routing table within the core. The cross-core backup routing table is used to determine a transmission path that bypasses the failed interconnecting link and includes a second interconnecting link.

[0079] S2: Use the second interconnection link to replace the first interconnection link for data transmission.

[0080] After acquiring a normal second interconnect link, the adaptive routing control module in the chip can use the second interconnect link to replace the first interconnect link for data transmission. This bypasses the abnormal interconnect link, ensuring that the chip can still operate normally even with partial link failures. A transmission path exists between the second interconnect link and the destination.

[0081] In one possible implementation, the data transmission method may further include: an adaptive routing control module monitoring the status of interconnecting links, and when an abnormality is detected in a first interconnecting link, recording the abnormal first interconnecting link in an abnormal link table so that the abnormal interconnecting link can be identified by accessing the abnormal link table.

[0082] The data transmission method between chip chips provided in this application embodiment has the same implementation principle and technical effect as the aforementioned chip embodiment. For the sake of brevity, any part not mentioned in the method embodiment can be referred to the corresponding content in the aforementioned chip embodiment.

[0083] This application also provides an electronic device, which may include the chip described above. In one possible implementation, such as... Figure 8 As shown, the electronic device 200 includes: a transceiver 210, a memory 220, a communication bus 230, and a processor 240. The aforementioned chip can be... Figure 8 The processor 240 shown.

[0084] The transceiver 210, memory 220, and processor 240 are electrically connected directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses 230 or signal lines. The transceiver 210 is used to send and receive data. The memory 220 is used to store computer programs, which include at least one software functional module that can be stored in the memory 220 in the form of software or firmware or embedded in the operating system (OS) of the electronic device 200. The processor 240 is used to execute the software functional modules or computer programs stored in the memory 220. For example, the processor 240 is used to execute the aforementioned inter-chip data transmission method.

[0085] The memory 220 may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.

[0086] Processor 240 may be an integrated circuit chip with signal processing capabilities. The aforementioned processor can be a general-purpose processor, including a Central Processing Unit (CPU), Network Processor (NP), Graphics Processing Unit (GPU), Accelerated Processing Unit (ACCU), Multimedia Application Processor (MAP), microprocessor, etc.; it can also be a Digital Signal Processor (DSP), Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. Alternatively, processor 240 can also be any conventional processor.

[0087] Among them, the aforementioned electronic devices 200 include, but are not limited to, tablet computers, laptops, servers, etc.

[0088] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0089] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip, characterized in that, include: Multiple cores and interconnect links, the multiple cores are connected to form a MESH network through the interconnect links, the multiple cores include M×N cores, where M and N are both integers greater than or equal to 2, each core is connected to at least two interconnect links, the at least two interconnect links include horizontal interconnect links and vertical interconnect links, each interconnect link is connected to a different core and is not a backup redundant link; Each of the cores is equipped with a preset routing table, which includes a cross-core primary routing table and a cross-core backup routing table. The cross-core primary routing table follows a configuration rule of either prioritizing the vertical interconnection link before the horizontal interconnection link or vice versa, and is used to determine the optimal transmission path for data transmission when the interconnection link is normal. The cross-core backup routing table follows a configuration rule of mutual backup between the horizontal interconnection link and the vertical interconnection link, and is used to determine a transmission path that bypasses the abnormal interconnection link and includes a second interconnection link. Each of the cores is used to obtain a cross-core backup routing table in the preset routing table when data is expected to be transmitted to the destination through the transmission path of the first interconnection link among the at least two interconnection links, and the first interconnection link is abnormal. It also automatically selects the second interconnection link according to the cross-core backup routing table and uses the second interconnection link to replace the first interconnection link for data transmission. The second interconnection link is a normal link and there is a transmission path between the second interconnection link and the destination.

2. The chip according to claim 1, characterized in that, Each of the cores is equipped with an adaptive routing control module, which is used to obtain the cross-core backup routing table when the first interconnection link of the at least two interconnection links is abnormal, and automatically select the transmission path of the second interconnection link for data transmission according to the cross-core backup routing table.

3. The chip according to claim 2, characterized in that, The adaptive routing control module includes: The routing lookup unit is used to look up the preset routing table built into the core. A path switching control unit is connected to the routing table lookup unit. When the first interconnection link is abnormal, the path switching control unit is used to look up the cross-core backup routing table through the routing table lookup unit, and automatically select the transmission path where the second interconnection link is located for data transmission based on the found cross-core backup routing table.

4. The chip according to claim 3, characterized in that, The adaptive routing control module further includes a link status monitoring unit, which is connected to the path switching control unit; The link status monitoring unit is used to monitor the status of interconnected links. When an abnormality is detected in the first interconnected link, the abnormal first interconnected link is recorded in the abnormal link table. The path switching control unit is also used to access the abnormal link table to identify abnormal interconnecting links.

5. The chip according to claim 2, characterized in that, The core also includes: A buffer queue is used to temporarily buffer the data transmitted externally by the core. The adaptive routing control module is also used to utilize the second interconnection link to transmit data transmitted externally by the core in the cache queue.

6. The chip according to claim 2, characterized in that, The core also includes: a master module, a slave module, a routing node, and at least two interconnect modules, wherein the at least two interconnect modules, the master module, and the slave module are all connected to the routing node; Each of the interconnect modules, master modules, and slave modules in the core is equipped with the adaptive routing control module; The adaptive routing control module in the interconnection module is also used to report the abnormal link information to the adaptive routing control modules in other modules in the core when an abnormality is detected in the first interconnection link.

7. The chip according to any one of claims 1-6, characterized in that, The chip in question is a server chip.

8. An electronic device, characterized in that, include: The chip as described in any one of claims 1-7.

9. A method for data transmission between chip chips, characterized in that, Applied to the chip as described in any one of claims 1-7; the method includes: When the core is expected to transmit data to the destination through the transmission path of the first interconnection link among the at least two interconnection links, and the first interconnection link is abnormal, the core obtains the preset cross-core backup routing table in the core and automatically selects the second interconnection link among the at least two interconnection links according to the cross-core backup routing table. The core uses the second interconnect link to replace the first interconnect link for data transmission; wherein the second interconnect link is a normal link, and there is a transmission path between the second interconnect link and the destination.

10. The method according to claim 9, characterized in that, Each core is equipped with an adaptive routing control module that automatically selects the second interconnection link from the at least two interconnection links, including: The adaptive routing control module obtains a preset cross-core backup routing table in the core, wherein the cross-core backup routing table is used to determine a transmission path that bypasses the abnormal interconnection link and includes a second interconnection link; The adaptive routing control module automatically selects the second interconnection link from the at least two interconnection links based on the cross-core backup routing table.

11. The method according to claim 9, characterized in that, Each core is equipped with an adaptive routing control module, and the method further includes: The adaptive routing control module monitors the status of interconnect links, and when it detects an anomaly in the first interconnect link, it records the anomaly in the anomaly link table.

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