A semiconductor device, a method of fabricating the same, and a memory system

Abstract

The application provides a semiconductor device and a preparation method thereof, and a memory system, the semiconductor device comprising: a plurality of silicon columns arranged in an array; an oxidation insulating layer arranged between any two adjacent silicon columns; a plurality of bit lines, the bit lines being arranged on one side of the silicon columns; and a first insulating layer arranged on a side of the bit lines away from the silicon columns, in the semiconductor device, an isolation structure for reducing coupling capacitance can be formed on the oxidation insulating layer between two adjacent bit lines, and since the first insulating layer is arranged on the side of the bit lines away from the silicon columns, the gap between the first insulating layers arranged on the sides of the two adjacent bit lines away from the silicon columns can be further utilized, so that the arrangement space of the isolation structure is increased, and the coupling capacitance between the bit lines is reduced, the sensing tolerance of the semiconductor device is improved, and the device performance is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor chip technology, and in particular to a semiconductor device and its fabrication method, and a memory system. Background Technology

[0002] In the electronics industry, three-dimensional (3D) stacking technology facilitates the integration of semiconductor devices. To form a 3D stack, two or more chips are arranged one on top of the other and bonded together.

[0003] In three-dimensional dynamic random access memory (3D DRAM), there is a coupling capacitance between two adjacent bit lines. When the coupling capacitance between bit lines is too large, the sensing tolerance of the 3D DRAM will be reduced, and the device performance will be degraded.

[0004] Therefore, how to reduce the coupling capacitance between bit lines, improve the sensing tolerance of 3D DRAM, and improve device performance is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] This application provides a semiconductor device and its fabrication method, as well as a memory system, which can effectively solve the problem of excessively large coupling capacitance between bit lines in semiconductor devices.

[0006] In a first aspect, embodiments of this application provide a semiconductor device, the semiconductor device comprising: a plurality of silicon pillars arranged in an array; an oxide insulating layer disposed between any two adjacent silicon pillars; a plurality of bit lines disposed on one side of the silicon pillars; and a first insulating layer disposed on the side of the bit lines opposite to the silicon pillars.

[0007] In some embodiments, the semiconductor device further includes a hollow dielectric layer disposed on the side of the first insulating layer away from the silicon pillars, and filling the gaps between the silicon pillars, the gaps between the bit lines, and the gaps between the first insulating layers.

[0008] In some embodiments, the hollow dielectric layer includes a plurality of air gaps, and at least one air gap is provided between any two adjacent bit lines.

[0009] In some embodiments, the bit line includes a first film layer and a second film layer sequentially stacked on one side of the silicon pillar, wherein a groove is provided on the side of the second film layer opposite to the first film layer, and the groove is filled with a third film layer; the first insulating layer is disposed on the surface of the second film layer and the third film layer on the side opposite to the first film layer.

[0010] In some embodiments, the first film layer comprises a silicon metal compound, the second film layer comprises a titanium nitride compound, and the third film layer comprises tungsten.

[0011] In some embodiments, the bit line includes a first film layer, wherein the first insulating layer is disposed on a surface of the first film layer on the side opposite to the oxide insulating layer.

[0012] In some embodiments, the first insulating layer comprises an oxide of the material of the first film layer.

[0013] In some embodiments, the first insulating layer comprises a non-metallic nitride.

[0014] In some embodiments, the material of the first insulating layer is the same as that of the oxide insulating layer.

[0015] Secondly, embodiments of this application provide a method for fabricating a semiconductor device, the method comprising the following steps:

[0016] Multiple silicon pillars are formed in an array, and an oxide insulating layer is formed between the silicon pillars;

[0017] Bit lines are formed on one side of each of the silicon pillars;

[0018] A first insulating layer is formed on the side of the bit line opposite to the silicon pillar;

[0019] A hollow dielectric layer is formed on the side of the first insulating layer opposite to the bit line.

[0020] In some embodiments, in the step of forming a plurality of silicon pillars arranged in an array and forming an oxide insulating layer between the silicon pillars, the oxide insulating layer and the silicon pillars form a plurality of first groove structures; in the step of forming a bit line on one side of each silicon pillar, the bit line is formed in the first groove structure, and the oxide insulating layer protrudes from the bit line; in the step of forming a first insulating layer on the side of the bit line away from the silicon pillar, the surface of the first insulating layer on the side away from the silicon pillar is flush with the surface of the oxide insulating layer; before forming a hollow dielectric layer on the side of the first insulating layer away from the bit line, the method further includes the steps of: removing a portion of the oxide insulating layer to expose at least a portion of the silicon pillars; in the step of forming a hollow dielectric layer on the side of the first insulating layer away from the bit line, the hollow dielectric layer fills the gaps between the silicon pillars, the gaps between the bit lines, and the gaps between the first insulating layers.

[0021] In some embodiments, in the step of forming a plurality of silicon pillars arranged in an array and forming an oxide insulating layer between the silicon pillars, the oxide insulating layer and the silicon pillars form a plurality of second groove structures; in the step of forming a bit line on one side of each silicon pillar, the bit line is formed in the second groove structure; in the step of forming a first insulating layer on the side of the bit line away from the silicon pillar, a portion of the bit line is converted into the first insulating layer by oxidizing the surface of the bit line; before forming a hollow dielectric layer on the side of the first insulating layer away from the bit line, the method further includes the following steps: removing a portion of the oxide insulating layer to expose at least a portion of the silicon pillars; in the step of forming a hollow dielectric layer on the side of the first insulating layer away from the bit line, the hollow dielectric layer fills the gaps between the silicon pillars, the gaps between the bit lines, and the gaps between the first insulating layers.

[0022] In some embodiments, prior to the step of forming a bit line on one side of each silicon pillar, the method further includes: removing a portion of an oxide insulating layer to expose at least a portion of the silicon pillar; forming a sacrificial layer on one side of the oxide insulating layer, wherein the surface of the sacrificial layer is flush with the surface of the silicon pillar; removing a portion of the silicon pillar to form a plurality of third groove structures with the sacrificial layer and the silicon pillar; in the step of forming a bit line on one side of each silicon pillar, the bit line is formed in the third groove structure, and the sacrificial layer protrudes from the bit line; in the step of forming a first insulating layer on the side of the bit line away from the silicon pillar, the surface of the first insulating layer on the side away from the silicon pillar is flush with the surface of the sacrificial layer; prior to forming a hollow dielectric layer on the side of the first insulating layer away from the bit line, the method further includes the steps of: removing the sacrificial layer to expose at least a portion of the silicon pillar; in the step of forming a hollow dielectric layer on the side of the first insulating layer away from the bit line, the hollow dielectric layer fills the gaps between silicon pillars, the gaps between bit lines, and the gaps between the first insulating layers.

[0023] Thirdly, this application provides a memory system, the memory system including a memory array structure and a peripheral structure connected to the memory array structure; at least one of the memory array structure and the peripheral structure includes the semiconductor device described in any of the above claims.

[0024] This application provides a semiconductor device and its fabrication method, as well as a memory system. The semiconductor device includes: a plurality of silicon pillars arranged in an array; an oxide insulating layer disposed between any two adjacent silicon pillars; a plurality of bit lines disposed on one side of the silicon pillars; and a first insulating layer disposed on the side of the bit lines away from the silicon pillars. In the semiconductor device provided by this application, an isolation structure for reducing coupling capacitance can be formed on the oxide insulating layer between two adjacent bit lines. Furthermore, since the first insulating layer is disposed on the side of the bit lines away from the silicon pillars, the gap between the first insulating layers disposed on the side of two adjacent bit lines away from the silicon pillars can be further utilized to increase the space for the isolation structure, thereby reducing the coupling capacitance between the bit lines, improving the sensing tolerance of the semiconductor device, and enhancing device performance. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1This is a planar schematic diagram of a semiconductor device provided for some embodiments of this application.

[0027] Figure 2 For some embodiments of this application, the following are provided: Figure 1 A schematic cross-sectional view of a semiconductor device cut along the CC' line.

[0028] Figure 3 This is a cross-sectional schematic diagram of a semiconductor device corresponding to different steps in some embodiments of this application.

[0029] Figure 4 For some embodiments of this application, the following are provided: Figure 1 A cross-sectional schematic diagram of another semiconductor device cut along the CC' line.

[0030] Figure 5 This is a cross-sectional schematic diagram of another semiconductor device provided in some embodiments of this application corresponding to different steps.

[0031] Figure 6 For some embodiments of this application, the following are provided: Figure 1 A cross-sectional schematic diagram of another semiconductor device cut along the CC' line.

[0032] Figure 7 This is a cross-sectional schematic diagram of another semiconductor device corresponding to different steps in some embodiments of this application.

[0033] Explanation of reference numerals in the attached figures:

[0034] Silicon pillar 10; oxide insulating layer 20; first groove structure 21; bit line 30; first film layer 31; second film layer 32; third film layer 33; first insulating layer 40; hollow dielectric layer 50; air gap 51; constriction portion 52; uniform opening portion 53;

[0035] Silicon pillar 10ˋ; Oxide insulating layer 20ˋ; Second groove structure 21ˋ; Bit line 30ˋ; First film layer 31ˋ; First insulating layer 40ˋ; Hollow dielectric layer 50ˋ; Air gap 51ˋ; Closure portion 52ˋ; Uniform opening portion 53ˋ;

[0036] Silicon pillar 10ˋˋ; Oxide insulating layer 20ˋˋ; Bit line 30ˋˋ; First film layer 31ˋˋ; First insulating layer 40ˋˋ; Hollow dielectric layer 50ˋˋ; Air gap 51ˋˋ; Closure portion 52ˋˋ; Uniform opening portion 53ˋˋ; Sacrificial layer 100; Third groove structure 101; First direction X; Second direction Y; Third direction Z; Detailed Implementation

[0037] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0038] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of this application.

[0039] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be an inserted component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0040] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, while the top side is relatively away from the substrate. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (where contacts, interconnects, and one or more dielectric layers are formed).

[0041] As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate, such that the array structure extends in a vertical direction relative to the substrate; "vertical" means perpendicular to the direction of the substrate.

[0042] It should be noted that the illustrations provided in the embodiments of this application are only schematic representations of the basic concept of this application. Although the illustrations only show the components related to this application and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0043] Figure 1A planar schematic diagram of a semiconductor device provided for some embodiments of this application; Figure 2 For some embodiments of this application, the following are provided: Figure 1 A schematic cross-sectional view of a semiconductor device taken along the CC' line. (Refer to...) Figure 1 and Figure 2 As shown, in a first aspect, embodiments of this application provide a semiconductor device, the semiconductor device comprising: a plurality of silicon pillars 10 arranged in an array; an oxide insulating layer 20 disposed between any two adjacent silicon pillars 10; a plurality of bit lines 30 disposed on one side of the silicon pillars 10; and a first insulating layer 40 disposed on the side of the bit lines 30 opposite to the silicon pillars 10.

[0044] In some embodiments of this application, a coupling capacitance effect occurs between two adjacent bit lines 30. By forming an isolation structure, such as an air gap 51, on the oxide insulating layer 20 between the two adjacent bit lines 30, the dielectric constant of the coupling capacitance can be reduced, thereby improving the operating efficiency of the semiconductor device. However, due to process limitations, the end of the air gap 51 facing away from the oxide insulating layer 20 has a tapered portion 52. The width of the tapered portion 52 gradually narrows in the direction away from the oxide insulating layer 20. When the tapered portion 52 between two adjacent bit lines 30 overlaps with the two adjacent bit lines 30 in the first direction X, the ability of the air gap 51 to improve the coupling capacitance decreases, resulting in a problem of excessively large coupling capacitance between the two adjacent bit lines 30.

[0045] In the semiconductor device provided in this application, since the first insulating layer 40 is disposed on the side of the bit line 30 away from the silicon pillar 10, and the position of the first insulating layer 40 corresponds to the position of the bit line 30, a gap can be formed between the two first insulating layers 40 on two adjacent bit lines 30, and the gap is connected to the gap between two adjacent bit lines 30. This increases the space for the air gap 51 disposed on the oxide insulating layer 20 between two adjacent bit lines 30, thereby raising the position of the closing portion 52. This allows the closing portion 52 to be formed above the gap between two adjacent bit lines 30, improving the ability of the air gap 51 to improve coupling capacitance, increasing the sensing tolerance of the semiconductor device, and improving device performance.

[0046] In some embodiments of this application, the bit line 30 extends along the second direction Y, and the silicon pillar 10, the bit line 30 and the first insulating layer 40 are stacked on the third direction Z. The arrangement of the first insulating layer 40 can change the position of the closing portion 52 on the third direction Z, so that the closing portion 52 does not overlap with the bit line 30 or the overlapping area is reduced in the first direction X.

[0047] In some embodiments of this application, the semiconductor device further includes a hollow dielectric layer 50, which is disposed on the side of the first insulating layer 40 away from the silicon pillars 10 and fills the gaps between the silicon pillars 10, the gaps between the bit lines 30, and the gaps between the first insulating layers 40.

[0048] In the semiconductor device provided in this application, the hollow dielectric layer 50 includes a plurality of hollow structures for forming the air gap 51 to reduce the dielectric constant of the coupling capacitor, thereby improving the operating efficiency of the semiconductor device.

[0049] In some embodiments of this application, the hollow dielectric layer 50 includes a plurality of air gaps 51, and at least one air gap 51 is provided between any two adjacent bit lines 30.

[0050] Furthermore, the air gap 51 includes a uniform opening 53 and a constricted opening 52. The constricted opening 52 is disposed on the side of the uniform opening 53 away from the oxide insulating layer 20. In the direction away from the oxide insulating layer 20, the uniform opening 53 has a uniform or nearly uniform width, and the width of the constricted opening 52 gradually decreases. The distance between the side of the uniform opening 53 away from the oxide insulating layer 20 and the plane where the oxide insulating layer 20 is located is greater than the distance between the bit line 30 and the plane where the oxide insulating layer 20 is located. This allows the uniform opening 53 to overlap with the bit line 30 in the first direction X, while the constricted opening 52 does not overlap with the bit line 30 in the first direction X. This ensures that the air gap 51 reduces the coupling capacitance between two adjacent bit lines 30, keeping the coupling capacitance between two adjacent bit lines 30 at a low level, improving the sensing tolerance of the semiconductor device, and improving device performance.

[0051] In some embodiments of this application, the bit line 30 includes a first film layer 31 and a second film layer 32 sequentially stacked on one side of the silicon pillar 10. The second film layer 32 has a groove on the side facing away from the first film layer 31, and the groove is filled with a third film layer 33. The first insulating layer 40 is disposed on the surfaces of the second film layer 32 and the third film layer 33 on the side facing away from the first film layer 31. Of course, this application does not limit the film layer structure of the bit line 30. In other embodiments of this application, the bit line 30 includes a first film layer, and the first insulating layer is disposed on the surface of the first film layer on the side facing away from the oxide insulating layer.

[0052] In some embodiments of this application, the first film layer 31 comprises a silicon metal compound, the second film layer 32 comprises a titanium nitride compound, and the third film layer 33 is made of tungsten.

[0053] In some embodiments of this application, the first insulating layer comprises a non-metallic nitride.

[0054] Figure 3 This is a cross-sectional schematic diagram of a semiconductor device corresponding to different steps in some embodiments of this application. (Refer to...) Figures 1-3 As shown, in a second aspect, embodiments of this application also provide a method for fabricating a semiconductor device, the method comprising the following steps:

[0055] A plurality of silicon pillars 10 are arranged in an array, and an oxide insulating layer 20 is formed between the silicon pillars 10;

[0056] Bit lines 30 are formed on one side of each of the silicon pillars 10;

[0057] A first insulating layer 40 is formed on the side of the bit line 30 opposite to the silicon pillar 10;

[0058] A hollow dielectric layer 50 is formed on the side of the first insulating layer 40 opposite to the bit line 30.

[0059] In some embodiments of this application, in the step of forming a plurality of silicon pillars 10 arranged in an array and forming an oxide insulating layer 20 between the silicon pillars 10, the oxide insulating layer 20 and the silicon pillars 10 form a plurality of first groove structures 21.

[0060] In some embodiments of this application, in the step of forming a bit line 30 on one side of each of the silicon pillars 10, the bit line 30 is formed in the first groove structure 21, and the oxide insulating layer 20 protrudes from the bit line 30.

[0061] In some embodiments of this application, in the step of forming a first insulating layer 40 on the side of the bit line 30 away from the silicon pillar 10, the surface of the first insulating layer 40 on the side away from the silicon pillar 10 is flush with the surface of the oxide insulating layer 20.

[0062] In some embodiments of this application, before forming the hollow dielectric layer 50 on the side of the first insulating layer 40 opposite to the bit line 30, the method further includes the step of removing a portion of the oxide insulating layer 20 to expose at least a portion of the silicon pillar 10. Exemplarily, a chemical mechanical polishing (CMP) process can be used to remove a portion of the oxide insulating layer 20.

[0063] In some embodiments of this application, in the step of forming a hollow dielectric layer 50 on the side of the first insulating layer 40 opposite to the bit line 30, the hollow dielectric layer 50 fills the gaps between the silicon pillars 10, the gaps between the bit lines 30, and the gaps between the first insulating layers 40. The hollow dielectric layer 50 includes a plurality of air gaps 51, and at least one air gap 51 is provided between any two adjacent bit lines 30.

[0064] It should be noted that, due to limitations in semiconductor processes, the surface of each film layer cannot be made completely flat. Therefore, the situation in which the surface of one film layer is flush with the surface of another film layer as described in this application includes being completely flush or nearly flush. Nearly flush means that the height difference between the highest point of the surface of one film layer and the lowest point of the surface of another film layer is within a preset threshold range.

[0065] Thirdly, embodiments of this application also provide a storage system, the storage system including a memory, the memory being a semiconductor device as described in any of the preceding claims or a part of the semiconductor device.

[0066] Figure 4 For some embodiments of this application, the following are provided: Figure 1 A cross-sectional schematic diagram of another semiconductor device cut along the CC' line. (Combined with...) Figure 1 and Figure 4 As shown, in a first aspect, embodiments of this application provide a semiconductor device, the semiconductor device comprising: a plurality of silicon pillars 10ˋ arranged in an array; an oxide insulating layer 20ˋ disposed between any two adjacent silicon pillars 10ˋ; a plurality of bit lines 30ˋ disposed on one side of the silicon pillars 10ˋ; and a first insulating layer 40ˋ disposed on the side of the bit lines 30ˋ facing away from the silicon pillars 10ˋ.

[0067] It should be noted that, as Figure 4 The semiconductor device shown is Figure 2 The structure of the semiconductor device shown is similar. For example, the semiconductor device further includes a hollow dielectric layer 50', which is disposed on the side of the first insulating layer 40' away from the silicon pillars 10' and fills the gaps between the silicon pillars 10', the gaps between the bit lines 30', and the gaps between the first insulating layers 40'. The hollow dielectric layer 50' includes a plurality of air gaps 51', and at least one air gap 51' is provided between any two adjacent bit lines 30'. The air gap 51' includes a constricted portion 52' and a uniformly open portion 53'. The same parts will not be described again.

[0068] The difference is that the bit line 30' includes a first film layer 31', and the first insulating layer 40' is disposed on the surface of the first film layer 31' opposite to the oxide insulating layer 20'. That is, the first film layer 31' is the film layer of the bit line 30' that is in contact with the first insulating layer 40'.

[0069] In some embodiments of this application, the bit line 30' only includes the first film layer 31', that is, the bit line 30' is a single film layer structure, so as to simplify the manufacturing process of the bit line 30' and improve the process efficiency.

[0070] In some embodiments of this application, the bit line 30' includes a first film layer 31' and other film layers, which are disposed between the first film layer 31' and the silicon pillar 10'. That is, the first film layer 31' is the film layer furthest from the silicon pillar 10' in the bit line 30'.

[0071] In some embodiments of this application, the first insulating layer 40' comprises an oxide of the material of the first film layer 31'.

[0072] For example, the first film layer 31' comprises a silicon metal compound, and the first insulating layer 40' comprises an oxide of the silicon metal compound.

[0073] In the semiconductor device provided in this application, since the first insulating layer 40' includes the oxide of the first film layer 31', that is, the first insulating layer 40' can be directly obtained by the oxidation process of the first film layer 31', the preparation process is simple, and the self-alignment effect of the first insulating layer 40' and the first film layer 31' can be achieved.

[0074] Figure 5 This is a cross-sectional schematic diagram showing different steps corresponding to another semiconductor device provided in some embodiments of this application. (In conjunction with...) Figure 1 , Figure 4 and Figure 5 As shown, in a second aspect, embodiments of this application also provide a method for fabricating a semiconductor device, the method comprising the following steps:

[0075] A plurality of silicon pillars 10ˋ are formed in an array, and an oxide insulating layer 20ˋ is formed between the silicon pillars 10ˋ;

[0076] Bit lines 30' are formed on one side of each of the silicon pillars 10';

[0077] A first insulating layer 40' is formed on the side of the bit line 30' that is away from the silicon pillar 10';

[0078] A hollow dielectric layer 50' is formed on the side of the first insulating layer 40' that is opposite to the bit line 30'.

[0079] In some embodiments of this application, in the step of forming a plurality of silicon pillars 10ˋ arranged in an array and forming an oxide insulating layer 20ˋ between the silicon pillars 10ˋ, the oxide insulating layer 20ˋ and the silicon pillars 10ˋ form a plurality of second groove structures 21ˋ.

[0080] In some embodiments of this application, in the step of forming a bit line 30' on one side of each silicon pillar 10', the bit line 30' is formed in the second groove structure 21'. Optionally, the surface of the oxide insulating layer 20' is flush with the surface of the bit line 30'.

[0081] In some embodiments of this application, in the step of forming the first insulating layer 40' on the side of the bit line 30' facing away from the silicon pillar 10', the surface of the bit line 30' is oxidized to convert a portion of the bit line 30' into the first insulating layer 40'. Optionally, the surface of the first insulating layer 40' facing away from the silicon pillar 10' is flush with the surface of the oxidized insulating layer 20'.

[0082] In some embodiments of this application, before forming the hollow dielectric layer 50' on the side of the first insulating layer 40' away from the bit line 30', the method further includes the step of removing a portion of the oxide insulating layer 20' to expose at least a portion of the silicon pillar 10'.

[0083] In some embodiments of this application, in the step of forming a hollow dielectric layer 50' on the side of the first insulating layer 40' away from the bit line 30', the hollow dielectric layer 50' fills the gaps between the silicon pillars 10', the gaps between the bit lines 30', and the gaps between the first insulating layers 40'.

[0084] In the semiconductor device fabrication method provided in this application embodiment, since the surface of the bit line 30' can be oxidized to transform a portion of the bit line 30' into a first insulating layer 40', the first insulating layer 40' can be directly obtained after the oxidation process of the first film layer 31'. The fabrication process is simple and can achieve the self-alignment effect of the first insulating layer 40' and the first film layer 31'.

[0085] Thirdly, embodiments of this application also provide a storage system, the storage system including a memory, the memory being a semiconductor device as described in any of the preceding claims or a part of the semiconductor device.

[0086] Figure 6 For some embodiments of this application, the following are provided: Figure 1A cross-sectional schematic diagram of another semiconductor device cut along the CC' line. (Combined with...) Figure 1 and Figure 6 As shown, in a first aspect, embodiments of this application provide a semiconductor device, the semiconductor device comprising: a plurality of silicon pillars 10ˋˋ arranged in an array; an oxide insulating layer 20ˋˋ disposed between any two adjacent silicon pillars 10ˋˋ; a plurality of bit lines 30ˋˋ disposed on one side of the silicon pillars 10ˋˋ; and a first insulating layer 40ˋˋ disposed on the side of the bit lines 30ˋˋ facing away from the silicon pillars 10ˋˋ.

[0087] It should be noted that, as Figure 5 The semiconductor device shown is Figure 1 The structure of the semiconductor device shown is similar. For example, the semiconductor device further includes a hollow dielectric layer 50ˋˋ, which is disposed on the side of the first insulating layer 40ˋˋ facing away from the silicon pillars 10ˋˋ and fills the gaps between the silicon pillars 10ˋˋ, the gaps between the bit lines 30ˋˋ, and the gaps between the first insulating layers 40ˋˋ. The hollow dielectric layer 50ˋˋ includes a plurality of air gaps 51ˋˋ, and at least one air gap 51ˋˋ is provided between any two adjacent bit lines 30ˋˋ. The air gap 51ˋˋ includes a constricted portion 52ˋˋ and a uniformly open portion 53. The bit line 30 includes a first film layer 31, and the first insulating layer 40 is disposed on the surface of the first film layer 31 opposite to the oxide insulating layer 20. Alternatively, the bit line 30 includes a first film layer and a second film layer sequentially stacked on one side of the silicon pillar 10, wherein the second film layer has a groove on the side opposite to the first film layer 31, and the groove is filled with a third film layer. The first insulating layer 40 is disposed on the surface of the second film layer and the third film layer on the side opposite to the first film layer 31. Alternatively, the same parts will not be described in detail.

[0088] The difference is that the material of the first insulating layer 40ˋˋ is the same as that of the oxide insulating layer 20ˋˋ.

[0089] In the semiconductor device provided in this application, since the material of the first insulating layer 40ˋˋ is the same as that of the oxide insulating layer 20ˋˋ, the first insulating layer 40ˋˋ can be prepared using existing materials without increasing the types of materials, thereby reducing the production cost.

[0090] Figure 7 This is a cross-sectional schematic diagram showing another semiconductor device corresponding to different steps in some embodiments of this application. (In conjunction with...) Figure 1 , Figure 6 and Figure 7As shown, in a second aspect, embodiments of this application also provide a method for fabricating a semiconductor device, the method comprising the following steps:

[0091] A plurality of silicon pillars 10ˋˋ are formed in an array, and an oxide insulating layer 20ˋˋ is formed between the silicon pillars 10ˋˋ.

[0092] Bit lines 30ˋˋ are formed on one side of each of the silicon pillars 10ˋˋ;

[0093] A first insulating layer 40ˋˋ is formed on the side of the bit line 30ˋˋ that is away from the silicon pillar 10ˋˋ.

[0094] A hollow dielectric layer 50 is formed on the side of the first insulating layer 40ˋˋ that is opposite to the bit line 30ˋˋ.

[0095] In some embodiments of this application, in the step of forming a plurality of silicon pillars 10ˋˋ arranged in an array and forming an oxide insulating layer 20ˋˋ between the silicon pillars 10ˋˋ, the surface of the oxide insulating layer 20ˋˋ is flush with the surface of the silicon pillars 10ˋˋ.

[0096] In some embodiments of this application, prior to the step of forming bit lines 30ˋˋ on one side of each silicon pillar 10ˋˋ, the method further includes: removing a portion of the oxide insulating layer 20ˋˋ to expose at least a portion of the silicon pillar 10ˋˋ; forming a sacrificial layer 100 on one side of the oxide insulating layer 20ˋˋ, with the surface of the sacrificial layer 100 flush with the surface of the silicon pillar 10ˋˋ; and removing a portion of the silicon pillar 10ˋˋ to form a plurality of third groove structures 101 by the sacrificial layer 100 and the silicon pillar 10ˋˋ.

[0097] In some embodiments of this application, in the step of forming a bit line 30ˋˋ on one side of each of the silicon pillars 10ˋˋ, the bit line 30ˋˋ is formed in the third groove structure 101, and the sacrificial layer 100 protrudes from the bit line 30ˋˋ.

[0098] In some embodiments of this application, in the step of forming a first insulating layer 40ˋˋ on the side of the bit line 30ˋˋ away from the silicon pillar 10ˋˋ, the surface of the first insulating layer 40ˋˋ away from the silicon pillar 10ˋˋ is flush with the surface of the sacrificial layer 100, and the first insulating layer 40ˋˋ is made of the same material as the oxide insulating layer 20ˋˋ.

[0099] In some embodiments of this application, before forming the hollow dielectric layer 50 on the side of the first insulating layer 40ˋˋ away from the bit line 30ˋˋ, the method further includes the step of removing the sacrificial layer 100 to expose at least a portion of the silicon pillar 10ˋˋ.

[0100] In some embodiments of this application, in the step of forming a hollow dielectric layer 50ˋˋ on the side of the first insulating layer 40ˋˋ away from the bit line 30ˋˋ, the hollow dielectric layer 50ˋˋ fills the gaps between the silicon pillars 10ˋˋ, the gaps between the bit lines 30ˋˋ, and the gaps between the first insulating layers 40ˋˋ.

[0101] In the semiconductor device fabrication method provided in this application embodiment, by setting the sacrificial layer 100, the sacrificial layer 100 and the silicon pillar 10ˋˋ can form a plurality of third groove structures 101, thereby enabling the first insulating layer 40ˋˋ to be fabricated using the same material as the oxide insulating layer 20ˋˋ. This achieves the fabrication of the first insulating layer 40ˋˋ using existing materials without increasing the types of materials, thereby reducing production and manufacturing costs.

[0102] Thirdly, embodiments of this application also provide a storage system, the storage system including a memory, the memory being a semiconductor device as described in any of the preceding claims or a part of the semiconductor device.

[0103] In summary, this application provides a semiconductor device and its fabrication method, as well as a memory system. The semiconductor device includes: a plurality of silicon pillars arranged in an array; an oxide insulating layer disposed between any two adjacent silicon pillars; a plurality of bit lines disposed on one side of the silicon pillars; and a first insulating layer disposed on the side of the bit lines away from the silicon pillars. In the semiconductor device provided by this application, an isolation structure for reducing coupling capacitance can be formed on the oxide insulating layer between two adjacent bit lines. Furthermore, since the first insulating layer is disposed on the side of the bit lines away from the silicon pillars, the gap between the first insulating layers disposed on the side of two adjacent bit lines away from the silicon pillars can be further utilized to increase the space for the isolation structure, thereby reducing the coupling capacitance between the bit lines, improving the sensing tolerance of the semiconductor device, and enhancing device performance.

[0104] The above provides a detailed description of a semiconductor device and its fabrication method, as well as a memory system, provided by the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: Multiple silicon pillars arranged in an array; An oxide insulating layer is disposed between any two adjacent silicon pillars; Multiple bit lines, said bit lines being disposed on one side of the silicon pillar; and A first insulating layer is disposed on the side of the bit line opposite to the silicon pillar.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a hollow dielectric layer disposed on the side of the first insulating layer away from the silicon pillars, and filling the gaps between the silicon pillars, the gaps between the bit lines, and the gaps between the first insulating layers.

3. The semiconductor device according to claim 2, characterized in that, The hollow dielectric layer includes multiple air gaps, and at least one air gap is provided between any two adjacent bit lines.

4. The semiconductor device according to claim 1, characterized in that, The bit line includes a first film layer and a second film layer stacked sequentially on one side of the silicon pillar, wherein the second film layer has a groove on the side away from the first film layer, and the groove is filled with a third film layer; the first insulating layer is disposed on the surface of the second film layer and the third film layer on the side away from the first film layer.

5. The semiconductor device according to claim 4, characterized in that, The first film layer comprises a silicon metal compound, the second film layer comprises a titanium nitride compound, and the third film layer comprises tungsten.

6. The semiconductor device according to claim 1, characterized in that, The bit line includes a first film layer, and the first insulating layer is disposed on the surface of the first film layer on the side opposite to the oxide insulating layer.

7. The semiconductor device according to claim 6, characterized in that, The first insulating layer comprises an oxide of the material of the first film layer.

8. The semiconductor device according to claim 4 or 6, characterized in that, The first insulating layer comprises a non-metallic nitride.

9. The semiconductor device according to claim 4 or 6, characterized in that, The material of the first insulating layer is the same as that of the oxide insulating layer.

10. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: Multiple silicon pillars are formed in an array, and an oxide insulating layer is formed between the silicon pillars; Bit lines are formed on one side of each of the silicon pillars; A first insulating layer is formed on the side of the bit line opposite to the silicon pillar; A hollow dielectric layer is formed on the side of the first insulating layer opposite to the bit line.

11. The method for fabricating a semiconductor device according to claim 10, characterized in that, In the step of forming an array of silicon pillars and forming an oxide insulating layer between the silicon pillars, the oxide insulating layer and the silicon pillars form a plurality of first groove structures; In the step of forming a bit line on one side of each of the silicon pillars, the bit line is formed in the first groove structure, and the oxide insulating layer protrudes from the bit line; In the step of forming a first insulating layer on the side of the bit line away from the silicon pillar, the surface of the first insulating layer on the side away from the silicon pillar is flush with the surface of the oxide insulating layer. Before forming a hollow dielectric layer on the side of the first insulating layer away from the bit line, the method further includes the step of removing a portion of the oxide insulating layer to expose at least a portion of the silicon pillar; In the step of forming a hollow dielectric layer on the side of the first insulating layer away from the bit line, the hollow dielectric layer fills the gaps between silicon pillars, the gaps between the bit lines, and the gaps between the first insulating layers.

12. The method for fabricating a semiconductor device according to claim 10, characterized in that, In the step of forming an array of silicon pillars and forming an oxide insulating layer between the silicon pillars, the oxide insulating layer and the silicon pillars form a plurality of second groove structures; In the step of forming a bit line on one side of each of the silicon pillars, the bit line is formed in the second groove structure; In the step of forming a first insulating layer on the side of the bit line away from the silicon pillar, the surface of the bit line is oxidized to convert a portion of the bit line into the first insulating layer. Before forming a hollow dielectric layer on the side of the first insulating layer away from the bit line, the method further includes the step of removing a portion of the oxide insulating layer to expose at least a portion of the silicon pillar; In the step of forming a hollow dielectric layer on the side of the first insulating layer away from the bit line, the hollow dielectric layer fills the gaps between silicon pillars, the gaps between the bit lines, and the gaps between the first insulating layers.

13. The method for fabricating a semiconductor device according to claim 10, characterized in that, Prior to the step of forming a bit line on one side of each of the silicon pillars, the method further includes: removing a portion of the oxide insulating layer to expose at least a portion of the silicon pillar; forming a sacrificial layer on one side of the oxide insulating layer, with the surface of the sacrificial layer flush with the surface of the silicon pillar; and removing a portion of the silicon pillar to form a plurality of third groove structures with the sacrificial layer and the silicon pillar. In the step of forming a bit line on one side of each of the silicon pillars, the bit line is formed in the third groove structure, and the sacrificial layer protrudes from the bit line; In the step of forming a first insulating layer on the side of the bit line away from the silicon pillar, the surface of the first insulating layer on the side away from the silicon pillar is flush with the surface of the sacrificial layer. Before forming a hollow dielectric layer on the side of the first insulating layer away from the bit line, the method further includes the step of removing the sacrificial layer to expose at least a portion of the silicon pillar. In the step of forming a hollow dielectric layer on the side of the first insulating layer away from the bit line, the hollow dielectric layer fills the gaps between silicon pillars, the gaps between the bit lines, and the gaps between the first insulating layers.

14. A storage system, characterized in that, Includes a memory, which is a semiconductor device according to any one of claims 1-9 or a part thereof.

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