Semiconductor device, memory system, and manufacturing method of semiconductor device

Abstract

Embodiments of the present application provide a semiconductor device, a memory system, and a manufacturing method of a semiconductor device. The semiconductor device includes a plurality of semiconductor pillars arranged in a first direction and a second direction, adjacent semiconductor pillars in the first direction each having first sidewalls opposite to each other; a conductive shielding layer located outside the first sidewalls and extending in the second direction; and a filling layer located between the conductive shielding layers; wherein the first direction is perpendicular to the second direction.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device, a memory system, and a method for manufacturing a semiconductor device. Background Technology

[0002] In recent years, in order to increase the storage density of semiconductor memories, the size of memory cells has been continuously reduced. However, as the size of memory cells decreases, the coupling effect between adjacent memory cells intensifies, and due to process limitations, it is difficult to improve the electrical performance caused by the coupling effect. Summary of the Invention

[0003] This application provides a semiconductor device, a memory system, and a method for manufacturing a semiconductor device that can at least partially solve the above-mentioned problems in related technologies or other problems in the art.

[0004] In a first aspect, some embodiments of this application provide a semiconductor device. The semiconductor device includes: a plurality of semiconductor pillars arranged in an array along a first direction and a second direction, wherein adjacent semiconductor pillars in the first direction each have a first sidewall facing each other; a conductive shielding layer located outside the first sidewalls and extending along the second direction; and filling layers located between the conductive shielding layers; wherein the first direction is perpendicular to the second direction.

[0005] In some implementations, the thickness of the conductive shielding layer is substantially the same in the first direction.

[0006] In some embodiments, the semiconductor device further includes a first oxide layer located between the first sidewall and the conductive shielding layer.

[0007] In some embodiments, the conductive shielding layer includes: a first adhesive layer located on the surface of the first oxide layer and extending in a second direction; and a first metal layer located on the surface of the first adhesive layer and extending in the second direction.

[0008] In some embodiments, the semiconductor device has a first region and a second region arranged along a second direction, the second region being located on both sides of the first region, a conductive shielding layer extending within the first and second regions, and in a third direction, the size of the conductive shielding layer within at least one second region being larger than its size within the first region, the third direction being perpendicular to the first and second directions.

[0009] In some embodiments, the semiconductor device further includes a first contact structure located within the second region and connected to a conductive shielding layer.

[0010] In some embodiments, the semiconductor pillar has a second sidewall opposite to the first sidewall, and the semiconductor device further includes: a gate oxide layer located on the surface of the second sidewall; and a gate layer located on the surface of the gate oxide layer and extending along a second direction.

[0011] In some embodiments, the gate layer includes: a second adhesive layer located on the surface of the gate oxide layer and extending in a second direction; and a second metal layer located on the surface of the second adhesive layer and extending in a second direction.

[0012] In some implementations, the ends of a plurality of semiconductor pillars arranged along a first direction are connected to each other.

[0013] Secondly, some embodiments of this application provide a memory system. The memory system includes: a memory device, including semiconductor devices as mentioned in any of the embodiments described above; and a controller coupled to the memory device for controlling the memory device to store data.

[0014] Thirdly, some embodiments of this application provide a method for manufacturing a semiconductor device. The method includes: forming a first trench extending along a first direction from a first side of a semiconductor layer, and filling the first trench with an insulating material; forming a second trench and a third trench extending along a second direction from the first side, the second trench and the third trench being alternately arranged, the first direction being perpendicular to the second direction; forming a conductive shielding layer inside the second trench, and forming a filling layer inside the conductive shielding layer; and forming a gate oxide layer and a gate layer in the third trench.

[0015] In some embodiments, the size of the second trench is smaller than the size of the third trench in the first direction; wherein forming the second trench and the third trench extending along the second direction from the first side includes: forming the second trench and the initial third trench extending along the second direction from the first side, wherein the size of the second trench is equal to the size of the initial third trench in the first direction; and increasing the size of the initial third trench in the first direction by an etching process to form the third trench.

[0016] In some embodiments, forming a gate oxide layer and a gate layer sequentially in a third trench includes: forming a barrier layer at the bottom of the third trench; forming a gate oxide layer on the sidewall of the third trench; forming an initial gate layer on the surface of the gate oxide layer and the surface of the barrier layer; removing a portion of the initial gate layer located on the surface of the barrier layer to disconnect the initial gate layer; and removing a portion of the initial gate layer near the first side to form a gate layer.

[0017] In some embodiments, forming a conductive shielding layer inside the second trench and forming a fill layer inside the conductive shielding layer includes: forming an initial conductive shielding layer inside the second trench; and removing a portion of the initial conductive shielding layer near the first side.

[0018] In some embodiments, the manufacturing method further includes removing a portion of the initial conductive shielding layer from a second side of the semiconductor layer opposite to the first side to form a conductive shielding layer.

[0019] In some embodiments, the semiconductor layer has a first region and a second region arranged along a second direction, with the second region located on both sides of the first region; wherein removing a portion of the initial conductive shielding layer from the second side of the semiconductor layer opposite to the first side includes: removing a portion of the initial conductive shielding layer located within the first region from the second side to form a conductive shielding layer; and filling the space formed after removing a portion of the initial conductive shielding layer with an insulating material.

[0020] In some embodiments, the manufacturing method further includes forming a first contact structure connected to the conductive shielding layer within the second region.

[0021] In some embodiments, before forming an initial conductive shielding layer on the inner side of the second trench, the manufacturing method further includes forming a first oxide layer on the inner wall of the second trench.

[0022] According to at least one embodiment of this application, the semiconductor device, memory system, and manufacturing method of the semiconductor device provided by this application, because the conductive shielding layer is a thin-layer structure and the filling layer is located inside the conductive shielding layer, can enable the conductive shielding layer to have a relatively uniform thickness in the D1 direction, and can also ensure the dimensional matching between the finally formed conductive shielding layer and the gate layer in the D3 direction. Furthermore, the filling layer can reduce the risk of damage to adjacent structures, thereby improving the yield and electrical performance of the final product. On the other hand, the conductive shielding layer with a thin-layer structure is easier to implement in terms of process and has a greater advantage in iterative miniaturization capability. Attached Figure Description

[0023] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0024] Figure 1A and Figure 1B These are cross-sectional schematic diagrams of the semiconductor device provided in the embodiments of this application, taken from different planes perpendicular to a third direction;

[0025] Figure 1C The semiconductor device provided in the embodiments of this application is along Figure 1A or Figure 1B The diagram shows a cross-section taken by line A-A';

[0026] Figure 2 This is a block diagram of a system with a memory system provided in an embodiment of this application;

[0027] Figure 3 This is a schematic flowchart of a method for manufacturing a semiconductor device provided in an embodiment of this application;

[0028] Figures 4A to 13 This is a schematic diagram of the semiconductor device provided in the embodiments of this application during the manufacturing process; and

[0029] Figures 14A to 17 This is a schematic diagram of the structure of a semiconductor device during the manufacturing process according to another embodiment of this application. Detailed Implementation

[0030] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first adhesive layer discussed herein may also be referred to as the second adhesive layer, and vice versa.

[0032] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0033] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0034] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0035] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0036] Furthermore, in this application, the use of "connection" or "linkage" may indicate direct or indirect contact between corresponding components, unless otherwise expressly defined or inferred from the context. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0037] This application provides a semiconductor device. Figure 1A and Figure 1B These are cross-sectional schematic diagrams of the semiconductor device provided in the embodiments of this application, taken from different planes perpendicular to the third (D3) direction. Figure 1C The semiconductor device provided in the embodiments of this application is along Figure 1A or Figure 1B The diagram shows a cross-section taken along line A-A'. Figure 1A and Figure 1B They are Figure 1C The diagram shows a cross-sectional view of a semiconductor device taken along the D3 direction. This semiconductor device may be a memory device or a portion thereof. For example, the memory device may be Dynamic Random Access Memory (DRAM). In DRAM memory, each memory cell typically includes a transistor and a capacitor.

[0038] It should be noted that, in the following figures, directions D1, D2, and D3 illustrate the spatial relationships of components within a semiconductor device. For example, direction D3 is the extension direction of a semiconductor pillar, and directions D1 and D2 are two directions that intersect (e.g., are perpendicular) to each other on a plane that intersects (e.g., is perpendicular) to this extension direction. For example, direction D1 is the bit line direction, and direction D2 is the word line direction. The same concepts will be used throughout this application to describe the spatial relationships of components within a semiconductor device.

[0039] like Figure 1A and Figure 1CAs shown, the semiconductor device 100 includes a plurality of semiconductor pillars (e.g., 111a) arranged in an array along directions D1 and D2. For example, each semiconductor pillar (e.g., 111a) extends along direction D3. As will be described in detail below, the semiconductor pillars (e.g., 111a) may be formed on a semiconductor substrate, and the extension direction of the semiconductor pillars (e.g., 111a) (e.g., direction D3) may be perpendicular to the planar extension direction of the semiconductor substrate.

[0040] In some embodiments, the semiconductor pillars (e.g., 111a) have first sidewalls 112 and second sidewalls 113 facing each other in the D1 direction. The semiconductor device 100 may also include a gate oxide layer 114. The gate oxide layer 114 is located on the surface of the second sidewall 113. For example, the gate oxide layer 114 extends continuously along the D2 direction and is located on the surface of the second sidewall 113 of a row of semiconductor pillars (e.g., 111a) arranged along the D2 direction. For example, the material of the gate oxide layer 114 may include silicon oxide (SiO2) or silicon oxynitride (SiO2). x N y (or any other suitable insulating oxide material) or one or more of these.

[0041] In some embodiments, the semiconductor device 100 may further include a gate layer 115 located on the surface of the gate oxide layer 114. The gate layer 115 extends along the D2 direction (e.g., continuously). For example, refer to... Figure 1C The gate layer 115 may include a second adhesive layer 116 and a second metal layer 117 bonded together. The second adhesive layer 116 may be located on the surface of the gate oxide layer 114 and extend along the D2 direction (e.g., continuously). The second metal layer 117 may be located on the surface of the second adhesive layer 116 and extend along the D2 direction (e.g., continuously). In other words, the second adhesive layer 116 is located between the second metal layer 117 and the gate oxide layer 114. The second adhesive layer 116 helps to improve the bonding performance between the second metal layer 117 and the gate oxide layer 114. For example, the material of the second adhesive layer 116 may include one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or any other suitable material. For example, the material of the second metal layer 117 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), or any other suitable metallic material. In other examples, the gate layer 115 may not have a composite structure but may be composed of a single conductive material, which is not specifically limited in this application.

[0042] As described above, in some embodiments, a transistor can be formed by a semiconductor pillar (e.g., 111a), and a gate oxide layer 114 and a gate layer 115 covering a portion of the second sidewall 113 of the semiconductor pillar (e.g., 111a). In the transistor, the semiconductor pillar (e.g., 111a) serves as the channel, the portion of the gate layer 115 corresponding to the second sidewall 113 of the semiconductor pillar (e.g., 111a) serves as the gate, and the two ends of the semiconductor pillar (e.g., 111a) extending in the direction of extension serve as the source and drain, respectively. Since the extension direction of the semiconductor pillar (e.g., 111a) (e.g., the D3 direction) is perpendicular to the planar extension direction of the semiconductor substrate, this transistor can also be called a vertical channel transistor. Vertical channel transistors can effectively reduce the planar area occupied and increase the storage density. In this case, the gate layer 115 extending in the D2 direction can serve as a word line controlling a row of memory cells arranged along the D2 direction.

[0043] In some implementations, the ends of a plurality of semiconductor pillars (e.g., 111a) arranged along the D1 direction are connected to each other. For example, the ends of a plurality of semiconductor pillars (e.g., 111a) arranged along the D1 direction are connected to the same bit line.

[0044] In some embodiments, a first isolation structure 118 is provided between adjacent gate layers 115 in the D1 direction. For example, the material of the first isolation structure 118 may include silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiO2). x N y (or one or more of any other suitable insulating material.) Figure 1A As shown, the transistors adjacent to each other in the D1 direction are mirror-symmetric with respect to the first isolation structure 118.

[0045] Continue to refer to Figure 1A and Figure 1CThe first sidewalls 112 of two adjacent semiconductor pillars (e.g., 111a and 111b) in the D1 direction face each other. The second sidewalls 113 of one of these two semiconductor pillars (e.g., 111a) and the other adjacent semiconductor pillar in the D1 direction (e.g., 111c) also face each other. The semiconductor device 100 also includes a conductive shielding layer 121 and a filling layer 125. The conductive shielding layer 121 is located outside the first sidewalls 112 of the semiconductor pillars (e.g., 111a or 111b) and extends along the D2 direction (e.g., continuously). For example, the conductive shielding layer 121 is generally parallel to the first sidewalls 112 of the semiconductor pillars (e.g., 111a or 111b). The filling layer 125 is located between the conductive shielding layers 121. For example, the material of the conductive shielding layer 121 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material. For example, the material of the filling layer 125 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO2), etc. x N y One or more of these materials, or any other suitable insulating material. For example, the thickness of the conductive shielding layer 121 is substantially the same in the D1 direction (e.g., with an error within ±10%).

[0046] In some implementations, such as Figure 1A As shown, the conductive shielding layer 121 can be generally annular when viewed perpendicular to the D3 direction. For example, the first end of the conductive shielding layer 121 in the D3 direction is open, and the second end in the D3 direction is at least partially open. The filling layer 125 can be located inside the annular conductive shielding layer 121.

[0047] As described above, in some embodiments, the conductive shielding layer 121 can control the transistor from the back side of the transistor channel (the side of the channel without a gate), for example, by applying a ground voltage to the conductive shielding layer 121 to improve the coupling effect between one row of memory cells arranged along the D2 direction and another row of memory cells.

[0048] In some exemplary embodiments, the conductive shielding layer and the filler layer are entirely replaced by conductive materials. However, due to process limitations, gaps may appear in the conductive shielding layer during its formation, making it difficult to ensure the thickness uniformity of the conductive shielding layer in the D1 direction and the dimensional matching between the conductive shielding layer and the gate layer in the D3 direction. Furthermore, because of the gaps in the conductive shielding layer, the etching process can damage adjacent structures, thus affecting yield and electrical performance. On the other hand, as semiconductor devices continue to shrink, forming a conductive shielding layer entirely composed of conductive materials will become increasingly difficult.

[0049] According to the semiconductor device provided in the embodiments of this application, since the conductive shielding layer is a thin-layer structure and the filling layer is located inside the conductive shielding layer, the conductive shielding layer can have a relatively uniform thickness in the D1 direction, and the dimensional matching between the finally formed conductive shielding layer and the gate layer in the D3 direction can also be guaranteed. Furthermore, the filling layer can reduce the risk of damage to adjacent structures, thereby improving the yield and electrical performance of the final product. On the other hand, the conductive shielding layer with a thin-layer structure is easier to implement in terms of process and has a greater advantage in iterative miniaturization capability.

[0050] In some embodiments, the semiconductor device 100 may further include a first oxide layer 124. The first oxide layer 124 may be located between the first sidewall 112 of the semiconductor pillar (e.g., 111a) and the conductive shielding layer 121. For example, the material of the first oxide layer 124 may include silicon oxide (SiO2) or silicon oxynitride (SiO2). x N y (or any other suitable insulating oxide material) or one or more of these. For example, refer to... Figure 1A Viewed perpendicular to the D3 direction, the first oxide layer 124 can be generally annular and surrounds the outer periphery of the conductive shielding layer 121. In this embodiment, disposing the first oxide layer 124 between the first sidewall 112 of the semiconductor pillar (e.g., 111a) and the conductive shielding layer 121 helps to improve the control effect of the conductive shielding layer 121.

[0051] In some implementations, such as Figure 1CAs shown, the conductive shielding layer 121 may include a first adhesive layer 122 and a first metal layer 123 bonded together. The first adhesive layer 122 may be located on the surface of the first oxide layer 124 and extend along the D2 direction (e.g., continuously). The first metal layer 123 may be located on the surface of the first adhesive layer 122 and extend along the D2 direction (e.g., continuously). In other words, the first adhesive layer 122 is located between the first metal layer 123 and the first oxide layer 124. The first adhesive layer 122 helps to improve the bonding performance between the first metal layer 123 and the first oxide layer 124. For example, the material of the first adhesive layer 122 may include one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or any other suitable material. For example, the material of the first metal layer 123 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), or any other suitable metallic material. In other examples, the conductive shielding layer 121 may not have a composite structure, but may be composed of a single conductive material; this application does not impose specific limitations on this.

[0052] In some implementations, such as Figure 1B and Figure 1C As shown, the semiconductor device 100 may include a first region 101 and a second region 102 arranged along the D2 direction, wherein the second region 102 is located on both sides of the first region 101. For example, at least a portion of the first region 101 may be a storage region, and the second region 102 may be a connection region. A conductive shielding layer 121 extends (e.g., continuously) within the first region 101 and the second region 102. In the D3 direction, the size of the conductive shielding layer 121 located within at least one second region 102 is larger than its size located within the first region 101. For example, the second end of the conductive shielding layer 121 in the D3 direction is open in the portion located in the first region 101. The second end is open in the portion located in one second region 102, while closed in the portion located in the other second region 102. In this embodiment, the conductive shielding layer 121 has different sizes in the D3 direction, which can achieve both dimensional matching of the conductive shielding layer 121 and the gate layer 115 in the D3 direction and lead-out of the conductive shielding layer 121 in the D3 direction.

[0053] In some implementations, such as Figure 1CAs shown, the semiconductor device 100 may further include a first contact structure 126. The first contact structure 126 is located within the second region 102 and is connected to the conductive shielding layer 121. For example, the first contact structure 126 extends along the D3 direction to the portion of the conductive shielding layer 121 located within the second region 102, to directly contact the conductive shielding layer 121, thereby achieving a connection between the first contact structure 126 and the conductive shielding layer 121. For example, the material of the first contact structure 126 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polycrystalline silicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material. In this embodiment, the first contact structure 126 utilizes the fact that the portion of the conductive shielding layer 121 located within the second region 102 has a larger size in the D3 direction, leading the conductive shielding layer 121 out in the D3 direction, which is more process-friendly for the fabrication of the first contact structure 126.

[0054] This application also provides a memory system. Figure 2 This is a block diagram of a system with a memory system provided in an embodiment of this application.

[0055] like Figure 2 As shown, system 200 can be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a memory system 210 located therein). Figure 2 As shown, system 200 may include host 220 and memory system 210. Memory system 210 has one or more memory devices 211 and a controller 212. Host 220 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). Host 220 may be configured to send or receive data to and from memory device 211.

[0056] In some implementations, controller 212 is coupled to memory device 211 and host 220 and is configured to control memory device 211. For example, controller 212 may be configured to control memory device 211 for operations such as read, erase, and program. Controller 212 may also manage data stored in memory device 211 and communicate with host 220. For example, controller 212 may communicate with external devices (e.g., host 220) according to a specific communication protocol.

[0057] This application also provides a method for manufacturing a semiconductor device. Figure 3 This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application. Figure 3 As shown, a semiconductor device manufacturing method 300 (hereinafter referred to as manufacturing method 300) may include the following steps.

[0058] S310, a first trench extending in a first direction is formed from a first side of the semiconductor layer, and an insulating material is filled in the first trench.

[0059] S320, a second groove and a third groove are formed from the first side extending along the second direction, and the second groove and the third groove are arranged alternately.

[0060] S330, a conductive shielding layer is formed inside the second trench, and a filling layer is formed inside the conductive shielding layer.

[0061] S340, a gate oxide layer and a gate layer are formed in the third trench.

[0062] According to the semiconductor device manufacturing method provided in this embodiment, since the conductive shielding layer is a thin-layer structure and a filling layer is formed on the inner side of the conductive shielding layer, the conductive shielding layer can have a relatively uniform thickness in the D1 direction. Furthermore, it reduces the difficulty of etching process control during the removal of the initial conductive shielding layer from the first side and / or the second side, which is beneficial for ensuring the dimensional matching between the finally formed conductive shielding layer and the gate layer in the D3 direction. In addition, since a filling layer is formed on the inner side of the conductive shielding layer, the risk of damage to adjacent structures during the etching of the initial conductive shielding layer can be reduced, thereby improving the yield and electrical performance of the final product. On the other hand, compared to filling the second trench with conductive material to form the conductive shielding layer, forming a conductive shielding layer with a thin-layer structure is easier to implement in terms of process and has a greater advantage in iterative miniaturization capability.

[0063] Figures 4A to 13 This is a schematic diagram of the semiconductor device during the manufacturing process according to an embodiment of this application. For example, the intermediate structures of the semiconductor device during the manufacturing process in this embodiment can be based on... Figure 3 The manufacturing method shown is used to form it. The following is in conjunction with... Figures 4A to 13Steps S310 to S340 described above are illustrated by way of example.

[0064] Figure 4A and Figure 4B An intermediate structure 400a is shown, comprising a semiconductor layer 431, a first dielectric layer 432, and a second dielectric layer 433. Figure 4A This is a top view of the intermediate structure 400a. Figure 4B It is along Figure 4A The diagram shows a cross-section taken by line B-B'. Figure 5A and Figure 5B The diagram shows the formation of the first trench and the intermediate structure 400b after filling with insulating material 435. Among them, Figure 5A This is a top view of the intermediate structure 400b. Figure 5B It is along Figure 5A The diagram shows a cross-sectional view taken along line B-B'. It should be noted that, to more clearly illustrate the spatial relationships of the components within the intermediate structure 400b, [the diagram is shown here]. Figure 5A The first dielectric layer 432 and the second dielectric layer 433 are omitted from the diagram, and the same representation is used for the top view diagrams below.

[0065] In step S310, as Figure 4A and Figure 4B As shown, in some embodiments, the semiconductor layer 431 may be a semiconductor substrate. For example, the material of the semiconductor substrate may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). As another example, the semiconductor substrate may be silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) substrates, etc.

[0066] In some embodiments, the material of the first dielectric layer 432 may include silicon oxide (SiO2), and the material of the second dielectric layer 433 may include silicon nitride (Si3N4). In some examples, the first dielectric layer 432 and the second dielectric layer 433 may be sequentially formed on the semiconductor layer 431 using thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In other examples, the first dielectric layer 432 may be formed on the semiconductor layer 431 using dry oxidation or wet oxidation methods.

[0067] like Figure 5A and Figure 5BAs shown, in some embodiments, photolithography and etching (e.g., dry etching and / or wet etching) processes can be used to pattern the semiconductor layer 431 from a first side (e.g., the front side of the semiconductor layer 431) to form a first trench (not shown) extending along the D1 direction, while simultaneously forming semiconductor walls 434 extending along the D1 direction. For example, a second dielectric layer 433 can be used as a hard mask layer for etching the semiconductor layer 431. The semiconductor walls 434 and the unetched semiconductor layer 431 are arranged perpendicularly in the D1 direction. Since the semiconductor walls 434 are formed by etching the semiconductor layer 431, the semiconductor walls 434 are made of the same material as the semiconductor layer 431. Further, thin film deposition processes such as CVD, PVD, ALD, or any combination thereof can be used to fill the first trench with an insulating material 435 to achieve insulating isolation between the semiconductor walls 434 through the insulating material 435.

[0068] Figure 6A and Figure 6B An intermediate structure 400c is shown after the formation of the second trench 436 and the initial third trench 437'. Wherein, Figure 6A This is a top view of the intermediate structure 400c. Figure 6B It is along Figure 6A The diagram shows a cross-section taken by line C-C'. Figure 7A and Figure 7B An intermediate structure 400d is shown after the second trench 436 and the initial third trench 437' are filled with the first sacrificial material 438. Figure 7A This is a top view of the intermediate structure 400d. Figure 7B It is along Figure 7A The diagram shows a cross-section taken by line C-C'. Figure 8A and Figure 8B The intermediate structure 400e is shown after the formation of the second trench 436 and the third trench 437. Figure 8A This is a top view of the intermediate structure 400e. Figure 8B It is along Figure 8A The diagram shows a cross-section taken by line C-C'.

[0069] In step S320, as Figure 8A and Figure 8B As shown, in some embodiments, photolithography and etching (e.g., dry etching and / or wet etching) processes can be used to etch the semiconductor wall 434 and insulating material 435 (see reference) formed above the semiconductor layer 431 from the first side. Figure 5A and Figure 5BThe process involves patterning to form a second trench 436 and a third trench 437 extending along the D2 direction, while simultaneously forming a plurality of semiconductor pillars 411 arrayed along the D1 and D2 directions. The second trench 436 and the third trench 437 are alternately arranged in the D1 direction. The semiconductor pillars 411 and the unetched semiconductor layer 431 are arranged perpendicularly in the D1 direction. Since the semiconductor pillars 411 are formed by etching the semiconductor layer 431, the semiconductor pillars 411 and the semiconductor layer 431 are made of the same material. For example, the depth of the second trench 436 and the third trench 437 is less than that of the semiconductor wall 434 (see reference). Figure 5A and Figure 5B The dimensions in the D3 direction. Thus, the ends of the semiconductor pillars 411 arranged along the D1 direction near the semiconductor layer 431 can be connected to each other through unetched semiconductor walls 434.

[0070] In some embodiments, the semiconductor layer 431 may include a first region 401 and a second region 402 arranged along the D2 direction, wherein the second region 402 is located on both sides of the first region 401. For example, at least a portion of the first region 401 may be a memory region, and the second region 402 may be a connection region. The second trench 436 and the third trench 437 extend within the first region 401 and the second regions 402 on both sides.

[0071] In some embodiments, the dimension of the second groove 436 in the D1 direction may be smaller than the dimension of the third groove 437 in the D1 direction. For example, the second groove 436 and the third groove 437 having the above-described dimensional relationship can be formed by the method described below.

[0072] like Figure 6A and Figure 6B As shown, photolithography and etching (e.g., dry etching and / or wet etching) processes can be used to etch the semiconductor wall 434 and insulating material 435 (see reference) formed above the semiconductor layer 431 from the first side. Figure 5A and Figure 5B The groove is patterned to form a second groove 436 and an initial third groove 437' extending along the D2 direction. The second groove 436 and the initial third groove 437' are arranged alternately in the D1 direction, and the size of the second groove 436 in the D1 direction may be equal to the size of the initial third groove 437' in the D1 direction.

[0073] like Figure 7A and Figure 7BAs shown, a first sacrificial material 438 can be filled in the second trench 436 and the initial third trench 437' using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. For example, the first sacrificial material 438 may include polysilicon, carbon, spin-on-carbon (SOC), spin-on-dielectric, or any other suitable sacrificial material.

[0074] In some embodiments, a mask layer (e.g., a photoresist layer and / or a hard mask layer) may be overlaid on the top surface of the initial third trench 437' filled with the first sacrificial material 438, and then the first sacrificial material 438 in the second trench 436 may be etched back to form the third dielectric layer 439 (see reference). Figure 8A and Figure 8B For example, the material of the third dielectric layer 439 may include silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiO2). x N y One or more of the following: (e.g., the material of the third dielectric layer 439) or any other suitable insulating material. For example, the material of the third dielectric layer 439 may be the same as the material of the second dielectric layer 433.

[0075] In some embodiments, an etching process (e.g., dry etching and / or wet etching) can be used to remove the first sacrificial material 438 in the initial third trench 437' and increase the size of the initial third trench 437' in the D1 direction to form a third trench 437 with a larger size in the D1 direction (see reference). Figure 8A and Figure 8B Optionally, during the process of increasing the size of the initial third trench 437' in the D1 direction, the size of the initial third trench 437' in the D3 direction will also increase. For example, the third dielectric layer 439 can protect the first sacrificial material 438 in the second trench 436 from being etched and maintain the size of the second trench 436 in the D1 direction. Optionally, after the third trench 437 is formed, an etching process (e.g., dry etching and / or wet etching) can be used to remove the first sacrificial material 438 and the third dielectric layer 439 in the second trench 436.

[0076] Figure 9A and Figure 9B The intermediate structure 400f is shown after the formation of the barrier layer 440. Among them, Figure 9A This is a top view of the intermediate structure 400f. Figure 9B It is along Figure 9A The diagram shows a cross-section taken by line C-C'. Figure 10A and Figure 10BAn intermediate structure 400g is shown after the formation of the gate oxide layer 414, the first oxide layer 424, the initial gate layer 415', and the initial conductive shielding layer 421'. Among them, Figure 10A This is a schematic diagram of a cross-section of the intermediate structure 400g taken on a plane perpendicular to the D2 direction. Figure 10B It is along Figure 10A The diagram shows a cross-section taken by line D-D'. Figure 11A and Figure 11B The diagram shows an intermediate structure 400h after the formation of the gate layer 415 and the removal of a portion of the initial conductive shielding layer 421' from the first side. Figure 11A This is a schematic diagram of a cross-section of the intermediate structure 400h taken perpendicular to the D3 direction. Figure 11B It is along Figure 11A The diagram shows a cross-section taken by line C-C'. Figure 12A and Figure 12B An intermediate structure 400i is shown after the formation of the conductive shielding layer 421. Among them, Figure 12A This is a schematic cross-sectional view of the intermediate structure 400i taken on a plane perpendicular to the D3 direction. Figure 12B It is along Figure 12A The diagram shows a cross-section taken by line A-A'.

[0077] The following is combined with Figures 9A to 12B Examples of steps S330 and S340 are provided.

[0078] In steps S330 and S340, as Figure 9A and Figure 9B As shown, in some embodiments, when the third trench 437 is unfilled, a barrier layer 440 can be formed at the bottom of the third trench 437 using a thin film deposition process and an etching process (e.g., dry etching and / or wet etching). Specifically, a thin film deposition process, such as CVD, PVD, ALD, or any combination thereof, can be used to fill the third trench 437 with material for forming the barrier layer 440. Optionally, a chemical mechanical planarization (CMP) process can be used for planarization. Next, a wet etching process can be used to etch back the material filled in the third trench 437 to form the barrier layer 440 at the bottom of the third trench 437. For example, by controlling the parameters of the wet etching process (e.g., etching time, etchant material, or etching rate), a predetermined distance can be maintained in the D3 direction between the top surface of the barrier layer 440 (e.g., the surface facing the opening of the third trench 437) and the bottom surface of the second trench 436.

[0079] In some embodiments, the material of the barrier layer 440 may include silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiO2). x N y (or any other suitable insulating material) or one or more of the following. For example, the barrier layer 440 may be made of a single material or multiple materials, and this application is not limited thereto. Optionally, the first sacrificial material 438 and the third dielectric layer 439 in the second trench 436 (see reference) Figure 8A and Figure 8B The second dielectric layer 433 (see reference 433) can be removed after the barrier layer 440 is formed. For example, the second dielectric layer 433 (see reference 434) can be removed simultaneously with the removal of the third dielectric layer 439. Figure 8B ) was also removed.

[0080] In some implementations, such as Figure 10A and Figure 10B As shown, a gate oxide layer 414 can first be formed on the sidewall of the third trench 437 using either a dry oxidation method or a wet oxidation method. Optionally, if the second trench 436 is also unfilled, during the formation of the gate oxide layer 414, for example, the same dry oxidation method or wet oxidation method can be used to form a first oxide layer 424 on the inner wall of the second trench 436. Alternatively, a first sacrificial material 438 and a third dielectric layer 439 (see reference) in the second trench 436... Figure 8A and Figure 8B If the gate oxide layer 414 is removed after its formation, the formation of the first oxide layer 424 on the inner wall of the second trench 436 can be avoided during the formation of the gate oxide layer 414. Next, refer to... Figure 10A and Figure 10BAn adhesive layer 441 and a metal layer 442 can be sequentially formed on the inner side of the second trench 436 (e.g., the inner wall of the second trench 436 or the surface of the first oxide layer 424), the surface of the gate oxide layer 414, the surface of the barrier layer 440, and the surface of the first dielectric layer 432 using CVD, PVD, ALD, or any combination thereof thin film deposition processes. The adhesive layer 441 and the metal layer 442 formed on the surface of the gate oxide layer 414 and the barrier layer 440 can serve as the initial gate layer 415', and the adhesive layer 441 and the metal layer 442 formed on the inner side of the second trench 436 (e.g., the inner wall of the second trench 436 or the surface of the first oxide layer 424) can serve as the initial conductive shielding layer 421'. For example, the material of the adhesive layer 441 may include one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or any other suitable material. For example, the material of metal layer 442 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), or any other suitable metallic material. In other examples, adhesive layer 441 and metal layer 442 may be replaced by a conductive material, and this application does not impose specific limitations on this.

[0081] In some implementations, such as Figure 11A and Figure 11B As shown, the initial gate layer 415' can be removed using a punch-etch process (see reference). Figure 10A and Figure 10B A portion of the surface of the barrier layer 440 is used to disconnect the initial gate layer 415'. For example, the cut that disconnects the initial gate layer 415' extends continuously along the D2 direction. In other words, viewed from the D3 direction, the annular initial gate layer 415' is open at a first end near the semiconductor layer 431. Next, a first isolation structure 418 can be formed inside the initial gate layer 415' using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. During this process, a fill layer 425 can be formed inside the initial conductive shielding layer 421'. Optionally, a planarization process can be used to remove portions of, for example, the adhesive layer 441 and the metal layer 442 located on the surface of the first dielectric layer 432.

[0082] In some embodiments, an etching process (e.g., dry etching and / or wet etching) can be used to remove a portion of the initial gate layer 415' near the first side to form the gate layer 415. For example, the gate layer 415 is smaller in size in the D3 direction compared to the initial gate layer 415'. During this process, the same etching process (e.g., dry etching and / or wet etching) can be used to remove a portion of the initial conductive shielding layer 421' near the first side. For example, the initial conductive shielding layer 421' is smaller in size in the D3 direction after removal. For example, for the two end faces of the gate layer 415 and the initial conductive shielding layer 421' near the first side in the D3 direction, the two end faces can be made substantially flush (e.g., with an error within ±10%), or the end face of the initial conductive shielding layer 421' can be made lower than the end face of the gate layer 415, depending on the actual control requirements of the transistor. This application does not impose specific limitations on this. It should be noted that the process of removing a portion of the initial gate layer 415' near the first side and a portion of the initial conductive shielding layer 421' near the first side can be achieved through different etching processes, and this application does not impose any specific limitations on this.

[0083] In some embodiments, the second isolation structure 419 may be formed using etching (e.g., dry etching and / or wet etching) and thin film deposition processes. For example, the second isolation structure 419 is located within the second region 402. For example, the material of the second isolation structure 419 may include silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiO2). x N y One or more of the following: ) or any other suitable insulating material. The second isolation structure 419 is used to disconnect the gate layer 415 located on both sides of it in the D1 direction into two parts, such that the semiconductor pillar 411 located in the first region 401 is controlled by the disconnected part of the gate layer 415.

[0084] In some embodiments, any process method known in the art can be used to form a capacitor connection structure and a capacitor (not shown) connected to the end face of the semiconductor pillar 411 away from the semiconductor layer 431. For example, the capacitor and transistor can constitute a memory cell of a DRAM memory.

[0085] In some implementations, it is possible to Figure 11A and Figure 11B The intermediate structure 400h shown is flipped 180° to allow subsequent processing from the second side of semiconductor layer 431 (e.g., the back side of semiconductor layer 431). Figures 12A to 12BAs shown, the semiconductor layer 431 can first be planarized from the second side using a CMP process. Then, a portion of the initial conductive shielding layer 421' is removed from the second side of the semiconductor layer 431, for example, using an etching process (e.g., dry etching and / or wet etching), to form the conductive shielding layer 421. Exemplarily, the portion of the initial conductive shielding layer 421' removed may include: a portion of the initial conductive shielding layer 421' near the second side and located in a first region 401, and a portion of the initial conductive shielding layer 421' near the second side and located in a second region 402. For example, among the initial conductive shielding layers 421' arranged in the D1 direction, the odd-numbered initial conductive shielding layers 421' are removed from a portion located in the second region 402 on the left, and the even-numbered initial conductive shielding layers 421' are removed from a portion located in the second region 402 on the right. For example, in the initial conductive shielding layers 421' arranged in the D1 direction, a portion of the entire initial conductive shielding layer 421' located in the second region 402 on the left side is removed, or a portion of the entire initial conductive shielding layer 421' located in the second region 402 on the right side is removed. During the process of removing a portion of the initial conductive shielding layer 421' from the second side to form the conductive shielding layer 421, the barrier layer 440 can be used to protect the gate layer 415 from damage. Next, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to fill the space formed after removing a portion of the initial conductive shielding layer 421' with an insulating layer material, thereby forming the third isolation structure 420. For example, the material of the third isolation structure 420 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO2), etc. x N y (or one or more of any other suitable insulating material).

[0086] In some implementations, compared to the initial conductive shielding layer 421', Figure 12B The portion of the conductive shielding layer 421 shown within the first region 401 has a further reduced size in the D3 direction. For example, for the two end faces of the gate layer 415 and the conductive shielding layer 421 near the second side in the D3 direction, the two end faces can be made substantially flush (e.g., with an error within ±10%), or the end face of the conductive shielding layer 421 can be made lower than the end face of the gate layer 415, depending on the actual control requirements of the transistor. This application does not impose any specific limitations on this.

[0087] In some embodiments, the manufacturing method 300 may further include the step of forming a first contact structure. Figure 13The semiconductor device 400 after the formation of the first contact structure 426 is shown. As described above, the conductive shielding layer 421 can be led out in the D3 direction using the portion of the conductive shielding layer 421 located in the second region 402 and the first contact structure 426. For example, an etching process (e.g., dry etching and / or wet etching) can be used to form a contact hole (corresponding to the outer contour of the first contact structure 426) extending into the portion of the conductive shielding layer 421 located in the second region 402 from the second side. For example, the contact hole can expose the conductive shielding layer 421. The first contact structure 426 can then be formed by filling the contact hole with one or more of the following materials: tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material, using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. In this embodiment, by utilizing the characteristic that the conductive shielding layer 421 has a large size in the D3 direction within the second region 402, the first contact structure 426 can have a smaller extension distance in the D3 direction, thereby reducing the manufacturing difficulty of the first contact structure 426.

[0088] In this embodiment, because the conductive shielding layer is a thin-layer structure and a filler layer is formed on its inner side, the conductive shielding layer can have a relatively uniform thickness in the D1 direction. This also reduces the difficulty of etching process control during the removal of the initial conductive shielding layer from the first and / or second side, which is beneficial for ensuring the dimensional matching between the final conductive shielding layer and the gate layer in the D3 direction. Furthermore, the filler layer on the inner side of the conductive shielding layer reduces the risk of damage to adjacent structures during the etching of the initial conductive shielding layer, thereby improving the yield and electrical performance of the final product. On the other hand, compared to filling the second trench with conductive material to form the conductive shielding layer, forming a thin-layer conductive shielding layer is easier to implement and offers greater advantages in iterative miniaturization.

[0089] Figures 14A to 17 This is a schematic diagram of the structure of a semiconductor device during the manufacturing process according to another embodiment of this application. For example, the intermediate structures of the semiconductor device during the manufacturing process in this embodiment can be based on... Figure 3 The manufacturing method shown is used to form the product. Steps S310 and S320 are essentially the same as in the previous embodiment, and will not be repeated here. The following describes the process in conjunction with... Figures 14A to 17 Steps S330 and S340 are illustrated by way of example.

[0090] Figure 14A and Figure 14BAn intermediate structure 500g is shown after the formation of the gate oxide layer 514, the first oxide layer 524, the initial gate layer 515', and the initial conductive shielding layer 521'. Among them, Figure 14A This is a schematic diagram of a cross-section of the intermediate structure 500g taken perpendicular to the D2 direction. Figure 14B It is along Figure 14A The diagram shows a cross-section taken by line D-D'. Figure 15A and Figure 15B An intermediate structure 500h is shown after a portion of the initial gate layer 515' and a portion of the initial conductive shielding layer 521' have been removed from the first side. Figure 15A This is a schematic cross-sectional view of the intermediate structure 500h taken on a plane perpendicular to the D3 direction. Figure 15B It is along Figure 15A The diagram shows a cross-section taken by line C-C'. Figure 16A and Figure 16B An intermediate structure 500i is shown after the formation of the gate layer 515 and the conductive shielding layer 521. Among them, Figure 16A This is a schematic cross-sectional view of the intermediate structure 500i taken on a plane perpendicular to the D3 direction. Figure 16B It is along Figure 16A The diagram shows a cross-section taken by line A-A'.

[0091] In steps S330 and S340, as Figure 14A and Figure 14B As shown, in some embodiments, the third trench 537 is in an unfilled state, and a gate oxide layer 514 can first be formed on the inner wall of the third trench 537 using a dry oxidation method or a wet oxidation method. Optionally, when the second trench 536 is also in an unfilled state, during the formation of the gate oxide layer 514, for example, the same dry oxidation method or wet oxidation method can be used to form a first oxide layer 524 on the inner wall of the second trench 536. As another option, the first sacrificial material 438 and the third dielectric layer 439 in the second trench 536 (see reference) Figure 8A and Figure 8B If the gate oxide layer 514 is removed after its formation, the formation of the first oxide layer 524 on the inner wall of the second trench 536 can be avoided during the formation of the gate oxide layer 514.

[0092] Next, continue to refer to Figure 14A and Figure 14BAn adhesive layer 541 and a metal layer 542 can be sequentially formed on the inner side of the second trench 536 (e.g., the inner wall of the second trench 536 or the surface of the first oxide layer 524), the surface of the gate oxide layer 514, and the surface of the first dielectric layer 532 using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. The adhesive layer 541 and the metal layer 542 formed on the surface of the gate oxide layer 514 can serve as the initial gate layer 515', and the adhesive layer 541 and the metal layer 542 formed on the inner side of the second trench 536 (e.g., the inner wall of the second trench 536 or the surface of the first oxide layer 524) can serve as the initial conductive shielding layer 521'. For example, the material of the adhesive layer 541 may include one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or any other suitable material. For example, the material of the metal layer 542 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), or any other suitable metallic material. In other examples, the adhesive layer 541 and the metal layer 542 may be replaced by a conductive material, and this application does not impose any specific restrictions on this.

[0093] In some implementations, such as Figure 15A and Figure 15B As shown, a first isolation structure 518 can be formed inside the initial gate layer 515' using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. During this process, a fill layer 525 can be formed inside the initial conductive shielding layer 521'. Optionally, a planarization process can be used to remove portions of, for example, the adhesive layer 541 and the metal layer 542 located on the surface of the first dielectric layer 532.

[0094] In some embodiments, an etching process (e.g., dry etching and / or wet etching) can be used to remove a portion of the initial gate layer 515' near the first side. During this process, the same etching process (e.g., dry etching and / or wet etching) can be used to remove a portion of the initial conductive shielding layer 521' near the first side. For example, for the two end faces of the initial gate layer 515' and the initial conductive shielding layer 521' near the first side in the D3 direction, the two end faces can be made substantially flush (e.g., with an error within ±10%), or the end face of the initial conductive shielding layer 521' can be made lower than the end face of the initial gate layer 515', depending on the actual control requirements of the transistor. This application does not impose specific limitations on this. It should be noted that the process of removing a portion of the initial gate layer 515' and the initial conductive shielding layer 521' near the first side can be implemented using different etching processes, and this application does not impose specific limitations on this.

[0095] In some implementations, it is possible to Figure 15A and Figure 15BThe intermediate structure 500h shown is flipped 180° to allow subsequent processing from the second side of semiconductor layer 531 (e.g., the back side of semiconductor layer 531). Figures 16A to 16B As shown, the semiconductor layer 531 is first planarized from the second side using a CMP process. Then, from the second side of the semiconductor layer 531, a portion of the initial conductive shielding layer 521' is removed using, for example, an etching process (e.g., dry etching and / or wet etching) to form the conductive shielding layer 521, and a portion of the initial gate layer 515' is removed to disconnect the initial gate layer 515' in the D1 direction, thereby forming the gate layer 515. Exemplarily, the portion of the initial conductive shielding layer 521' removed may include: a portion of the initial conductive shielding layer 521' near the second side and located in a first region 501, and a portion of the initial conductive shielding layer 521' near the second side and located in a second region 502.

[0096] Next, a thin film deposition process, such as CVD, PVD, ALD, or any combination thereof, can be used to fill the space formed after removing a portion of the initial gate layer 515' and the initial conductive shielding layer 521' with an insulating layer material, thereby forming the third isolation structure 520. For example, the material of the third isolation structure 520 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO2), etc. x N y (or one or more of any other suitable insulating material).

[0097] In some implementations, compared to the initial conductive shielding layer 521', Figure 16B The portion of the conductive shielding layer 521 shown within the first region 501 has a further reduced size in the D3 direction. For example, for the two end faces of the gate layer 515 and the conductive shielding layer 521 near the second side in the D3 direction, the two end faces can be made substantially flush (e.g., with an error within ±10%), or the end face of the conductive shielding layer 521 can be made lower than the end face of the gate layer 515, depending on the actual control requirements of the transistor. This application does not impose any specific limitations on this.

[0098] In some embodiments, the manufacturing method 300 may further include the step of forming a first contact structure. Figure 17The semiconductor device 500 after the formation of the first contact structure 526 is shown. As described above, the conductive shielding layer 521 can be led out in the D3 direction using the portion of the conductive shielding layer 521 located in the second region 502 and the first contact structure 526. For example, an etching process (e.g., dry etching and / or wet etching) can be used to form a contact hole (corresponding to the outer contour of the first contact structure 526) extending into the portion of the conductive shielding layer 521 located in the second region 502 from the second side. For example, the contact hole can expose the conductive shielding layer 521. The first contact structure 526 can then be formed by filling the contact hole with one or more of the following materials: tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material, using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. In this embodiment, by utilizing the characteristic that the conductive shielding layer 521 has a large size in the D3 direction within the second region 502, the first contact structure 526 can have a smaller extension distance in the D3 direction, thereby reducing the manufacturing difficulty of the first contact structure 526.

[0099] In this embodiment, the conductive shielding layer has a relatively uniform thickness in the D1 direction, which reduces the difficulty of etching process control and helps ensure the dimensional matching between the final conductive shielding layer and the gate layer in the D3 direction. Furthermore, it reduces the risk of damage to adjacent structures during the etching of the initial conductive shielding layer, thereby improving the yield and electrical performance of the final product. On the other hand, forming a conductive shielding layer with a thin-layer structure is easier to achieve in terms of process and offers greater advantages in iterative miniaturization.

[0100] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor device, characterized in that, include: Multiple semiconductor pillars are arranged in an array along a first direction and a second direction, and adjacent semiconductor pillars in the first direction each have a first sidewall that is opposite to each other. A conductive shielding layer is located on the outside of the first sidewall and extends along the second direction; as well as A filling layer is located between the conductive shielding layers; Wherein, the first direction is perpendicular to the second direction.

2. The semiconductor device according to claim 1, wherein, The thickness of the conductive shielding layer is substantially the same in the first direction.

3. The semiconductor device according to claim 1, wherein, It also includes a first oxide layer located between the first sidewall and the conductive shielding layer.

4. The semiconductor device according to claim 3, wherein, The conductive shielding layer includes: A first adhesive layer is located on the surface of the first oxide layer and extends along the second direction; and A first metal layer is located on the surface of the first adhesive layer and extends along the second direction.

5. The semiconductor device according to claim 1, wherein, The semiconductor device has a first region and a second region arranged along the second direction, the second region being located on both sides of the first region, the conductive shielding layer extending within the first region and the second region, and in a third direction, the size of the conductive shielding layer within at least one of the second regions being larger than its size within the first region, the third direction being perpendicular to the first direction and the second direction.

6. The semiconductor device according to claim 5, wherein, Also includes: The first contact structure is located within the second region and is connected to the conductive shielding layer.

7. The semiconductor device according to claim 1, wherein, The semiconductor pillar has a second sidewall opposite to the first sidewall, and the semiconductor device further includes: Gate oxide layer, located on the surface of the second sidewall; A gate layer is located on the surface of the gate oxide layer and extends along the second direction.

8. The semiconductor device according to claim 7, wherein, The gate layer includes: A second adhesive layer is located on the surface of the gate oxide layer and extends along the second direction; and The second metal layer is located on the surface of the second adhesive layer and extends along the second direction.

9. The semiconductor device according to claim 1, wherein, The ends of the plurality of semiconductor pillars arranged along the first direction are connected to each other.

10. A memory system, characterized in that, Also includes: The memory includes the semiconductor device as described in any one of claims 1 to 9; as well as A controller, coupled to the memory, is used to control the memory to store data.

11. A method for manufacturing a semiconductor device, characterized in that, include: A first trench extending in a first direction is formed from a first side of the semiconductor layer, and an insulating material is filled in the first trench; A second groove and a third groove are formed from the first side and extend along the second direction, the second groove and the third groove are arranged alternately, and the first direction is perpendicular to the second direction; A conductive shielding layer is formed inside the second trench, and a filling layer is formed inside the conductive shielding layer; and A gate oxide layer and a gate layer are formed in the third trench.

12. The manufacturing method according to claim 11, wherein, In the first direction, the size of the second trench is smaller than the size of the third trench; The second and third trenches extending along the second direction from the first side include: A second groove and an initial third groove are formed from the first side extending along the second direction, wherein, in the first direction, the size of the second groove is equal to the size of the initial third groove; and The size of the initial third trench in the first direction is increased by etching process to form the third trench.

13. The manufacturing method according to claim 11, wherein, The gate oxide layer and the gate layer are sequentially formed in the third trench, including: A barrier layer is formed at the bottom of the third trench; The gate oxide layer is formed on the sidewall of the third trench; An initial gate layer is formed on the surface of the gate oxide layer and the surface of the barrier layer; Remove a portion of the initial gate layer located on the surface of the barrier layer to disconnect the initial gate layer; A portion of the initial gate layer near the first side is removed to form the gate layer.

14. The manufacturing method according to claim 11 or 13, wherein, Forming a conductive shielding layer inside the second trench, and forming a filling layer inside the conductive shielding layer, includes: An initial conductive shielding layer is formed on the inner side of the second trench; and Remove a portion of the initial conductive shielding layer near the first side.

15. The manufacturing method according to claim 14, wherein, Also includes: A portion of the initial conductive shielding layer is removed from the second side of the semiconductor layer opposite to the first side to form the conductive shielding layer.

16. The manufacturing method according to claim 15, wherein, The semiconductor layer has a first region and a second region arranged along the second direction, with the second region located on both sides of the first region; Removing a portion of the initial conductive shielding layer from the second side of the semiconductor layer, opposite to the first side, includes: From the second side, a portion of the initial conductive shielding layer located within the first region is removed to form the conductive shielding layer; and The space formed after a portion of the initial conductive shielding layer is removed is filled with insulating material.

17. The manufacturing method according to claim 16, wherein, Also includes: Within the second region, a first contact structure is formed that is connected to the conductive shielding layer.

18. The manufacturing method according to claim 14, wherein, Before forming an initial conductive shielding layer inside the second trench, the method further includes: A first oxide layer is formed on the inner wall of the second trench.

Images