MOS device and preparation method thereof

Abstract

The present invention provides a MOS device and a preparation method thereof, wherein the MOS device comprises a gate structure arranged on a substrate, and a source region and a drain region in the substrate located on both sides of the gate structure, wherein the gate structure comprises an M-type polysilicon gate, and the polysilicon gate is provided with insulating materials at two gate holes of the M-type. The present invention can reduce the contact area between the surface of the polysilicon gate facing the substrate and the substrate by designing an M-type polysilicon gate, while keeping the line width the same as that of the prior art, thereby effectively reducing the parasitic capacitance, thereby reducing the effect of RC delay, and also enabling the polysilicon gate to retain good control over the channel.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a MOS device and a preparation method thereof. Background Art

[0002] MOS (metal-oxide-semiconductor) transistors are one of the most important components in modern integrated circuits. Figure 1 As shown, the MOS transistor includes a semiconductor substrate 10 and a gate structure located on the surface of the semiconductor substrate 10. The gate structure includes a gate oxide layer 21 and a polysilicon gate 22 located on the surface of the semiconductor substrate 10, and a source region S and a drain region D located on both sides of the gate structure. Since the cross section of the polysilicon gate is rectangular, the contact surface between the polysilicon gate and the gate oxide layer 21 is the entire rectangular surface, that is, the full area contact within the line width a, which makes the full area of ​​the polysilicon gate 22 serve as the electrode plate of the parasitic capacitance in the parasitic capacitance between the polysilicon gate 22 and the semiconductor substrate 10, resulting in a large parasitic capacitance between the polysilicon gate and the semiconductor substrate. Summary of the invention

[0003] The object of the present invention is to provide a MOS device and a method for manufacturing the same, which can reduce parasitic capacitance.

[0004] In order to solve the above technical problems, the present invention provides a MOS device, including a gate structure arranged on a substrate, and a source region and a drain region in the substrate located on both sides of the gate structure, wherein the gate structure includes an M-type polysilicon gate, and the polysilicon gate is provided with insulating material at two gate holes of the M-type.

[0005] Optionally, the gate structure includes a gate dielectric layer, a first polysilicon gate, a second polysilicon gate, a first side wall and a second side wall, the gate dielectric layer is arranged on the surface of the substrate, the first polysilicon gate is arranged on the gate dielectric layer, the first side wall is arranged on the side walls on both sides of the first polysilicon gate and is located on the gate dielectric layer, the second polysilicon gate covers the upper surface of the first polysilicon gate, and also covers the first side wall and a partial length of the gate dielectric layer outside the first side wall, and the second side wall is arranged on the second polysilicon gate on both sides of the first polysilicon gate.

[0006] Furthermore, the cross section and the longitudinal section of the first polysilicon gate are both rectangular; the longitudinal section of the second polysilicon gate is V-shaped, and the opening is arranged toward the substrate.

[0007] Furthermore, the thickness of the second polysilicon gate is smaller than the thickness of the first polysilicon gate.

[0008] Furthermore, the second polysilicon gate includes a connecting portion and two side wall portions, the connecting portion is connected and arranged between the two side wall portions, and the connecting portion covers the upper surface of the first polysilicon gate, the two side wall portions respectively cover the first side wall, and also cover the gate dielectric layer of the outer portion of the length of the first side wall.

[0009] Furthermore, an angle θ between the side wall portion and a straight line perpendicular to the substrate direction is 30° to 45°.

[0010] On the other hand, the present invention also provides a method for preparing a MOS device, comprising the following steps:

[0011] Providing a substrate, and a gate structure on the substrate, wherein the gate structure comprises an M-shaped polysilicon gate, and the polysilicon gate is provided with insulating material at two gate holes of the M-shaped gate;

[0012] A source region and a drain region are formed in the substrate at both sides of the gate structure.

[0013] Optionally, the method for forming the gate structure is specifically:

[0014] Providing a substrate, and depositing a gate dielectric layer and a first polysilicon film layer on the substrate;

[0015] forming a patterned first photoresist layer on the first polysilicon film layer;

[0016] Using the patterned first photoresist layer as a mask, etching the first polysilicon film layer to form a first polysilicon gate, and removing the remaining first photoresist layer;

[0017] Depositing a first insulating layer on the substrate, wherein the first insulating layer covers the upper surface and sidewalls of the first polysilicon gate;

[0018] Etching the first insulating layer to form a first sidewall, wherein the first sidewall is arranged on the sidewalls on both sides of the first polysilicon gate and is located on the gate dielectric layer;

[0019] Depositing a second polysilicon film layer, a second insulating layer and a third insulating layer in sequence on the first polysilicon gate, wherein the second polysilicon film layer covers a surface of the first sidewall and a surface of the substrate;

[0020] The third insulating layer, the second insulating layer and the second polysilicon film layer are sequentially etched to form a second sidewall and a second polysilicon gate, thereby forming a gate structure.

[0021] Furthermore, the material of the first sidewall spacer is silicon oxide.

[0022] Furthermore, at the first sidewall, an angle θ between the first polysilicon gate and the second polysilicon gate is 30° to 45°.

[0023] Compared with the prior art, the present invention has the following unexpected technical effects:

[0024] The present invention provides a MOS device and a method for preparing the same. The MOS device includes a gate structure disposed on a substrate, and a source region and a drain region in the substrate located on both sides of the gate structure. The gate structure includes an M-type polysilicon gate, and the polysilicon gate is provided with insulating materials at two gate holes of the M-type. The present invention can reduce the contact area between the surface of the polysilicon gate facing the substrate and the substrate by designing an M-type polysilicon gate, while keeping the line width the same as that of the prior art, thereby effectively reducing the parasitic capacitance, thereby reducing the effect of RC delay, and also enabling the polysilicon gate to retain good control over the channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of the structure of a MOS device.

[0026] Figure 2 A schematic structural diagram of a semiconductor substrate provided for a MOS device.

[0027] Figure 3 The schematic diagram is a structural diagram of a MOS device after a gate structure is formed.

[0028] Figure 4 A schematic structural diagram of a substrate provided in one embodiment of the present invention.

[0029] Figure 5 It is a schematic diagram of the structure after forming the first polysilicon gate according to an embodiment of the present invention.

[0030] Figure 6 It is a schematic diagram of the structure after forming the first insulating layer according to an embodiment of the present invention.

[0031] Figure 7 It is a schematic diagram of the structure after the first sidewall is formed according to an embodiment of the present invention.

[0032] Figure 8 It is a schematic diagram of the structure after forming the second polysilicon gate according to an embodiment of the present invention.

[0033] Fig. 9 It is a schematic diagram of the structure after forming the second insulating layer and the third insulating layer according to an embodiment of the present invention.

[0034] Fig.10 It is a schematic diagram of the structure after forming the second sidewall spacer and the second polysilicon gate according to an embodiment of the present invention.

[0035] Fig.11 It is a schematic diagram of the structure after the source region and the drain region are formed according to an embodiment of the present invention.

[0036] Fig.12 It is a schematic diagram of the structure after forming a dielectric layer according to an embodiment of the present invention.

[0037] Fig.13 A schematic structural diagram of a MOS device provided by an embodiment of the present invention.

[0038] Description of reference numerals:

[0039] Figure 1-Figure 3 In the figure: 10-semiconductor substrate; 21-gate oxide layer; 22′-polysilicon film layer; 22-polysilicon gate; 23-sidewall; 24-metal silicide layer; 30-first initial photoresist layer; 41-second silicon nitride film layer; 42-oxide layer; 43-source plug; 44-gate plug;

[0040] Figure 4-Figure 13 In the figure: 100-substrate; 110-source region; 120-drain region; 210-gate dielectric layer; 220′-first polysilicon film layer; 220-first polysilicon gate; 230′-first insulating layer; 230-first sidewall; 240′-second polysilicon film layer; 240-second polysilicon gate; 250′-second insulating layer; 260′-third insulating layer; 250-second sidewall; 300-first photoresist layer; 310-metal silicide layer; 320-etching stop layer; 330-dielectric layer; 341-first plug; 342-second plug; 343-third plug. DETAILED DESCRIPTION

[0041] As described in the background technology, the current method for preparing a MOS device is as follows:

[0042] like Figure 2 As shown, first, a semiconductor substrate 10 is provided, on which a gate oxide layer 21, a polysilicon film layer 22' and a patterned first initial photoresist layer 30 are sequentially formed in an active region.

[0043] like Figure 3 As shown, the polysilicon film layer 22 ′ is then etched using the patterned first initial photoresist layer 30 as a mask to form a polysilicon gate 22 , and the remaining first initial photoresist layer 30 is removed.

[0044] Next, a first silicon oxide film layer and a first silicon nitride film layer are sequentially formed on the surface of the semiconductor substrate 10 , wherein the first silicon oxide film layer covers the upper surface and sidewalls of the polysilicon gate 22 .

[0045] Next, a patterned second initial photoresist layer (not shown in the figure) is formed on the first silicon nitride film layer, and the patterned second initial photoresist layer covers the first silicon nitride film layer on the polysilicon gate 22 and the first silicon nitride film layer near the polysilicon gate 22 to retain the first silicon oxide film layer and the first silicon nitride film layer on the side wall of the polysilicon gate 22, thereby forming a sidewall 23 and a gate structure, and removing the remaining second initial photoresist layer.

[0046] Next, using the sidewall spacer 23 as a mask, a source region S and a drain region D are formed in the semiconductor substrate.

[0047] Next, a metal silicide layer 24 is formed on the surface of the source region S and the drain region D, and a metal silicide layer 24 is formed on the polysilicon gate 22 at the same time.

[0048] like Figure 1 As shown, then, a second silicon nitride film layer 41 and an oxide layer 42 are formed on the metal silicide layer 24, wherein the second silicon nitride film layer 41 covers the outer surface of the sidewall 23, and the surface of the oxide layer 42 is located above the gate structure; and two source plugs 43 and a gate plug 44 are provided on the oxide layer 42, wherein the two source plugs 43 are respectively connected to the source region S and the drain region D, and the gate plug 44 is connected to the polysilicon gate 22.

[0049] It can be seen that the polysilicon gate in the prior art covers the entire surface facing the semiconductor substrate, resulting in a relatively large parasitic capacitance between the polysilicon gate and the semiconductor substrate.

[0050] In order to solve the problem, the present invention provides a MOS device and a method for preparing the same. The MOS device includes a gate structure arranged on a substrate, and a source region and a drain region in the substrate located on both sides of the gate structure. The gate structure includes an M-type polysilicon gate, and the polysilicon gate is provided with insulating materials at two gate holes of the M-type. The present invention can reduce the contact area between the surface of the polysilicon gate facing the substrate and the substrate by designing an M-type polysilicon gate, while keeping the line width the same as that of the prior art, thereby effectively reducing the parasitic capacitance, thereby reducing the effect of RC delay, and also enabling the polysilicon gate to retain good control over the channel.

[0051] A MOS device and a method for manufacturing the same of the present invention will be described in further detail below. The present invention will be described in more detail below with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown. It should be understood that those skilled in the art may modify the present invention described herein and still achieve the beneficial effects of the present invention. Therefore, the following description should be understood as being broadly known to those skilled in the art and not as a limitation of the present invention.

[0052] For the sake of clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not described in detail because they would clutter the invention with unnecessary detail. It should be recognized that in the development of any actual embodiment, a large number of implementation details must be made to achieve the developer's specific goals, such as changing from one embodiment to another according to the limitations of the relevant system or the relevant business. In addition, it should be recognized that such development work may be complex and time-consuming, but it is just a routine task for those skilled in the art.

[0053] In order to make the purpose and features of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are further described below in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and use inaccurate ratios, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0054] like Fig.13 As shown, this embodiment provides a MOS device, including a gate structure arranged on a substrate 100, and a source region 110 and a drain region 120 in the substrate 100 located on both sides of the gate structure, wherein the gate structure includes an M-type polysilicon gate, and the polysilicon gate is provided with insulating material at two gate holes of the M-type.

[0055] By designing an M-type polysilicon gate, this embodiment can reduce the contact area between the polysilicon gate on the surface facing the substrate 100 and the substrate 100 while keeping the line width unchanged from the prior art (i.e., the value is a), thereby effectively reducing the parasitic capacitance and thus reducing the RC delay effect, and also enabling the polysilicon gate to retain good control over the channel.

[0056] In detail, the substrate 100 is, for example, a P-type substrate 100, the substrate 100 includes an active region, and a gate structure is arranged on the substrate 100 in the active region. The gate structure includes a gate dielectric layer 210, a first polysilicon gate 220, a second polysilicon gate 240, a first sidewall 230, and a second sidewall 250. The gate dielectric layer 210 is arranged on the surface of the substrate 100, the first polysilicon gate 220 is arranged on the gate dielectric layer 210, and the line width of the first polysilicon gate 220 is less than a. The first sidewall 230 is arranged on the sidewalls on both sides of the first polysilicon gate 220 and is located on the gate dielectric layer 210. The second polysilicon gate 240 covers the upper surface of the first polysilicon gate 220, and also covers the first sidewall 230 and the gate dielectric layer 210 of a portion of the length outside the first sidewall 230. The second sidewall spacer 250 is disposed on the second polysilicon gate 240 outside the first sidewall spacer 230 (ie, on both sides of the first polysilicon gate 220 ).

[0057] Among them, the cross-section (the cross-section parallel to the substrate 100 ) and the longitudinal section (the cross-section perpendicular to the substrate 100 ) of the first polysilicon gate 220 are both rectangular, and the longitudinal section of the second polysilicon gate 240 is generally V-shaped, with the opening facing the substrate 100 .

[0058] The thickness of the second polysilicon gate 240 is less than the thickness of the first polysilicon gate 220. At the first sidewall 230, the angle θ between the first polysilicon gate 220 and the second polysilicon gate 240 is an acute angle, and the specific angle is, for example, 30°~45°. In detail, the second polysilicon gate 240 includes a connecting portion and two sidewall portions, the connecting portion is connected and arranged between the two sidewall portions, and the connecting portion covers the upper surface of the first polysilicon gate 220 (i.e., the surface away from the substrate 100), and the two sidewall portions respectively cover the first sidewall 230 and also cover the gate dielectric layer 210 of the outer part of the first sidewall 230. The angle θ between the sidewall portion and the straight line perpendicular to the direction of the substrate 100 is an acute angle, and the specific angle is, for example, 30°~45°. On the upper surface of the gate dielectric layer 210 , the distance from the end of one sidewall portion away from the first polysilicon gate 220 to the end of the other sidewall portion away from the first polysilicon gate 220 is the line width of the gate structure, and the value is a.

[0059] Under the premise of the same line width a, the contact area between the gate structure of this embodiment and the substrate 100 becomes smaller, which can effectively reduce the parasitic capacitance between the gate structure and the substrate 100, thereby effectively reducing the RC delay effect. At the same time, the existence of the first polysilicon gate 220 can enable the gate structure to retain good control over the channel.

[0060] The gate dielectric layer 210, the first sidewall 230 and the second sidewall 250 are made of insulating materials, and the gate dielectric layer 210 and the first sidewall 230 are silicon oxide, for example. The second sidewall 250 includes a silicon oxide layer and a silicon nitride layer from the inside to the outside.

[0061] A metal silicide layer 310 is disposed on the substrate 100 in the source region 110 and the drain region 120 . The metal silicide layer 310 is also disposed above the first polysilicon gate 220 and in contact with the second polysilicon gate 240 .

[0062] An etch stop layer 320 and a dielectric layer 330 are disposed on the substrate 100, and the etch stop layer 320 covers the metal silicide layer 310 on the substrate 100, the metal silicide layer 310 on the second polysilicon gate 240, and the second sidewall 250. The dielectric layer 330 fills the recess between adjacent gate structures and also covers the etch stop layer 320 above the gate structure, so that the surface of the dielectric layer 330 is located above the gate structure.

[0063] The material of the etching stop layer 320 is silicon nitride, and the material of the dielectric layer 330 includes but is not limited to silicon oxide.

[0064] A first plug 341, a second plug 342 and a third plug 343 are provided in the dielectric layer 330. The first plug 341, the second plug 342 and the third plug 343 all penetrate the dielectric layer 330 and the etching stop layer 320. The first plug 341 contacts the source region 110, the second plug 342 contacts the drain region 120, and the third plug 343 contacts the second polysilicon gate 240.

[0065] This embodiment also provides a method for preparing a MOS device, comprising the following steps:

[0066] Step S1: providing a substrate, and a gate structure on the substrate, wherein the gate structure comprises an M-shaped polysilicon gate, and insulating materials are provided at two gate holes of the M-shaped polysilicon gate;

[0067] Step S2: forming a source region and a drain region in the substrate at both sides of the gate structure.

[0068] The following combination Figure 4-Figure 13 A method for preparing a MOS device provided in this embodiment is described in detail.

[0069] See also Figure 4-Figure 10 First, step S1 is performed to provide a substrate 100, and a gate structure on the substrate 100, wherein the gate structure includes an M-type polysilicon gate, and the polysilicon gate is provided with insulating material at two gate holes of the M-type.

[0070] This step specifically includes:

[0071] like Figure 4 As shown, first, a substrate 100 is provided, and a gate dielectric layer 210 and a first polysilicon film layer 220' are deposited on the substrate 100. The substrate 100 is, for example, a P-type substrate 100, and the substrate 100 includes an active region.

[0072] Next, a patterned first photoresist layer 300 is formed on the first polysilicon film layer 220 ′. The patterned first photoresist layer 300 covers the region in the active region for forming the first polysilicon gate 220 .

[0073] like Figure 5 As shown, next, the first polysilicon film layer 220 ′ is etched using the patterned first photoresist layer 300 as a mask to form a first polysilicon gate 220 , and the remaining first photoresist layer 300 is removed.

[0074] like Figure 6 As shown, next, a first insulating layer 230' is deposited on the substrate 100, and the first insulating layer 230' covers the upper surface and sidewalls of the first polysilicon gate 220. The material of the first insulating layer 230' is silicon oxide.

[0075] like Figure 7 As shown, then, the first insulating layer 230′ is etched to form a first side wall 230. The first side wall 230 is arranged on the side walls on both sides of the first polysilicon gate 220 and is located on the gate dielectric layer 210. The first side wall 230 exposes the upper surface of the first polysilicon gate 220 and also exposes most of the surface of the substrate 100.

[0076] like Figure 8 As shown, a second polysilicon film layer 240′ is deposited on the first polysilicon gate 220, and the second polysilicon film layer 240′ covers the surface of the first sidewall 230 and the surface of the substrate 100. The thickness of the second polysilicon film layer 240′ is less than the thickness of the first polysilicon gate 220. At the first sidewall 230, the angle θ between the first polysilicon gate 220 and the second polysilicon film layer 240′ is an acute angle, and the specific angle is, for example, 30° to 45°.

[0077] like Fig. 9 As shown, then, a second insulating layer 250' and a third insulating layer 260' are sequentially deposited on the second polysilicon film layer 240'. The material of the second insulating layer 250' is silicon oxide, and the material of the third insulating layer 260' is silicon nitride.

[0078] like Fig.10As shown, the third insulating layer 260', the second insulating layer 250' and the second polysilicon film layer 240' are sequentially etched to form a second sidewall 250 and a second polysilicon gate 240, thereby forming a gate structure. The second polysilicon gate 240 covers the upper surface of the first polysilicon gate 220, and also covers the first sidewall 230, and also covers a portion of the gate dielectric layer 210 outside the first sidewall 230, so that the cross section (the cross section parallel to the substrate 100 direction) and the longitudinal section (the cross section perpendicular to the substrate 100 direction) of the first polysilicon gate 220 are both rectangular, and the longitudinal section of the second polysilicon gate 240 is generally V-shaped, and the opening is arranged toward the substrate 100 direction.

[0079] The second polysilicon gate 240 includes a connecting portion and two sidewall portions, wherein the connecting portion is connected and arranged between the two sidewall portions, and the connecting portion covers the upper surface of the first polysilicon gate 220 (i.e., the surface away from the substrate 100), and the two sidewall portions respectively cover the exposed surface of the first sidewall 230, and also cover the gate dielectric layer 210 outside the first sidewall 230. The angle θ between the sidewall portion and the straight line perpendicular to the direction of the substrate 100 on the side facing the substrate 100 is an acute angle, and the specific angle is, for example, 30° to 45°. On the upper surface of the gate dielectric layer 210, the distance between the end of one sidewall portion away from the first polysilicon gate 220 and the end of the other sidewall portion away from the first polysilicon gate 220 is the line width of the gate structure, and the value is a.

[0080] The second spacer 250 covers the surface of the sidewall portion and exposes the second polysilicon gate 240 .

[0081] See also Figure 11-13 Then, step S2 is performed to form a source region 110 and a drain region 120 in the substrate 100 on both sides of the gate structure.

[0082] This step specifically includes:

[0083] like Fig.11 As shown, first, by ion implantation, a source region 110 and a drain region 120 are formed in the substrate 100 of the active region, and the source region 110 and the drain region 120 are located on both sides of the gate structure. The ion type of the source region 110 and the drain region 120 is, for example, N-type.

[0084] like Fig.12 As shown, next, a metal silicide layer 310 is formed, and the metal silicide layer 310 covers the substrate 100 of the source region 110 and the drain region 120 , and also covers the upper surface of the second polysilicon gate 240 .

[0085] Next, an etch stop layer 320 and a dielectric layer 330 are sequentially deposited on the substrate 100, wherein the etch stop layer 320 covers the metal silicide layer 310 and the second sidewall 250, and the dielectric layer 330 covers the etch stop layer 320 and fills the recess between adjacent gate structures, and the upper surface of the dielectric layer 330 is located above the gate structure. The material of the etch stop layer 320 is silicon nitride, and the material of the dielectric layer 330 includes but is not limited to silicon oxide.

[0086] like Fig.13 As shown, then, a first through hole, a second through hole and a third through hole are formed in the dielectric layer 330 by an etching process, wherein the first through hole, the second through hole and the third through hole penetrate the dielectric layer 330 and the etching stop layer 320, the first through hole exposes the metal silicide layer 310 above the source region 110, the second through hole exposes the metal silicide layer 310 above the drain region 120, and the third through hole exposes the metal silicide layer 310 above the second polysilicon gate 240.

[0087] Next, metal material is filled in the first through hole, the second through hole and the third through hole through a filling process to form a first plug 341 in the first through hole, a second plug 342 in the second through hole, and a third plug 343 in the third through hole.

[0088] In summary, the present invention provides a MOS device and a method for manufacturing the same, wherein the MOS device comprises a gate structure disposed on a substrate, and a source region and a drain region in the substrate located on both sides of the gate structure, wherein the gate structure comprises an M-type polysilicon gate, and the polysilicon gate is provided with insulating materials at two gate openings of the M-type. The present invention can reduce the contact area between the surface of the polysilicon gate facing the substrate and the substrate by designing an M-type polysilicon gate, while keeping the line width the same as that of the prior art, thereby effectively reducing the parasitic capacitance, thereby reducing the effect of RC delay, and also enabling the polysilicon gate to retain good control over the channel.

[0089] In addition, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0090] It is to be understood that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A MOS device, characterized in that: It includes a gate structure arranged on a substrate, and a source region and a drain region in the substrate located on both sides of the gate structure, wherein the gate structure includes an M-type polysilicon gate, and the polysilicon gate is provided with insulating material at two gate holes of the M-type; Wherein, the gate structure includes a gate dielectric layer, a first polysilicon gate, a second polysilicon gate, a first side wall and a second side wall, the gate dielectric layer is arranged on the surface of the substrate, the first polysilicon gate is arranged on the gate dielectric layer, the first side wall is arranged on the side walls on both sides of the first polysilicon gate and is located on the gate dielectric layer, the second polysilicon gate covers the upper surface of the first polysilicon gate, and also covers the first side wall and the gate dielectric layer of a partial length outside the first side wall, and the second side wall is arranged on the second polysilicon gate on both sides of the first polysilicon gate.

2. The MOS device according to claim 1, characterized in that The cross section and the longitudinal section of the first polysilicon gate are both rectangular; the longitudinal section of the second polysilicon gate is V-shaped, and the opening is arranged toward the substrate.

3. The MOS device according to claim 1, wherein: The thickness of the second polysilicon gate is smaller than the thickness of the first polysilicon gate.

4. The MOS device according to claim 1, characterized in that: The second polysilicon gate includes a connecting portion and two side wall portions, wherein the connecting portion is connected and arranged between the two side wall portions, and the connecting portion covers the upper surface of the first polysilicon gate, and the two side wall portions respectively cover the first side wall and also cover the gate dielectric layer of the outer portion of the length of the first side wall.

5. The MOS device according to claim 4, characterized in that: An included angle θ between the side wall portion and a straight line perpendicular to the substrate direction is 30° to 45°.

6. A method for preparing a MOS device, characterized in that: The following steps are involved: Providing a substrate, and a gate structure on the substrate, wherein the gate structure comprises an M-shaped polysilicon gate, and the polysilicon gate is provided with insulating material at two gate holes of the M-shaped gate; forming a source region and a drain region in the substrate on both sides of the gate structure; The method for forming the gate structure is specifically as follows: Providing a substrate, and depositing a gate dielectric layer and a first polysilicon film layer on the substrate; forming a patterned first photoresist layer on the first polysilicon film layer; Using the patterned first photoresist layer as a mask, etching the first polysilicon film layer to form a first polysilicon gate, and removing the remaining first photoresist layer; Depositing a first insulating layer on the substrate, wherein the first insulating layer covers the upper surface and sidewalls of the first polysilicon gate; Etching the first insulating layer to form a first sidewall, wherein the first sidewall is arranged on the sidewalls on both sides of the first polysilicon gate and is located on the gate dielectric layer; Depositing a second polysilicon film layer, a second insulating layer and a third insulating layer in sequence on the first polysilicon gate, wherein the second polysilicon film layer covers a surface of the first sidewall and a surface of the substrate; The third insulating layer, the second insulating layer and the second polysilicon film layer are sequentially etched to form a second sidewall and a second polysilicon gate, thereby forming a gate structure.

7. The method for preparing a MOS device according to claim 6, wherein: The material of the first sidewall spacer is silicon oxide.

8. The method for preparing a MOS device according to claim 6, wherein: At the first sidewall, an angle θ between the first polysilicon gate and the second polysilicon gate is 30° to 45°.

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