Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for preparing the same. In the method for preparing the semiconductor device, after forming a silicon germanium trench structure, a sacrificial layer is used as a sacrificial medium, and a hard mask layer is formed on the surface of each exposed gate structure to fill the height difference of the surface of each gate structure. In addition, the hard mask layer is flattened by a chemical mechanical polishing process so that the height of each gate structure is restored to the same horizontal plane. Based on this, each gate structure having the same height is not only conducive to chemical mechanical polishing of a larger window using the same load parameters in the subsequent preparation process, but also conducive to etching the dummy gate cleanly and fully filling the polysilicon in the subsequent process of removing the dummy gate and filling the polysilicon, ensuring a better process effect, thereby being able to obtain ideal key parameters and improve the device yield.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor preparation, and in particular to a semiconductor device and a preparation method thereof. Background Art

[0002] As the integration of CMOS technology increases and the key dimensions shrink, the stress-increasing method used in the traditional CMOS process can no longer meet the device's requirements for PMOS drive current. In response to this, the existing technology uses silicon germanium epitaxial growth technology to increase the compressive stress of PMOS, thereby improving the overall response speed of the device.

[0003] See also Figures 1 to 3 The preparation of the silicon germanium trench structure 100 is generally to first form a trench in the source and drain doping regions, and then grow the silicon germanium material. The details are as follows: Figure 1 The semiconductor structure shown integrates a high-voltage NMOS transistor (HVNMOS), a high-voltage PMOS transistor (HV PMOS), a medium-voltage NMOS transistor (MV NMOS), a medium-voltage PMOS transistor (MVPMOS), a low-voltage NMOS transistor (LV NMOS) and a low-voltage PMOS transistor (LV PMOS). In order to improve the performance of the device, it is necessary to form a silicon-germanium trench structure 100 in the source-drain doping regions on both sides of the pseudo-gate structure 101 of the LV PMOS. First, a patterned photoresist layer 102 is formed on the semiconductor structure, and the patterned photoresist layer 102 is used as a barrier to form a rectangular trench T1 in the source-drain doping region of the LV PMOS by a dry etching process. In the process of etching to form the rectangular trench T1, a certain amount of loss will be caused to the oxide layer 103 covering the pseudo-gate structure 101, so that the height of the etched LV PMOS pseudo-gate structure 101 is lower than that of other pseudo-gate structures 101. In addition, since the sigma morphology has the advantages of increasing the breakdown voltage of the device and reducing the on-resistance. Therefore, as Figure 2 As shown in FIG. 1 , after the rectangular trench T1 is formed, a wet cleaning process is used to transform the rectangular trench T1 into a sigma trench T2. This process further increases the loss of the oxide layer 103 and even consumes the nitride layer 104 covered by the oxide layer 103, so that the pseudo gate structure 101 of the LV PMOS will have a significant height difference with other pseudo gate structures 101. Finally, as Figure 3 As shown, the sigma trench T2 is filled with a silicon germanium material to form a silicon germanium trench structure 100 .

[0004] However, in the subsequent preparation process, due to the height difference between the pseudo-gate structure 101 of the LV PMOS and other pseudo-gate structures 101, the window of chemical mechanical polishing (CMP) will be small, and the CMP load parameters in different areas are different, resulting in poor surface flatness of the film layer. In addition, because the film thickness of the oxide layer 103 and the nitride layer 104 on each pseudo-gate structure 101 is different, when removing the pseudo-gate, part of the nitride layer 104 will not be able to be removed, which seriously affects the filling of the polysilicon material, and then leads to abnormal key parameters such as threshold voltage (Vt), causing device failure and greatly reducing the device yield.

[0005] Therefore, a new method for preparing a semiconductor device is urgently needed to solve the above technical problems. Summary of the invention

[0006] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to solve at least one of the problems of how to reduce the gate height difference between a PMOS having a silicon germanium trench structure and other MOS tubes, and how to improve device performance and yield.

[0007] In order to solve the above technical problems, the present invention provides a method for preparing a semiconductor device, comprising:

[0008] A semiconductor structure is provided; the semiconductor structure comprises a plurality of MOS tubes; a silicon germanium trench structure is formed in the source and drain of some of the MOS tubes, and the height of the gate structure of some of the MOS tubes is lower than the height of the gate structure of the remaining MOS tubes;

[0009] forming a sacrificial layer on the surface of the semiconductor structure, wherein the sacrificial layer exposes the surface of each of the gate structures;

[0010] forming a hard mask layer on the sacrificial layer, wherein the hard mask layer covers the exposed surfaces of each of the gate structures;

[0011] planarizing the hard mask layer using a chemical mechanical polishing process;

[0012] forming a patterned photoresist layer on the hard mask layer to expose a portion of the hard mask layer located on the sacrificial layer;

[0013] The exposed portion of the hard mask layer is removed, and the portion of the hard mask layer located on the surface of each of the gate structures is retained, so that the heights of each of the gate structures are the same.

[0014] Optionally, in the method for preparing the semiconductor device, the material of the sacrificial layer includes amorphous carbon.

[0015] Optionally, in the method for preparing the semiconductor device, a process of forming a sacrificial layer on the surface of the semiconductor structure, wherein the sacrificial layer exposes the surface of each gate structure includes:

[0016] Forming a sacrificial material layer on the surface of the semiconductor structure, wherein the sacrificial material layer covers the surface of each of the gate structures;

[0017] planarizing the sacrificial material layer using a chemical mechanical polishing process;

[0018] The sacrificial material layer is etched by a dry etching process until the lowest surface of the gate structure is exposed; and the etched sacrificial material layer serves as the sacrificial layer.

[0019] Optionally, in the method for preparing the semiconductor device, after removing the exposed portion of the hard mask layer and retaining the portion of the hard mask layer located on the surface of each of the gate structures so that the heights of each of the gate structures are the same, the method for preparing the semiconductor device further comprises:

[0020] The sacrificial layer is removed by etching using the patterned photoresist layer as a barrier and a dry etching process is adopted.

[0021] Optionally, in the method for preparing the semiconductor device, the etching gas used in the dry etching process includes oxygen.

[0022] Optionally, in the method for preparing the semiconductor device, the hard mask layer is formed by a chemical vapor deposition process.

[0023] Optionally, in the method for preparing the semiconductor device, a dry etching process is used to remove the exposed portion of the hard mask layer.

[0024] Optionally, in the method for preparing the semiconductor device, the surface of the gate structure is covered with an oxide layer, and the material of the hard mask layer is the same as that of the oxide layer.

[0025] Optionally, in the method for preparing the semiconductor device, the material of the oxide layer and the hard mask layer both include silicon dioxide.

[0026] Based on the same inventive concept, the present invention also provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method.

[0027] In summary, the present invention provides a semiconductor device and a method for preparing the same. Compared with the prior art, the method for preparing the semiconductor device uses the sacrificial layer as a sacrificial medium after forming the silicon germanium trench structure, and forms the hard mask layer on the surface of each exposed gate structure to fill the height difference of the surface of each gate structure. Also, the hard mask layer is planarized using a chemical mechanical polishing process so that the height of each gate structure is restored to the same horizontal plane. Based on this, each gate structure having the same height is not only conducive to chemical mechanical polishing of a larger window using the same load parameters in the subsequent preparation process, but also conducive to etching the dummy gate cleanly and fully filling the polysilicon in the subsequent process of removing the dummy gate and filling the polysilicon, thereby ensuring a better process effect, thereby being able to obtain ideal key parameters and improve the device yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Those skilled in the art will appreciate that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0029] Figure 1 It is a schematic diagram of forming a rectangular trench in the source and drain doping regions of a LV PMOS in the prior art.

[0030] Figure 2 It is a schematic diagram of forming a sigma trench in the source and drain doping regions of a LV PMOS in the prior art.

[0031] Figure 3 It is a schematic diagram of filling and forming a silicon germanium trench structure and causing a height difference of a pseudo gate structure in the prior art.

[0032] Figure 4 It is a flow chart of a method for preparing a semiconductor device in an embodiment of the present invention.

[0033] Figure 5 It is a schematic diagram of the semiconductor structure provided in step 1 in an embodiment of the present invention.

[0034] Figure 6 It is a flowchart of the specific process of step 2 in the embodiment of the present invention.

[0035] Figure 7 Schematic diagram of forming a sacrificial material layer in an embodiment of the present invention.

[0036] Figure 8 Schematic diagram of the sacrificial material layer after planarization in an embodiment of the present invention.

[0037] Fig. 9 It is a schematic diagram of etching the sacrificial material layer and exposing the surfaces of each gate structure in an embodiment of the present invention.

[0038] Fig.10 Schematic diagram of forming a hard mask layer in an embodiment of the present invention.

[0039] Fig.11 Schematic diagram of a hard mask layer after planarization in an embodiment of the present invention.

[0040] Fig.12 Schematic diagram of forming a patterned photoresist layer in an embodiment of the present invention.

[0041] Fig.13 It is a schematic diagram of etching and removing a portion of the hard mask layer in an embodiment of the present invention.

[0042] Fig.14 It is a schematic diagram of etching and removing the sacrificial layer in an embodiment of the present invention.

[0043] Fig.15 It is a schematic diagram of the semiconductor structure after the patterned photoresist layer is removed in an embodiment of the present invention.

[0044] And, in the attached drawings:

[0045] 100-silicon germanium trench structure; 101-pseudo gate structure; 102-patterned photoresist layer; 103-oxide layer;

[0046] 104-nitride layer;

[0047] 200-substrate; 201-deep trench isolation structure; 202-silicon germanium trench structure; 203-gate structure; 204-nitride layer; 205-oxide layer; 206-sacrificial material layer; 207-sacrificial layer; 208-hard mask layer; 209-patterned photoresist layer;

[0048] T1- rectangular trench; T2- sigma trench; D- height of the gate structure in the semiconductor device. DETAILED DESCRIPTION

[0049] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different proportions are used. It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to represent the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0050] See also Figure 4This embodiment provides a method for preparing a semiconductor device, comprising:

[0051] Step 1 S10: providing a semiconductor structure; the semiconductor structure comprises a plurality of MOS tubes; and a silicon germanium trench structure is formed in the source and drain of some of the MOS tubes, and the height of the gate structure of some of the MOS tubes is lower than the height of the gate structure of the remaining MOS tubes;

[0052] Step 2 S20: forming a sacrificial layer on the surface of the semiconductor structure, wherein the sacrificial layer exposes the surface of each of the gate structures;

[0053] Step three S30: forming a hard mask layer on the sacrificial layer, wherein the hard mask layer covers the exposed surfaces of each of the gate structures;

[0054] Step 4 S40: planarizing the hard mask layer using a chemical mechanical polishing process;

[0055] Step five S50: forming a patterned photoresist layer on the hard mask layer to expose a portion of the hard mask layer located on the sacrificial layer;

[0056] Step six S60: removing the exposed portion of the hard mask layer and retaining the portion of the hard mask layer located on the surface of each of the gate structures, so that the heights of each of the gate structures are the same.

[0057] It can be seen that the preparation method of the semiconductor device provided in this embodiment is to use the sacrificial layer as a sacrificial medium after forming the silicon germanium trench structure, and form the hard mask layer on the exposed surface of each gate structure to fill and repair the height difference on the surface of each gate structure.

[0058] The following is combined with Figures 4 to 15 , specifically describe the method for preparing the semiconductor device provided in this embodiment.

[0059] Step 1 S10: Please refer to Figure 5 , providing a semiconductor structure; the semiconductor structure includes a plurality of MOS tubes; and a silicon germanium trench structure 202 is formed in the source and drain of some of the MOS tubes, and the height of the gate structure 203 of some of the MOS tubes is lower than the height of the gate structure 203 of the remaining MOS tubes.

[0060] Specifically, the semiconductor structure includes a plurality of MOS transistors. And the plurality of MOS transistors may be NMOS and PMOS of different types. For example, Figure 5As shown, the semiconductor structure includes HV NMOS, HV PMOS, MV NMOS, MVPMOS, 1.2v LV NMOS, 1.2v LV PMOS, 0.9v LV NMOS and 0.9v LV PMOS. Each of the MOS tubes is distributed on the substrate 200 and is separated by a deep trench isolation structure 201. In addition, corresponding to different types of MOS tubes, N-type well regions (N well) and P-type well regions (P well, P+ well) with different doping concentrations are formed in the substrate 200 (the figure is only a simplified schematic diagram of each well region). In order to improve the performance of the LV PMOS, the silicon germanium trench structure 202 is also formed in the source and drain of the LV PMOS. Since the silicon germanium trench structure 202 is formed through processes such as dry etching, wet cleaning and silicon germanium deposition (such as Figures 1 to 3 As shown in FIG. 2 ), part of the nitride layer 204 and the oxide layer 205 on the gate structure 203 of the LV PMOS will inevitably be consumed, and the overall height of the gate structure 203 of the LV PMOS protruding from the surface of the substrate 200 will be significantly lower than the overall height of the gate structure 203 of the remaining MOS tubes, thereby affecting the implementation of subsequent processes.

[0061] It should be noted that the nitride layer 204 and the oxide layer 205 are sequentially formed on the surface of the dummy gate of the gate structure 203 of each MOS tube to protect the structure of the MOS tube and prevent it from being affected by other film structures or the external environment.

[0062] Step 2 S20: Please refer to Figures 6 to 9 A sacrificial layer 207 is formed on the surface of the semiconductor structure, and the sacrificial layer 207 exposes the surface of each of the gate structures 203 .

[0063] Specifically, the step 2 S20 includes:

[0064] Sub-step 1 S201: Please refer to Figure 7 A sacrificial material layer 206 is formed on the surface of the semiconductor structure, and the sacrificial material layer 206 covers the surface of each of the gate structures 203 .

[0065] Exemplarily, the sacrificial material layer 206 is formed on the surface of the semiconductor structure by chemical vapor deposition process, and the sacrificial material layer 206 completely covers each of the gate structures 203 on the substrate 200. Preferably, the material of the sacrificial layer 207 includes but is not limited to amorphous carbon (A-Carbon).

[0066] Sub-step 2 S202: Please refer to Figure 7 and Figure 8, the sacrificial material layer 206 is planarized using a chemical mechanical polishing process.

[0067] like Figure 7 As shown, due to the low height of the gate structure 203 of some MOS tubes, such as LV PMOS, the surface of the sacrificial material layer 206 will have an uneven morphology, which affects the subsequent process effect. Therefore, a chemical mechanical polishing process is used to flatten the sacrificial material layer 206. It should be noted that the sacrificial material layer 206 after flattening still covers each of the gate structures 203.

[0068] Sub-step 3 S203: Please refer to Fig. 9 , the sacrificial material layer 206 is etched by a dry etching process until the lowest surface of the gate structure 203 is exposed; and the etched sacrificial material layer 206 serves as the sacrificial layer 207.

[0069] Since oxygen has a high etching selectivity for A-Carbon, this embodiment uses oxygen as an etching gas to etch the sacrificial material layer 206 through a dry etching process. The sacrificial material layer 206 has a flat surface after the sub-step two S202. Therefore, during the etching process, the etching amount of each area of ​​the sacrificial material layer 206 is balanced, which can ensure that the sacrificial material layer 206 still has a flat surface after etching. It should be noted that this embodiment does not limit the specific material of the sacrificial layer 207 and the etching gas for etching the sacrificial layer 207, but it is necessary to meet the requirement that the etching gas has a higher etching selectivity for the sacrificial layer 207 when etching the sacrificial layer 207 than the etching of the nitride layer 204 and the oxide layer 205.

[0070] In order to fill the lower portion of the gate structure 203, the surface of the gate structure 203 must be exposed. Therefore, when the lowest surface of the gate structure 203 is exposed, the etching process stops etching. Fig. 9 As shown in the schematic diagram of the semiconductor structure, the top surface of the gate structure 203 of a relatively low height portion is exposed, the top surface and part of the side surfaces of the remaining gate structure 203 of a normal height are exposed, and the remaining surfaces of all the gate structures 203 are covered by the sacrificial layer 207.

[0071] Step 3 S30: Please refer to Fig.10 , a hard mask layer 208 is formed on the sacrificial layer 207 , and the hard mask layer 208 covers the exposed surfaces of each of the gate structures 203 .

[0072] It should be noted that the purpose of forming the hard mask layer 208 is to fill the height difference of part of the gate structure 203, so preferably, the material of the hard mask layer 208 is consistent with the material of the topmost oxide layer 205 of the gate structure 203. Exemplarily, the materials of the hard mask layer 208 and the oxide layer 205 both include silicon dioxide, and the hard mask layer 208 can be formed by a chemical vapor deposition process.

[0073] Step 4 S40: Please refer to Fig.11 , the hard mask layer 208 is planarized using a chemical mechanical polishing process.

[0074] like Fig.10 As shown, although the sacrificial layer 207 has a flat surface, there is a height difference between the surfaces of the exposed gate structures 203. Therefore, the formed hard mask layer 208 also has an uneven surface, and it is necessary to use a chemical mechanical polishing process to flatten the hard mask layer 208 to ensure that the subsequent etching process is implemented on the same horizontal plane. Among them, the hard mask layer 208 after the flattening process still covers the surface of each gate structure 203, and preferably, the top surface of the hard mask layer 208 is close to the top surface of the gate structure 203 at a normal height. That is, only a thin layer of the hard mask layer 208 is formed on the top surface of the gate structure 203 at a normal height, and the hard mask layer 208 formed on the top surface of the gate structure 203 with a lower height is thicker, so that each gate structure 203 has a top surface of the same height under the filling and repair of the hard mask layer 208.

[0075] Step 5 S50: Please refer to Fig.12 , forming a patterned photoresist layer 209 on the hard mask layer 208 to expose a portion of the hard mask layer 208 located on the sacrificial layer 207 .

[0076] It can be understood that the hard mask layer 208 is used to repair the height difference of the top surface of each gate structure 203, so only the portion of the hard mask layer 208 located on the top surface of the gate structure 203 needs to be retained. In addition, the sacrificial layer 207 is a sacrificial dielectric for forming the hard mask layer 208, and in the subsequent process, an interlayer dielectric layer required for the device structure will be formed on the surface of each gate structure 203. Therefore, after the hard mask layer 208 is formed, it is necessary to remove the portion of the hard mask layer 208 located on the sacrificial layer 207 and remove the sacrificial layer 207.

[0077] Exemplarily, a photoresist layer is coated on the hard mask layer 208 having a flat surface, and a mask is used to expose the photoresist layer, and the patterned photoresist layer 209 is formed after development. The photoresist layer 209 can be a positive photoresist or a negative photoresist. The patterned photoresist layer 209 exposes a portion of the hard mask layer 208 located on the sacrificial layer 207 for subsequent etching and removal; and covers a portion of the hard mask layer 208 located on the gate structure 203, so that the portion of the hard mask layer 208 is etched and retained as a partial film layer structure of the gate structure 203, thereby filling the height difference of each gate structure 203.

[0078] It should be noted that the mask used to expose the photoresist layer does not need to be prepared separately, and the mask used in preparing the semiconductor structure can be used, which effectively reduces the process cost. For example, 1G Mask can be reused.

[0079] Step 6 S60: Please refer to Fig.13 , removing the exposed portion of the hard mask layer 208 and retaining the portion of the hard mask layer 208 located on the surface of each of the gate structures 203, so that the heights of each of the gate structures 203 are the same.

[0080] Optionally, a dry etching process is used to remove the exposed portion of the hard mask layer 208. That is, the portion of the hard mask layer 208 located on the sacrificial layer 207 is removed, and the portion of the hard mask layer 208 located on the gate structure 203 is retained. Fig.13 As shown, the thickness of the portion of the hard mask layer 208 located on the gate structure 203 with a relatively low height is greater than the thickness of the portion of the hard mask layer 208 located on the gate structure 203 with a normal height, so that the top surfaces of all the retained hard mask layers 208 are located at the same height. Since the material of the hard mask layer 208 is consistent with the material of the oxide layer 205, the portion of the hard mask layer 208 located on each of the gate structures 203 can not only fill and repair the height difference between each of the gate structures 203, so that each of the gate structures 203 has the same height, but also can be well integrated with the oxide layer 205 and play the same protective role as the oxide layer 205.

[0081] Further, after executing step six S60, as Fig.14As shown, the patterned photoresist layer 209 is used as a barrier, and the sacrificial layer 207 is etched away by a dry etching process. Based on the fact that the material of the sacrificial layer 207 is A-Carbon, oxygen is preferably used as an etching gas to efficiently etch away the sacrificial layer 207 without affecting other film structures. After the etching is completed, the patterned photoresist layer 209 is removed by a cleaning process to form Fig.15 The semiconductor structure shown.

[0082] Based on the same concept, this embodiment also provides a semiconductor device. Fig.15 The semiconductor device is manufactured by the above-mentioned method for manufacturing a semiconductor device. In the semiconductor device, the top surface of the original gate structure 203 is covered with the hard mask layer 208 to form a new gate structure. The hard mask layer 208 is used to fill the height difference of the top surface of each of the original gate structures 203, so that the new gate structure has the same height D, which is conducive to ensuring the process effect of the subsequent process implementation.

[0083] In summary, the semiconductor device and its preparation method provided in this embodiment use the sacrificial layer 207 as a sacrificial medium, and form the hard mask layer 208 on the surface of each exposed gate structure 203 to fill the height difference of the surface of each gate structure 203. And, the hard mask layer 208 is planarized by a chemical mechanical polishing process so that the height of each gate structure 203 can be restored to the same horizontal plane. Based on this, the new gate structure with the same height is not only conducive to chemical mechanical polishing of a larger window using the same load parameters in the subsequent preparation process, but also conducive to etching the dummy gate cleanly and fully filling the polysilicon in the process of removing the dummy gate and filling the polysilicon, ensuring better process effects, and then being able to obtain ideal key parameters and improve the device yield.

[0084] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: A semiconductor structure is provided; the semiconductor structure comprises a plurality of MOS tubes; a silicon germanium trench structure is formed in the source and drain of some of the MOS tubes, and the height of the gate structure of some of the MOS tubes is lower than the height of the gate structure of the remaining MOS tubes; forming a sacrificial layer on the surface of the semiconductor structure, wherein the sacrificial layer exposes the surface of each of the gate structures; forming a hard mask layer on the sacrificial layer, wherein the hard mask layer covers the exposed surfaces of each of the gate structures; The hard mask layer is planarized by a chemical mechanical polishing process; wherein the planarized hard mask layer covers the surface of each gate structure; forming a patterned photoresist layer on the hard mask layer to expose a portion of the hard mask layer located on the sacrificial layer; The exposed portion of the hard mask layer is removed, and the portion of the hard mask layer located on the surface of each of the gate structures is retained, so that the heights of each of the gate structures are the same.

2. The method for preparing a semiconductor device according to claim 1, wherein: The material of the sacrificial layer includes amorphous carbon.

3. The method for preparing a semiconductor device according to claim 1, characterized in that: The process of forming a sacrificial layer on the surface of the semiconductor structure, wherein the sacrificial layer exposes the surface of each gate structure comprises: Forming a sacrificial material layer on the surface of the semiconductor structure, wherein the sacrificial material layer covers the surface of each of the gate structures; planarizing the sacrificial material layer using a chemical mechanical polishing process; The sacrificial material layer is etched by a dry etching process until the lowest surface of the gate structure is exposed; and the etched sacrificial material layer serves as the sacrificial layer.

4. The method for preparing a semiconductor device according to claim 1, wherein: After removing the exposed portion of the hard mask layer and retaining the portion of the hard mask layer located on the surface of each gate structure so that the heights of each gate structure are the same, the method for preparing the semiconductor device further includes: The sacrificial layer is removed by etching using the patterned photoresist layer as a barrier and a dry etching process is adopted.

5. The method for preparing a semiconductor device according to claim 3 or 4, characterized in that: The etching gas used in the dry etching process includes oxygen.

6. The method for preparing a semiconductor device according to claim 1, wherein: The hard mask layer is formed by a chemical vapor deposition process.

7. The method for preparing a semiconductor device according to claim 1, characterized in that: The exposed portion of the hard mask layer is removed by a dry etching process.

8. The method for preparing a semiconductor device according to claim 1, wherein: The surface of the gate structure is covered with an oxide layer, and the material of the hard mask layer is the same as that of the oxide layer.

9. The method for preparing a semiconductor device according to claim 8, characterized in that: The oxide layer and the hard mask layer are both made of silicon dioxide.

10. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 9.

Images