A bidirectional asymmetric voltage protection device and preparation method thereof

Abstract

The present invention provides a bidirectional asymmetric voltage protection device and a preparation method thereof, belonging to the technical field of semiconductor protection devices, comprising: a first unidirectional conduction unit, whose input end is connected to a first port; a second unidirectional conduction unit, whose input end is connected to a second port; a third unidirectional conduction unit, whose output end is connected to the first port; a fourth unidirectional conduction unit, whose output end is connected to the second port; a first transistor unit, whose input end is connected to the output end of the first unidirectional conduction unit; a second transistor unit, whose input end is respectively connected to the output end of the first transistor unit and the output end of the second unidirectional conduction unit, and whose output end is respectively connected to the input end of the third unidirectional conduction unit and the fourth unidirectional conduction unit. Beneficial effect: One direction of the device of the present invention has a higher breakdown voltage, which can withstand the high voltage impact caused by misinsertion, and the other direction has a lower breakdown voltage, which can ensure the integrity of signal transmission and the effective protection of the subsequent circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor protection devices, and in particular to a bidirectional asymmetric voltage protection device and a preparation method thereof. Background Art

[0002] Transient Voltage Suppressor (TVS) is a commonly used protection device, widely used in the interface circuits of various electronic devices, including but not limited to mobile phones, tablets, televisions, and computer hosts. The input and output (IO) ports of TVS devices are usually connected to the IO ports of the circuit, and its ground terminal is connected to the ground wire of the circuit, that is, the TVS device and the protected chip are in parallel. When the IO end of the circuit faces a transient voltage threat from electrostatic discharge (ESD) or surge voltage, the TVS device will be triggered to conduct first, and the current will be released to the ground through the TVS device, which can clamp these high voltages at a relatively low level in a very short time, thereby ensuring that the subsequent integrated circuit (IC) will not be damaged by excessive voltage.

[0003] With the rapid development of microelectronics technology, integrated circuits are constantly developing in the direction of low voltage, low power consumption, and high-speed transmission. Correspondingly, higher requirements are placed on the performance of TVS protection devices, requiring them to have lower parasitic capacitance and stronger protection capabilities. In certain specific application scenarios, in order to prevent damage caused by incorrect connections, some special requirements are placed on bidirectional protection devices. For example, in the Type-C interface, since the D+ and D- ports of the Type-C interface are close to the VBUS port, when misplugging occurs, the D+ and D- ports may withstand voltages as high as 12V or more. Therefore, a TVS device with bidirectional protection function is required. The breakdown voltage in one direction needs to be high enough to withstand the high voltage impact caused by such misplugging; while the breakdown voltage in the other direction is kept low to ensure the integrity of signal transmission and effective protection of the subsequent circuits. Summary of the invention

[0004] In order to solve the above technical problems, the present invention provides a bidirectional asymmetric voltage protection device; on the other hand, it also provides a method for preparing the bidirectional asymmetric voltage protection device.

[0005] The technical problem solved by the present invention can be achieved by the following technical scheme: a bidirectional asymmetric voltage protection device, the device is formed in a semiconductor substrate and connected between a first port and a second port, comprising: a first unidirectional conduction unit, the input end of the first unidirectional conduction unit is connected to the first port; a second unidirectional conduction unit, the input end of the second unidirectional conduction unit is connected to the second port; a third unidirectional conduction unit, the output end of the third unidirectional conduction unit is connected to the first port; a fourth unidirectional conduction unit, the output end of the fourth unidirectional conduction unit is connected to the second port; a first transistor unit, the input end of the first transistor unit is connected to the output end of the first unidirectional conduction unit; a second transistor unit, the input end of the second transistor unit is respectively connected to the output end of the first transistor unit and the output end of the second unidirectional conduction unit, and the output end of the second transistor unit is respectively connected to the input ends of the third unidirectional conduction unit and the fourth unidirectional conduction unit.

[0006] Preferably, the semiconductor substrate includes: a P-type first epitaxial layer formed on the surface of a P+ type substrate; an N-type buried layer formed on the surface of the P-type first epitaxial layer; an N-type second epitaxial layer formed on the surface of the N-type buried layer, and the device is formed in the N-type second epitaxial layer of the semiconductor substrate.

[0007] Preferably, it also includes: a plurality of isolation trenches, which respectively extend downward from the surface of the semiconductor substrate to isolate the first unidirectional conduction unit, the second unidirectional conduction unit, the third unidirectional conduction unit, the fourth unidirectional conduction unit, the first transistor unit and the second transistor unit.

[0008] Preferably, the control end of the first transistor unit is connected to the output end of the first transistor unit or is floatingly connected; and the control end of the second transistor unit is connected to its own output end or is floatingly connected.

[0009] Preferably, the first unidirectional conductive unit includes a first P+ region and a first N+ region, and the first P+ region and the first N+ region are respectively formed in the semiconductor substrate; the second unidirectional conductive unit includes a second P+ region and a second N+ region, and the second P+ region and the second N+ region are respectively formed in the semiconductor substrate; the third unidirectional conductive unit includes a first P-type well region, a third P+ region and a third N+ region, the first P-type well region is formed in the semiconductor substrate, and the third P+ region and the third N+ region are respectively formed in the first P-type well region; the fourth unidirectional conductive unit includes a second P-type well region, a fourth P+ region and a fourth N+ region, the second P-type well region is formed in the semiconductor substrate, and the fourth P+ region and the fourth N+ region are respectively formed in the second P-type well region.

[0010] Preferably, the first transistor unit includes: an N-type well region formed in the semiconductor substrate; a penetration region extending downward from the surface of the semiconductor substrate to the bottom of the N-type well region; a fifth N+ region formed in the penetration region; a P-type base region formed in the N-type well region; and a sixth N+ region formed in the P-type base region.

[0011] Preferably, the first transistor unit further includes: a fifth P+ region formed in the P-type base region.

[0012] Preferably, the first transistor unit includes: an N-type well region formed in the semiconductor substrate; a fifth N+ region formed in the N-type well region; a P-type base region formed in the N-type well region; a fifth P+ region and a sixth N+ region respectively formed in the P-type base region; and a polysilicon layer formed on the surface of the field oxide layer between the fifth N+ region and the P-type base region.

[0013] Preferably, the second transistor unit includes: a third P-type well region formed in the semiconductor substrate; a seventh N+ region formed in the third P-type well region; a fourth P-type well region formed in the third P-type well region; and an eighth N+ region formed in the fourth P-type well region.

[0014] Preferably, the second transistor unit further includes: a sixth P+ region formed in the third P-type well region.

[0015] The present invention also provides a method for preparing a bidirectional asymmetric voltage protection device, comprising: forming a first unidirectional conduction unit, a second unidirectional conduction unit, a third unidirectional conduction unit, a fourth unidirectional conduction unit, a first transistor unit and a second transistor unit in a semiconductor substrate respectively; wherein the input end of the first unidirectional conduction unit is connected to the first port, the output end of the first unidirectional conduction unit is connected to the input end of the first transistor unit, the output end of the first transistor unit is connected to the input end of the second transistor unit, the output end of the second transistor unit is respectively connected to the input ends of the third unidirectional conduction unit and the fourth unidirectional conduction unit, the output end of the fourth unidirectional conduction unit is connected to the second port, the input end of the second unidirectional conduction unit is connected to the second port, the output end of the second unidirectional conduction unit is connected to the input end of the second transistor unit, and the output end of the third unidirectional conduction unit is connected to the first port.

[0016] The advantages or beneficial effects of the technical solution of the present invention are: the device of the present invention has a bidirectional protection function, and the two directions have different breakdown voltages. The direction from the first port to the second port has a higher breakdown voltage and can withstand the high voltage impact caused by misplugging; and the direction from the second port to the first port has a lower breakdown voltage because it does not pass through the first transistor unit, which can better protect signal transmission, more effectively protect the subsequent circuit, and ensure the integrity of high-speed signal data transmission; at the same time, by utilizing the negative resistance characteristics of the transistor, both directions have low on-resistance and high surge capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of an equivalent circuit of a bidirectional asymmetric voltage protection device in preferred embodiment 1 of the present invention;

[0018] Figure 2 It is a structural schematic diagram of a bidirectional asymmetric voltage protection device in a preferred embodiment 1 of the present invention;

[0019] Figure 3a-3j It is a cross-sectional schematic diagram of each step of the preparation method in the preferred embodiment 1 of the present invention;

[0020] Figure 4 It is a structural schematic diagram of a bidirectional asymmetric voltage protection device in a preferred embodiment 2 of the present invention;

[0021] Figure 5 Schematic diagram of an equivalent circuit of a bidirectional asymmetric voltage protection device in a preferred embodiment 2 of the present invention;

[0022] Figure 6 This is a schematic diagram of an equivalent circuit of a bidirectional asymmetric voltage protection device in a preferred embodiment 3 of the present invention.

[0023] Description of reference numerals:

[0024] 100, first unidirectional conduction unit; 200, second unidirectional conduction unit; 300, third unidirectional conduction unit; 400, fourth unidirectional conduction unit; 500, first transistor unit; 600, second transistor unit; 10, semiconductor substrate; 1, substrate; 2, first epitaxial layer; 3, buried layer; 4, second epitaxial layer; 5, isolation groove; 61, N-type well region; 62, first P-type well region; 63, second P-type well region; 64, third P-type well region; 65, fourth P-type well region; 7, penetration region; 8, field oxide layer; 9, P-type base region; 101, first P+ region; 102, second P+ region; 103, third P+ region ; 104, fourth P+ region; 105, fifth P+ region; 106, sixth P+ region; 111, first N+ region; 112, second N+ region; 113, third N+ region; 114, fourth N+ region; 115, fifth N+ region; 116, sixth N+ region; 117, seventh N+ region; 118, eighth N+ region; 12, polysilicon layer; 13, dielectric layer; 131, contact hole; 141, first metal layer; 142, second metal layer; 143, third metal layer; 144, fourth metal layer; 145, fifth metal layer; 146, sixth metal layer; 147, seventh metal layer; 148, eighth metal layer. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0027] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0028] Embodiment 1:

[0029] See also Figure 1 and Figure 2In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, a bidirectional asymmetric voltage protection device is provided. The device is formed in a semiconductor substrate 10 and connected between a first port IO1 and a second port IO2, and includes: a first unidirectional conduction unit 100, wherein the input end of the first unidirectional conduction unit 100 is connected to the first port; a second unidirectional conduction unit 200, wherein the input end of the second unidirectional conduction unit 200 is connected to the second port; a third unidirectional conduction unit 300, wherein the output end of the third unidirectional conduction unit 300 is connected to the first port; a fourth unidirectional conduction unit 400, wherein the output end of the fourth unidirectional conduction unit 400 is connected to the second port; a first transistor unit 500, wherein the input end of the first transistor unit 500 is connected to the output end of the first unidirectional conduction unit 100; and a second transistor unit 600, wherein the input end of the second transistor unit 600 is respectively connected to the output end of the first transistor unit 500 and the output end of the second unidirectional conduction unit 200, and the output end of the second transistor unit 600 is respectively connected to the input ends of the third unidirectional conduction unit 300 and the fourth unidirectional conduction unit 400.

[0030] Specifically, the device of the present invention is composed of a first unidirectional conduction unit 100, a second unidirectional conduction unit 200, a third unidirectional conduction unit 300, a fourth unidirectional conduction unit 400, a first transistor unit 500, and a second transistor unit 600. The first port IO1 is connected to the input end of the first transistor unit 500 through the first unidirectional conduction unit 100, the output end of the first transistor unit 500 is connected to the input end of the second transistor unit 600, and the output end of the second transistor unit 600 is connected to the second port IO2 through the fourth unidirectional conduction unit 400; the second port IO2 is connected to the input end of the second transistor unit 600 through the second unidirectional conduction unit 200, and the output end of the second transistor unit 600 is connected to the first port IO1 through the third unidirectional conduction unit 300.

[0031] The device has a bidirectional protection function, and has different breakdown voltages in two directions, that is, the device has a first breakdown voltage in the IO1-IO2 direction, and has a second breakdown voltage in the IO2-IO1 direction, and the first breakdown voltage is greater than the second breakdown voltage. Wherein: from the first port IO1 to the second port IO2: the current flows from the first port IO1 to the second port IO2 through the first unidirectional conduction unit 100, the first transistor unit 500, the second transistor unit 600, and the fourth unidirectional conduction unit 400 to the second port IO2. The device has a first breakdown voltage in the IO1-IO2 direction, which is relatively high and can withstand the high voltage impact caused by the mis-insertion of the port; from the second port IO2 to the first port IO1: the current flows from the second port IO2 to the first port IO1 through the second unidirectional conduction unit 200, the second transistor unit 600, and the third unidirectional conduction unit 300 to the first port IO1. Since it does not pass through the first transistor unit 500, the device has a lower second breakdown voltage in the IO2-IO1 direction, which can better protect signal transmission, more effectively protect the subsequent circuit, and ensure the integrity of high-speed signal data transmission.

[0032] In this embodiment, the first unidirectional conducting unit 100, the second unidirectional conducting unit 200, the third unidirectional conducting unit 300 and the fourth unidirectional conducting unit 400 are all diodes. That is, the first unidirectional conducting unit 100 includes a first diode D1, the second unidirectional conducting unit 200 includes a second diode D2, the third unidirectional conducting unit 300 includes a third diode D3, and the fourth unidirectional conducting unit 400 includes a fourth diode D4.

[0033] The first to fourth diodes may be PN junction diodes, Schottky diodes, or other types of unidirectional conductive diodes.

[0034] In this embodiment, the first transistor unit 500 includes a first transistor T1, and the second transistor unit 600 includes a second transistor T2. The first transistor T1 and the second transistor T2 are bipolar transistors, field effect transistors, or other types of transistors. By utilizing the negative resistance characteristics of transistors, the device of the present invention has low on-resistance and high surge capability in both directions.

[0035] The equivalent circuit of the device of the present invention is as follows Figure 1 As shown, the anode of the first diode D1 is connected to the first port IO1, the cathode of the first diode D1 is connected to the collector of the first transistor T1, the emitter of the first transistor T1 and the collector of the second transistor T2 are respectively connected to the cathode of the second diode D2, the anode of the second diode D2 is connected to the second port IO2, the emitter of the second transistor T2 is respectively connected to the cathodes of the third diode D3 and the fourth diode D4, the anode of the third diode D3 is connected to the first port IO1, and the anode of the fourth diode D4 is connected to the second port IO2.

[0036] Further, the semiconductor substrate 10 includes a substrate 1, a first epitaxial layer 2, a buried layer 3 and a second epitaxial layer 4; wherein the substrate 1 has a first conductivity type; the first epitaxial layer 2 is formed on the surface of the substrate 1, and the conductivity type of the first epitaxial layer 2 is the same as that of the substrate 1 but the doping concentration is lower than the doping concentration of the substrate 1; the buried layer 3 is formed on the surface of the first epitaxial layer 2, and the buried layer 3 has a second conductivity type opposite to the first conductivity type; the second epitaxial layer 4 is formed on the surface of the buried layer 3, and the conductivity type of the second epitaxial layer 4 is the same as that of the buried layer 3 but the doping concentration is lower than the doping concentration of the buried layer 3. The device of the present invention is formed in the second epitaxial layer 4 of the semiconductor substrate 10.

[0037] In this embodiment, the first conductivity type is P type and the second conductivity type is N type. In the drawings, the corresponding doping concentration is indicated by indicating "+" after the doping type "N" or "P". For example, "N+" indicates a doping concentration that is higher than the doping concentration of the N-type doping region. Doping regions with the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different n-doping regions can have the same or different absolute doping concentrations.

[0038] As a preferred embodiment, the semiconductor substrate 10 includes: a P-type first epitaxial layer 2 formed on the surface of a P+ type substrate 1; an N-type buried layer 3 formed on the surface of the P-type first epitaxial layer 2; an N-type second epitaxial layer 4 formed on the surface of the N-type buried layer 3, and the device is formed in the N-type second epitaxial layer 4 of the semiconductor substrate 10.

[0039] In this embodiment, the P+ type substrate 1 is made of a low-resistance material, and its resistivity is less than 0.1Ω·cm.

[0040] In this embodiment, the thickness of the P-type first epitaxial layer 2 is 5 μm to 15 μm, and its resistivity is greater than 1 Ω·cm. Preferably, the resistivity of the P-type first epitaxial layer 2 is 10 Ω·cm to 20 Ω·cm. The present invention uses a P-type first epitaxial layer 2 with a high resistivity, or a P-type first epitaxial layer 2 with a relatively high thickness, which is beneficial to improving the isolation voltage and ensuring the normal operation of the device.

[0041] In this embodiment, the implanted element of the N-type buried layer 3 is arsenic or antimony, the implantation dose is 1E15-1E16 / cm2, and the implantation energy is 80-200KeV. After the implantation of the element, a high temperature driving process is performed. The high temperature driving temperature is 1100°C-1200°C, and the time is 60-120 minutes, so that the N-type buried layer has a certain thickness.

[0042] Furthermore, before growing the N-type second epitaxial layer 4, the silicon wafer (including the P+ type substrate 1, the P-type first epitaxial layer 2 and the N-type buried layer 3) needs to be cleaned to ensure that there are no impurity particles and native oxide layer on the surface of the silicon wafer. Subsequently, the N-type second epitaxial layer 4 is grown.

[0043] In this embodiment, the N-type second epitaxial layer 4 is of high resistance, with a resistivity of at least greater than 10Ω·cm and a thickness greater than 5μm. The use of high resistivity epitaxy is beneficial to reducing the capacitance of the device, so that the device of the present invention can be applied to high-speed signal transmission ports.

[0044] As a preferred embodiment, it also includes: multiple isolation trenches 5, which extend downward from the surface of the semiconductor substrate 10 to isolate the first unidirectional conduction unit 100, the second unidirectional conduction unit 200, the third unidirectional conduction unit 300, the fourth unidirectional conduction unit 400, the first transistor unit 500 and the second transistor unit 600.

[0045] Specifically, the surface of the semiconductor substrate 10 is coated with glue, exposed, and developed to define a deep trench etching area window, and then a deep trench is etched by dry etching, and silicon dioxide or undoped polysilicon is filled in the deep trench to form an isolation trench 5 (DTI).

[0046] Furthermore, after the isolation trench 5 is formed, the excess silicon dioxide or undoped polysilicon on the upper surface of the semiconductor substrate 10 is removed, and only the film in the trench is retained.

[0047] Preferably, the depth of the isolation trench 5 is greater than the sum of the thicknesses of the P-type first epitaxial layer 2 and the N-type second epitaxial layer 4. The width of the isolation trench 5 is 0.8 μm to 1.6 μm.

[0048] As a preferred embodiment, the control end of the first transistor unit 500 is connected to its own output end; and the control end of the second transistor unit 600 is connected to its own output end.

[0049] Specifically, the first transistor unit 500 and the second transistor unit 600 are both semiconductor devices having a control terminal. During normal operation of the device, the control terminal is configured not to directly participate in the voltage protection process, or the control terminal is fixedly biased to maintain the transistor unit in a specific working state.

[0050] As a preferred embodiment, the first unidirectional conductive unit 100 includes a first P+ region 101 and a first N+ region 111 , and the first P+ region 101 and the first N+ region 111 are respectively formed in the semiconductor substrate 10 .

[0051] Specifically, in this embodiment, the first diode D1 is an ultra-low capacitance diode formed by the first P+ region 101 , the N-type second epitaxial layer 4 and the first N+ region 111 .

[0052] The first P+ region 101 serves as an anode of the first diode D1 and contacts a metal layer corresponding to the first port IO1.

[0053] As a preferred embodiment, the second unidirectional conductive unit 200 includes a second P+ region 102 and a second N+ region 112 , and the second P+ region 102 and the second N+ region 112 are respectively formed in the semiconductor substrate 10 .

[0054] Specifically, in this embodiment, the second diode D2 is an ultra-low capacitance diode formed by the second P+ region 102 , the N-type second epitaxial layer 4 , and the second N+ region 112 .

[0055] The second P+ region 102 serves as an anode of the second diode D2 and contacts the metal layer corresponding to the second port IO2.

[0056] As a preferred embodiment, the third unidirectional conductive unit 300 includes a first P-type well region 62, a third P+ region 103 and a third N+ region 113, wherein the first P-type well region 62 is formed in the semiconductor substrate 10, and the third P+ region 103 and the third N+ region 113 are respectively formed in the first P-type well region 62.

[0057] Specifically, in this embodiment, the third diode D3 is an ultra-low capacitance diode formed by the third P+ region 103 , the first P-type well region 62 , and the third N+ region 113 .

[0058] The third N+ region 113 serves as a cathode of the third diode D3 and contacts the metal layer corresponding to the first port IO1.

[0059] As a preferred embodiment, the fourth unidirectional conductive unit 400 includes a second P-type well region 63, a fourth P+ region 104 and a fourth N+ region 114, the second P-type well region 63 is formed in the semiconductor substrate 10, and the fourth P+ region 104 and the fourth N+ region 114 are respectively formed in the second P-type well region 63.

[0060] Specifically, in the present embodiment, the fourth diode D4 is an ultra-low capacitance diode formed by the fourth P+ region 104 , the second P-type well region 63 and the fourth N+ region 114 .

[0061] The fourth N+ region 114 serves as a cathode of the fourth diode D4 and contacts the metal layer corresponding to the second port IO2.

[0062] Furthermore, the first P-type well region 62 and the second P-type well region 63 can be formed by the same PW1 photolithography implantation process to simplify the manufacturing process, specifically, by defining a PW1 implantation window by PW1 photolithography and then performing PW1 ion implantation.

[0063] In this embodiment, the implanted elements of the first P-type well region 62 and the second P-type well region 63 are both boron elements, the implanted dose is 1E11-1E13 / cm2, and the implanted energy is 60-100 KeV.

[0064] As a preferred embodiment, the first transistor unit 500 includes: an N-type well region 61 formed in the semiconductor substrate 10; a penetration region 7 extending downward from the surface of the semiconductor substrate 10 to the bottom of the N-type well region 61; a fifth N+ region 115 formed in the penetration region 7; a P-type base region 9 formed in the N-type well region 61; a sixth N+ region 116 and a fifth P+ region 105, respectively formed in the P-type base region 9.

[0065] Furthermore, in the step of forming the N-type well region 61, the NW implantation window is defined by NW lithography, and then NW ion implantation is performed. Preferably, the implantation element of the N-type well region 61 is phosphorus, the implantation dose is 1E12-5E13 / cm2, and the implantation energy is 60-150KeV.

[0066] Furthermore, in the step of forming the penetration region 7 (Sink), the Sink injection window is defined by Sink lithography, and then Sink ion implantation is performed. Preferably, the implantation element of the penetration region 7 is phosphorus, the implantation dose is 1E14~1E15 / cm2, high-energy ion implantation is used, and the implantation energy is 500K~1MeV. More preferably, the penetration region 7 can be implanted multiple times with different energies to form a better doping morphology.

[0067] Furthermore, in the step of forming the P-type base region 9, a PB injection window is defined by PB photolithography, and then PB ion injection is performed, followed by entering the furnace tube for high-temperature advancement.

[0068] Preferably, the implanted element of the P-type base region 9 is boron or boron difluoride, the implantation dose is 5E13-1E15 / cm2, and the implantation energy is 40-120 KeV. The temperature during high temperature advancement is above 900°C, and the time is 30-60 minutes.

[0069] In this embodiment, the first transistor T1 is a bipolar transistor formed by the fifth N+ region 115, the penetration region 7, the N-type well region 61, the sixth N+ region 116 and the fifth P+ region 105, and has a relatively high breakdown voltage.

[0070] Specifically, the penetration region 7 is a relatively concentrated N-type doping region, and the space charge region (depletion region) of the P-type base region 9 and the N-type well region 61 will expand toward the penetration region 7. When expanding to the Sink region, breakdown occurs.

[0071] Furthermore, according to application requirements, the breakdown voltage of the transistor can be controlled to a first breakdown voltage through process adjustment. The first breakdown voltage is preferably 10V to 40V.

[0072] As a preferred embodiment, the second transistor unit 600 includes: a third P-type well region 64, formed in the semiconductor substrate 10; a seventh N+ region 117 and a sixth P+ region 106, respectively formed in the third P-type well region 64; a fourth P-type well region 65, formed in the third P-type well region 64; and an eighth N+ region 118, formed in the fourth P-type well region 65.

[0073] Furthermore, in the step of forming the third P-type well region 64, a PW2 injection window is defined by PW2 photolithography, and then PW2 ion implantation is performed. Subsequently, the PW2 is placed in a furnace for high-temperature advancement, so that NW, PW1, and PW2 diffuse to a certain depth.

[0074] Preferably, the implantation element of the third P-type well region 64 is boron, the implantation dose is 1E13-1E14 / cm2, and the implantation energy is 40-60 KeV. The temperature during high temperature advancement is above 1100° C., and the time is 30-120 minutes.

[0075] Furthermore, in the step of forming the fourth P-type well region 65, a PW3 injection window is defined by PW3 photolithography, and then PW3 ion implantation is performed. Subsequently, the PW3 is placed in a furnace for high-temperature advancement, so that Sink and PW3 diffuse to a certain depth.

[0076] Preferably, the implantation element of the fourth P-type well region 65 is boron, the implantation dose is 1E14-1E15 / cm2, and the implantation energy is 50-100 KeV. The temperature during high temperature advancement is above 1000° C., and the time is 30-120 minutes.

[0077] In this embodiment, the second transistor T2 is another bipolar transistor formed by the eighth N+ region 118, the fourth P-type well region 65, the third P-type well region 64, the seventh N+ region 117 and the sixth P+ region 106, and has a higher breakdown voltage.

[0078] Furthermore, according to application requirements, the breakdown voltage of the transistor can be controlled to a second breakdown voltage through process adjustment. The second breakdown voltage is preferably in the range of 3.3V to 10V.

[0079] Furthermore, the device of the present invention also includes: a field oxide layer 8, formed on the surface of the semiconductor substrate 10, and alternately arranged with the active area of ​​each unit (including the first to eighth N+ areas and the first to sixth P+ areas mentioned above); a dielectric layer 13, formed on the surface of the semiconductor substrate 10, and a plurality of contact holes 131 are formed in the dielectric layer 13; and a metal layer, formed in the contact holes 131.

[0080] Specifically, in the step of forming the field oxide layer 8, the active area is formed by using a local oxidation technique on the surface of the semiconductor substrate 10. Specifically, a thin oxide layer is first grown, and then a layer of silicon nitride is deposited, and part of the silicon nitride is removed by photolithography and dry etching, and then the field oxide layer 8 (FOX) is grown, and then the remaining silicon nitride is removed by wet etching.

[0081] Preferably, the field oxide layer 8 has a thickness of 4000-8000Å and is grown in a high-temperature furnace tube at a temperature of 950-1050°C, with oxygen and hydrogen being the gases introduced.

[0082] The deposition thickness of the silicon nitride layer is 1000~2000Å. The wet etching process for removing silicon nitride uses 80°C hot phosphoric acid. After 45~60 minutes of etching, the silicon nitride can be completely removed.

[0083] Furthermore, the first to eighth N+ regions can be prepared by the same N+ ion implantation process. Similarly, the first to sixth P+ regions can also be prepared by the same P+ ion implantation process. Specifically, the N+ implantation window is first defined by N+ photolithography, and then N+ ion implantation is performed; then the P+ implantation window is defined by P+ photolithography, and then P+ ion implantation is performed; then a rapid thermal annealing process is performed to repair implantation damage and activate impurity ions.

[0084] Preferably, the implanted element of the first to eighth N+ regions is phosphorus, the implanted dose is 1E15~1E16 / cm2, and the implanted energy is 40~120KeV. The implanted element of the first to sixth P+ regions is boron or boron difluoride, the implanted dose is 1E15~1E16 / cm2, and the implanted energy is 30~100KeV. The rapid thermal annealing process temperature is above 1000°C and the time is 20~40 seconds.

[0085] Furthermore, the contact hole 131 includes a plurality of contact holes, and the plurality of contact holes 131 are windows corresponding to the first to eighth N+ regions and the first to sixth P+ regions respectively.

[0086] Furthermore, in the present embodiment, the metal layers include, from left to right, a first metal layer 141 , a second metal layer 142 , a third metal layer 143 , a fourth metal layer 144 , a fifth metal layer 145 , a sixth metal layer 146 , a seventh metal layer 147 and an eighth metal layer 148 .

[0087] The first metal layer 141 is used as a grounding metal to contact the third P+ region 103 to achieve the grounding connection of the anode of the third diode D3.

[0088] The second metal layer 142 serves as a contact metal corresponding to the first port IO1 and contacts the third N+ region 113 and the first P+ region 101 respectively, so that the cathode of the third diode D3 and the anode of the first diode D1 are simultaneously connected to the first port IO1.

[0089] The third metal layer 143 is in contact with the first N+ region 111 and the fifth N+ region 115 , respectively, so as to connect the cathode of the first diode D1 with the collector of the first transistor T1 .

[0090] The fourth metal layer 144 is in contact with the sixth N+ region 116 , the fifth P+ region 105 , and the eighth N+ region 118 , respectively, so that the base and the emitter of the first transistor T1 are simultaneously connected to the collector of the second transistor T2 .

[0091] The fifth metal layer 145 serves as a grounding metal and contacts the seventh N+ region 117 , the sixth P+ region 106 and the fourth P+ region 104 respectively, so as to realize the grounding connection of the base and emitter of the second transistor T2 and the anode of the fourth diode D4 .

[0092] The sixth metal layer 146 serves as a contact metal corresponding to the second port IO2 and contacts the fourth N+ region 114 and the second P+ region 102 respectively, so that the anode of the second diode D2 and the cathode of the fourth diode D4 are simultaneously connected to the second port IO2.

[0093] The seventh metal layer 147 contacts the second N+ region 112, and the eighth metal layer 148 adopts a "C"-shaped design so that the seventh metal layer 147 contacts the fourth metal layer 144, thereby connecting the cathode of the second diode D2 with the collector of the second transistor T2.

[0094] The present invention also provides a method for preparing a bidirectional asymmetric voltage protection device, comprising: forming a first unidirectional conduction unit 100, a second unidirectional conduction unit 200, a third unidirectional conduction unit 300, a fourth unidirectional conduction unit 400, a first transistor unit 500 and a second transistor unit 600 in a semiconductor substrate 10 respectively; wherein the input end of the first unidirectional conduction unit 100 is connected to the first port IO1, the output end of the first unidirectional conduction unit 100 is connected to the input end of the first transistor unit 500, the output end of the first transistor unit 500 is connected to the input end of the second transistor unit 600, the output end of the second transistor unit 600 is connected to the input end of the third unidirectional conduction unit 300 and the fourth unidirectional conduction unit 400 respectively, the output end of the fourth unidirectional conduction unit 400 is connected to the second port IO2, the input end of the second unidirectional conduction unit 200 is connected to the second port IO2, the output end of the second unidirectional conduction unit 200 is connected to the input end of the second transistor unit 600, and the output end of the third unidirectional conduction unit 300 is connected to the first port IO1.

[0095] Specifically, the bidirectional asymmetric voltage protection device prepared by the preparation method of the present invention has the characteristics of flexible application. The preparation method of the present invention is described in detail below, including the following steps:

[0096] Step 1: Figure 3a As shown, first, a P-type first epitaxial layer 2 (P-epi) is grown on a P+ type substrate 1 by an epitaxial process.

[0097] Preferably, the P+ substrate is made of low-resistance material with a resistivity less than 0.1Ω·cm. The thickness of the P-type first epitaxial layer 2 is 5-15μm, and the resistivity should be greater than 1Ω·cm, which is 10-20Ω·cm in this embodiment. Using a high-resistivity P-type epitaxial layer or a relatively thick P-type epitaxial layer is beneficial to improving the isolation voltage and ensuring the normal operation of the device.

[0098] Step 2: If Figure 3b As shown, N-type ion implantation is performed on the surface, followed by high temperature driving to form an N-type buried layer 3 (NBL).

[0099] Preferably, the implanted element of the N-type buried layer 3 is arsenic or antimony, the implantation dose is 1E15-1E16 / cm2, and the implantation energy is 80-200KeV. In the high temperature driving process, the temperature is 1100°C-1200°C, and the time is 60-120 minutes, so that the N-type buried layer 3 has a certain thickness.

[0100] Step 3: If Figure 3c As shown, on the above surface, an N-type second epitaxial layer 4 (N-epi) is grown by an epitaxial process.

[0101] Preferably, the silicon wafer needs to be cleaned before growing the epitaxial layer to ensure that there are no impurity particles and native oxide layer on the surface before growing the epitaxial layer. The N-type second epitaxial layer 4 uses a high resistance specification, which should be at least greater than 10Ω·cm, and the thickness should be greater than 5μm. The use of high resistivity epitaxy is conducive to reducing the capacitance of the device, and the device of the present invention can be applied to high-speed signal transmission ports.

[0102] Step 4: Figure 3d As shown, the surface is coated with glue, exposed, and developed to define a deep trench etching area window, and then a deep trench is etched by dry etching, and silicon dioxide or undoped polysilicon is filled in the deep trench to form an isolation trench 5 (DTI), and then the excess silicon dioxide or undoped polysilicon on the front side is removed to retain only the film quality in the trench.

[0103] Preferably, the depth of the isolation trench 5 is greater than the sum of the thicknesses of the P-type first epitaxial layer 2 and the N-type second epitaxial layer 4. The width of the isolation trench 5 is 0.8-1.6 μm.

[0104] Step 5: Figure 3e As shown, the NW injection window is defined by NW lithography, and then NW ion implantation is performed to form an N-type well region 61; the PW1 injection window is defined by PW1 lithography, and then PW1 ion implantation is performed to form a first P-type well region 62 and a second P-type well region 63; the PW2 injection window is defined by PW2 lithography, and then PW2 ion implantation is performed to form a third P-type well region 64. Subsequently, the furnace tube is entered for high-temperature advancement, so that the N-type well region 61, the first P-type well region 62, the second P-type well region 63 and the third P-type well region 64 diffuse to a certain depth.

[0105] Preferably, the implantation element of the N-type well region 61 is phosphorus, the implantation dose is 1E12~5E13 / cm2, and the implantation energy is 60~150KeV. The first P-type well region 62 and the second P-type well region 63 are formed by the same PW1 process, and the implantation element thereof is boron, the implantation dose is 1E11~1E13 / cm2, and the implantation energy is 60~100KeV. The implantation element of PW2 is boron, the implantation dose is 1E13~1E14 / cm2, and the implantation energy is 40~60KeV. During high temperature advancement, the temperature is above 1100°C, and the time is 30~120 minutes.

[0106] Step 6: Figure 3f As shown, a Sink injection window is defined by Sink photolithography, and then Sink ion implantation is performed to form a penetration region 7 in the N-type well region 61; a PW3 injection window is defined by PW3 photolithography, and then PW3 ion implantation is performed to form a fourth P-type well region 65. Subsequently, the furnace tube is entered for high-temperature advancement, so that the penetration region 7 and the fourth P-type well region 65 diffuse to a certain depth.

[0107] Preferably, the penetration region 7 is located in the N-type well region 61, and the depth of the penetration region 7 is the same as the depth of the N-type well region 61, and its width is smaller than the width of the N-type well region 61. The implantation element of the penetration region 7 is phosphorus, the implantation dose is 1E14~1E15 / cm2, and high-energy ion implantation is used, and the implantation energy is 500K~1MeV. More preferably, the Sink can be implanted with multiple different energies to form a better doping morphology. The fourth P-type well region 65 is located in the second P-type well region 63, and the implantation element is boron, the implantation dose is 1E14~1E15 / cm2, and the implantation energy is 50~100KeV. During high-temperature advancement, the temperature is above 1000°C and the time is 30~120 minutes.

[0108] Step 7: Figure 3g As shown, the active area is made on the above surface by using local oxidation technology: first, a thin oxide layer is grown, then a layer of silicon nitride is deposited, part of the silicon nitride is removed by photolithography and dry etching, then a field oxide layer 8 (FOX) is grown, and then the remaining silicon nitride is removed by wet etching.

[0109] Preferably, the field oxide layer 8 has a thickness of 4000-8000Å and is grown in a high temperature furnace tube at a temperature of 950-1050°C with oxygen and hydrogen as the gas. The silicon nitride deposition thickness is 1000-2000Å, and the wet etching process for removing silicon nitride uses hot phosphoric acid at 80°C. After 45-60 minutes of etching, the silicon nitride can be completely removed.

[0110] Step 8: Figure 3h As shown, the PB injection window is defined by PB lithography, and then PB ion implantation is performed to form a P-type base region 9 (PB), whose doping type is P-type, which is the base region (base) in the NPN transistor. Then it enters the furnace tube for high-temperature advancement.

[0111] Preferably, the implanted element of the P-type base region 9 is boron or boron difluoride, the implantation dose is 5E13-1E15 / cm2, and the implantation energy is 40-120 KeV. The temperature during high temperature advancement is above 900°C, and the time is 30-60 minutes.

[0112] Step 9: Figure 3i As shown, the N+ implantation window is defined by N+ lithography, and then N+ ion implantation is performed to form the first to eighth N+ regions; the P+ implantation window is defined by P+ lithography, and then P+ ion implantation is performed to form the first to sixth P+ regions. A rapid thermal annealing process is then performed to repair implantation damage and activate impurity ions.

[0113] Preferably, the implanted element of the first to eighth N+ regions is phosphorus, the implanted dose is 1E15~1E16 / cm2, and the implanted energy is 40~120KeV. The implanted element of the first to sixth P+ regions is boron or boron difluoride, the implanted dose is 1E15~1E16 / cm2, and the implanted energy is 30~100KeV. The rapid thermal annealing process temperature is above 1000°C and the time is 20~40 seconds.

[0114] Step 10: Figure 3j As shown, a dielectric layer 13 is deposited on the above surface, and then photolithography and etching are performed to form a contact hole 131.

[0115] Preferably, the dielectric layer 13 may be an oxide layer, or borophosphorus glass, or a combination of multiple insulating layers.

[0116] Step 11: Deposit metal on the above surface, and then use photolithography and metal etching to form metal wiring. The connection method is as follows: Figure 2 shown.

[0117] like Figure 1 As shown is an equivalent circuit diagram of a device according to an embodiment of the present invention, wherein the first diode D1 and the second diode D2 are ultra-low capacitance diodes formed by P+ / N-epi / N+, the third diode D3 and the fourth diode D4 are another ultra-low capacitance diode formed by P+ / PW1 / N+, the anode of the first diode D1 and the cathode of the third diode D3 are connected to the first port IO1, and the anode of the second diode D2 and the cathode of the fourth diode D4 are connected to the second port IO2.

[0118] The first transistor T1 is a bipolar transistor formed by N+ / Sink / NW / PB / N+ / P+, and its breakdown voltage is relatively high. According to the application requirements, the voltage can be controlled within the range of 10V~40V through process adjustment. The second transistor T2 is another bipolar transistor formed by N+ / PW3 / PW2 / N+ / P+, and its breakdown voltage is relatively low, and the breakdown voltage can be controlled within the range of 3.3V~10V. The collector of the first transistor T1 is connected to the cathode of the first diode D1, the base and emitter of the first transistor T1 are short-circuited together, and are simultaneously connected to the cathode of the second diode D2 and the collector of the second transistor T2, and the base and emitter of the second transistor T2 are short-circuited together, and are simultaneously connected to the anodes of the third diode D3 and the fourth diode D4.

[0119] The present invention has different breakdown voltages in two directions. In the IO1-IO2 direction, after being turned on, the current passes through the first diode D1, the first transistor T1, the second transistor T2, and the fourth diode D4 from the IO1 port in sequence to reach the IO2 port, and has a higher breakdown voltage. In the IO2-IO1 direction, after being turned on, the current passes through D2, the second transistor T2, and the third diode D3 from the IO2 port in sequence to reach the IO1 port. Since it does not pass through the first transistor T1, it has a lower breakdown voltage.

[0120] In the device of the present invention, since both the first transistor T1 and the second transistor T2 utilize the negative resistance characteristic of the bipolar transistor, both directions have very low on-resistance and higher surge capability during protection.

[0121] The device of the present invention has a lower parasitic capacitance after being connected in series, because the first diode D1, the second diode D2, the third diode D3 and the fourth diode D4 are ultra-low capacitance diodes, and can ensure the integrity of high-speed signal data transmission.

[0122] Embodiment 2:

[0123] A second embodiment of the present invention provides a bidirectional asymmetric voltage protection device, such as Figure 4 As shown, the difference from the first embodiment is that the fifth P+ region 105 and the sixth P+ region 106 are removed to change the connection mode of the first transistor T1 and the second transistor T2, and the base electrodes of the two transistors are not led out, but the function realized by the device remains unchanged.

[0124] As a preferred embodiment, wherein Figure 5 As shown, the control terminal of the first transistor unit 500 is connected in a floating manner; and the control terminal of the second transistor unit 600 is connected in a floating manner.

[0125] Specifically, in this embodiment, the control terminals of the first transistor unit 500 and the second transistor unit 600 are both in a floating connection mode, that is, the bases of the first transistor T1 and the second transistor T2 are both in a floating state without being electrically connected to the surroundings.

[0126] Embodiment three:

[0127] Embodiment 3 of the present invention provides a bidirectional asymmetric voltage protection device, such as Figure 6 As shown, the difference from the first embodiment is that the penetration region 7 (Sink) is removed, and a polysilicon layer 12 is added as a field plate on the field oxide layer 8 (FOX) on the left side of the P-type base region 9 (PB) to further improve the breakdown voltage of the first transistor T1.

[0128] As a preferred embodiment, the first transistor unit 500 includes: an N-type well region 61 formed in a semiconductor substrate 10; a fifth N+ region 115 formed in the N-type well region 61; a P-type base region 9 formed in the N-type well region 61; a sixth N+ region 116 and a fifth P+ region 105 formed in the P-type base region 9, respectively; and a polysilicon layer 12 formed on the surface of the field oxide layer 8 between the fifth N+ region 115 and the P-type base region 9.

[0129] Specifically, in the above-mentioned first and second embodiments, due to the existence of the penetration region 7, the space charge region (depletion region) of the P-type base region 9 and the N-type well region 61 will expand toward the penetration region 7, and when expanding to the Sink region, breakdown occurs.

[0130] In the third embodiment of the present invention, after the penetration region 7 is removed, the space charge region of the P-type base region 9 and the N-type well region 61 is no longer restricted by the Sink region, but will continue to expand toward the N+ region, making the space charge region of the device wider. Therefore, the device of the present invention has a higher breakdown voltage.

[0131] The field plate can change the distribution of electric field lines. In this embodiment, by adding a polysilicon layer 12 as a field plate on the field oxide layer 8 on the left side of the P-type base region 9, the breakdown point is improved from the silicon surface to the device body. Since the breakdown in the silicon body usually has a higher energy threshold than the surface breakdown, the device of the present invention has a higher breakdown voltage and improves the voltage resistance of the device.

[0132] The advantages or beneficial effects of adopting the above technical solution are: the two directions of the present invention have different breakdown voltages, the IO1-IO2 direction has a higher breakdown voltage, and by utilizing the negative resistance characteristics of the transistor, both directions have very low on-resistance and higher surge capability. The IO2-IO1 direction does not pass through the first transistor unit and therefore has a lower breakdown voltage, which better protects signal transmission, can more effectively protect the subsequent circuits, and ensure the integrity of high-speed signal data transmission.

[0133] The above are only preferred embodiments of the present invention, and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the contents of this specification and illustrations should be included in the protection scope of the present invention.

Claims

1. A bidirectional asymmetric voltage protection device, characterized in that: The device is formed in a semiconductor substrate and connected between a first port and a second port, and includes: a first unidirectional conduction unit, an input end of the first unidirectional conduction unit is connected to the first port; a second unidirectional conduction unit, an input end of the second unidirectional conduction unit is connected to the second port; a third unidirectional conduction unit, an output end of the third unidirectional conduction unit is connected to the first port; a fourth unidirectional conduction unit, an output end of the fourth unidirectional conduction unit is connected to the second port; a first transistor unit, an input end of the first transistor unit is connected to an output end of the first unidirectional conduction unit; a second transistor unit, an input end of the second transistor unit is respectively connected to an output end of the first transistor unit and an output end of the second unidirectional conduction unit, and an output end of the second transistor unit is respectively connected to an input end of the third unidirectional conduction unit and an input end of the fourth unidirectional conduction unit.

2. The bidirectional asymmetric voltage protection device according to claim 1, characterized in that: The semiconductor substrate comprises: a P-type first epitaxial layer formed on the surface of a P+-type substrate; an N-type buried layer formed on the surface of the P-type first epitaxial layer; an N-type second epitaxial layer formed on the surface of the N-type buried layer, and the device is formed in the N-type second epitaxial layer of the semiconductor substrate.

3. The bidirectional asymmetric voltage protection device according to claim 1, characterized in that: Also includes: A plurality of isolation trenches are respectively extended downward from the surface of the semiconductor substrate to isolate the first unidirectional conduction unit, the second unidirectional conduction unit, the third unidirectional conduction unit, the fourth unidirectional conduction unit, the first transistor unit and the second transistor unit.

4. The bidirectional asymmetric voltage protection device according to claim 1, characterized in that: The control end of the first transistor unit is connected to the output end of the first transistor unit or is floatingly connected; and the control end of the second transistor unit is connected to its own output end or is floatingly connected.

5. The bidirectional asymmetric voltage protection device according to claim 1, characterized in that: The first unidirectional conductive unit includes a first P+ region and a first N+ region, and the first P+ region and the first N+ region are respectively formed in the semiconductor substrate; the second unidirectional conductive unit includes a second P+ region and a second N+ region, and the second P+ region and the second N+ region are respectively formed in the semiconductor substrate; the third unidirectional conductive unit includes a first P-type well region, a third P+ region and a third N+ region, the first P-type well region is formed in the semiconductor substrate, and the third P+ region and the third N+ region are respectively formed in the first P-type well region; the fourth unidirectional conductive unit includes a second P-type well region, a fourth P+ region and a fourth N+ region, the second P-type well region is formed in the semiconductor substrate, and the fourth P+ region and the fourth N+ region are respectively formed in the second P-type well region.

6. The bidirectional asymmetric voltage protection device according to claim 1, characterized in that: The first transistor unit includes: an N-type well region formed in the semiconductor substrate; a penetration region extending downward from the surface of the semiconductor substrate to the bottom of the N-type well region; a fifth N+ region formed in the penetration region; a P-type base region formed in the N-type well region; and a sixth N+ region formed in the P-type base region.

7. The bidirectional asymmetric voltage protection device according to claim 6, characterized in that: The first transistor unit further includes: a fifth P+ region formed in the P-type base region.

8. The bidirectional asymmetric voltage protection device according to claim 1, characterized in that: The first transistor unit includes: an N-type well region formed in the semiconductor substrate; a fifth N+ region formed in the N-type well region; a P-type base region formed in the N-type well region; a fifth P+ region and a sixth N+ region respectively formed in the P-type base region; and a polysilicon layer formed on the surface of a field oxide layer between the fifth N+ region and the P-type base region.

9. The bidirectional asymmetric voltage protection device according to claim 1, characterized in that: The second transistor unit includes: a third P-type well region formed in the semiconductor substrate; a seventh N+ region and a sixth P+ region respectively formed in the third P-type well region; a fourth P-type well region formed in the third P-type well region; and an eighth N+ region formed in the fourth P-type well region.

10. A method for preparing a bidirectional asymmetric voltage protection device, characterized in that: Used to prepare the bidirectional asymmetric voltage protection device as described in any one of claims 1 to 9, comprising: forming a first unidirectional conduction unit, a second unidirectional conduction unit, a third unidirectional conduction unit, a fourth unidirectional conduction unit, a first transistor unit and a second transistor unit in a semiconductor substrate respectively; wherein the input end of the first unidirectional conduction unit is connected to the first port, the output end of the first unidirectional conduction unit is connected to the input end of the first transistor unit, the output end of the first transistor unit is connected to the input end of the second transistor unit, the output end of the second transistor unit is connected to the input end of the third unidirectional conduction unit and the fourth unidirectional conduction unit respectively, the output end of the fourth unidirectional conduction unit is connected to the second port, the input end of the second unidirectional conduction unit is connected to the second port, the output end of the second unidirectional conduction unit is connected to the input end of the second transistor unit, and the output end of the third unidirectional conduction unit is connected to the first port.

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