Accelerator chip instruction running analysis method, device, equipment, medium and product

Abstract

The application relates to an accelerator chip instruction operation analysis method, device, equipment, medium and product. The method comprises the following steps: obtaining a plurality of data streams by acquiring a binary file corresponding to a target kernel function executed by an accelerator chip; then, according to the binary file, acquiring a plurality of assembly instruction codes corresponding to the binary file; and then, according to the time sequence of clock cycles, sequentially matching each assembly instruction code with a data stream corresponding to the assembly instruction code to obtain an instruction code analysis result corresponding to the assembly instruction code, wherein the instruction code analysis result comprises at least one of the number of clock cycles required for the accelerator chip to execute the assembly instruction code and the execution times corresponding to the assembly instruction code. The method can improve the accuracy of the analysis result.

Description

Technical Field

[0001] This application relates to the field of high-performance computer technology, and in particular to an accelerator chip instruction execution analysis method, apparatus, device, medium and product. Background Technology

[0002] With the development of computer technology, high-performance computers have become widely used. High-performance computers refer to computer systems accelerated by clusters and dedicated accelerator chips. They are characterized by high computational complexity and large amounts of computational data, and are typically used in scientific computing, deep learning training and inference, and other fields. To optimize the computational performance of high-performance computers, it is usually necessary to study the dedicated programs of the accelerator chips—kernel functions.

[0003] In existing technologies, ROC Prof (GPU performance analysis tool) is typically used to analyze the running status of kernel functions running on accelerator chips. The analysis results of kernel functions can show the execution process of various instructions contained in the kernel function. However, the analysis results obtained by the above method have the problem of low accuracy. Summary of the Invention

[0004] Therefore, it is necessary to provide an accelerator chip instruction execution analysis method, apparatus, device, medium, and product that can improve the accuracy of kernel function analysis results in response to the above-mentioned technical problems.

[0005] Firstly, this application provides a method for analyzing the instruction execution of an accelerator chip. The method includes:

[0006] Obtain multiple data streams from the binary file corresponding to the target kernel function executed by the accelerator chip;

[0007] Based on the binary file, obtain multiple assembly instruction codes corresponding to the binary file;

[0008] According to the timing sequence of the clock cycles, each assembly instruction code is matched with the corresponding data stream in turn to obtain the instruction code analysis result corresponding to the assembly instruction code. The instruction code analysis result includes at least one of the number of clock cycles required for the accelerator chip to execute the assembly instruction code and the number of times the assembly instruction code is executed.

[0009] By analyzing the data flow corresponding to each assembly instruction code on a clock cycle, the resulting instruction code analysis can accurately reflect the execution process of each assembly instruction code. For example, it can reflect the number of clock cycles required to execute the assembly instruction code and the number of times the assembly instruction code is executed. This avoids the problem of low accuracy in the analysis results obtained when using ROC Prof to analyze the kernel functions running on the accelerator chip in traditional technology, which can only roughly reflect the execution process of various types of assembly instruction codes. The accelerator chip instruction execution analysis method provided in this application refines the analysis granularity of kernel function analysis, and the resulting instruction code analysis results are more accurate.

[0010] In one embodiment, based on the binary file, multiple assembly instruction codes corresponding to the binary file are obtained, including:

[0011] By using performance analysis tools, the binary file is disassembled to obtain multiple assembly instruction codes corresponding to the binary file.

[0012] In this embodiment, a performance analysis tool with disassembly capabilities is used to automatically disassemble the binary file, thereby improving the efficiency of disassembly.

[0013] In one embodiment, each assembly instruction code is matched with its corresponding data stream in chronological order according to the clock cycle, to obtain the instruction code analysis result, including:

[0014] According to the timing sequence of the clock cycle, each assembly instruction code is matched with the corresponding data stream in turn to determine the execution start time, execution end time and execution number of the assembly instruction code.

[0015] Determine the number of clock cycles required to execute the assembly instruction code based on the execution start time and execution end time.

[0016] In this embodiment, the computer device matches each assembly instruction code with each data stream sequentially according to the timing sequence, making the matching method more convenient. After the matching process, the execution start time and execution end time, the number of times the assembly instruction code is executed, and the number of clock cycles required for each assembly instruction code are determined. This allows developers to quickly identify the areas where the target kernel function needs to be optimized and improved based on the instruction code analysis results obtained in the above embodiment, thereby improving the efficiency of developers in optimizing the target kernel function.

[0017] In one embodiment, the method further includes:

[0018] The analysis results of the instruction code corresponding to each assembly instruction code are displayed visually according to the preset display method.

[0019] In this embodiment, the computer device visualizes the instruction code analysis results corresponding to each assembly instruction code according to a preset display method, which more intuitively reflects the instruction code analysis results corresponding to each assembly instruction code, enabling developers to more intuitively and accurately determine the running status of each assembly instruction code, thereby improving the efficiency of optimizing the target kernel function.

[0020] In one embodiment, the instruction code analysis results corresponding to each assembly instruction code are visualized according to a preset display method, including:

[0021] Determine the instruction class to which each assembly instruction code belongs, and the computing unit in the accelerator chip corresponding to the instruction class;

[0022] In the preset display interface, the analysis results of each instruction code under the instruction category are displayed in correspondence with the calculation unit identifier of the calculation unit corresponding to the instruction category.

[0023] In the visualization of instruction code analysis results, this embodiment not only displays the instruction code analysis results corresponding to the assembly instruction code, but also displays the instruction category and calculation unit corresponding to each assembly instruction code, providing a richer display dimension.

[0024] In one embodiment, in a preset display interface, the analysis results of each instruction code under the instruction category are displayed in correspondence with the calculation unit identifier of the calculation unit corresponding to the instruction category, including:

[0025] For each instruction category corresponding to the computing unit identifier, the timeline control corresponding to the instruction category is displayed in the display interface according to the timing sequence of the clock cycle, so as to display the instruction code analysis results of each assembly instruction code under the instruction category.

[0026] In this embodiment, the timeline control can more vividly display the analysis results of each instruction code in a timeline.

[0027] In one embodiment, the timeline control is used to display the clock cycles in which each assembly instruction code under an instruction category is executed, and the method further includes:

[0028] If a click operation is detected on the target timeline control, the target assembly instruction code corresponding to the target timeline control is determined, and the instruction code analysis result of the target assembly instruction code is displayed in a preset position on the display interface.

[0029] In this embodiment, the instruction code analysis results are displayed in more detail at a preset location.

[0030] Secondly, this application also provides an accelerator chip instruction execution analysis device. The device includes:

[0031] The first acquisition module is used to acquire multiple data streams obtained from the binary file corresponding to the target kernel function executed by the accelerator chip;

[0032] The second acquisition module is used to acquire multiple assembly instruction codes corresponding to the binary file based on the binary file.

[0033] The matching module is used to match each assembly instruction code with the corresponding data stream in the order of clock cycles to obtain the instruction code analysis result. The instruction code analysis result includes at least one of the following: the number of clock cycles required for the accelerator chip to execute the assembly instruction code and the number of times the assembly instruction code is executed.

[0034] Thirdly, this application also provides a computer device. The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps of the method described in the first aspect above.

[0035] Fourthly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program thereon, which, when executed by a processor, implements the steps of the method described in the first aspect above.

[0036] Fifthly, this application also provides a computer program product. The computer program product includes a computer program that, when executed by a processor, implements the steps of the method described in the first aspect above.

[0037] The aforementioned accelerator chip instruction execution analysis method, apparatus, device, medium, and product obtain multiple data streams from the binary file corresponding to the target kernel function executed by the accelerator chip. Then, based on the binary file, multiple assembly instruction codes corresponding to the binary file are obtained. Next, each assembly instruction code is matched with the corresponding data stream in the order of clock cycles to obtain the instruction code analysis result. The instruction code analysis result includes at least one of the number of clock cycles required for the accelerator chip to execute the assembly instruction code and the number of times the assembly instruction code is executed. In this way, by analyzing the data flow corresponding to each assembly instruction code on a clock cycle, the resulting instruction code analysis can accurately reflect the execution process of each assembly instruction code. For example, it can reflect the number of clock cycles required to execute the assembly instruction code, the number of times the assembly instruction code is executed, etc. This avoids the problem of low accuracy in the analysis results obtained when using ROC Prof to analyze the kernel functions running on the accelerator chip in traditional technology, which can only roughly reflect the execution process of various types of assembly instruction codes. The accelerator chip instruction execution analysis method provided in this application refines the analysis granularity of kernel function analysis, and the resulting instruction code analysis results are more accurate. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a flowchart illustrating an accelerator chip instruction execution analysis method in one embodiment;

[0040] Figure 2 This is a flowchart illustrating step 102 in another embodiment;

[0041] Figure 3 This is a flowchart illustrating step 103 in another embodiment;

[0042] Figure 4 This is a flowchart illustrating the visualization of instruction code analysis results in another embodiment;

[0043] Figure 5 This is a flowchart illustrating step 401 in another embodiment;

[0044] Figure 6A display interface for visualizing instruction code analysis results, as exemplified in another embodiment;

[0045] Figure 7 This is a flowchart illustrating step 501 in another embodiment;

[0046] Figure 8 A display interface for visualizing instruction code analysis results, as exemplified in another embodiment;

[0047] Figure 9 This is a structural block diagram of an accelerator chip instruction execution analysis device in one embodiment;

[0048] Figure 10 This is a flowchart illustrating the execution of the accelerator chip instruction execution analysis method by the accelerator chip instruction execution analysis device in another embodiment;

[0049] Figure 11 This is a structural block diagram of an accelerator chip instruction execution analysis device in one embodiment;

[0050] Figure 12 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0052] With the development of computer technology, high-performance computers have become widely used. High-performance computers refer to computer systems accelerated by clusters and dedicated accelerator chips. They are characterized by high computational complexity and large amounts of data processed, demanding high efficiency in computational algorithms and the efficient and rational use of system resources. Currently, in fields such as scientific computing, deep learning training and inference, which involve massive amounts of data computation, clusters and heterogeneous computing are used for acceleration. The research and optimization of heterogeneous computing applications focuses more on the effects of acceleration, performance improvement, and optimization tools and methods.

[0053] Currently, in the programming process of accelerator chips, in addition to writing the usual CPU program to control the overall logic, it is also necessary to write separate programs specifically for the accelerator chip—kernel functions. Improving the performance of kernel functions is crucial for the overall performance of the accelerator chip, and the optimization of kernel function performance relies heavily on performance analysis tools.

[0054] Therefore, to optimize the computing performance of high-performance computers, it is often necessary to study the dedicated programs of accelerator chips—kernel functions. ROC Prof (GPU performance analysis tool) is currently the performance analysis tool for the ROCCM computing platform (an open-source computing architecture from AMD). It can analyze the running status of kernel functions on accelerator chips and currently provides the display of hardware performance counters, performing statistical counting of hardware behavior during kernel function execution.

[0055] The problem with the above method is that ROC Prof can only display the running status of various instructions contained in the kernel function, and cannot refine the execution flow to the fine granularity of assembly instruction execution. Therefore, kernel function optimization based on this analysis result requires constant guessing and trial and error, which is a time-consuming and laborious task, and also requires a high level of experience from the optimization personnel. In some scenarios that pursue ultimate optimization, it is usually difficult to achieve the ideal effect, that is, the analysis result cannot accurately reflect the name and parameters of each assembly instruction code, and the accuracy is low.

[0056] In view of this, embodiments of this application provide an accelerator chip instruction execution analysis method, apparatus, device, medium, and product. This involves acquiring multiple data streams from a binary file corresponding to the target kernel function executed by the accelerator chip, then acquiring multiple assembly instruction codes corresponding to the binary file based on the binary file, and then sequentially matching each assembly instruction code with its corresponding data stream according to the clock cycle sequence to obtain an instruction code analysis result. The instruction code analysis result includes at least one of the number of clock cycles required for the accelerator chip to execute the assembly instruction code and the number of executions corresponding to the assembly instruction code. In this way, by analyzing the data flow corresponding to each assembly instruction code on a clock cycle, the resulting instruction code analysis can accurately reflect the execution process of each assembly instruction code. For example, it can reflect the number of clock cycles required to execute the assembly instruction code, the number of times the assembly instruction code is executed, etc. This avoids the problem of low accuracy in the analysis results obtained when using ROC Prof to analyze the kernel functions running on the accelerator chip in traditional technology, which can only roughly reflect the execution process of various types of assembly instruction codes. The accelerator chip instruction execution analysis method provided in this application refines the analysis granularity of kernel function analysis, and the resulting instruction code analysis results are more accurate.

[0057] This application provides an accelerator chip instruction execution analysis method, which can be applied to computer devices. The computer device can be an accelerator chip instruction execution analysis device, which can be a server or a terminal. The terminal can be, but is not limited to, various personal computers, laptops, smartphones, tablets, IoT devices, and portable wearable devices. IoT devices can be smart speakers, smart TVs, smart air conditioners, smart vehicle devices, etc. Portable wearable devices can be smartwatches, smart bracelets, head-mounted devices, etc. The server can be a standalone server or a server cluster composed of multiple servers.

[0058] In one exemplary embodiment, such as Figure 1 As shown, an accelerator chip instruction execution analysis method is provided. Taking the application of this method to a computer device as an example, the method includes steps 101 to 103.

[0059] Step 101: Obtain multiple data streams from the binary file corresponding to the target kernel function executed by the accelerator chip.

[0060] The target kernel function can be a dedicated program written for the accelerator chip. In this embodiment, the target kernel function is the kernel function to be analyzed. In this embodiment, when the computer device analyzes the running status of the target kernel function, it needs to send the target kernel function to the accelerator chip so that the accelerator chip can execute the target kernel function to obtain the running status of the target kernel function.

[0061] In one possible implementation, before the computer device sends the target kernel function to be analyzed to the accelerator chip for execution, it needs to determine whether the system environment variables in the current system conform to the preset system environment variables.

[0062] In one possible implementation of a method for a computer device to determine whether system environment variables conform to preset system environment variables, the computer device detects the system environment variables through a runtime system and matches the detected system environment variables with preset system environment variables. Optionally, if the match is successful, it indicates that the system environment variables configured in the current system support the accelerator chip to execute the target kernel function, and the computer device executes other steps of the embodiments of this application. Optionally, if the match fails, the computer device configures the system environment accordingly based on the preset system environment variables, so that the system environment variables of the current system conform to the preset system environment variables.

[0063] When the system environment variables within the system meet the preset system environment variables, for the target kernel function to be analyzed, the computer device converts the target kernel function into a file that the accelerator chip can recognize and execute, namely the binary file corresponding to the target kernel function. The computer device then sends the binary file to the accelerator chip, and the accelerator chip executes the target kernel function.

[0064] The accelerator chip can be a GPU (Graphics Processing Unit), and the computer device can send the binary file corresponding to the target kernel function to the accelerator chip through the runtime system.

[0065] The binary file contains multiple assembly instruction codes. When the accelerator chip executes the assembly instruction codes sequentially, it generates data streams corresponding to each assembly instruction code. These data streams are stored in registers on the accelerator chip. Regarding the method by which the computer device obtains these data streams, alternatively, a memory space of a preset size can be allocated, for example, 64MB. The accelerator chip and the computer device can operate on this memory space. After the accelerator chip finishes executing the binary file, it can write the data streams stored in the registers back to the memory space, allowing the computer device to obtain the data streams through this memory space. Alternatively, a buffer can be established. The accelerator chip and the computer device can operate on the buffer. When the accelerator chip executes the binary file, the corresponding data streams are stored in the registers. The accelerator chip writes the contents of the registers back to the buffer in real time, allowing the computer device to obtain the multiple data streams generated by the accelerator chip during binary file execution in real time through the buffer. Here, no restrictions are placed on the method by which the computer device obtains the data streams.

[0066] Step 102: Obtain multiple assembly instruction codes corresponding to the binary file.

[0067] Regarding the method for a computer device to obtain the assembly instruction code corresponding to a binary file, in one possible implementation, the computer device disassembles the binary file using a disassembler to obtain multiple assembly instruction codes corresponding to the binary file; optionally, the computer device obtains multiple assembly instruction codes corresponding to a binary file input from another device.

[0068] Step 103: According to the timing sequence of the clock cycle, each assembly instruction code is matched with the corresponding data stream in turn to obtain the instruction code analysis result.

[0069] When an accelerator chip executes a binary file, the data stream is generated sequentially line by line as the accelerator chip executes the assembly instruction code contained in the binary file. In one possible implementation, using clock cycles as the timing unit, the computer device matches each assembly instruction code with the sequentially generated data streams line by line according to the timing execution order to obtain the mapping relationship between each assembly instruction code and each data stream.

[0070] Computer equipment can analyze the execution process of assembly instruction codes based on the data stream corresponding to each assembly instruction code to obtain the instruction code analysis results. The instruction code analysis results include at least one of the number of clock cycles required for the accelerator chip to execute the assembly instruction code and the number of times the assembly instruction code is executed.

[0071] In one possible implementation, the computer device matches each assembly instruction code with the corresponding data stream, and then counts the number of times each executed assembly instruction code is executed.

[0072] In another possible implementation, when the computer device matches each assembly instruction code sequentially with the data stream generated in each time sequence, it can determine the clock cycle at which each assembly instruction code begins execution and the clock cycle at which execution ends. For a given assembly instruction code, the computer device can determine the number of clock cycles required for the accelerator chip to execute the assembly instruction code by taking the difference between the clock cycle at which execution ends and the clock cycle at which execution begins for that assembly instruction code.

[0073] The above-described accelerator chip instruction execution analysis method obtains multiple data streams from the binary file corresponding to the target kernel function executed by the accelerator chip. Then, based on the binary file, it obtains multiple assembly instruction codes corresponding to the binary file. Next, according to the clock cycle sequence, it sequentially matches each assembly instruction code with the corresponding data stream to obtain the instruction code analysis result. The instruction code analysis result includes at least one of the number of clock cycles required for the accelerator chip to execute the assembly instruction code and the number of times the assembly instruction code is executed. In this way, by analyzing the data flow corresponding to each assembly instruction code on a clock cycle, the resulting instruction code analysis can accurately reflect the execution process of each assembly instruction code. For example, it can reflect the number of clock cycles required to execute the assembly instruction code, the number of times the assembly instruction code is executed, etc. This avoids the problem of low accuracy in the analysis results obtained when using ROC Prof to analyze the kernel functions running on the accelerator chip in traditional technology, which can only roughly reflect the execution process of various types of assembly instruction codes. The accelerator chip instruction execution analysis method provided in this application refines the analysis granularity of kernel function analysis, and the resulting instruction code analysis results are more accurate.

[0074] In one embodiment, based on the above Figure 1 The illustrated embodiment can be found in [reference]. Figure 2 This embodiment involves the process of obtaining multiple assembly instruction codes corresponding to a binary file. For example... Figure 2 As shown, step 102 may include step 201.

[0075] Step 201: Use a performance analysis tool to disassemble the binary file to obtain multiple assembly instruction codes corresponding to the binary file.

[0076] Computer devices use performance analysis tools to analyze the operation of target kernel functions on accelerator chips. In one possible implementation, the performance analysis tool has the ability to disassemble binary files into assembly instruction code. The computer devices can use the performance analysis tool to disassemble the obtained binary files to obtain multiple assembly instruction codes corresponding to the binary files.

[0077] In this embodiment, a performance analysis tool with disassembly capabilities is used to automatically disassemble the binary file, thereby improving the efficiency of disassembly.

[0078] In one embodiment, based on the above Figure 1 The illustrated embodiment can be found in [reference]. Figure 3This embodiment involves matching each assembly instruction code with its corresponding data stream in chronological order according to the clock cycle, to obtain the instruction code analysis result. For example... Figure 3 As shown, step 103 may include steps 301 and 302.

[0079] Step 301: According to the timing sequence of the clock cycle, each assembly instruction code is matched with the corresponding data stream in turn to determine the execution start time, execution end time and execution count of the assembly instruction code.

[0080] When an accelerator chip executes a binary file, the data stream is generated sequentially line by line as the accelerator chip executes the assembly instruction code contained in the binary file. Therefore, the computer device uses clock cycles as the timing unit and matches each assembly instruction code with the sequentially generated data streams line by line according to the timing execution order. This allows the computer device to obtain the mapping relationship between each assembly instruction code and each data stream. Since the data streams are generated sequentially in timing, for a given mapping relationship, the computer device can determine the start and end times of the execution of each assembly instruction code based on the generation and end times of the data stream.

[0081] In one possible implementation, the computer device performs statistics on each mapping relationship, counts the number of repeatedly executed assembly instruction codes, and the number of repeatedly executed assembly instruction codes is the number of times the assembly instruction codes are executed.

[0082] Step 302: Determine the number of clock cycles required to execute the assembly instruction code based on the execution start time and execution end time.

[0083] In one possible implementation, for a given assembly instruction code, a computer device can determine the number of clock cycles required for the accelerator chip to execute the assembly instruction code by taking the difference between the execution start time and execution end time corresponding to the assembly instruction code.

[0084] In this embodiment, the computer device matches each assembly instruction code with each data stream sequentially according to the timing sequence, making the matching method more convenient. After the matching process, the execution start time and execution end time, the number of times the assembly instruction code is executed, and the number of clock cycles required for each assembly instruction code are determined. This allows developers to quickly identify the areas where the target kernel function needs to be optimized and improved based on the instruction code analysis results obtained in the above embodiment, thereby improving the efficiency of developers in optimizing the target kernel function.

[0085] In one embodiment, based on the above Figure 1 The illustrated embodiment can be found in [reference]. Figure 4 This embodiment relates to the process of visualizing the results of instruction code analysis. For example... Figure 4 As shown, the accelerator chip instruction execution analysis method in this embodiment may further include step 401.

[0086] Step 401: Visualize the instruction code analysis results corresponding to each assembly instruction code according to the preset display method.

[0087] In one possible implementation, in order to make the instruction code analysis results obtained in the embodiments of this application more intuitive and accurate in showing the execution status of each assembly instruction code to the user, the computer device visualizes the instruction code analysis results corresponding to each assembly instruction code according to a preset display method.

[0088] Regarding the preset display method, optionally, the computer device directly displays each assembly instruction code and its corresponding instruction code analysis results in a table format on a preset display interface; optionally, the computer device determines the calculation unit corresponding to each assembly instruction code, and then performs statistical analysis on each assembly instruction code and its corresponding instruction code according to the calculation unit, and displays the statistical results on the display interface. Here, no specific restrictions are placed on the preset display method.

[0089] During the execution of the binary file corresponding to the target kernel function, hundreds or thousands of threads on the accelerator chip execute the assembly instruction code contained in the binary file in parallel. Therefore, in order to optimize the target kernel function and improve the performance of the accelerator chip, in addition to understanding hardware performance metrics, developers also need to analyze the execution process of each assembly instruction code. Existing analysis tools cannot intuitively reflect the execution status of specific assembly instruction codes. However, in this embodiment, the computer device visualizes the instruction code analysis results corresponding to each assembly instruction code according to a preset display method, which more intuitively reflects the instruction code analysis results corresponding to each assembly instruction code. This allows developers to more intuitively and accurately determine the execution status of each assembly instruction code, thereby improving the efficiency of optimizing the target kernel function.

[0090] In one embodiment, based on the above Figure 4 The illustrated embodiment can be found in [reference]. Figure 5 This embodiment relates to the process of visually displaying the instruction code analysis results corresponding to each assembly instruction code according to a preset display method. For example... Figure 5 As shown, step 401 may include steps 501 and 502.

[0091] Step 501: Determine the instruction category to which each assembly instruction code belongs, and the computing unit in the accelerator chip corresponding to the instruction category.

[0092] Accelerator chips consist of hundreds or thousands of parallel computing units. Each computing unit can execute assembly instruction code according to the binary file received by the accelerator chip. That is, a computing unit can execute assembly instruction code of multiple instruction types, and an instruction type includes multiple assembly instruction codes.

[0093] Step 502: In the preset display interface, the analysis results of each instruction code under the instruction category are displayed in correspondence with the calculation unit identifier of the calculation unit corresponding to the instruction category.

[0094] In one possible implementation, for a computing unit, the computer device counts multiple assembly instruction codes executed by that computing unit, and then, according to the instruction category corresponding to each assembly instruction code, displays the computing unit representation of each computing unit in relation to the instruction code analysis results corresponding to the executed assembly instruction codes. For example... Figure 6 As shown, after the computer device obtains the preset query command, it displays a statistical table of the instruction code analysis results corresponding to the multiple assembly instruction codes executed by a computing unit on the preset display page. The leftmost column of the statistical table is the name of the assembly instruction code corresponding to each assembly instruction code, the middle column is the number of times each assembly instruction code is repeatedly executed, and the rightmost column is the total number of clock cycles for each assembly instruction code (the sum of the number of clock cycles required for each execution of an assembly instruction code).

[0095] In the visualization of instruction code analysis results, this embodiment not only displays the instruction code analysis results corresponding to the assembly instruction code, but also displays the instruction category and calculation unit corresponding to each assembly instruction code, providing a richer display dimension.

[0096] In one embodiment, based on the above Figure 5 The illustrated embodiment can be found in [reference]. Figure 7 This embodiment relates to the process of displaying the analysis results of each instruction code under an instruction category and the corresponding calculation unit identifier of the calculation unit of the instruction category in a preset display interface. For example... Figure 7 As shown, step 501 may include step 701.

[0097] Step 701: For each instruction category corresponding to the computing unit identifier, display the timeline control corresponding to the instruction category in the display interface according to the timing sequence of the clock cycle, so as to display the instruction code analysis results of each assembly instruction code under the instruction category.

[0098] In one possible implementation, the timeline control is used to display the data flow generated when each assembly instruction code under an instruction category is executed. For example, the timeline control can be shown as a progress bar on a timeline. The timeline represents the overall timing of the execution of the target kernel function by the accelerator chip, with clock cycles as the timing unit. The progress bar represents the execution progress of the assembly instruction codes included in an instruction category. Each progress bar can characterize the sequential relationship of the parallel logic of each assembly instruction code. The starting node of the progress bar is the execution start time corresponding to the assembly instruction code, and the ending node is the execution end time corresponding to the assembly instruction code. The length of the progress bar and the portion corresponding to the timeline can characterize the number of clock cycles required for the execution of the assembly instruction code.

[0099] In one possible implementation, if a click operation is detected on the target timeline control, the target assembly instruction code corresponding to the target timeline control is determined, and the instruction code analysis result of the target assembly instruction code is displayed in a preset position on the display interface.

[0100] In one possible implementation, when a computer device clicks on a target timeline control, the name of the target assembly instruction code corresponding to the target timeline control can be displayed on the timeline control. Then, the instruction code analysis result of the target instruction code is displayed in a preset position of the display boundary assembly surface. Optionally, the preset position can also display basic attribute information of the target assembly instruction code, such as the name of the target assembly instruction code and the corresponding calculation unit.

[0101] like Figure 8 As shown, the computer device displays the analysis results of each instruction code on a preset display interface according to the display method provided in this embodiment. The display interface has display controls arranged on the left side to display the identifier of the computing unit. See [link to relevant documentation]. Figure 8 The compute unit identifiers include SIMD0, SIMD1, SIMD2, and SIMD3. Each compute unit identifier corresponds to a set of instruction categories for the assembly instruction code included in that compute unit. These instruction categories include SALU, VALU, Memory, Branch, and WARP_END. A timeline is displayed at the top right, with timing units in clock cycles. Below the timeline are timeline controls corresponding to each instruction category included in each compute unit. See [link to relevant documentation]. Figure 8The marked timeline controls, specifically those corresponding to the SALU instruction category under the SIMD1 computation unit, reflect the timing progress of the SIMD1 computation unit executing the assembly instruction code of the SALU instruction category. The order of the timeline controls indicates the sequential relationship of the parallel logic of each assembly instruction code. Clicking on a target timeline control identifies the name of the target assembly instruction code. The instruction code analysis results and basic attribute information of the target assembly instruction code, such as its name and corresponding computation unit, are displayed in a preset position below. See [link to relevant documentation]. Figure 8 The default location displays the name (Title) of the target assembly instruction code, the start time (Start) of the target assembly instruction code, the required execution time (Wall Duration), etc.

[0102] Thus, the above embodiments introduce a method for a computer device to visually display the instruction code analysis results of each assembly instruction code on a display interface according to a preset display method, so that the instruction code analysis results can be displayed more intuitively.

[0103] In one embodiment, an exemplary accelerator chip instruction execution analysis method is provided for a computer device, the method comprising:

[0104] Step a: The computer device obtains multiple data streams from the binary file corresponding to the target kernel function executed by the accelerator chip.

[0105] Step b: The computer device uses a performance analysis tool to disassemble the binary file, obtaining multiple assembly instruction codes corresponding to the binary file.

[0106] Step c: The computer device sequentially matches each assembly instruction code with its corresponding data stream according to the clock cycle sequence to determine the execution start time, execution end time, and execution count of the assembly instruction code.

[0107] Step d: The computer device determines the number of clock cycles required to execute the assembly instruction code based on the execution start time and execution end time.

[0108] The instruction code analysis results include at least one of the following: the number of clock cycles required for the accelerator chip to execute assembly instruction code and the number of times the assembly instruction code is executed.

[0109] In step e, the computer device determines the instruction class to which each assembly instruction code belongs, and the computing unit in the accelerator chip corresponding to the instruction class.

[0110] Step f: For each instruction category corresponding to the computing unit identifier, the computer device displays the timeline control corresponding to the instruction category in the display interface according to the clock cycle sequence, so as to display the instruction code analysis results of each assembly instruction code under the instruction category.

[0111] The timeline control is used to display the clock cycles during which each assembly instruction code under the instruction category is executed.

[0112] Step g: If a click operation is detected on the target timeline control, the computer device determines the target assembly instruction code corresponding to the target timeline control and displays the instruction code analysis result of the target assembly instruction code in a preset position on the display interface.

[0113] The above-described method steps of the accelerator chip instruction execution analysis method in this application embodiment can be executed by different functional modules in a computer device. For example, see... Figure 9 The computer equipment may include performance analysis tools, a runtime system, and an accelerator chip, combined with... Figure 9 The functional modules shown illustrate the accelerator chip instruction execution analysis method:

[0114] Step 1) The performance analysis tool obtains multiple data streams from the binary file corresponding to the target kernel function executed by the accelerator chip.

[0115] Step 2) The performance analysis tool disassembles the binary file to obtain multiple assembly instruction codes corresponding to the binary file.

[0116] Step 3): The performance analysis tool matches each assembly instruction code with its corresponding data stream according to the clock cycle sequence to determine the execution start time, execution end time, and execution count of the assembly instruction code.

[0117] Step 4): The performance analysis tool determines the number of clock cycles required to execute the assembly instruction code based on the execution start time and execution end time.

[0118] The instruction code analysis results include at least one of the following: the number of clock cycles required for the accelerator chip to execute assembly instruction code and the number of times the assembly instruction code is executed.

[0119] Step 5) The performance analysis tool determines the instruction category to which each assembly instruction code belongs, and the computing unit in the accelerator chip corresponding to the instruction category.

[0120] Step 6): For each instruction category corresponding to the computing unit identifier, the performance analysis tool displays the timeline control corresponding to the instruction category in the display interface according to the timing sequence of the clock cycle, so as to display the analysis results of each assembly instruction code under the instruction category.

[0121] The timeline control is used to display the clock cycles during which each assembly instruction code under the instruction category is executed.

[0122] Step 7): If a click operation is detected on the target timeline control, the performance analysis tool determines the target assembly instruction code corresponding to the target timeline control and displays the instruction code analysis result of the target assembly instruction code in a preset position on the display interface.

[0123] In this embodiment, before the performance analysis tool obtains the multiple data streams from the binary file corresponding to the target kernel function executed by the accelerator chip, the process also involves system runtime environment configuration, target kernel function distribution, and execution. Please refer to [link to relevant documentation]. Figure 10 Based on the above-described system operating environment configuration process, target kernel function issuance, and execution process, the accelerator chip instruction execution analysis method of this application embodiment is explained as follows:

[0124] Step 1001: The performance analysis tool obtains the target kernel function and the data being executed.

[0125] Step 1002: The Runtime system configures the system environment and distributes the target kernel function.

[0126] Step 1003: The Runtime system requests memory space.

[0127] Step 1004: The accelerator chip executes the binary file of the target kernel function to generate the corresponding data stream.

[0128] Step 1005: Obtain the data stream and the binary file to be executed from the memory space.

[0129] The process of obtaining multiple data streams from the binary file corresponding to the target kernel function executed by the accelerator chip using the performance analysis tool can be found in steps 1) to 7) above, and will not be repeated here.

[0130] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0131] Based on the same inventive concept, this application also provides an accelerator chip instruction execution analysis apparatus for implementing the aforementioned accelerator chip instruction execution analysis method. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more embodiments of the accelerator chip instruction execution analysis apparatus provided below can be found in the limitations of the accelerator chip instruction execution analysis method described above, and will not be repeated here.

[0132] In one exemplary embodiment, such as Figure 11 As shown, an accelerator chip instruction execution analysis device is provided, comprising:

[0133] The first acquisition module 1101 is used to acquire multiple data streams obtained from the binary file corresponding to the target kernel function executed by the accelerator chip;

[0134] The second acquisition module 1102 is used to acquire multiple assembly instruction codes corresponding to the binary file based on the binary file;

[0135] The matching module 1103 is used to match each assembly instruction code with the corresponding data stream in the order of clock cycles to obtain the instruction code analysis result. The instruction code analysis result includes at least one of the number of clock cycles required for the accelerator chip to execute the assembly instruction code and the number of times the assembly instruction code is executed.

[0136] In one embodiment, the second acquisition module 1102 includes:

[0137] The disassembly unit is used to disassemble binary files using performance analysis tools to obtain multiple assembly instruction codes corresponding to the binary files.

[0138] In one embodiment, the matching module 1103 includes:

[0139] The matching processing unit is used to match each assembly instruction code with the corresponding data stream in the clock cycle sequence to determine the execution start time, execution end time, and execution count of the assembly instruction code.

[0140] The first determining unit is used to determine the number of clock cycles required to execute the assembly instruction code based on the execution start time and execution end time.

[0141] In one embodiment, the accelerator chip instruction execution analysis apparatus further includes:

[0142] The visualization module is used to visualize the instruction code analysis results corresponding to each assembly instruction code according to a preset display method.

[0143] In one embodiment, the visualization module includes:

[0144] The second determining unit is used to determine the instruction category to which each assembly instruction code belongs, and the computing unit in the accelerator chip corresponding to the instruction category;

[0145] The display unit is used to display the analysis results of each instruction code under the instruction category and the corresponding calculation unit identifier of the calculation unit of the instruction category in a preset display interface.

[0146] In one embodiment, the display unit is further configured to perform the following steps:

[0147] For each instruction category corresponding to the computing unit identifier, the timeline control corresponding to the instruction category is displayed in the display interface according to the timing sequence of the clock cycle, so as to display the instruction code analysis results of each assembly instruction code under the instruction category.

[0148] In one embodiment, the timeline control is used to display the clock cycles in which each assembly instruction code under the instruction category is executed, and the display unit is also used to perform the following steps:

[0149] If a click operation is detected on the target timeline control, the target assembly instruction code corresponding to the target timeline control is determined, and the instruction code analysis result of the target assembly instruction code is displayed in a preset position on the display interface.

[0150] Each module in the aforementioned accelerator chip instruction execution analysis device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware within or independently of the processor in a computer device, or stored in software within the memory of the computer device, so that the processor can call and execute the operations corresponding to each module.

[0151] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 12 As shown, this computer device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores accelerator chip operation data analysis data. The I / O interfaces are used for information exchange between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements an accelerator chip instruction execution analysis method.

[0152] Those skilled in the art will understand that Figure 12 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0153] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0154] Obtain multiple data streams from the binary file corresponding to the target kernel function executed by the accelerator chip;

[0155] Based on the binary file, obtain multiple assembly instruction codes corresponding to the binary file;

[0156] According to the timing sequence of the clock cycles, each assembly instruction code is matched with the corresponding data stream in turn to obtain the instruction code analysis result. The instruction code analysis result includes at least one of the following: the number of clock cycles required for the accelerator chip to execute the assembly instruction code and the number of times the assembly instruction code is executed.

[0157] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0158] By using performance analysis tools, the binary file is disassembled to obtain multiple assembly instruction codes corresponding to the binary file.

[0159] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0160] According to the timing sequence of the clock cycle, each assembly instruction code is matched with the corresponding data stream in turn to determine the execution start time, execution end time and execution number of the assembly instruction code.

[0161] Determine the number of clock cycles required to execute the assembly instruction code based on the execution start time and execution end time.

[0162] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0163] The analysis results of the instruction code corresponding to each assembly instruction code are displayed visually according to the preset display method.

[0164] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0165] Determine the instruction class to which each assembly instruction code belongs, and the computing unit in the accelerator chip corresponding to the instruction class;

[0166] In the preset display interface, the analysis results of each instruction code under the instruction category are displayed in correspondence with the calculation unit identifier of the calculation unit corresponding to the instruction category.

[0167] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0168] For each instruction category corresponding to the computing unit identifier, the timeline control corresponding to the instruction category is displayed in the display interface according to the timing sequence of the clock cycle, so as to display the instruction code analysis results of each assembly instruction code under the instruction category.

[0169] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0170] If a click operation is detected on the target timeline control, the target assembly instruction code corresponding to the target timeline control is determined, and the instruction code analysis result of the target assembly instruction code is displayed in a preset position on the display interface.

[0171] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0172] Obtain multiple data streams from the binary file corresponding to the target kernel function executed by the accelerator chip;

[0173] Based on the binary file, obtain multiple assembly instruction codes corresponding to the binary file;

[0174] According to the timing sequence of the clock cycles, each assembly instruction code is matched with the corresponding data stream in turn to obtain the instruction code analysis result. The instruction code analysis result includes at least one of the following: the number of clock cycles required for the accelerator chip to execute the assembly instruction code and the number of times the assembly instruction code is executed.

[0175] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0176] By using performance analysis tools, the binary file is disassembled to obtain multiple assembly instruction codes corresponding to the binary file.

[0177] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0178] According to the timing sequence of the clock cycle, each assembly instruction code is matched with the corresponding data stream in turn to determine the execution start time, execution end time and execution number of the assembly instruction code.

[0179] Determine the number of clock cycles required to execute the assembly instruction code based on the execution start time and execution end time.

[0180] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0181] The analysis results of the instruction code corresponding to each assembly instruction code are displayed visually according to the preset display method.

[0182] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0183] Determine the instruction class to which each assembly instruction code belongs, and the computing unit in the accelerator chip corresponding to the instruction class;

[0184] In the preset display interface, the analysis results of each instruction code under the instruction category are displayed in correspondence with the calculation unit identifier of the calculation unit corresponding to the instruction category.

[0185] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0186] For each instruction category corresponding to the computing unit identifier, the timeline control corresponding to the instruction category is displayed in the display interface according to the timing sequence of the clock cycle, so as to display the instruction code analysis results of each assembly instruction code under the instruction category.

[0187] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0188] If a click operation is detected on the target timeline control, the target assembly instruction code corresponding to the target timeline control is determined, and the instruction code analysis result of the target assembly instruction code is displayed in a preset position on the display interface.

[0189] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, performs the following steps:

[0190] Obtain multiple data streams from the binary file corresponding to the target kernel function executed by the accelerator chip;

[0191] Based on the binary file, obtain multiple assembly instruction codes corresponding to the binary file;

[0192] According to the timing sequence of the clock cycles, each assembly instruction code is matched with the corresponding data stream in turn to obtain the instruction code analysis result. The instruction code analysis result includes at least one of the following: the number of clock cycles required for the accelerator chip to execute the assembly instruction code and the number of times the assembly instruction code is executed.

[0193] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0194] By using performance analysis tools, the binary file is disassembled to obtain multiple assembly instruction codes corresponding to the binary file.

[0195] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0196] According to the timing sequence of the clock cycle, each assembly instruction code is matched with the corresponding data stream in turn to determine the execution start time, execution end time and execution number of the assembly instruction code.

[0197] Determine the number of clock cycles required to execute the assembly instruction code based on the execution start time and execution end time.

[0198] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0199] The analysis results of the instruction code corresponding to each assembly instruction code are displayed visually according to the preset display method.

[0200] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0201] Determine the instruction class to which each assembly instruction code belongs, and the computing unit in the accelerator chip corresponding to the instruction class;

[0202] In the preset display interface, the analysis results of each instruction code under the instruction category are displayed in correspondence with the calculation unit identifier of the calculation unit corresponding to the instruction category.

[0203] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0204] For each instruction category corresponding to the computing unit identifier, the timeline control corresponding to the instruction category is displayed in the display interface according to the timing sequence of the clock cycle, so as to display the instruction code analysis results of each assembly instruction code under the instruction category.

[0205] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0206] If a click operation is detected on the target timeline control, the target assembly instruction code corresponding to the target timeline control is determined, and the instruction code analysis result of the target assembly instruction code is displayed in a preset position on the display interface.

[0207] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0208] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0209] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0210] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for analyzing the execution of instructions in an accelerator chip, characterized in that, The method includes: The accelerator chip obtains multiple data streams from the binary file corresponding to the target kernel function. The multiple data streams are data streams generated sequentially line by line when the accelerator chip executes the assembly instruction code contained in the binary file, and data streams stored in the registers of the accelerator chip. Based on the binary file, obtain multiple assembly instruction codes corresponding to the binary file; According to the clock cycle sequence, each assembly instruction code is matched with the corresponding data stream in turn to determine the execution start clock cycle, execution end clock cycle, and actual execution count of each assembly instruction code. The difference between the execution start clock cycle and the execution end clock cycle is calculated to determine the number of clock cycles required to execute the assembly instruction code, and the instruction code analysis result corresponding to the assembly instruction code is obtained. The instruction code analysis result includes at least one of the number of clock cycles required for the accelerator chip to execute the assembly instruction code and the actual execution count of the assembly instruction code.

2. The method according to claim 1, characterized in that, The step of obtaining multiple assembly instruction codes corresponding to the binary file based on the binary file includes: The binary file is disassembled using a performance analysis tool to obtain the multiple assembly instruction codes corresponding to the binary file.

3. The method according to claim 1, characterized in that, The method further includes: Determine the instruction category to which each assembly instruction code belongs, and the computing unit in the accelerator chip corresponding to the instruction category; In the preset display interface, the analysis results of each instruction code under the instruction category are displayed in correspondence with the calculation unit identifier of the calculation unit corresponding to the instruction category.

4. The method according to claim 3, characterized in that, The step of displaying the analysis results of each instruction code under the instruction category and the corresponding calculation unit identifier of the calculation unit under the instruction category in the preset display interface includes: For each instruction category corresponding to the computing unit identifier, the timeline control corresponding to the instruction category is displayed in the display interface in the order of clock cycles, so as to display the instruction code analysis results of each assembly instruction code under the instruction category.

5. The method according to claim 4, characterized in that, The timeline control is used to display the clock cycles in which each assembly instruction code under the instruction category is executed, and the method further includes: If a click operation is detected on the target timeline control, the target assembly instruction code corresponding to the target timeline control is determined, and the instruction code analysis result of the target assembly instruction code is displayed in a preset position on the display interface.

6. The method according to claim 1, characterized in that, The method further includes: Check whether the current system environment variables conform to the preset system environment variables; If the matching fails, the system environment is configured accordingly based on the preset system environment variables until the system environment variables match the preset system environment variables.

7. An accelerator chip instruction execution analysis device, characterized in that, The device includes: The first acquisition module is used to acquire multiple data streams obtained by the accelerator chip executing the binary file corresponding to the target kernel function. The multiple data streams are data streams generated sequentially line by line when the accelerator chip executes the assembly instruction code contained in the binary file, and data streams stored in the registers of the accelerator chip. The second acquisition module is used to acquire multiple assembly instruction codes corresponding to the binary file based on the binary file; The matching module is used to sequentially match each assembly instruction code with its corresponding data stream according to the clock cycle sequence, determine the execution start clock cycle, execution end clock cycle, and actual execution count for each assembly instruction code; calculate the difference between the execution start clock cycle and the execution end clock cycle to determine the number of clock cycles required to execute the assembly instruction code, and obtain the instruction code analysis result corresponding to the assembly instruction code. The instruction code analysis result includes at least one of the number of clock cycles required for the accelerator chip to execute the assembly instruction code and the actual execution count for the assembly instruction code.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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