Memory and operating method thereof, memory system

Abstract

The embodiment of the present disclosure provides a memory and an operation method thereof, and a memory system, the memory comprises a row hammer control circuit, including a plurality of counters, each of the counters is used for counting the number of times of access of a storage row and generating a first count value; an adjustment circuit connected to the plurality of counters; the adjustment circuit is used for resetting each of the counters when the plurality of first count values all reach a target threshold value, adjusting each of the first count values by a same offset value, and generating a plurality of second count values; and the row hammer control circuit is further used for determining a target storage row according to the plurality of second count values.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a memory and its operating method, and a memory system. Background Technology

[0002] Counters are among the most commonly used logic circuits in integrated circuits. In integrated circuits, counters primarily count entries to perform functions such as measurement, counting, control, and frequency division. For example, in a row hammer control circuit addressing the row hammer effect, a counter counts the number of times a memory row is accessed. This allows the row hammer control circuit to determine the invading row based on the count results and then refresh the adjacent victim row. In some scenarios, such as the row hammer control circuit mentioned above, a large number of counters and their counting capacity are required. This leads to increased power consumption of the memory and requires a larger area, hindering memory miniaturization. Summary of the Invention

[0003] In view of the above, embodiments of the present disclosure provide a memory and its operation method, and a memory system.

[0004] According to a first aspect of this disclosure, a memory is provided, comprising:

[0005] The row hammer control circuit includes multiple counters, each counter being used to count the number of times a storage row is accessed and to generate a first count value;

[0006] An adjustment circuit is connected to the plurality of counters; the adjustment circuit is used to reset each of the counters when the plurality of first count values ​​all reach the target threshold, so as to adjust each of the first count values ​​to the same offset value and generate a plurality of second count values;

[0007] The row hammer control circuit is also used to determine the target storage row based on the plurality of second count values.

[0008] According to a second aspect of this disclosure, a memory system is provided, comprising: the memory described in any one of the first aspects of this disclosure; and,

[0009] A memory controller, connected to the memory and used to control the memory.

[0010] According to a third aspect of this disclosure, a method for operating a memory is provided, comprising:

[0011] Multiple counters are used to count the number of accesses to multiple storage rows, generating multiple first count values;

[0012] When multiple first count values ​​reach the target threshold, each counter is reset to adjust each first count value to the same offset value, thereby generating multiple second count values;

[0013] The target storage row is determined based on the plurality of second count values, and a refresh operation is performed on the adjacent storage rows of the target storage row.

[0014] The memory provided in this embodiment adds an adjustment circuit for the counters in the hammer control circuit. This adjustment circuit resets each counter when all first count values ​​reach a target threshold, adjusting each first count value by the same offset to obtain a second count value. The relationship between all second count values ​​is the same as the relationship between all first count values; therefore, the target storage row determined by multiple second count values ​​is the same as the target storage row determined by multiple first count values. It is evident that this adjustment circuit not only does not affect the hammer control circuit's determination of the target storage row, but also increases the remaining counting space of the counters after adjustment, thereby avoiding the problem of the counters getting stuck due to all count values ​​being at a high level. Furthermore, this disclosure does not require increasing the number of valid bits in the counters, i.e., it does not require increasing the number of flip-flops in the counters, saving the counter's occupied area, facilitating memory miniaturization, and reducing memory power consumption. Moreover, adding the adjustment circuit does not affect the hammer control circuit itself, other circuits in the memory, or the memory controller; therefore, this improvement has a short verification cycle and low cost. Attached Figure Description

[0015] Figure 1a A block diagram of an exemplary system with a memory provided in an embodiment of this disclosure;

[0016] Figure 1b A block diagram of yet another exemplary system with memory provided for embodiments of this disclosure;

[0017] Figure 2 A schematic diagram of the hammering effect;

[0018] Figure 3 A schematic diagram of a memory provided for an embodiment of this disclosure;

[0019] Figure 4a A schematic diagram of a hammer control circuit provided in an embodiment of this disclosure;

[0020] Figure 4b A schematic diagram of a counting circuit provided in an embodiment of this disclosure;

[0021] Figure 5 This is a schematic diagram of the operation of a counting circuit provided in an embodiment of the present disclosure;

[0022] Figure 6a and Figure 6b This is yet another schematic diagram of the operation of the counting circuit provided in the embodiments of this disclosure;

[0023] Figure 7 A schematic diagram of a memory provided for an embodiment of this disclosure;

[0024] Figure 8 The adjustment circuit provided in the embodiments of this disclosure is for Figure 6b The diagram shows the count values ​​of multiple counters before and after adjustment.

[0025] Figure 9 A schematic diagram of a counter provided in an embodiment of this disclosure;

[0026] Figure 10 A schematic diagram of a hammer control circuit and an adjustment circuit provided in an embodiment of this disclosure;

[0027] Figure 11 for Figure 10 The table shown illustrates the adjustment circuit before and after adjusting the count values ​​of multiple counters.

[0028] Figure 12 for Figure 10 The bar graph shown illustrates the adjustment circuit before and after adjusting the count values ​​of multiple counters.

[0029] Figure 13 A schematic diagram of another hammer control circuit and adjustment circuit provided in the embodiments of this disclosure;

[0030] Figure 14 for Figure 13 The table shown illustrates the adjustment circuit before and after adjusting the count values ​​of multiple counters.

[0031] Figure 15 for Figure 13 The bar graph shown illustrates the adjustment circuit before and after adjusting the count values ​​of multiple counters.

[0032] Figure 16 A schematic diagram of a hammer control circuit and an adjustment circuit provided in an embodiment of this disclosure;

[0033] Figure 17 for Figure 16 The table shown illustrates the adjustment circuit before and after adjusting the count values ​​of multiple counters.

[0034] Figure 18 for Figure 16 The bar graph shown illustrates the adjustment circuit before and after adjusting the count values ​​of multiple counters.

[0035] Figure 19A schematic diagram of a hammer control circuit and an adjustment circuit provided in an embodiment of this disclosure;

[0036] Figure 20 for Figure 19 The table shown illustrates the adjustment circuit before and after adjusting the count values ​​of multiple counters.

[0037] Figure 21 for Figure 19 The bar graph shown illustrates the adjustment circuit before and after adjusting the count values ​​of multiple counters.

[0038] Figure 22 A schematic diagram of a delay circuit provided in an embodiment of this disclosure;

[0039] Figure 23 A schematic diagram of yet another adjustment circuit provided in an embodiment of this disclosure;

[0040] Figure 24 A schematic diagram of another hammer control circuit and adjustment circuit provided in the embodiments of this disclosure;

[0041] Figure 25 for Figure 24 A schematic diagram showing the operation method of the moving hammer control circuit and adjustment circuit;

[0042] Figure 26 This is a flowchart illustrating a method for operating a memory according to an embodiment of the present disclosure. Detailed Implementation

[0043] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments. In the description of this disclosure, it should be understood that the terms "length," "width," "depth," "upper," "lower," "outer," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0044] Figure 1a and Figure 1b This is a block diagram of an exemplary system with memory provided in embodiments of this disclosure. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1aAs shown, system 100 may include a host 110 and a memory system 120, the memory system 120 having one or more memories 130 and a memory controller 140. The host 110 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The host 110 may be configured to send data to or receive data from the memory system 120.

[0045] In some embodiments, memory controller 140 is coupled to memory 130 and host 110 and is configured to control memory 130. Memory controller 140 can operate memory 130 by providing various combinations of control and address signals. For example, memory controller 140 can control memory 130 to perform read and write operations. Memory controller 140 can also control memory 130 to perform refresh operations. Memory 130 can include all types of memory that perform refresh operations to retain data stored in memory cells. For example, memory 130 can include Dynamic Random Access Memory (DRAM). Dynamic Random Access Memory includes, but is not limited to, Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM, abbreviated as DDR).

[0046] The memory 130 may include a memory cell array and peripheral circuitry coupled to the memory cell array. The memory cell array may be a DRAM memory cell array, wherein each DRAM memory cell may include a transistor and a capacitor, the gate of the transistor being connected to a word line, the source to a bit line, and the drain to a capacitor. The memory cell array includes multiple memory rows, with memory cells in each memory row coupled to the same word line, and the word line coupled to a row decoder. A column decoder is coupled to multiple memory columns via multiple bit lines.

[0047] Peripheral circuitry can be coupled to the memory cell array via word lines and bit lines. By controlling the word line voltage, the peripheral circuitry can control the switching on and off of transistors, thereby reading data stored in capacitors via bit lines or writing data to capacitors.

[0048] In some embodiments, the memory controller 140 may provide an activation command ACT, a read command RD, and a write command WT to access the memory 130. The activation command ACT is a row access command. The memory controller 140 simultaneously issues the activation command ACT and a row address signal. The memory 130 synchronously receives the activation command ACT and the row address signal, and enables the word lines of the memory cell array according to the row address signal.

[0049] The memory controller 140 can also provide a read command RD to control the memory 130 to perform a read operation, or a write command WT to control the memory 130 to perform a write operation. The column address signal is issued simultaneously with the read / write command.

[0050] For example, the memory 130 can synchronously receive a read command RD and a column address signal, and select a bit line of the memory cell array according to the column address signal, thereby performing a read operation on the data in the memory cell located at the intersection of the enabled word line and the selected bit line.

[0051] For example, memory 130 can synchronously receive write command WT and column address signal, and select the bit line of the memory cell array according to the column address signal. Memory 130 can receive data sent from memory controller 140 during write operation, and can store the received data in the memory cell located at the intersection of the enabled word line and the selected bit line.

[0052] In some embodiments, the memory controller 140 may provide a refresh command REF to control the memory 130 to perform a refresh operation. For example, the memory controller 140 provides the refresh command REF to the memory 130 at fixed intervals. One refresh command REF is valid for only one storage row, and the memory 130 can perform refresh operations on all storage rows sequentially according to the refresh command REF. In some embodiments, when performing a refresh, the memory 130 does not require externally provided row address information; the memory can automatically generate row addresses internally.

[0053] In some embodiments, such as Figure 1b As shown, the memory 130 can also be directly coupled to the host 110 and perform various operations under the control of the host 110. For example, the host 110 can replace the aforementioned memory controller by providing various combinations of control and address signals to operate the memory 130. For instance, the host provides an activation command ACT and row address information to activate a memory row, a read command RD and column address signal to perform a read operation, a write command WT and column address signal to perform a write operation, and a refresh command REF to perform a refresh operation.

[0054] In DRAM, if a memory row is accessed repeatedly during the refresh window, it can cause charge leakage in the memory cells of physically adjacent memory rows. This is known as row hammering. Figure 2 This is a schematic diagram of the hammering effect. For example... Figure 2 As shown, a storage row that is accessed repeatedly is called an aggressor row. Storage rows that are physically adjacent to an aggressor row (e.g., ...) Figure 2 In traditional Chinese databases, the two memory rows physically adjacent to the invading row are called the victim rows. Victim rows suffer charge loss due to repeated access to the invading row. If the number of accesses to the invading row reaches a certain threshold, row hammering can lead to data corruption in the victim rows.

[0055] A relatively effective method to address the row hammering effect is target row refresh (TRR). Target row refresh involves identifying the invading row and refreshing its victim row. By refreshing the victim row, the data in the victim row's memory location is preserved.

[0056] In some embodiments, the memory can track the row address signal sent by the memory controller in sync with the activation command to obtain the number of times each storage row is accessed, and then determine the storage row that is accessed the most times in a certain period of time. This most accessed row is the aggressor row (i.e., the target storage row). The memory can refresh the victim row of the aggressor row, thereby reducing the adverse effects of the row hammering effect.

[0057] Figure 3 This is a schematic diagram of a memory provided in an embodiment of the present disclosure. Figure 3 It shows Figure 1a and Figure 1b An example of memory in a system. For example... Figure 3 As shown, the memory may include a memory cell array 131 and peripheral circuits, wherein the peripheral circuits may include a control logic circuit 132, an address buffer 133, a refresh circuit 134, a row decoder 135, a column decoder 136, an I / O gating circuit 137, a data I / O buffer 138, and a row hammer control circuit 200, etc.

[0058] Address buffer 133 can receive row address signals and column address signals from memory controller 140 or host 110. Address buffer 133 can provide the received column address signals to column decoder 136 and the received row address signals to row decoder 135 and row hammer control circuit 200. Address buffer 133 receiving row address signals and control logic circuit 132 receiving activation command ACT are synchronized.

[0059] Control logic circuit 132 can receive various commands (CMD) from memory controller 140 or host 110 and generate various control signals for controlling the operation of memory 130. Specifically, command decoder 1321 in control logic circuit 132 is used to receive various commands (CMD) and generate various control signals. Control logic circuit 132 can read data from or write data to memory cell array 131, or perform other operations, by using control signals. For example, control logic circuit 132 can receive an activation command (ACT) to control row decoder 135 to activate the memory row indicated by the row address signal. Control logic circuit 132 can receive a refresh command (REF) to control refresh circuit 134 to perform a refresh operation on a memory row. Although... Figure 3 The control logic circuit 132 and address buffer 133 are shown as separate components, but they could also be a single, integrated component. Although Figure 3 The activation command ACT and the row address signal are shown as separate signals, but the row address signal can be considered to be included within the activation command ACT. Similarly, the column address signal can be considered to be included within the read command RD or the write command WT.

[0060] Row decoder 135 can decode the row address signal received from address buffer 133 to select the word line WL corresponding to the accessed row address from a plurality of word lines WL, and can connect the selected word line WL to a word line driver. Column decoder 136 can select a specific bit line BL from a plurality of bit lines BL connected to memory cell array 131. Column decoder 136 can select one bit line or, in burst mode, multiple bit lines BL.

[0061] Data I / O buffer 138 can receive data from host 110 or memory controller 140 or transfer data to host 110 or memory controller 140. I / O gating circuit 137 is connected to data I / O buffer 138. I / O gating circuit 137 can receive data from data I / O buffer 138 and write it to memory cell array 131, or read data from memory cell array 131 and transfer it to data I / O buffer 138.

[0062] The row hammer control circuit 200 can monitor the number of times a storage row is accessed and detect the row address of the target storage row that is frequently accessed during the refresh window. For example, the row hammer control circuit 200 is connected to the address buffer 133 and the refresh circuit 134. The row hammer control circuit 200 is used to receive the accessed row addresses provided by the address buffer 133, count the number of times each storage row is accessed, determine the storage row with the most accesses as the target storage row, determine the row address to be refreshed based on the target storage row, and provide the row address to be refreshed to the refresh circuit 134.

[0063] The refresh circuit 134 can respond to the refresh command REF and the row address to be refreshed provided by the row hammer control circuit 200 to perform a refresh operation on the row address to be refreshed, so as to retain the data in the storage cell of the victim row (i.e. the adjacent storage row of the target storage row), thereby weakening the adverse effects of the row hammer effect.

[0064] Figure 4a This is a schematic diagram of a hammer control circuit provided in an embodiment of this disclosure. Figure 4b This is a schematic diagram of a counting circuit provided in an embodiment of this disclosure. Figure 4a and Figure 4b As shown, the hammer control circuit 200 includes a counting circuit 220 and a counting control circuit 230.

[0065] The counting circuit 220 is connected to the address buffer 133. The counting circuit 220 includes multiple address registers 221 and multiple counters 222, with each address register 221 corresponding to one counter 222. Each address register 221 can be used to store a row address, and the counter 222 is used to count the number of times the row address in the address register 221 connected to it is accessed.

[0066] In some embodiments, after receiving the accessed row address, the counting circuit 220 can store the accessed row address in an empty address register 221 and set the count value of the counter 222 corresponding to the address register 221 to 1.

[0067] In some embodiments, the number of address registers 221 is less than the number of rows stored in the storage cell array 131; when all address registers 221 store row addresses, after the counting circuit 220 receives the accessed row address, it matches the accessed row address with the row addresses stored in all address registers 221 to obtain a matching result.

[0068] The counting control circuit 230 is connected to the counting circuit 220. When the matching result is that the accessed row address is the same as the row address stored in the first address register 221, the counting control circuit 230 is used to increment the count value of the counter 222 corresponding to the first address register 221 by 1.

[0069] When the matching result is that the row address being accessed is different from the row address stored in all address registers 221, the counting control circuit 230 replaces the row address in the second address register 221 with the row address being accessed, and increments the count value of the counter 222 corresponding to the second address register 221 by 1; the second address register 221 is the address register 221 occupied by the row address that has been accessed the least.

[0070] Here, the naming of the first address register and the second address register is for convenience only. The first address register or the second address register does not specifically refer to an address register at a certain physical location in the counting circuit. On the contrary, the first address register or the second address register can be any address register in the counting circuit. In some cases, the first address register and the second address register may be the same address register.

[0071] In some embodiments, when the matching result is that the accessed row address is the same as the row address stored in the first address register 221, the counting circuit 220 may not send the matching result to the counting control circuit 230. Instead, the counting circuit 220 itself can increment the count value of the counter 222 corresponding to the first address register 221 by 1.

[0072] In some embodiments, when the matching result is that the accessed row address and the row address stored in all address registers 221 are not the same, the counting control circuit 230 is also used to indicate (i.e. select) the second address register 221 corresponding to the row address that has been accessed the fewest times.

[0073] In some embodiments, the counting circuit 220 further includes a plurality of content-addressable memories (CAMs) 223, each CAM 223 being connected to an address register 221 and a counter 222 corresponding to that address register 221. The CAM 223 receives the accessed address, matches the accessed address with the row address stored in its corresponding address register 221 to obtain a matching result, and transmits the matching result to the counting control circuit 230. The counting control circuit 230 can be connected to a plurality of address registers 221, a plurality of CAMs 223, and a plurality of counters 222.

[0074] Figure 5 This is a schematic diagram of the operation of a counting circuit provided in an embodiment of the present disclosure. Figure 5 The table shows, from left to right, the current state of the row address stored in the address register and the counter value, the state after receiving the first activation command ACT1, the state after receiving the second activation command ACT2, and the state after executing the row hammer refresh command. For example... Figure 5 As shown, the counting circuit includes four address registers and four counters. The row address and access count stored in the four address registers and four counters in the current state are as follows: address 0XA0 has been accessed 0XA9 times, address 0XB0 has been accessed 0X80 times, address 0XC0 has been accessed 0XB1 times, and address 0XD0 has been accessed 0XCA times.

[0075] See Figure 5When the counting circuit receives the accessed row address 0XA0 synchronized with the first activation command ACT1, it determines that the address register already stores the address 0XA0. Therefore, the access count of the address 0XA0 stored in the counting circuit is increased by 1, so that the access count increases from 0XA9 to 0XAA.

[0076] See also Figure 5 When the counting circuit receives the accessed row address 0XE0 synchronized with the second activation command ACT2, it determines through matching that the accessed address 0XE0 does not match any of the currently stored row addresses in the counting circuit, and all address registers are already occupied. In this case, the address entry 0XB0 with the fewest access counts (0X80) can be evicted, and the accessed address 0XE0 can be stored in that address register, with the counter value corresponding to that address register incremented by 1. Therefore, the access count corresponding to the accessed address 0XE0 is 0X81. This is done to prevent malicious attacks by hackers. If the counter value corresponding to the address register is set to 1 immediately after the accessed address 0XE0 is stored in the address register, it would give a hacker an opportunity to maliciously attack the data of a certain stored row. For example, if a hacker wants to attack a specific memory row, they can first frequently access that memory row, making it appear frequently accessed but not the most frequently accessed among all address registers. Then, they can mask it as the least frequently accessed memory row and replace its address by sending a different memory row address. This makes the access count of the specified memory row zero. If the specified memory row is accessed again, its access count starts from zero, making it unlikely to become the most frequently accessed memory row and thus unable to be identified as the target memory row for a refresh command, resulting in data loss. To prevent malicious attacks, in the row hammer control circuit provided in this disclosure, if the address entry in the address register is replaced, its access count is not zero when the row address is accessed again, giving that row address a chance to become the most frequently accessed and be subject to a refresh command.

[0077] In some embodiments, the counting control circuit 230 is further configured to indicate the target row address that has been accessed the most times, and the row hammer control circuit 200 is further configured to determine the row address to be refreshed based on the target row address and provide the row address to be refreshed to the refresh circuit 134; wherein, the storage row corresponding to the target row address that has been accessed the most times is the target storage row, and the storage row corresponding to the row address to be refreshed is the adjacent storage row of the target storage row.

[0078] The refresh circuit 134 is connected to the command decoder 1321. The refresh circuit 134 is used to perform a refresh operation on the address of the row to be refreshed in response to the refresh command REF and the address of the row to be refreshed.

[0079] In this embodiment, the row hammer control circuit 200 indicates the target row address that has been accessed the most times and determines the row address to be refreshed. The row address to be refreshed is the row address of the adjacent storage row of the target storage row. The refresh circuit 134 responds to the refresh command REF and the row address to be refreshed and performs a refresh operation on the row address to be refreshed. This can reduce the impact of the row hammer effect on the adjacent storage rows of the target storage row (i.e., the victim row) and avoid data loss of the victim row.

[0080] In some embodiments, the row hammer control circuit 200 is used to increment and / or decrement the target row address by 1 (+1 and / or -1) to generate the row address to be refreshed, which is the row address of the adjacent storage row of the target storage row. In some embodiments, the operation of determining the row address to be refreshed from the target row address can be performed by the counting control circuit 230 or by other circuits in the row hammer control circuit. For example, the row hammer control circuit 200 may further include: an address generation circuit, which is connected to the counting control circuit 230, and is used to obtain the target row address, determine the row address to be refreshed, and transmit the row address to be refreshed to the refresh circuit 134.

[0081] It should be noted that the memory controller only provides refresh commands (REF) to the memory, without distinguishing whether the refresh command provided to the memory is a row hammer refresh command (RH REF). Based on the received refresh command (REF), the row hammer control circuit 200 inside the memory 130 will provide the row address information of the adjacent storage rows of the target storage row at regular intervals, so that the refresh circuit 134 can perform a refresh operation on the adjacent storage rows of the target storage row. This refresh operation can be considered as a row hammer refresh command (RH REF).

[0082] For refresh commands REF that are not used as row hammer refresh commands (RH REF), the memory controls the refresh circuit 134 to perform regular refresh operations based on these refresh commands REF. For example, the memory performs refresh operations on the memory rows sequentially in a certain order.

[0083] In some embodiments, the hammer control circuit 200 periodically selects a refresh command REF as the hammer refresh command RH REF. This can be understood as the hammer control circuit 200 selecting one refresh command REF as the hammer refresh command RH REF after a preset number of refresh command REF intervals. For example, the hammer control circuit 200 selects one refresh command REF as the hammer refresh command RH REF after a 7-refresh-command-REF interval. That is, with 8 refresh command REFs as a cycle, the hammer control circuit 200 selects the last refresh command REF within this cycle as the hammer refresh command RH REF.

[0084] For example, the hammer control circuit 200 may include a command counter for counting refresh commands REF. When the count value is the maximum count value of the command counter, the refresh command REF corresponding to that count value is selected as the hammer refresh command RH REF. Taking the example of selecting a refresh command REF as the hammer refresh command RH REF after every 7 refresh commands REF, the maximum count value of the command counter can be 7, and after reaching the maximum value, the count value of the command counter is reset to 0. The hammer control circuit 200 is used to determine the refresh command REF corresponding to the count value of 7 as the hammer refresh command RH REF when the count value of the command counter is 7.

[0085] In some embodiments, the counting control circuit 230 is further configured to reset the access count of the row address with the most accesses to the minimum access count among all row addresses when or after the refresh circuit 134 performs a refresh operation.

[0086] like Figure 5 As shown, the counting control circuit 230 indicates the address 0XD0 with the most accesses (0XCA), and after the refresh circuit 134 completes the refresh operation, it resets the access count of address 0XD0 to the minimum access count among all row addresses. The minimum access count among these four row addresses is 0X81, therefore the access count of address 0XD0 is reset to 0X81.

[0087] It is understandable that after performing a refresh operation on the adjacent storage rows of the target storage row, the access count of the target storage row is reset to the minimum access count. This is to avoid repeatedly specifying a storage row as the target storage row, which would prevent the adjacent storage rows of other storage rows with more access counts from being refreshed and thus avoid the adverse effects of the row hammering effect.

[0088] As described above, in this disclosure, the counting circuit 220 performs three operations: an increment operation, a replacement operation, and an additional refresh operation. The increment operation occurs when the matched row address matches a row address stored in one of the address registers, and the counter value corresponding to that address register is incremented by 1. The replacement operation occurs when the matched row address does not match any of the row addresses stored in any of the address registers, and the row address with the fewest accesses is replaced with the row address being accessed, and the counter value corresponding to that address register is incremented by 1. The additional refresh operation occurs when the refresh circuit 134 executes the row hammer refresh command RH REF, or subsequently, resetting the access count of the row address with the most accesses to the minimum access count among all row addresses.

[0089] Figure 6a and Figure 6b This is another schematic diagram of the operation of the counting circuit provided in the embodiments of this disclosure. Figure 6a The left side shows the current count values ​​of multiple counters in the counting circuit, and the right side shows the count values ​​of multiple counters after the row hammer refresh command RH REF is executed. Figure 6b The display shows the count values ​​of multiple counters at a certain moment after multiple increment, replacement, and reset operations have been performed.

[0090] like Figure 6a As shown, the counting circuit includes 8 address registers and 8 counters. The row address in the address register corresponding to counter 4 is accessed the most times; therefore, the row address in the address register corresponding to counter 4 is the row address of the target storage row. After executing the row hammer refresh command RH REF, the counting circuit performs an additional refresh operation, resetting the count value of counter 4 to the minimum value among all count values. Therefore, the count values ​​of counter 4 and counter 2 are tied for the minimum value.

[0091] See also Figure 6a and Figure 6b The additional refresh operation resets the maximum count value to the minimum count value, reducing the difference between the count values ​​of different counters. Furthermore, as the activation command (ACT) increases, the minimum count value also increases, causing all counters to have high count values, potentially leading to multiple counters freezing. One way to mitigate this problem is to increase the number of valid bits in each counter to increase the maximum count value. However, this would require more area, hindering memory miniaturization and increasing memory power consumption.

[0092] Figure 7 A schematic diagram of another type of memory provided in this disclosure embodiment, in some embodiments, such as Figure 7 As shown, the memory includes:

[0093] The row hammer control circuit 200 includes multiple counters 222, each counter 222 being used to count the number of times a storage row is accessed and to generate a first count value;

[0094] The adjustment circuit 300 is connected to multiple counters 222. When multiple first count values ​​reach the target threshold, the adjustment circuit 300 resets each counter 222 to adjust each first count value to the same offset value, thereby generating multiple second count values.

[0095] The row hammer control circuit 200 is also used to determine the target storage row based on a plurality of second count values.

[0096] In some embodiments, the target threshold can be a specific value, such as 128. Multiple first count values ​​reaching the target threshold means that each first count value is greater than or equal to the target threshold. In other embodiments, the target threshold can be a range, such as 160 to 191. Multiple first count values ​​reaching the target threshold means that each first count value is within the range indicated by the target threshold.

[0097] In this disclosure, the row hammer control circuit 200 is used to reduce the impact of the row hammer effect on adjacent memory rows of the target memory row. The row hammer control circuit 200 uses multiple counters 222 to count the number of times each accessed memory row is accessed, generating a first count value. Each memory row in the memory cell array may be an accessed memory row.

[0098] This disclosure does not limit the specific implementation of the row hammer control circuit 200 using multiple counters 222 to count the number of times a storage row is accessed. In some embodiments, the row hammer control circuit 200 may include the same number of entries and counters as the storage rows in the storage cell array to count the number of times each storage row in the storage cell array is accessed. In yet other embodiments, to avoid malicious attacks by hackers, the counting circuit 220 in the row hammer control circuit 200 shown in any of the above embodiments of this disclosure may also be used to count the number of times a storage row is accessed. That is... Figure 7 The plurality of counters 222 shown may be the plurality of counters 222 in the counting circuit 220 of any of the embodiments of the present disclosure.

[0099] In the foregoing of this disclosure, the hammer control circuit 200 determines the target storage row based on the first count values ​​of a plurality of counters 222. For example, the hammer control circuit 200 selects the storage row corresponding to the largest first count value among all the first count values ​​as the target storage row.

[0100] like Figure 6b As shown, with the continuous increase of activation commands, the first count value of the counters continuously increases, causing the first count values ​​of all counters to be in a high state, which may lead to multiple counters getting stuck. In this embodiment, an adjustment circuit 300 is set up connected to all counters 222. The adjustment circuit 300 is used to reset each counter 222 when all first count values ​​reach the target threshold, adjusting each first count value to the same offset value to generate multiple second count values. The row hammer control circuit 200 determines the target storage row based on the multiple second count values.

[0101] The target threshold can be set according to actual needs, and this disclosure does not limit the specific value of the target threshold. For example, the target threshold can be equal to half the counting capacity of the counter. For instance, if the counting capacity of an 8-bit binary counter is 256, then the target threshold could be 128. For example, the target threshold can also be equal to three-quarters of the counting capacity of the counter; for example, for an 8-bit binary counter, the target threshold could also be 192. Furthermore, the target threshold can also be greater than or equal to three-eighths of the counting capacity, and less than seven-eighths of the counting capacity. For example, for an 8-bit binary counter, the target threshold could also be between 160 and 191.

[0102] Figure 8 The adjustment circuit provided in the embodiments of this disclosure is for Figure 6b The diagram shows the first count values ​​of multiple counters before and after adjustment. For example, Figure 8 In this context, the target threshold is equal to half the counter's counting capacity. For example... Figure 8 As shown, when the first count value of each counter reaches the target threshold, the adjustment circuit resets each counter, reduces each first count value by the same offset value, and updates the reduced first count value as the second count value.

[0103] The adjustment circuit 300 reduces all first count values ​​by the same offset value, which is equivalent to folding the bar charts of all first count values ​​along the target threshold, thus hiding a segment of the bar chart. For example... Figure 8 As shown, after folding, all second count values ​​retain their original size order. In other words, the size relationship between all second count values ​​is the same as the size relationship between all first count values. Therefore, selecting the storage row corresponding to the largest second count value from all second count values ​​as the target storage row is the same as selecting the storage row corresponding to the largest first count value from all first count values. That is, the target storage row determined based on multiple second count values ​​is the same as the target storage row determined based on multiple first count values. This shows that the adjustment circuit provided in this embodiment can adjust the first count values ​​of all counters to the same offset value. Not only will it not affect the row hammer control circuit in determining the target storage row, but it can also increase the remaining counting space of the counter after adjustment, which is equivalent to a counter with infinite counting capacity. Even if the activation commands continue to increase, the probability of the counter getting stuck is greatly reduced, and it will basically not get stuck. In addition, the adjustment circuit of this embodiment does not need to increase the effective bits of the counter, that is, it does not need to increase the number of flip-flops in the counter, saving the counter's occupied area, which is conducive to the miniaturization of the memory and can reduce the power consumption of the memory.

[0104] It should be understood that the adjustment circuit 300 provided in this embodiment can be applied not only to the hammer control circuit 200, but also to other circuits that include multiple counters, to increase the remaining counting space of the counter without increasing the effective bits of the counter.

[0105] It should also be understood that the adjustment circuit 300 provided in this embodiment can be used not only to increase the remaining counting space of the adder counter, but also to increase the remaining counting space of the subtractor counter.

[0106] In some embodiments, the regulating circuit does not operate when at least one first count value is less than a target threshold. This reduces the influence of the regulating circuit on the hammer control circuit.

[0107] In some embodiments, each counter 222 includes a plurality of flip-flops, each flip-flop corresponding to a valid bit of a first count value, and the output level of the flip-flop is used to indicate the value of the valid bit.

[0108] When the values ​​of the preset valid bits among the valid bits of multiple first count values ​​are the same, the adjustment circuit is used to reset the output level of the flip-flop corresponding to the preset valid bit so as to set the value of the preset valid bit to the preset value; wherein, the first count value of resetting the preset valid bit is updated to the second count value.

[0109] Figure 9 This is a schematic diagram of a counter provided in an embodiment of the present disclosure. The counter 222 is an asynchronous adder counter. Figure 9 As shown, the counter 222 includes eight flip-flops: DFF0, DFF1, DFF2, DFF3, DFF4, DFF5, DFF6, and DFF7. These eight flip-flops form an 8-bit binary counter. The outputs of flip-flops DFF0, DFF1, DFF2, DFF3, DFF4, DFF5, DFF6, and DFF7 correspond to the significant bits Q0, Q1, Q2, Q3, Q4, Q5, Q6, and Q7 of the count value, respectively. Q7 is the most significant bit, and Q0 is the least significant bit. The count value of this binary counter 222 can be represented as Q7Q6Q5Q4Q3Q2Q1Q0, for example, 10001111.

[0110] The output level of the flip-flop is used to indicate the value of the valid bit. The output of the flip-flop can be high or low. In this embodiment and the following embodiments of this disclosure, a high output level of the flip-flop indicates that the value of the corresponding valid bit is 1, and a low output level of the flip-flop indicates that the value of the corresponding valid bit is 0. In other embodiments, a high output level of the flip-flop may indicate that the value of the corresponding valid bit is 0, and a high output level of the flip-flop may indicate that the value of the corresponding valid bit is 1.

[0111] The initial value of each valid bit can be either 0 or 1. This disclosure does not impose any limitation on this. The following embodiments illustrate the technical solution of this disclosure with the initial value of the valid bits being 0.

[0112] The preset valid bits are specified from multiple valid bits of the count value. The preset valid bits may include one or more valid bits. However, the number of valid bits in the preset valid bits is less than the total number of valid bits in the first count value. The preset valid bits may include one or more of the most significant bit, the second most significant bit, the second most significant bit, etc., among the multiple valid bits. The number and position of the valid bits included in the preset valid bits depend on the requirement for the target threshold.

[0113] In some embodiments, the preset valid bit may be the most significant bit among a plurality of valid bits of the first count value.

[0114] In other embodiments, the preset valid bits may include a plurality of valid bits sequentially set from the most significant bit to the least significant bit of the first count value; the number of valid bits in the preset valid bits is less than the number of valid bits in the first count value. For example, the preset valid bits may include the most significant bit and the second most significant bit. Also for example, the preset valid bits may include the most significant bit, the second most significant bit, and the second second most significant bit.

[0115] In some embodiments, when the preset significant bits include multiple significant bits, "the values ​​of the preset significant bits among the significant bits of multiple first count values ​​are the same" means that the values ​​of significant bits at the same position in all the preset significant bits of the first count values ​​are equal. For example, if the preset significant bits include a most significant bit and a second most significant bit, "the values ​​of the preset significant bits among the significant bits of multiple first count values ​​are the same" means that the most significant bit of all the first count values ​​is the same, and the second most significant bit of all the first count values ​​is also the same. However, the most significant bit and the second most significant bit can be the same or different. That is, when the values ​​of the preset significant bits of multiple first count values ​​are the same, the values ​​of the multiple significant bits among the preset significant bits can be different. For example, the value of the most significant bit can be 1, and the value of the second most significant bit can be 0.

[0116] It's understandable that the target threshold should be greater than the initial value. Therefore, when multiple first count values ​​have the same preset valid bit value, the preset valid bit value should also be different from the initial value of the preset valid bit. The so-called initial value of the preset valid bit means that the value of each valid bit in the preset valid bit is the initial value.

[0117] "The value of the preset significant bit is different from the initial value of the preset significant bit" can mean that at least one of the multiple significant bits of the preset significant bit has a value different from the initial value. Of course, the values ​​of all multiple significant bits of the preset significant bit can be different from the initial value.

[0118] The adjustment circuit sets the value of the preset valid bit to a preset value so that each first count value is adjusted by the same offset value. The preset value is less than a target threshold. Specifically, when the target threshold indicates a range, the preset value is less than the minimum value within that range. For example, the offset value is equal to the difference between the target threshold and the preset value.

[0119] In some embodiments, the preset value is the initial value of the preset valid bits. The initial value is the minimum preset value. In this case, the offset value is equal to the target threshold.

[0120] In some embodiments, the regulating circuit includes:

[0121] The adjustment unit has multiple input terminals connected to the output terminals of the flip-flops corresponding to the preset valid bits in multiple counters, and the output terminals of the adjustment unit are connected to the reset or set terminals of the flip-flops corresponding to the preset valid bits in multiple counters.

[0122] When the values ​​of the preset valid bits of multiple first count values ​​are the same, the adjustment unit is used to send a control signal to the reset or set terminal of the trigger corresponding to the preset bit, so as to set the value of the preset valid bit to the preset value.

[0123] In some embodiments, the reset terminal of the flip-flop is used to set the output of the flip-flop to an initial level, such as a low level, representing "0". The set terminal of the flip-flop is used to set the output of the flip-flop to a non-initial level, such as a high level, representing "1".

[0124] In some embodiments, the preset value includes "1" and "0". Therefore, the adjustment circuit can send a control signal to the reset or set terminal of the multiple flip-flops corresponding to the preset valid bit to set the value of the preset valid bit to the preset value.

[0125] In some embodiments, the preset value is the initial value of the preset valid bit; the adjustment unit is used to send a control signal to the reset terminal of the trigger corresponding to the preset bit to set the value of the preset valid bit to the initial value.

[0126] The multiple input terminals of the adjustment circuit are connected to the output terminals of preset flip-flops in multiple counters, and the output terminal of the adjustment circuit is connected to the reset terminal of the preset flip-flops in multiple counters.

[0127] In some embodiments, the adjustment unit includes:

[0128] The AND gate circuit has multiple input terminals connected to the output terminals of the flip-flops corresponding to the preset valid bits in multiple counters, and the output terminal of the AND gate circuit is connected to the reset terminal of the flip-flops corresponding to the preset valid bits in multiple counters.

[0129] Specifically, when the output levels of the flip-flops corresponding to the preset valid bits in multiple counters are the same, and the output levels of the flip-flops corresponding to each of the preset valid bits are different from the initial level, a control signal is sent to the reset terminal of the flip-flop corresponding to the preset valid bit to set the output of the flip-flop corresponding to the preset valid bit to the initial level, and the initial level indicates the initial value of the valid bit.

[0130] Here, taking an initial value of 0 as an example, "the output level of the flip-flops corresponding to the preset valid bits in multiple counters is the same, and the output level of the flip-flops corresponding to each of the preset valid bits is different from the initial level" indicates that the value of each valid bit in the preset valid bits of multiple first count values ​​is 1.

[0131] The following detailed description is based on Examples 1 and 2.

[0132] Example 1: Figure 10 This is a schematic diagram of a hammer control circuit and an adjustment circuit provided in an embodiment of the present disclosure. Figure 11 and Figure 12 They are Figure 10 The table and bar graph shown illustrate the adjustment circuit before and after adjusting the count values ​​of multiple counters. Figure 10 The counter in can be Figure 9 The counter shown. Figure 10 As shown, in this embodiment, the preset significant bit is the most significant bit of the first count value, and the most significant bit corresponds to flip-flop DFF7. The initial value of the most significant bit is 0.

[0133] In this embodiment, the adjustment circuit 300 includes an adjustment unit 310, which includes an AND gate circuit 311. Multiple inputs of the AND gate circuit 311 are connected to the outputs of all flip-flops DFF7 corresponding to the most significant bit, and the output of the AND gate circuit 311 is connected to the reset terminals of all flip-flops DFF7. The AND gate circuit 311 is used to send a control signal to the reset terminals of the flip-flops DFF7 when the outputs of all flip-flops DFF7 are set to a high level (indicating the value of the most significant bit is 1), thereby setting the outputs of all flip-flops DFF7 to a low level (indicating the value of the most significant bit is reset to 0).

[0134] Figure 11 Let's take four address registers and four counters as an example for illustration. Figure 11As shown, the row addresses and access counts stored in the four address registers and four counters in the current state are as follows: the access count of address 0XA0 is 0X8F (10001111), where the number in parentheses is the binary data corresponding to hexadecimal 0X8F; the access count of address 0XB0 is 0X7F (01111111); the access count of address 0XC0 is 0X8A (10001010); and the access count of address 0XD0 is 0X8B (10001011).

[0135] When the counting circuit receives the accessed address 0XB0 synchronized with the third activation command ACT3, the access count of address 0XB0 in the counting circuit increases by 1. Therefore, the access count increases from 0X7F to 0X80 (10000000).

[0136] When the access count of address 0XB0 becomes 0X80 (10000000), the value of the most significant bit of all counters changes from the initial value of 0 to 1. At this time, the adjustment circuit 300 resets the flip-flop DFF7 corresponding to the most significant bit, so that the value of the most significant bit of all counters becomes 0.

[0137] See also Figure 11 Before resetting trigger DFF7, the four first count values, ordered by size, are: 0X8F > 0X8B > 0X8A > 0X80. The row address of the target storage line determined by the largest of the four first count values ​​is 0XA0.

[0138] After resetting trigger DFF7, the access counts of addresses 0XA0, 0XB0, 0XC0, and 0XD0 are 0X0F (00001111), 0X00 (00000000), 0X0A (00001010), and 0X0B (00001011), respectively. These four second count values, ordered by size, are: 0X0F > 0X0B > 0X0A > 0X00. Address 0XA0 is the most accessed address; therefore, the memory row corresponding to address 0XA0 is the target memory row. Thus, resetting the counters does not change the relative sizes of all counter values; therefore, the determined target memory row remains unchanged.

[0139] Figure 12 The following explanation uses eight address registers and eight counters as an example. These eight address registers and eight counters can include... Figure 11The diagram shows four address registers and four counters. Each counter is an 8-bit binary counter with a count capacity of 256 in decimal. The most significant bit of the first count value is 1, indicating that the first count value is equal to or greater than 10,000,000. Therefore, the target threshold is 10,000,000 (corresponding to hexadecimal 0x80 and binary 128). The target threshold is half the count capacity of the counter.

[0140] The adjustment circuit 300 sets the most significant bit of each first count value to 0, which is equivalent to decreasing each first count value by 10,000,000. For example... Figure 12 The method of reducing each first count value by 10,000,000 is equivalent to folding the bar chart of the first count value along the target threshold Th to hide a segment of the bar chart. The size relationship between the multiple second count values ​​remains unchanged from the size relationship between the multiple first count values. Therefore, the adjustment circuit to adjust the counter will not affect the determination of the target storage line.

[0141] In this embodiment, the preset value of the most significant bit is the initial value, therefore the preset value is 0. The offset value is equal to the target threshold, both being 100000000.

[0142] Example 2: Figure 13 This is a schematic diagram of another hammer control circuit and adjustment circuit provided in an embodiment of the present disclosure. Figure 14 and Figure 15 They are Figure 13 The table and bar graph shown illustrate how the adjustment circuit 300 adjusts the count values ​​of multiple counters 222 before and after adjustment. Figure 13 As shown, in this embodiment, the preset valid bits include the most significant bit and the second most significant bit of the first count value, which correspond to flip-flop DFF7 and flip-flop DFF6, respectively.

[0143] The adjustment unit 310 includes an AND gate circuit 312, the multiple input terminals of the AND gate circuit 312 are respectively connected to the flip-flops DFF7 corresponding to the most significant bit and the flip-flops DFF6 corresponding to the second most significant bit, and the output terminal of the AND gate circuit 312 is connected to the reset terminal of all preset flip-flops DFF7 and DFF6.

[0144] The AND gate circuit 312 is used to send a control signal to the reset terminal of each preset flip-flop DFF7 and DFF6 when the output terminals of all preset flip-flops DFF7 and DFF6 are high (indicating that the values ​​of the most significant bit and the second most significant bit are both 1), so that the output terminals of each preset flip-flop DFF7 and DFF6 are reset to low, indicating that the values ​​of the most significant bit and the second most significant bit are both 0, that is, the initial value of the preset significant bit is 00, thus obtaining multiple second count values.

[0145] In some embodiments, AND gate circuit 312 may include an AND gate. In other embodiments, AND gate circuit 311 may include a series NAND gate and a NOT gate. The NAND gate circuit is simpler and occupies less area than the AND gate circuit; therefore, the AND gate circuit 312 composed of NAND gates and NOT gates occupies less layout area.

[0146] Figure 14 Let's take four address registers and four counters as an example for illustration. Figure 14 As shown, the row addresses and access counts stored in the four address registers and four counters in the current state are as follows: the access count of address 0XA0 is 0XDF (11011111), the access count of address 0XB0 is 0XCA (11001010), the access count of address 0XC0 is 0XBF (10111111), and the access count of address 0XD0 is 0XFB (11111011).

[0147] When the counting circuit receives the accessed address 0XC0 synchronized with the fourth activation command ACT4, the access count of address 0XC0 in the counting circuit increases by 1. Therefore, the access count increases from 0XBF to 0XC0 (11000000).

[0148] When the access count of address 0XC0 becomes 0XC0 (11000000), the values ​​of the most significant bit and the second most significant bit of all counters change from the initial value of 0 to 1. At this time, the adjustment circuit resets the flip-flops DFF7 and DFF6 corresponding to the most significant bit and the second most significant bit, so that the values ​​of the most significant bit and the second most significant bit of all counters become 0.

[0149] like Figure 14 As shown, before resetting triggers DFF7 and DFF6, the four first count values ​​are ordered by size as follows: 0XFB > 0XDF > 0XCA > 0XC0. The row address of the target storage line determined by the largest of the four first count values ​​is 0XD0.

[0150] After resetting triggers DFF7 and DFF6, the access counts of addresses 0XA0, 0XB0, 0XC0, and 0XD0 are 0X1F (00011111), 0X0A (00001010), 0X00 (00000000), and 0X3B (00111011), respectively. These four second count values, ordered by size, are: 0X3B > 0X1F > 0X0A > 0X00. Address 0XD0 is the most accessed address; therefore, the memory row corresponding to address 0XD0 is the target memory row. Thus, resetting the counters does not change the relative sizes of the counter values, and therefore, the determined target memory row remains unchanged.

[0151] Figure 15 The following explanation uses eight address registers and eight counters as an example. These eight address registers and eight counters can include... Figure 14 The diagram shows four address registers and four counters. Each counter is an 8-bit binary counter with a count capacity of 256 in decimal. The most significant bit and the second most significant bit of the first count value are both 1, indicating that the first count value is equal to or greater than 11,000,000. Therefore, the target threshold is 11,000,000 (corresponding to hexadecimal 0xC0 and binary 192). The target threshold is three-quarters of the counter's count capacity.

[0152] The adjustment circuit 300 resets the most significant bit and the second most significant bit of each first count value to 0, which is equivalent to decreasing each first count value by 11,000,000. Figure 15 The reduction of each first count value by 11,000,000 is equivalent to folding the bar chart of the first count value along the target threshold Th to hide a segment of the bar chart. The size relationship between the multiple second count values ​​remains unchanged from the size relationship between the multiple first count values. Therefore, the adjustment circuit to adjust the counter will not affect the determination of the target storage line.

[0153] In this embodiment, the preset value of the most significant bit is the initial value, therefore the preset value is 0. The offset value is equal to the target threshold, both being 110000000.

[0154] In some embodiments, the preset valid bits include a first type of valid bits and a second type of valid bits; the adjustment unit includes:

[0155] Multiple NOT gates are connected to the outputs of the flip-flops corresponding to the first type of valid bits in multiple counters.

[0156] An AND gate circuit includes multiple first input terminals and multiple second input terminals. The first input terminals are connected to the output terminals of a NOT gate circuit, the multiple second input terminals are connected to the output terminals of flip-flops corresponding to the second type of valid bits in multiple counters, and the output terminals of the AND gate circuit are connected to the reset terminals of the flip-flops corresponding to the second type of valid bits in multiple counters.

[0157] Specifically, when the output level of the flip-flop corresponding to the first type of valid bit in multiple counters is equal to the initial level, and the output level of the flip-flop corresponding to the second type of valid bit is the same but different from the initial level, the adjustment unit is used to send a control signal to the reset terminal of the flip-flop corresponding to the second type of valid bit, so that the output level of the flip-flop corresponding to the second type of valid bit is set to the initial level.

[0158] It should be understood that the output of the AND gate can also be connected to the reset terminal of the flip-flop corresponding to the first type of valid bit, so that the output of the flip-flop corresponding to the first type of valid bit also performs a reset operation. Although the input level of the flip-flop is the initial level before and after the reset, a reset operation can still be performed.

[0159] The following analysis will be conducted in conjunction with Example 3. Figure 16 This is a schematic diagram of another hammer control circuit and adjustment circuit provided in an embodiment of the present disclosure. Figure 17 and Figure 18 They are Figure 16 The table and bar graph shown illustrate the adjustment circuit before and after adjusting the count values ​​of multiple counters. Figure 16 As shown, in this embodiment, the preset valid bits include the most significant bit, the second most significant bit, and the second most significant bit of the first count value, which correspond to flip-flops DFF7, DFF6, and DFF5, respectively. The second most significant bit is a first type of valid bit, while the most significant bit and the second most significant bit are second type of valid bits.

[0160] The adjustment unit 310 includes multiple NOT gate circuits 314 and AND gate circuits 313, wherein the input terminal of each NOT gate circuit 314 is connected to the output terminal of the flip-flop DFF6 corresponding to the second most significant bit in a counter.

[0161] The multiple first input terminals of AND gate 313 are connected to the output terminals of multiple NOT gate 314, and the multiple second input terminals of AND gate 313 are connected to the flip-flop DFF7 corresponding to the most significant bit and the flip-flop DFF5 corresponding to the next most significant bit in all counters.

[0162] The adjustment unit 310 is configured to send a control signal to the reset terminal of each preset flip-flop DFF7 and DFF5 when the output terminals of all flip-flops DFF6 are low (indicating the value of the second most significant bit is 0) and the output terminals of all flip-flops DFF7 and DFF5 are high (indicating the values ​​of the most significant bit and the second most significant bit are both 1). This resets the output terminals of each preset flip-flop DFF7 and DFF5 to low (indicating the values ​​of the most significant bit and the second most significant bit are both 0). This results in the output terminals of all flip-flops DFF7, DFF6, and DFF5 being low, indicating the preset significant bit value is initially 000, thus obtaining multiple second count values.

[0163] In this embodiment, the control signal applied to the reset terminal is a reset signal, which includes a valid pulse with a high level. That is, the reset signal is active high. When the reset terminal of the flip-flop receives a high level, the flip-flop resets, thereby setting the output terminal to a low level.

[0164] The logic of AND gate 313 is that the output is set to high when all inputs are high simultaneously. Therefore, the output level of flip-flop DFF6 needs to be inverted by a NOT gate before being input to the AND gate.

[0165] In some embodiments, each NOT gate 314 may include an odd number of NOT gates (e.g., inverters), such as 1, 3, or 5, etc.

[0166] In some embodiments, such as Figure 16 As shown, the AND gate circuit 313 may include multiple AND gates 3131, 3132, 3133, and 3134, and the multiple AND gates 3131, 3132, 3133, and 3134 can form a multi-level sub-circuit. Figure 16 In this circuit, AND gates 3131, 3132, and 3133 constitute the first-level sub-circuit, and AND gate 3134 constitutes the second-level sub-circuit. The multiple inputs of AND gate 3132 include the multiple first inputs of AND gate circuit 313, the multiple inputs of AND gates 3131 and 3132 include the multiple second inputs of AND gate circuit 313, the inputs of AND gate 3134 are connected to the outputs of AND gates 3131, 3132, and 3133, and the output of AND gate 3134 is the output of AND gate circuit 313.

[0167] Figure 17 Let's take four address registers and four counters as an example for illustration. Figure 17 As shown, the row addresses and access counts stored in the four address registers and four counters in the current state are as follows: the access count of address 0XA0 is 0XA7 (10100111), the access count of address 0XB0 is 0X9F (10011111), the access count of address 0XC0 is 0XBF (10111111), and the access count of address 0XD0 is 0XBB (10111011).

[0168] When the counting circuit receives the accessed address 0XB0 synchronized with the fifth activation command ACT5, the access count of address 0XB0 in the counting circuit increases by 1. Therefore, the access count increases from 0X9F to 0XA0 (10100000).

[0169] When the access count of address 0XB0 becomes 0XA0 (10100000), the values ​​of the most significant bit, the second most significant bit, and the second most significant bit of all counters are the same, displaying as 101. At this time, the adjustment circuit resets the flip-flops DFF7 and DFF5 corresponding to the most significant bit and the second most significant bit, making the values ​​of the most significant bit, the second most significant bit, and the second most significant bit of all counters become 0.

[0170] like Figure 17As shown, before resetting triggers DFF7 and DFF5, the four first count values ​​are ordered by size as follows: 0XBF > 0XBB > 0XA7 > 0XA0. The row address of the target storage line determined by the largest of the four first count values ​​is 0XC0.

[0171] After resetting triggers DFF7 and DFF5, the access counts of addresses 0XA0, 0XB0, 0XC0, and 0XD0 are 0X07 (00000111), 0X00 (00000000), 0X1F (00011111), and 0X1B (00011011), respectively. These four second count values, ordered by size, are: 0X1F > 0X1B > 0X0A > 0X00. Address 0XB0 is the most accessed address; therefore, the memory row corresponding to address 0XB0 is the target memory row. Thus, resetting the counters does not change the relative sizes of the counter values, and therefore, the determined target memory row remains unchanged.

[0172] Figure 18 The following explanation uses eight address registers and eight counters as an example. These eight address registers and eight counters can include... Figure 17 The diagram shows four address registers and four counters. Each counter is an 8-bit binary counter with a count capacity of 256 (decimal). The most significant bit, second most significant bit, and second most significant bit of the first count value are 1, 0, and 1 respectively, indicating that the first count value should be equal to or greater than 10100000 (decimal 160) and less than 11000000 (decimal 192). Therefore, the target threshold is greater than or equal to three-eighths of the counter's count capacity and less than seven-eighths of the count capacity.

[0173] The adjustment circuit 300 sets the most significant bit and the second most significant bit corresponding to flip-flops DFF7 and DFF5 to 0, which is equivalent to decreasing each first count value by 10100000. Figure 18 The method of reducing each first count value by 10100000 is equivalent to folding the bar chart of the first count value along the target threshold Th and hiding a segment of the bar chart. The size relationship between the multiple second count values ​​remains unchanged from the size relationship between the multiple first count values. Therefore, the adjustment circuit to adjust the counter will not affect the determination of the target storage line.

[0174] Figure 19 This is a schematic diagram of another hammer control circuit and adjustment circuit provided in an embodiment of the present disclosure. Figure 20 and Figure 21 They are Figure 19The diagram shows a table and bar graph illustrating the adjustment circuit before and after adjusting the count values ​​of multiple counters. In this embodiment, the preset valid bits include the most significant bit, the second most significant bit, and the second most significant bit of the first count value, corresponding to flip-flops DFF7, DFF6, and DFF5, respectively. The second most significant bit is a first-type valid bit, while the most significant bit and the second most significant bit are second-type valid bits.

[0175] and Figure 16 Similarly, the inputs of multiple NOT gates 314 are connected to the outputs of flip-flops DFF6 corresponding to the second most significant bit in all counters; the multiple first inputs of AND gate 313 are connected to the outputs of multiple NOT gates 314, the multiple second inputs of AND gate 313 are connected to flip-flops DFF7 corresponding to the most significant bit and DFF5 corresponding to the second most significant bit in all counters; and the output of AND gate 313 is connected to the reset terminals of all flip-flops DFF7 and DFF5.

[0176] Unlike Figure 16 In this embodiment, the output of AND gate 313 is also connected to the set terminal of all flip-flops DFF6;

[0177] The adjustment unit 310 is used to send control signals to the reset terminal of each preset flip-flop DFF7 and DFF5 and the set terminal of flip-flop DFF6 when the output terminals of all flip-flops DFF6 are low (indicating that the value of the second most significant bit is 0) and the output terminals of all flip-flops DFF7 and DFF5 are high (indicating that the value of the most significant bit and the second most significant bit is 1). This causes the output terminals of each preset flip-flop DFF7 and DFF5 to be reset to low (indicating that the value of the most significant bit and the second most significant bit is 0), and the output terminal of each preset flip-flop DFF6 to be reset to high (indicating that the value of the second most significant bit is 1). This indicates that the preset value of the preset significant bit is 0, 1, 0, thus obtaining multiple second count values.

[0178] In this embodiment, the control signal applied to the set terminal is a set signal, which includes a valid pulse with a high level. That is, the set signal is active high. When the set terminal of the flip-flop receives a high level, the flip-flop is set, thereby setting the output terminal to a high level.

[0179] Figure 20 Let's take four address registers and four counters as an example. The current state of the four address registers and four counters is the same as their state after receiving the fifth activation command ACT5. Figure 17 Therefore, it is not traced back.

[0180] When the access count of address 0XB0 becomes 0XA0 (10100000), the values ​​of the most significant bit, the second most significant bit, and the second most significant bit of all counters are the same, and the preset values ​​of the significant bits are displayed as 1, 0, and 1. At this time, the adjustment unit 310 resets flip-flops DFF7, DFF6, and DFF5, so that the values ​​of the most significant bit, the second most significant bit, and the second most significant bit of all counters become 0, 1, and 0 respectively.

[0181] After resetting triggers DFF7, DFF6, and DFF5, the access counts of addresses 0XA0, 0XB0, 0XC0, and 0XD0 are 0X47 (01000111), 0X40 (01000000), 0X5F (01011111), and 0X5B (01011011). These four second count values, ordered by size, are: 0X5F > 0X5B > 0X4A > 0X40. Address 0XB0 is the most accessed address; therefore, the memory row corresponding to address 0XB0 is the target memory row. Thus, resetting the counters does not change the relative sizes of the counter values, and therefore, the determined target memory row remains unchanged.

[0182] Figure 21 The following explanation uses 8 address registers and 8 counters as an example. The adjustment unit 310 changes the values ​​of the most significant bit, the second most significant bit, and the second second most significant bit to 0, 1, and 0 respectively. This is equivalent to the difference between the offset of each first count value: 10100000 (corresponding to decimal 160) and 01000000 (corresponding to decimal 64), which is decimal 96. Figure 21 The dashed box on each counter represents the size of the offset value. When all first counter values ​​are adjusted to the same offset value (e.g., the offset value is 96), the size relationship between the multiple second counter values ​​remains unchanged, as does the size relationship between the multiple first counter values. Therefore, adjusting the counters by the adjustment circuit will not affect the determination of the target storage line.

[0183] It should be understood that in some other embodiments, the target threshold may also be seven-eighths of the counter's counting capacity. For example, if the counting capacity is 256, the target threshold may be 224. Correspondingly, the preset valid bits are the most significant bit, the second most significant bit, and the second second most significant bit. When the value of each valid bit in the preset valid bits is 1, the value of each valid bit in the preset valid bits is set to 0.

[0184] In some embodiments, such as Figure 10 , Figure 13 , Figure 16 and Figure 19 As shown, the adjustment circuit 300 also includes:

[0185] The delay unit 320 has one end connected to the output of the adjustment unit 310 and the other end connected to the reset or set terminal of the flip-flop corresponding to the preset valid bit in the plurality of counters 222. The delay unit 320 is used to extend the pulse width of the valid pulse of the control signal. In other words, the delay unit is used to extend the duration for which the output terminals of AND gates 311, 312 and 313 are set to a high level.

[0186] like Figure 10 As shown, since there are many preset flip-flops, the line length from the output of AND gate 311 to the reset terminal of each preset valid bit is not exactly the same. The flip-flop with the shorter line may reset first and set its output to low level. In this case, the input of AND gate 311 will not all be high level, causing the output of AND gate 311 to switch to low level. Consequently, the flip-flop with the longer line cannot reset and cannot reset its output to low level.

[0187] Therefore, in this embodiment, after setting the delay unit 320 at the output of AND gate 311, when the short-circuit flip-flop is reset, causing the output of AND gate 311 to switch to a low level, the delay unit 320 can delay the time for the low level to reach the reset terminal of other flip-flops, thereby extending the duration of the high level at the output of AND gate 311, that is, extending the pulse width of the effective pulse of the reset signal, and thus causing all flip-flops to be reset.

[0188] From another perspective, the delay unit 320 delays the time it takes for the signal at the output of the AND gate circuit 311 to reach the reset terminal of the flip-flop, thereby delaying the time it takes for the output of the AND gate circuit 311 to switch from a high level to a low level, which also prolongs the duration for the AND gate circuit 311 to be set to a high level.

[0189] In some embodiments, such as Figure 22 As shown, the delay unit 320 may include an even number of NOT gates 321 connected in series. For example, 2 NOT gates, 4 NOT gates, 6 NOT gates, etc. The number of NOT gates included in the delay unit 320 depends on the required duration for which the output of the AND gate circuit 311 is held high. Therefore, it can be adjusted according to actual needs.

[0190] Figure 23 This is a schematic diagram of another adjustment circuit provided in an embodiment of this disclosure. For example... Figure 23 As shown, the adjustment unit includes an AND gate circuit 315, which may include multiple sub-circuits 301 and 302. Each sub-circuit 301 and 302 includes one or more AND gate logic units (such as 3151).

[0191] In this circuit, the input terminals of multiple AND gate logic units in the first-stage sub-circuit 301 are connected to the output terminals of flip-flops DFF7 and DFF6 corresponding to the preset valid bits in multiple counters 222. The input terminals of the AND gate logic units in the next-stage sub-circuit are connected to the output terminals of the AND gate logic units in the previous-stage sub-circuit. The output terminals of the AND gate logic units in the last-stage sub-circuit 302 are connected to the reset terminals of flip-flops DFF7 and DFF6 corresponding to the preset valid bits in multiple counters 222.

[0192] For example, the adjustment circuit 300 also includes a delay unit 320, which is located between the output of the last stage sub-circuit 302 and the reset terminals of the flip-flops DFF7 and DFF6 corresponding to the preset valid bits of the multiple counters 222.

[0193] In some embodiments, in the first-level sub-circuit 301, the preset valid bits corresponding to the flip-flops connected to the input terminals of each AND gate logic unit 3151 are the same. For example... Figure 23 As shown, the first-level sub-circuit 301 includes a first AND gate logic unit 3151 and a second AND gate logic unit 3152. The first AND gate logic unit 3151 is connected to the output terminal of flip-flop DFF7, and the second AND gate logic unit 3152 is connected to the output terminal of flip-flop DFF6.

[0194] It should be understood that in other embodiments, the preset valid bits corresponding to the flip-flops connected to the input of each AND gate logic unit may also be different. The input of each AND gate logic unit may be connected to the flip-flops corresponding to all the preset valid bits of several counters 222 as close as possible.

[0195] In some embodiments, each AND gate logic unit (such as 3151) may include four inputs.

[0196] In some embodiments, each AND gate logic unit (such as 3151) may include a series of NAND gates and NOT gates.

[0197] As shown above, this embodiment adds an adjustment circuit to the counters in the row hammer control circuit. This adjustment circuit consists only of simple AND gates and NOT gates, or NAND gates and NOT gates. Although simple, the circuit is powerful, capable of folding the count values ​​of all counters, thereby increasing the counter's counting space without increasing the number of valid bits. This avoids the problem of counters getting stuck when all count values ​​are at a high level. Furthermore, the adjustment circuit does not affect the magnitude relationship between the count values ​​after folding them, thus not affecting the row hammer control circuit's determination of the target storage row, and therefore not affecting the row hammer control circuit's ability to reduce the row hammer effect on the memory cell array. In addition, adding the adjustment circuit does not affect the row hammer control circuit itself, other circuits in the memory, or the memory controller, etc. Therefore, this improvement has a short verification cycle and low cost.

[0198] Figure 24 A schematic diagram of another hammer control circuit and adjustment circuit provided in the embodiments of this disclosure; Figure 25 for Figure 24 The diagram shows the operation method of the circuit. (For example...) Figure 24 and Figure 25 As shown, when the memory receives the command CMD from the memory controller, it determines whether the command CMD is the activation command ACT.

[0199] If the command CMD is the activation command ACT, then the command decoder 1321 will transmit the accessed row address information contained in the row address information synchronized with the activation command ACT to the counting circuit 220.

[0200] After receiving the accessed row address, the counting circuit 220 matches the accessed row address with the row addresses stored in the all address register 221 to obtain the matching result.

[0201] When the matching result is that the accessed row address is the same as the row address stored in the first address register 221, the count value of the counter 222 corresponding to the first address register 221 is increased by 1; that is, an increment operation is performed.

[0202] When the matching result is that the row address being accessed is different from the row address stored in all address registers 221, the row address in the second address register 221 with the fewest accesses is replaced with the row address being accessed, and the counter 222 corresponding to the second address register 221 is incremented by 1; that is, a replacement operation is performed.

[0203] If the command CMD is not the activation command ACT, the command decoder 1321 continues to determine whether the command CMD is a refresh command REF. If it is a refresh command REF, it is provided to the horizontal hammer control circuit 200, which then further determines whether the refresh command is a horizontal hammer refresh command RH REF. The determination method is as described above and will not be repeated here.

[0204] See also Figure 24 and Figure 25 If the row hammer refresh command is RH REF, then the row hammer control circuit 200 indicates the target row address that has been accessed the most times, and determines the row address to be refreshed based on the target row address, and transmits the row address to be refreshed to the refresh circuit 134; the storage row corresponding to the row address that has been accessed the most times is the target storage row, and the storage row corresponding to the row address to be refreshed is the victim row.

[0205] When the refresh circuit 134 responds to the refresh command REF and the address of the row to be refreshed, it performs a refresh operation on the adjacent storage rows of the target storage row.

[0206] After the refresh circuit 134 completes the refresh operation on the row address to be refreshed, the counter circuit 220 resets the access count of the row address with the most accesses to the minimum access count in the all address register 221; that is, it performs an additional refresh operation.

[0207] Both the increment and replacement operations described above will increase a certain first count value. Therefore, after these two operations, the adjustment circuit 300 will determine whether the first count values ​​of all counters 222 are greater than or equal to the target threshold. For example, the adjustment circuit 300 will determine whether the most significant bit of all counters 222 is 1. When the first count values ​​of all counters 222 are greater than or equal to the target threshold, for example, when the most significant bit of all counters 222 is 1, the adjustment circuit 300 resets multiple counters 222 to obtain a second count value. When the condition that the first count values ​​of all counters 222 are greater than or equal to the target threshold is not met, the adjustment circuit 300 does not perform any operation.

[0208] It should be understood that the adjustment circuit 300 can adjust the multiple counters 222 after either of the two operations. Regardless of which operation the counting circuit 220 performs, the adjustment circuit 300 will reset the counter to obtain the second count value as long as the condition is met.

[0209] pass Figure 24 and Figure 25It can be seen that the operation of the adjustment circuit 300 on the counter 222 does not affect the counting control circuit 230 in determining the row address accessed the fewest times during the replacement operation and in determining the row address accessed the most times during the additional refresh operation. Therefore, the adjustment circuit 300 does not affect the operation of the row hammer control circuit 200.

[0210] See also Figure 24 and Figure 25 If the refresh command REF is not the row refresh command RH REF, then the refresh command REF is determined to be a regular refresh command REF. The refresh circuit 134 performs a regular refresh operation based on the regular refresh command REF. For example, the refresh circuit 134 performs refresh operations on the storage rows sequentially in a certain order.

[0211] This disclosure also provides a method for operating a memory. Figure 26 This is a flowchart illustrating a method for operating a memory according to an embodiment of this disclosure. Figure 26 As shown, the operation method includes:

[0212] S100: Use multiple counters to count the number of accesses to multiple storage rows separately, and generate multiple first count values;

[0213] S200: When multiple first count values ​​reach the target threshold, reset each counter to adjust each first count value to the same offset value and generate multiple second count values;

[0214] S300: Determine the target storage row based on multiple second count values, and perform a refresh operation on the adjacent storage rows of the target storage row.

[0215] In some embodiments, each counter includes multiple flip-flops, each flip-flop corresponding to a valid bit of a first count value, and the output level of the flip-flop is used to indicate the value of the valid bit; step S200 specifically includes:

[0216] When the values ​​of the preset valid bits among the valid bits of multiple first count values ​​are the same, the output level of the flip-flop corresponding to the preset valid bit is reset to set the value of the preset valid bit to the preset value; wherein, the first count value of resetting the preset valid bit is updated to the second count value.

[0217] In some embodiments, the preset valid bits for each first count value may include one or more valid bits.

[0218] In some embodiments, the preset valid bit may be the most significant bit among a plurality of valid bits of the first count value.

[0219] In some embodiments, the preset valid bits may include: a plurality of valid bits sequentially set from the most significant bit to the least significant bit of the first count value; the number of valid bits in the preset valid bits is less than the number of valid bits in the first count value. For example, the preset valid bits may include the most significant bit and the second most significant bit. Also for example, the preset valid bits may include the most significant bit, the second most significant bit, and the second most significant bit.

[0220] In some implementations, the memory includes an adjustment circuit, which includes an adjustment unit. Multiple input terminals of the adjustment unit are connected to the output terminals of flip-flops corresponding to preset valid bits in multiple counters. The output terminal of the adjustment unit is connected to the reset or set terminal of the flip-flops corresponding to preset valid bits in the multiple counters. Step S200 specifically includes:

[0221] When the values ​​of the preset valid bits of multiple first count values ​​are the same, a control signal is sent to the reset or set terminal of the trigger corresponding to the preset bit to set the value of the preset valid bit to the preset value.

[0222] In some embodiments, the initial value of each valid bit in the preset valid bits is 0; step S200 specifically includes:

[0223] When the value of each valid bit in the preset valid bits of the multiple first count values ​​is 1, a control signal is sent to the reset terminal of each trigger corresponding to the preset valid bit to set the value of each valid bit in the preset valid bits to 0, so that the preset valid bits are set to the initial value, and multiple second count values ​​are obtained.

[0224] In some embodiments, the output of the flip-flop is high to indicate that the value of the valid bit is 1, and the output of the flip-flop is low to indicate that the value of the valid bit is 0; the initial value of the valid bit is 0.

[0225] In some embodiments, the adjustment unit includes an AND gate circuit, wherein multiple input terminals of the AND gate circuit are respectively connected to the output terminals of flip-flops corresponding to preset valid bits in multiple counters, and the output terminal of the AND gate circuit is connected to the reset terminal of the flip-flops corresponding to preset valid bits in multiple counters; step S200 specifically includes:

[0226] When the output level of the flip-flops corresponding to the preset valid bits in multiple counters is the same, and the output level of the flip-flops corresponding to each of the preset valid bits is different from the initial level, a control signal is sent to the reset terminal of the flip-flop corresponding to the preset valid bit to set the output of the flip-flop corresponding to the preset valid bit to the initial level, and the initial level indicates the initial value.

[0227] In some embodiments, the preset valid bits include a first type of valid bits and a second type of valid bits; the adjustment unit includes: a NOT gate circuit and an AND gate circuit, wherein multiple input terminals of the NOT gate circuit are connected to the output terminals of the flip-flops corresponding to the first type of valid bits in multiple counters; the AND gate circuit includes a first input terminal and multiple second input terminals, the first input terminal is connected to the output terminal of the NOT gate circuit, the multiple second input terminals are connected to the output terminals of the flip-flops corresponding to the second type of valid bits in multiple counters, and the output terminal of the AND gate circuit is connected to the reset terminal of the flip-flops corresponding to the second type of valid bits in multiple counters; step S200 specifically includes:

[0228] When the output level of the flip-flop corresponding to the first type of valid bit in multiple counters is equal to the initial level, and the output level of the flip-flop corresponding to the second type of valid bit is the same but different from the initial level, a control signal is sent to the reset terminal of the flip-flop corresponding to the second type of valid bit so that the output level of the flip-flop corresponding to the second type of valid bit is set to the initial level.

[0229] In some embodiments, the control signal includes a valid pulse; the memory further includes a delay unit connected to the output of the adjustment unit and the reset or set terminals of triggers corresponding to multiple preset valid bits. Correspondingly, the operation method further includes:

[0230] Extend the pulse width of the effective pulse of the control signal.

[0231] In some embodiments, the control signal includes a reset signal and a set signal, and the effective pulses of the reset signal and the set signal have a high level, that is, both the reset signal and the control signal are active high. Extending the pulse width of the effective pulse of the control signal includes:

[0232] The duration for which the output of the delay adjustment unit is set to a high level.

[0233] In the memory operation method provided in this embodiment, when the first count value of multiple counters in the row hammer control circuit reaches a target threshold, the multiple counters are reset to adjust each first count value to the same offset value to obtain a second count value. The row hammer control circuit determines the target storage row based on the multiple second count values ​​and performs a refresh operation on the adjacent storage rows of the target storage row. This operation method does not affect the operation of the row hammer control circuit and can increase the remaining counting space of the counters after resetting the counters, avoiding the problem of the counters being stuck at a high level.

[0234] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory, characterized in that, include: The row hammer control circuit includes multiple counters, each counter being used to count the number of times a storage row is accessed and to generate a first count value; each counter includes multiple flip-flops, each flip-flop corresponding to a valid bit of the first count value, and the output level of the flip-flop being used to indicate the value of the valid bit; The adjustment circuit is connected to the plurality of counters; When the values ​​of the preset valid bits among the valid bits of multiple first count values ​​are the same, the adjustment circuit is used to reset the output level of the flip-flop corresponding to the preset valid bit, so as to set the value of the preset valid bit to a preset value; wherein, the first count value of resetting the preset valid bit is updated to a second count value; The row hammer control circuit is also used to determine the target storage row based on the plurality of second count values.

2. The memory according to claim 1, characterized in that, Each of the preset valid bits for the first count value includes one or more of the valid bits.

3. The memory according to claim 1, characterized in that, The preset valid bit is the highest valid bit among the multiple valid bits of the first count value; or, The preset valid bits include: a plurality of valid bits set sequentially from the most significant bit to the least significant bit of the first count value; The number of valid bits in the preset valid bits is less than the number of valid bits in the first count value.

4. The memory according to claim 1, characterized in that, The regulating circuit includes: An adjustment unit, wherein multiple input terminals of the adjustment unit are connected to the output terminals of the flip-flops corresponding to the preset valid bits in multiple counters, and the output terminals of the adjustment unit are connected to the reset or set terminals of the flip-flops corresponding to the preset valid bits in multiple counters; When multiple first count values ​​have the same preset valid bit, the adjustment unit is used to send a control signal to the reset or set terminal of the trigger corresponding to the preset valid bit, so as to set the value of the preset valid bit to a preset value.

5. The memory according to claim 4, characterized in that, The preset value is the initial value of the preset valid bit; The adjustment unit is used to send a control signal to the reset terminal of the trigger corresponding to the preset valid bit, so as to set the value of the preset valid bit to the initial value.

6. The memory according to claim 5, characterized in that, The adjustment unit includes: An AND gate circuit, wherein the multiple input terminals of the AND gate circuit are respectively connected to the output terminals of the flip-flops corresponding to the preset valid bits of the multiple counters, and the output terminal of the AND gate circuit is connected to the reset terminal of the flip-flops corresponding to the preset valid bits of the multiple counters; When the output levels of the flip-flops corresponding to the preset valid bits in the plurality of counters are the same, and the output level of the flip-flops corresponding to each of the preset valid bits is different from the initial level, the adjustment unit sends a control signal to the reset terminal of the flip-flop corresponding to the preset valid bit to set the output of the flip-flop corresponding to the preset valid bit to the initial level, wherein the initial level indicates the initial value.

7. The memory according to claim 5, characterized in that, The preset valid bits include a first type of valid bits and a second type of valid bits; the adjustment unit includes: Multiple NOT gate circuits, wherein the input terminals of the multiple NOT gate circuits are connected to the output terminals of the flip-flops corresponding to the first type of valid bits in the multiple counters; An AND gate circuit includes multiple first input terminals and multiple second input terminals. The first input terminals are connected to the output terminals of the NOT gate circuit. The multiple second input terminals are connected to the output terminals of the flip-flops corresponding to the second type of valid bits in the multiple counters. The output terminals of the AND gate circuit are connected to the reset terminals of the flip-flops corresponding to the second type of valid bits in the multiple counters. Wherein, when the output level of the flip-flop corresponding to the first type of valid bit in the plurality of counters is equal to the initial level, and the output level of the flip-flop corresponding to the second type of valid bit is the same as but different from the initial level, the adjustment unit is used to send a control signal to the reset terminal of the flip-flop corresponding to the second type of valid bit, so that the output level of the flip-flop corresponding to the second type of valid bit is set to the initial level.

8. The memory according to claim 4, characterized in that, The control signal includes a valid pulse; the adjustment circuit further includes: The delay unit has one end connected to the output terminal of the adjustment unit and the other end connected to the reset or set terminal of the trigger corresponding to the preset valid bit among the multiple counters; the delay unit is used to extend the pulse width of the valid pulse.

9. The memory according to claim 1, characterized in that, The row hammer control circuit is used to compare the plurality of second count values ​​and take the storage row corresponding to the largest count value among the plurality of second count values ​​as the target storage row; The row hammer control circuit is also used to determine the adjacent storage rows of the target storage row based on the target storage row; The memory further includes a refresh circuit connected to the row hammer control circuit, the refresh circuit being used to perform refresh operations on adjacent storage rows of the target storage row.

10. A memory system, characterized in that, include: The memory as described in any one of claims 1 to 9; as well as, A memory controller, connected to the memory and used to control the memory.

11. A method for operating a memory, characterized in that, include: Multiple counters are used to count the number of accesses to multiple storage rows, generating multiple first count values; Each counter includes multiple flip-flops, each flip-flop corresponding to a valid bit of the first count value, and the output level of the flip-flop is used to indicate the value of the valid bit. When the values ​​of the preset valid bits among the valid bits of multiple first count values ​​are the same, the output level of the flip-flop corresponding to the preset valid bit is reset to set the value of the preset valid bit to a preset value; wherein, the first count value of resetting the preset valid bit is updated to a second count value; The target storage row is determined based on the plurality of second count values, and a refresh operation is performed on the adjacent storage rows of the target storage row.

12. The method of operating the memory according to claim 11, characterized in that, Each of the preset valid bits for the first count value includes one or more of the valid bits.

13. The method of operating the memory according to claim 11, characterized in that, The preset valid bit is the highest valid bit among the multiple valid bits of the first count value; or, The preset valid bits include: a plurality of valid bits set sequentially from the most significant bit to the least significant bit of the first count value; The number of valid bits in the preset valid bits is less than the number of valid bits in the first count value.

14. The method of operating the memory according to claim 11, characterized in that, The memory includes an adjustment circuit, which includes an adjustment unit. The multiple input terminals of the adjustment unit are connected to the output terminals of the flip-flops corresponding to the preset valid bits in the multiple counters, and the output terminal of the adjustment unit is connected to the reset terminal or set terminal of the flip-flops corresponding to the preset valid bits in the multiple counters. When the values ​​of the preset valid bits among the valid bits of multiple first count values ​​are the same, resetting the output level of the flip-flop corresponding to the preset valid bit to set the value of the preset valid bit to a preset value includes: When the values ​​of the preset valid bits of the plurality of first count values ​​are the same, a control signal is sent to the reset or set terminal of the trigger corresponding to the preset valid bit to set the value of the preset valid bit to a preset value.

15. The method of operating the memory according to claim 14, characterized in that, The adjustment circuit further includes: a delay unit, one end of which is connected to the output terminal of the adjustment unit, and the other end of which is connected to the reset or set terminal of the flip-flop corresponding to the preset valid bit among the plurality of counters; the control signal includes a valid pulse; The operation method further includes: Extend the pulse width of the effective pulse of the control signal.

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