A chip design method and device, electronic equipment and storage medium

Abstract

Embodiments of the present application disclose a chip design method and device, electronic equipment and storage medium, and relate to the field of integrated circuits, which can design a chip considering 2D testing and 3D testing with high efficiency. The method comprises: obtaining original layout information of a target chip, the original layout information comprising distribution information of a first metal pattern; the first metal pattern is used to form a first metal layer of the target chip, and the first metal layer is a metal layer used to contact a test probe in a first test of the target chip; generating a first via pattern and a second metal pattern according to the original layout information, the first via pattern meeting a preset design rule; the first via pattern is used to form a first via of the target chip, and the second metal pattern is used to form a second metal layer of the target chip, wherein the second metal layer is a metal layer used to contact a test probe in a second test of the target chip; and generating a target layout of the target chip according to the first via pattern and the second metal pattern.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a chip design method and apparatus, electronic device, and storage medium. Background Technology

[0002] As advanced manufacturing processes slow down, miniaturizing chip designs becomes increasingly difficult, highlighting challenges such as yield and cost in large-chip design. To address this, more and more chips are adopting 3D integration. 3D integration stacks and bonds multiple 2D micro-dies, resulting in advantages in performance, power consumption, and area.

[0003] In the process of 3D integrated chip manufacturing, before the individual 2D dies are stacked and bonded, a series of tests can be performed on the 2D dies to eliminate defective 2D dies before 3D stacking, reducing yield loss. However, during 2D die testing, contact between the test probes and the die pads can cause pin marks on the pads, affecting the testing of the chip after 3D stacking. To address this, a double-layer aluminum process can be used. After performing 2D testing on the dies using the first layer of aluminum pads, a new dielectric layer, vias, and a second layer of aluminum pads are generated based on the first layer. This allows the second layer of aluminum pads to contact the test probes for 3D chip testing.

[0004] However, traditional EDA (Electronic Design Automation) tools do not have a corresponding rule deck for this double-layer aluminum process scenario when designing chips. Therefore, if EDA tools are used to further generate 3D vias and pads on 2D pads, not only do complex design rules need to be set, wasting a lot of time, but also, since EDA tools need to perform overall routing on the die, for dies that have already completed 2D design, a lot of work that has been completed in the early stages has to be abandoned, resulting in serious waste of resources.

[0005] There is currently no effective solution in the technology for efficiently designing chips that can accommodate both 2D and 3D testing. Summary of the Invention

[0006] In view of this, embodiments of the present invention provide a chip design method and apparatus, electronic device, and storage medium, which can design chips that can accommodate both 2D and 3D testing with high efficiency.

[0007] In a first aspect, embodiments of the present invention provide a chip design method, comprising: acquiring original layout information of a target chip, the original layout information including distribution information of a first metal pattern; the first metal pattern being used to form a first metal layer of the target chip, the first metal layer being a metal layer used to contact test probes in a first test of the target chip; generating a first via pattern and a second metal pattern according to the original layout information, the first via pattern conforming to a preset design rule; the first via pattern being used to form a first via of the target chip, the second metal pattern being used to form a second metal layer of the target chip, the first via being used to electrically connect the first metal layer and the second metal layer, wherein the second metal layer is a metal layer used to contact test probes in a second test of the target chip; and generating a target layout of the target chip according to the first via pattern and the second metal pattern.

[0008] In one embodiment, the number of the first metal patterns is at least one; generating the first via pattern and the second metal pattern according to the original layout information includes: generating the second metal pattern according to the distribution information of each of the first metal patterns, and dividing each of the first metal patterns into at least two pattern groups according to the distribution information of each of the first metal patterns; generating the first via pattern based on each of the pattern groups.

[0009] In one embodiment, dividing each first metal pattern into at least two pattern groups based on the distribution information of each first metal pattern includes: dividing the layout layer where each first metal pattern is located into at least two layout areas; for each layout area, based on the distribution information of each first metal pattern in the layout area, dividing each first metal pattern that has an electrical connection with each other into the same pattern group, and dividing each first metal pattern that has no electrical connection with each other into different pattern groups.

[0010] In one embodiment, generating the first via pattern based on each of the pattern groups includes: for each pattern group, generating at least one pre-existing via pattern according to the distribution information of each of the first metal patterns in the pattern group; checking whether the at least one pre-existing via pattern conforms to the preset design rules within its respective pattern group to obtain a first inspection result; if the first inspection result includes a non-compliant via pattern, determining the pattern group corresponding to the non-compliant via pattern as the first pattern group, determining the layout area where the first pattern group is located as the re-inspection layout area, determining the layout area adjacent to the re-inspection layout area as the adjacent layout area, and determining the pattern group in the adjacent layout area as the second pattern group; wherein, the non-compliant via pattern is the pre-existing via pattern that does not conform to the preset design rules; checking whether there is an interconnection relationship between the first pattern group and the second pattern group; if there is an interconnection relationship between the first pattern group and any of the second pattern groups, correcting the first inspection result according to the interconnection relationship to obtain a second inspection result; and determining the pre-existing via pattern that conforms to the preset design rules in the second inspection result as the first via pattern.

[0011] In one implementation, when the first inspection result includes a non-compliant via pattern, determining the pattern group corresponding to the non-compliant via pattern as a first pattern group, determining the layout area where the first pattern group is located as a re-inspection layout area, determining the layout area adjacent to the re-inspection layout area as an adjacent layout area, and determining the pattern group in the adjacent layout area as a second pattern group includes: when the first inspection result includes a non-compliant via pattern and the non-compliant via pattern is located within a first preset range of its layout area, determining the pattern group corresponding to the non-compliant via pattern as a first pattern group, determining the layout area where the first pattern group is located as a re-inspection layout area, determining the layout area adjacent to the re-inspection layout area as an adjacent layout area, and determining the pattern group within a second preset range of the adjacent layout area as a second pattern group.

[0012] In one embodiment, the ratio of the distance from a point within the first preset range to the first edge of the first layout area to the distance from the first edge of the first layout area to the second edge of the first layout area is less than a first ratio threshold, or the ratio of the distance from a point within the first preset range to the third edge of the first layout area to the distance from the third edge of the first layout area to the fourth edge of the first layout area is less than the first ratio threshold; wherein, the first layout area is the layout area where the non-compliant via pattern is located, the first layout area is a rectangle, the first edge and the second edge are two opposite sides of the rectangle, and the third edge and the fourth edge are two opposite sides of the rectangle; the ratio of the distance from a point within the second preset range to the first edge of the adjacent layout area to the distance from the first edge of the adjacent layout area to the second edge of the adjacent layout area is less than a second ratio threshold, or the ratio of the distance from a point within the second preset range to the third edge of the adjacent layout area to the distance from the third edge of the adjacent layout area to the fourth edge of the adjacent layout area is less than the second ratio threshold; wherein, the adjacent layout area is a rectangle, the first edge and the second edge are two opposite sides of the rectangle, and the third edge and the fourth edge are two opposite sides of the rectangle.

[0013] In one embodiment, when there is an interconnection relationship between the first pattern group and the second pattern group, correcting the first inspection result according to the interconnection relationship includes: taking the first pattern group and the second pattern group as a merged pattern group, determining whether the non-compliant via pattern conforms to the preset design rule within the merged pattern group; and correcting the non-compliant via pattern to the prepared via pattern that conforms to the preset design rule if the non-compliant via pattern conforms to the preset design rule within the merged pattern group.

[0014] In one embodiment, after checking whether there is an interconnection relationship between the first pattern group and the second pattern group, the method further includes: if there is no interconnection relationship between the first pattern group and the second pattern group, determining the prepared via pattern that conforms to the preset design rule in the first inspection result as the first via pattern.

[0015] In one embodiment, the original layout information further includes distribution information of a second via pattern; the second via pattern is used to form a second via of the target chip, and the second via is used to electrically connect the first metal layer to the internal circuitry of the target chip; generating the first via pattern and the second metal pattern according to the original layout information includes: generating the first via pattern and the second metal pattern according to the distribution information of the first metal pattern and the distribution information of the second via pattern.

[0016] In one embodiment, the number of the second via patterns is at least one; generating the first via pattern and the second metal pattern according to the distribution information of the first metal pattern and the distribution information of the second via pattern includes: generating the second metal pattern according to the distribution information of the first metal pattern, and generating at least one pre-existing via pattern according to the distribution information of the second via pattern, wherein the pre-existing via pattern corresponds one-to-one with the second via pattern; and obtaining the first via pattern by translating each of the pre-existing via patterns relative to the second via pattern.

[0017] In one embodiment, obtaining the first via pattern by translating the prepared via pattern relative to the second via pattern includes: determining the total number of the at least one prepared via pattern generated; performing a step-by-step translation of each prepared via pattern along each of at least one preset direction, and determining the translation efficiency of each step-by-step translation, wherein the translation efficiency is equal to the ratio of the number of prepared via patterns conforming to the preset design rules after each step-by-step translation to the number of prepared via patterns participating in this translation; among the prepared via patterns obtained in the translation operation with the highest translation efficiency, determining the prepared via patterns conforming to the preset design rules as retained patterns, and determining the prepared via patterns that do not conform to the preset design rules as retained patterns. Each of the prepared via patterns is determined as the remaining prepared via patterns; the position of the reserved pattern is fixed, and the process jumps to each of the at least one preset direction, performing a step-by-step translation of each of the prepared via patterns as a whole, and determining the translation efficiency of each step-by-step translation. The remaining prepared via patterns are then further translated step-by-step until a preset condition is met. The preset condition includes: the ratio of the cumulative number of reserved patterns to the total number of prepared via patterns is greater than a preset ratio threshold, or the number of step-by-step translations is greater than a preset number threshold. If the ratio of the cumulative number of reserved patterns to the total number of prepared via patterns is greater than the preset ratio threshold, each reserved pattern is used as the first via pattern.

[0018] In one embodiment, the method further includes prompting for manual verification if the ratio of the cumulative number of retained patterns to the total number of prepared via patterns is less than or equal to the preset ratio threshold.

[0019] In one embodiment, generating the first via pattern and the second metal pattern based on the original layout information includes: generating a pre-prepared via pattern and the second metal pattern based on the original layout information; checking whether the pre-prepared via pattern conforms to the preset design rules; and determining the pre-prepared via pattern as the first via pattern if the pre-prepared via pattern conforms to the preset design rules.

[0020] In one embodiment, the original layout information further includes the distribution information of a second via pattern; the second via pattern is used to form a second via of the target chip, and the second via is used to electrically connect the first metal layer to the internal circuitry of the target chip; the prepared via pattern is identified based on its own center point coordinates; each prepared via pattern is equal in size and has the same shape, or each prepared via pattern includes at least two categories, and each prepared via pattern in the same category is equal in size and has the same shape; checking whether the prepared via pattern conforms to the preset design rules includes at least one of the following: determining whether the spacing between each prepared via pattern conforms to the preset design rules based on the center point coordinates of each prepared via pattern; determining whether the spacing between each prepared via pattern and the second via pattern conforms to the preset design rules based on the center point coordinates of each prepared via pattern and the distribution information of the second via pattern; determining whether the relative positional relationship between each prepared via pattern and the first metal pattern conforms to the preset design rules based on the center point coordinates of each prepared via pattern and the distribution information of the first metal pattern.

[0021] In one embodiment, generating the target layout of the target chip based on the first via pattern and the second metal pattern includes: generating the target layout of the target chip based on the first via pattern, the second metal pattern, and the original layout information of the target chip.

[0022] Secondly, embodiments of the present invention also provide a chip design apparatus, comprising: an acquisition unit, configured to acquire original layout information of a target chip, the original layout information including distribution information of a first metal pattern; the first metal pattern being used to form a first metal layer of the target chip, the first metal layer being a metal layer used to contact a test probe in a first test of the target chip; a first generation unit, configured to generate a first via pattern and a second metal pattern according to the original layout information, the first via pattern conforming to a preset design rule; the first via pattern being used to form a first via of the target chip, the second metal pattern being used to form a second metal layer of the target chip, the first via being used to electrically connect the first metal layer and the second metal layer, wherein the second metal layer is a metal layer used to contact a test probe in a second test of the target chip; and a second generation unit, configured to generate a target layout of the target chip according to the first via pattern and the second metal pattern.

[0023] In one embodiment, the number of the first metal patterns is at least one; the first generation unit includes: a first generation module, configured to generate a second metal pattern according to the distribution information of each of the first metal patterns; a division module, configured to divide each of the first metal patterns into at least two pattern groups according to the distribution information of each of the first metal patterns; and a second generation module, configured to generate the first via pattern based on each of the pattern groups.

[0024] In one embodiment, the partitioning module is specifically used to: divide the layer containing each of the first metal patterns into at least two pattern areas; for each pattern area, based on the distribution information of each of the first metal patterns in the pattern area, divide the first metal patterns that are electrically connected to each other into the same pattern group, and divide the first metal patterns that are not electrically connected to each other into different pattern groups.

[0025] In one embodiment, the second generation module includes: a generation submodule, configured to generate at least one pre-prepared via pattern for each pattern group based on the distribution information of each of the first metal patterns in the pattern group; a first inspection submodule, configured to inspect whether the at least one pre-prepared via pattern conforms to the preset design rules within its respective pattern group, and obtain a first inspection result; and a first determination submodule, configured to, if the first inspection result includes a non-compliant via pattern, determine the pattern group corresponding to the non-compliant via pattern as the first pattern group, determine the layout area where the first pattern group is located as the re-inspection layout area, and determine the layout adjacent to the re-inspection layout area as the first pattern group. The region is defined as an adjacent layout region, and the pattern group in the adjacent layout region is defined as the second pattern group; wherein, the non-compliant via pattern is the prepared via pattern that does not conform to the preset design rule; a second inspection submodule is used to check whether there is an interconnection relationship between the first pattern group and the second pattern group; a correction submodule is used to correct the first inspection result according to the interconnection relationship when there is an interconnection relationship between the first pattern group and any of the second pattern groups, to obtain a second inspection result; a second determination submodule is used to determine the prepared via pattern that conforms to the preset design rule in the second inspection result as the first via pattern.

[0026] In one implementation, the first determining submodule is specifically configured to: when the first inspection result includes a non-compliant via pattern and the non-compliant via pattern is located within a first preset range of its respective layout area, determine the pattern group corresponding to the non-compliant via pattern as a first pattern group, determine the layout area where the first pattern group is located as a re-inspection layout area, determine the layout area adjacent to the re-inspection layout area as an adjacent layout area, and determine the pattern group within a second preset range of the adjacent layout area as a second pattern group.

[0027] In one embodiment, the ratio of the distance from a point within the first preset range to the first edge of the first layout area to the distance from the first edge of the first layout area to the second edge of the first layout area is less than a first ratio threshold, or the ratio of the distance from a point within the first preset range to the third edge of the first layout area to the distance from the third edge of the first layout area to the fourth edge of the first layout area is less than the first ratio threshold; wherein, the first layout area is the layout area where the non-compliant via pattern is located, the first layout area is a rectangle, the first edge and the second edge are two opposite sides of the rectangle, and the third edge and the fourth edge are two opposite sides of the rectangle; the ratio of the distance from a point within the second preset range to the first edge of the adjacent layout area to the distance from the first edge of the adjacent layout area to the second edge of the adjacent layout area is less than a second ratio threshold, or the ratio of the distance from a point within the second preset range to the third edge of the adjacent layout area to the distance from the third edge of the adjacent layout area to the fourth edge of the adjacent layout area is less than the second ratio threshold; wherein, the adjacent layout area is a rectangle, the first edge and the second edge are two opposite sides of the rectangle, and the third edge and the fourth edge are two opposite sides of the rectangle.

[0028] In one embodiment, the correction submodule is specifically configured to: combine the first pattern group and the second pattern group as a merged pattern group; determine whether the non-compliant via pattern conforms to the preset design rule within the merged pattern group; and, if the non-compliant via pattern conforms to the preset design rule within the merged pattern group, correct the non-compliant via pattern to the prepared via pattern that conforms to the preset design rule.

[0029] In one embodiment, the second generation module further includes a third determining submodule, configured to determine the prepared via pattern that conforms to the preset design rules in the first inspection result as the first via pattern when there is no interconnection relationship between the first pattern group and the second pattern group.

[0030] In one embodiment, the original layout information further includes the distribution information of a second via pattern; the second via pattern is used to form a second via of the target chip, and the second via is used to electrically connect the first metal layer to the internal circuit of the target chip; the first generation unit is specifically used to generate the first via pattern and the second metal pattern according to the distribution information of the first metal pattern and the distribution information of the second via pattern.

[0031] In one embodiment, the number of the second via patterns is at least one; the first generation unit includes: a third generation module, configured to generate the second metal pattern according to the distribution information of the first metal pattern, and generate at least one pre-existing via pattern according to the distribution information of the second via pattern, wherein the pre-existing via pattern corresponds one-to-one with the second via pattern; and a translation module, configured to obtain the first via pattern by translating each of the pre-existing via patterns relative to the second via pattern.

[0032] In one embodiment, the translation module includes: a fourth determining submodule, configured to determine the total number of the at least one pre-selected via patterns generated; a translation submodule, configured to perform step-by-step translation of each of the pre-selected via patterns along each of at least one preset direction, and determine the translation efficiency of each step-by-step translation, wherein the translation efficiency is equal to the ratio of the number of pre-selected via patterns conforming to the preset design rules after each step-by-step translation to the number of pre-selected via patterns participating in this translation; and a fifth determining submodule, configured to determine the pre-selected via patterns conforming to the preset design rules as retained patterns from the pre-selected via patterns obtained in the translation operation with the highest translation efficiency, and to determine the remaining pre-selected via patterns as retained patterns. Each of the prepared via patterns conforming to the preset design rules is determined as the remaining prepared via patterns; a fixing submodule is used to fix the position of the reserved patterns; a triggering submodule is used to trigger the translation submodule to continue to perform step-by-step translation on the remaining prepared via patterns until a preset condition is met, the preset condition including: the ratio of the cumulative number of reserved patterns to the total number of prepared via patterns is greater than a preset ratio threshold, or the number of step-by-step translations is greater than a preset number threshold; a sixth determining submodule is used to determine each reserved pattern as each of the first via patterns when the ratio of the cumulative number of reserved patterns to the total number of prepared via patterns is greater than the preset ratio threshold.

[0033] In one embodiment, the translation module further includes a prompting submodule, used to prompt for manual verification when the ratio of the cumulative number of retained patterns to the total number of prepared via patterns is less than or equal to the preset ratio threshold.

[0034] In one embodiment, the first generation unit includes: a fourth generation module, configured to generate a pre-via pattern and a second metal pattern based on the original layout information; a checking module, configured to check whether the pre-via pattern conforms to the preset design rules; and a determining module, configured to determine the pre-via pattern as the first via pattern if the pre-via pattern conforms to the preset design rules.

[0035] In one embodiment, the original layout information further includes the distribution information of the second via pattern; the second via pattern is used to form the second via of the target chip, and the second via is used to electrically connect the first metal layer to the internal circuit of the target chip; the prepared via pattern is identified based on its own center point coordinates; each prepared via pattern is equal in size and has the same shape, or each prepared via pattern includes at least two categories, and each prepared via pattern in the same category is equal in size and has the same shape; the inspection module is specifically used for at least one of the following: determining whether the spacing between each prepared via pattern conforms to the preset design rule based on the center point coordinates of each prepared via pattern; determining whether the spacing between each prepared via pattern and the second via pattern conforms to the preset design rule based on the center point coordinates of each prepared via pattern and the distribution information of the second via pattern; determining whether the relative positional relationship between each prepared via pattern and the first metal pattern serves the preset design rule based on the center point coordinates of each prepared via pattern and the distribution information of the first metal pattern.

[0036] In one embodiment, the second generation unit is specifically used to: generate a target layout of the target chip based on the first via pattern, the second metal pattern, and the original layout information of the target chip.

[0037] Thirdly, embodiments of the present invention also provide an electronic device, the electronic device comprising: a processor and a memory, the processor being electrically connected to the memory; the memory being used to store executable program code; the processor running a program corresponding to the executable program code by reading the executable program code stored in the memory, thereby implementing any chip design method provided by embodiments of the present invention.

[0038] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing one or more programs that can be executed by one or more processors to implement the chip design method provided in any embodiment of the present invention.

[0039] The chip design method, apparatus, electronic device, and computer-readable storage medium provided in the embodiments of the present invention can acquire the original layout information of a target chip, generate a first via pattern and a second metal pattern based on the original layout information, wherein the first via pattern conforms to preset design rules; and generate the target layout of the target chip based on the first via pattern and the second metal pattern. In this way, the first via pattern and the second metal pattern can be directly generated based on the original layout information of the target chip, thereby electrically connecting the first metal layer and the second metal layer through the first via. A first test is completed by contacting the test probe through the first metal layer, and a second test is completed by contacting the test probe through the second metal layer. Since no EDA tools are required to participate in the generation of the first via pattern and the second metal pattern, there is no need to set up a complex rule base for the EDA tools, and the already completed 2D chip design work is not forced to be abandoned and re-routed. Therefore, chips that can accommodate both 2D and 3D testing can be designed with high efficiency. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 A flowchart of a chip design method provided for an embodiment of the present invention; Figure 2 This is a schematic diagram of a pattern group in an embodiment of the present invention; Figure 3 This is a schematic diagram of a first preset range in an embodiment of the present invention; Figure 4 This is a schematic diagram of a second preset range in an embodiment of the present invention; Figure 5 This is a schematic diagram illustrating the translation of a pre-prepared via pattern in an embodiment of the present invention; Figure 6 A detailed flowchart of a chip design method provided for embodiments of the present invention; Figure 7 A schematic diagram of a chip design apparatus provided for an embodiment of the present invention; Figure 8 A schematic diagram of an electronic device provided as an embodiment of the present invention. Detailed Implementation

[0042] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0043] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0044] Embodiments of the present invention provide a chip that can be designed with high efficiency to accommodate both 2D and 3D testing.

[0045] like Figure 1 As shown, an embodiment of the present invention provides a chip design method, including: S11. Obtain the original layout information of the target chip, the original layout information including the distribution information of the first metal pattern; the first metal pattern is used to form the first metal layer of the target chip, the first metal layer is the metal layer used to contact the test probe in the first test of the target chip; In embodiments of the present invention, the target chip may refer to a chip whose layout design has been partially completed and requires further refinement. The original layout may be the completed layout design of the target chip. The original layout information may include all or part of the information contained in the original layout.

[0046] In one embodiment of the present invention, the original layout information may include distribution information of a first metal pattern, wherein the first metal pattern may be a pattern of one layer in the original layout. In semiconductor processing, the first metal pattern may be used to manufacture a first metal layer of the target chip, thereby transferring the first metal pattern in the layout onto the first metal layer of the target chip. In an embodiment of the present invention, the first metal layer may be a metal layer in the target chip, and the first metal layer may contact a test probe to perform a first test on the target chip, wherein the first test may be, for example, a test performed on a 2D die by a probe. The first metal layer may include various metal materials; for example, in one embodiment of the present invention, the first metal layer may include aluminum.

[0047] S12. Generate a first via pattern and a second metal pattern according to the original layout information. The first via pattern conforms to a preset design rule. The first via pattern is used to form a first via of the target chip. The second metal pattern is used to form a second metal layer of the target chip. The first via is used to electrically connect the first metal layer and the second metal layer. The second metal layer is a metal layer used to contact the test probe in the second test of the target chip. After obtaining the original layout information of the target chip, in this step, a first via pattern and a second metal pattern can be generated based on the original layout information. The first via pattern can be a layout pattern used to form the first via of the target chip. The first via can be formed, for example, by etching the via in a dielectric layer and placing a conductive material in the via. The second metal pattern can be another layout pattern used to form the second metal layer of the target chip. The second metal layer can contact a test probe to perform a second test on the target chip. The second test can be, for example, a test performed on a 3D die using a probe. The second metal layer can include various metal materials; for example, in one embodiment of the present invention, the second metal layer can include aluminum. In one embodiment of the present invention, after obtaining the distribution information of the first metal pattern, the first via pattern can be generated based on the distribution information of the first metal pattern. For example, the first via pattern can be generated within the projection coverage area of ​​the first metal pattern. The first via pattern conforms to a preset design rule, so that the first via generated by the first via pattern can be electrically connected to the first metal layer generated by the first metal pattern.

[0048] The first via pattern conforms to a preset design rule. This preset design rule can include rules related to processing requirements (such as width, spacing, etc.) or rules related to electrical interconnection (such as being electrically connected to A, but not electrically connected to B, etc.). The embodiments of the present invention do not limit this.

[0049] S13. Generate the target layout of the target chip based on the first via pattern and the second metal pattern.

[0050] After obtaining the first via pattern and the second metal pattern, this step involves generating the target layout of the target chip based on the first via pattern and the second metal pattern. The target layout can be used to fabricate a chip that supports both 2D and 3D testing.

[0051] The chip design method provided by the embodiments of the present invention can obtain the original layout information of the target chip, generate a first via pattern and a second metal pattern based on the original layout information, wherein the first via pattern conforms to preset design rules; and generate the target layout of the target chip based on the first via pattern and the second metal pattern. In this way, the first via pattern and the second metal pattern can be directly generated based on the original layout information of the target chip, thereby electrically connecting the first metal layer and the second metal layer through the first via. A first test is completed by contacting the test probe through the first metal layer, and a second test is completed by contacting the test probe through the second metal layer. Since no EDA tools are required to participate in the generation of the first via pattern and the second metal pattern, there is no need to set up a complex rule base for the EDA tools, and the already completed 2D chip design work is not forced to be abandoned and the entire routing is redone. Therefore, a chip that can accommodate both 2D and 3D testing can be designed with high efficiency.

[0052] Specifically, in one embodiment of the present invention, the number of first metal patterns can be at least one. Based on this, step S12, generating the first via pattern and the second metal pattern according to the original layout information, can specifically include: generating the second metal pattern according to the distribution information of each of the first metal patterns, and dividing each of the first metal patterns into at least two pattern groups according to the distribution information of each of the first metal patterns; generating the first via pattern based on each of the pattern groups. That is to say, in the embodiments of the present invention, at least two operations can be performed using the distribution information of each of the first metal patterns: firstly, the second metal pattern can be generated according to the distribution information of each of the first metal patterns; secondly, each of the first metal patterns can be divided into two or more pattern groups according to the distribution information of each of the first metal patterns, and the first via pattern can be further generated based on each pattern group.

[0053] In one embodiment of the present invention, when generating a second metal pattern based on the distribution information of each first metal pattern, the shape and number of the second metal pattern can be the same as the shape and number of the first metal patterns, and the distribution position of the second metal pattern can also be aligned with the distribution position of the first metal pattern. Thus, the second metal layer made using the second metal pattern has the same structure as the first metal layer made using the first metal pattern. After the first metal layer contacts the test probe and performs a first test, the second metal layer can replace the first metal layer, contact the test probe, and perform a second test.

[0054] In one embodiment, dividing the first metal pattern into at least two pattern groups based on the distribution information of each first metal pattern may include: dividing the layer containing each first metal pattern into at least two layout areas; and for each layout area, dividing the first metal patterns that are electrically connected to each other into the same pattern group, and dividing the first metal patterns that are not electrically connected to each other into different pattern groups, based on the distribution information of each first metal pattern in that layout area.

[0055] In this embodiment, the shape and size of each divided map region can be the same or different, and the embodiments of the present invention do not limit this. For ease of processing, in one embodiment of the present invention, the map layer containing each of the first metal patterns can be divided into at least two map regions, each map region being of equal size and the same shape, for example, all being rectangles. The number of map regions can be set and adjusted as needed; for example, in one example, the number of map regions can be 500 to 2000. After obtaining each map region, for each map region, based on the distribution information of each of the first metal patterns in the map region, the first metal patterns that have an electrical connection with each other can be divided into the same pattern group, and the first metal patterns that do not have an electrical connection with each other can be divided into different pattern groups. For example, in one example, for each map region, the vertex coordinates of each of the first metal patterns in the map region can be obtained, thereby determining whether different first metal patterns in the map region overlap and whether different first metal patterns have an electrical connection based on the vertex coordinates, so as to obtain the corresponding pattern group.

[0056] After obtaining the pattern groups, a first via pattern can be generated based on each pattern group. Specifically, in one embodiment of the present invention, generating a first via pattern based on each pattern group may include: for each pattern group, generating at least one pre-prepared via pattern according to the distribution information of each of the first metal patterns in the pattern group; checking whether the at least one pre-prepared via pattern conforms to the preset design rules within its respective pattern group to obtain a first check result; if the first check result includes a non-compliant via pattern, determining the pattern group corresponding to the non-compliant via pattern as the first pattern group, and determining the layout area where the first pattern group is located as a re-inspection area. The layout area is defined as the adjacent layout area to the re-inspection layout area, and the pattern group in the adjacent layout area is defined as the second pattern group; wherein, the non-compliant via pattern is the prepared via pattern that does not conform to the preset design rules; check whether there is an interconnection relationship between the first pattern group and the second pattern group; if there is an interconnection relationship between the first pattern group and the second pattern group, correct the first inspection result according to the interconnection relationship to obtain a second inspection result; the prepared via pattern that conforms to the preset design rules in the second inspection result is defined as the first via pattern.

[0057] For example, such as Figure 2As shown, in one embodiment of the present invention, layout area R1 and layout area R2 are two adjacent layout areas. The first metal patterns in layout area R1 can be divided into pattern group A and pattern group B. The first metal patterns in pattern group A may include first metal pattern a1, first metal pattern a2, and first metal pattern a3, and the first metal patterns in pattern group B may include first metal pattern b1 and first metal pattern b2. Based on the distribution information of the first metal patterns a1, a2, and a3 in pattern group A, at least one pre-existing via pattern viaA can be generated, and based on the distribution information of the first metal patterns b1 and b2 in pattern group B, at least one pre-existing via pattern viaB can be generated. Next, it can be checked whether each pre-existing via pattern viaA conforms to a preset design rule within its respective pattern group A, and whether each pre-existing via pattern viaB conforms to a preset design rule within its respective pattern group B, to obtain a first check result. If the first inspection result includes a non-compliant via pattern, for example, if the distance between the prepared via pattern viaA and the boundary of pattern group A is less than a preset distance threshold, causing the prepared via pattern viaA to be non-compliant, then pattern group A can be determined as the first pattern group, layout area R1 can be determined as the re-inspection layout area, layout area R2 can be determined as the adjacent layout area, and pattern group C and pattern group D in layout area R2 can be determined as the second pattern group; check whether there is an interconnection relationship between pattern group A and pattern group C, and between pattern group A and pattern group D. If there is an interconnection relationship between pattern group A and pattern group C, then the first inspection result can be corrected according to the interconnection relationship to obtain the second inspection result, and the prepared via pattern that conforms to the preset design rule in the second inspection result can be determined as the first via pattern. For example, in one example, according to the second inspection result, if viaA1, viaA3, viaB1, and viaB3 conform to the design rule, while viaA2 and viaB2 do not conform to the design rule, then the prepared via patterns viaA1, viaA3, viaB1, and viaB3 can be determined as the first via patterns. Since each first metal pattern is divided into multiple pattern groups, when performing design rule checks, for the prepared via patterns generated within a pattern group, it is only necessary to check whether each prepared via pattern conforms to the preset design rules within the pattern group. There is no need to check whether the elements of two different pattern groups conform to the preset design rules across different pattern groups. Therefore, the computational load of design rule checks can be greatly reduced.

[0058] In the foregoing embodiments, when a non-compliant via pattern appears anywhere in its layout area, the corresponding first pattern group and second pattern group can be determined. However, the embodiments of the present invention are not limited to this. In some embodiments of the present invention, more specific conditions can be set for determining the first pattern group and the second pattern group. For example, in one embodiment of the present invention, when the first inspection result includes a non-compliant via pattern, the pattern group corresponding to the non-compliant via pattern is determined as the first pattern group, the layout area where the first pattern group is located is determined as the re-inspection layout area, the layout area adjacent to the re-inspection layout area is determined as the adjacent layout area, and the pattern group in the adjacent layout area is determined as the second pattern group. Specifically, this may include: when the first inspection result includes a non-compliant via pattern and the non-compliant via pattern is located within a first preset range of its layout area, the pattern group corresponding to the non-compliant via pattern is determined as the first pattern group, the layout area where the first pattern group is located is determined as the re-inspection layout area, the layout area adjacent to the re-inspection layout area is determined as the adjacent layout area, and the pattern group within a second preset range of the adjacent layout area is determined as the second pattern group.

[0059] In other words, the first and second pattern groups are only determined when the non-existent via pattern is located within a first preset range of its layout area, in order to further examine the interconnection relationship between the first and second pattern groups. If the non-existent via pattern is located outside the first preset range of its layout area, the first and second pattern groups are not determined, nor is the interconnection relationship between them checked. When determining the second pattern group, only pattern groups located within the second preset range of adjacent layout areas can be identified as the second pattern group, while pattern groups located outside the second preset range are excluded, thus significantly reducing the computational load.

[0060] Optionally, the first preset range and the second preset range can be a small area near the edge of the corresponding map region. For example, the first preset range and the second preset range can be determined in the following ways.

[0061] like Figure 3As shown, in one embodiment, the ratio of the distance from a point within the first preset range to the first edge of the first layout area to the distance from the first edge of the first layout area to the second edge of the first layout area is less than a first ratio threshold; or, the ratio of the distance from a point within the first preset range to the third edge of the first layout area to the distance from the third edge of the first layout area to the fourth edge of the first layout area is less than the first ratio threshold; wherein, the first layout area is the layout area where the non-compliant via pattern is located, the first layout area is a rectangle, the first edge and the second edge are two opposite sides of the rectangle, and the third edge and the fourth edge are two opposite sides of the rectangle.

[0062] like Figure 4 As shown, in another embodiment, the ratio of the distance from a point within the second preset range to the first edge of the adjacent map area to the distance from the first edge to the second edge of the adjacent map area is less than a second ratio threshold, or the ratio of the distance from a point within the second preset range to the third edge of the adjacent map area to the distance from the third edge to the fourth edge of the adjacent map area is less than a second ratio threshold; wherein, the adjacent map area is a rectangle, the first edge and the second edge are two opposite sides of the rectangle, and the third edge and the fourth edge are two opposite sides of the rectangle.

[0063] Optionally, in embodiments of the present invention, the first proportional threshold and the second proportional threshold may be equal or unequal. The specific values ​​of the first proportional threshold and the second proportional threshold can be set and adjusted as needed. For example, in one example, both the first proportional threshold and the second proportional threshold can be between 5% and 10%.

[0064] In embodiments of the present invention, when dividing the layout area, it is possible that two first metal patterns that are originally interconnected may be divided into two different layout areas, causing positions that are not metal edges to be mistakenly identified as metal edges, resulting in some non-metal via patterns being non-compliant. Such non-compliant patterns can be corrected using the methods described above, thereby effectively improving the accuracy of the first via pattern generation.

[0065] In specific implementation, when there is an interconnection relationship between the first pattern group and any of the second pattern groups, correcting the first inspection result based on the interconnection relationship may include: taking the first pattern group and any of the second pattern groups as a merged pattern group, determining whether the non-compliant via pattern conforms to the preset design rule within the merged pattern group; if the non-compliant via pattern conforms to the preset design rule within the merged pattern group, correcting the non-compliant via pattern to a pre-existing via pattern that conforms to the preset design rule. That is, when there is an interconnection relationship between the first pattern group and the second pattern group, the first pattern group and the second pattern group can be merged into a single pattern group. Based on this merged pattern group, the non-compliant via pattern can be re-checked for conformity to the preset design rule. If it conforms to the preset design rule, then the non-compliant via pattern can be corrected to a non-compliant via pattern, that is, a pre-existing via pattern that conforms to the preset design rule, thus obtaining the second inspection result. The pre-existing via patterns that originally conformed to the preset design rule and the pre-existing via patterns that conformed to the preset design rule after correction in the second inspection result are determined as the first via pattern.

[0066] Furthermore, after checking whether there is an interconnection relationship between the first pattern group and the second pattern group, the chip design method provided by the embodiments of the present invention may further include: if there is no interconnection relationship between the first pattern group and the second pattern group, determining the prepared via pattern that conforms to the preset design rules in the first inspection result as the first via pattern. That is to say, if there is no interconnection relationship between the first pattern group and the second pattern group, the first via pattern can be determined based on the first inspection result without the need to modify the first inspection result.

[0067] In the above embodiments, a first via pattern and a second metal pattern can be generated based on the distribution information of the first metal pattern in the original layout information; however, the embodiments of the present invention are not limited thereto. In other embodiments of the present invention, the first via pattern and the second metal pattern can also be generated in other ways.

[0068] For example, in one embodiment of the present invention, the original layout information of the target chip may further include the distribution information of the second via pattern; the second via pattern is used to form the second via of the target chip, and the second via is used to electrically connect the first metal layer to the internal circuitry of the target chip. Based on this, step S12, generating the first via pattern and the second metal pattern according to the original layout information, may include: generating the first via pattern and the second metal pattern according to the distribution information of the first metal pattern and the distribution information of the second via pattern. That is to say, in some embodiments of the present invention, the second via pattern may also affect the generation of the first via pattern or the second metal pattern.

[0069] Specifically, in one embodiment of the present invention, the number of second via patterns can be at least one; based on this, generating the first via pattern and the second metal pattern according to the distribution information of the first metal pattern and the distribution information of the second via pattern may include: generating the second metal pattern according to the distribution information of the first metal pattern, and generating at least one pre-existing via pattern according to the distribution information of the second via pattern, wherein the pre-existing via pattern corresponds one-to-one with the second via pattern; and obtaining the first via pattern by translating each of the pre-existing via patterns relative to the second via pattern.

[0070] In one embodiment, generating the second metal pattern based on the distribution information of the first metal pattern may specifically include copying the first metal pattern to obtain the second metal pattern. The shape and number of the second metal pattern may be the same as those of the first metal pattern, and the distribution positions of the second metal pattern may also be aligned with the distribution positions of the first metal pattern. Thus, the second metal layer made using the second metal pattern has the same structure as the first metal layer made using the first metal pattern. After the first metal layer contacts the test probe and performs a first test, the second metal layer can replace the first metal layer and contact the test probe to perform a second test.

[0071] In one embodiment, at least one pre-prepared via pattern is generated based on the distribution information of the second via pattern, wherein the pre-prepared via pattern corresponds one-to-one with the second via pattern. Specifically, this may include: copying each of the second via patterns to obtain the corresponding pre-prepared via pattern; furthermore, the shape or size of each pre-prepared via pattern may be adjusted as needed. That is, the number and distribution position of the pre-prepared via patterns may be the same as the second via patterns, and the shape and size of the pre-prepared via patterns may be the same as or different from the second via patterns.

[0072] After obtaining the pre-prepared via pattern, the first via pattern can be obtained by translating the pre-prepared via pattern relative to the second via pattern. In one embodiment of the present invention, obtaining the first via pattern by translating the pre-prepared via pattern relative to the second via pattern may include: determining the total number of the at least one pre-prepared via patterns generated; performing a step-by-step translation of each pre-prepared via pattern along each of at least one preset direction, and determining the translation efficiency of each step-by-step translation, wherein the translation efficiency is equal to the ratio of the number of pre-prepared via patterns conforming to the preset design rules after each step-by-step translation to the number of pre-prepared via patterns participating in this translation; among the pre-prepared via patterns obtained in the translation operation with the highest translation efficiency, selecting the pre-prepared via patterns conforming to the preset design rules... The process involves determining the via pattern as a retained pattern, identifying any pre-designed via patterns that do not conform to the preset design rules as the remaining pre-designed via patterns, fixing the position of the retained patterns, jumping to each preset direction along at least one preset direction, performing a step-by-step translation of each pre-designed via pattern as a whole, and determining the translation efficiency of each step-by-step translation. This step-by-step translation of the remaining pre-designed via patterns continues until a preset condition is met. The preset condition includes: the ratio of the cumulative number of retained patterns to the total number of pre-designed via patterns is greater than a preset ratio threshold, or the number of step-by-step translations is greater than a preset number threshold. Each retained pattern is then used as the first via pattern. The specific direction and number of preset directions can be set and adjusted as needed, and the embodiments of the present invention do not limit this. For example, in one example, the preset directions may include four directions: up, down, left, and right. In another example, the preset directions may include eight directions: up, down, left, right, upper left, lower left, upper right, and lower right.

[0073] For example, such as Figure 5 As shown, in one embodiment of the present invention, the preset direction may include four directions: up, down, left, and right. Then, with a preset length as the step size, each prepared via pattern can be translated stepwise up, down, left, and right respectively. Figure 3The diagram only shows upward and downward translations; the principles for left and right translations are similar (and are not shown here). For example, if the step size is 10 nanometers, the device can first be translated 10 nanometers upward, downward, left, and right respectively. Then, based on the 10-nanometer translations, it can be translated another 10 nanometers upward, downward, left, and right, and so on. With each step translation, each prepared via pattern will have a new position. It is then possible to check whether the prepared via pattern at each new position conforms to the preset design rules and calculate the translation efficiency corresponding to this translation operation. The translation efficiency is equal to the ratio of the number of prepared via patterns conforming to the preset design rules after each step translation to the total number of prepared via patterns participating in this translation. For example, if the number of prepared via patterns participating in this translation is 400, and 300 of them conform to the preset design rules while one does not, then the translation efficiency of this operation is 300 / 400 = 0.75. In each translation operation, the translation operation with the highest translation efficiency is selected. Among the prepared via patterns obtained from the translation operation with the highest translation efficiency, the prepared via patterns that conform to the preset design rules are determined as retained patterns and left in their corresponding positions. The prepared via patterns that do not conform to the preset rules are determined as the remaining prepared via patterns, and a new round of step-by-step translation is performed on the remaining prepared via patterns. For example, in one example, prepared via patterns viaC1 and viaC2 conform to the preset design rules, while prepared via pattern viaC3 does not conform to the preset design rules. In this case, prepared via patterns viaC1 and viaC2 can be left at their positions after this step, and prepared via pattern viaC3 can be translated upwards, downwards, etc., by 10 nanometers from the position where prepared via pattern viaC3 was generated. After each translation, the prepared via pattern viaC3 is checked to see if it conforms to the preset design rules.

[0074] Optionally, in embodiments of the present invention, the step-by-step translation can be terminated as long as any one of the following preset conditions is met: Condition 1: The ratio of the cumulative number of retained patterns to the total number of prepared via patterns is greater than a preset ratio threshold. For example, after multiple rounds of translation, 390 out of 400 prepared via patterns become retained patterns, that is, the ratio of the cumulative number of retained patterns to the total number of prepared via patterns is 390 / 400 = 0.975, which is greater than the preset ratio threshold (e.g., the preset ratio threshold is 0.95), so the translation operation can be terminated. Condition 2: The number of step-by-step translations is greater than a preset number threshold, that is, after multiple (e.g., 32) step-by-step translations, there are still a large number of prepared via patterns that have not become retained patterns.

[0075] Optionally, if the ratio of the cumulative number of reserved patterns to the total number of prepared via patterns is greater than the preset ratio threshold, each reserved pattern can be used as a first via pattern. That is, through this step-by-step translation operation, first via patterns conforming to preset design rules are generated. If the ratio of the cumulative number of reserved patterns to the total number of prepared via patterns is less than or equal to the preset ratio threshold, manual verification is prompted. That is, through this step-by-step translation operation, not enough first via patterns have been arranged, therefore manual processing is required.

[0076] As can be seen from the foregoing embodiments, in step S12, the first via pattern generated according to the original layout information is in accordance with the preset design rules. Therefore, in one embodiment of the present invention, a preliminary via pattern and a second metal pattern can be generated first according to the original layout information, and then the preliminary via pattern can be checked to see if it conforms to the preset design rules. If the preliminary via pattern conforms to the preset design rules, the preliminary via pattern is determined as the first via pattern.

[0077] In one embodiment of the present invention, the original layout information may include the distribution information of a first metal pattern and the distribution information of a second via pattern; the second via pattern is used to form a second via of the target chip, and the second via is used to electrically connect the first metal layer to the internal circuitry of the target chip. In an embodiment of the present invention, the prepared via patterns are identified based on their own center point coordinates; each prepared via pattern is equal in size and has the same shape, or each prepared via pattern includes at least two categories, and each prepared via pattern in the same category is equal in size and has the same shape; based on this, checking whether the prepared via patterns conform to the preset design rules may include at least one of the following: determining whether the spacing between each prepared via pattern conforms to the preset design rules based on the center point coordinates of each prepared via pattern; determining whether the spacing between each prepared via pattern and the second via pattern conforms to the preset design rules based on the center point coordinates of each prepared via pattern and the distribution information of the second via pattern; determining whether the relative positional relationship between each prepared via pattern and the first metal pattern conforms to the preset design rules based on the center point coordinates of each prepared via pattern and the distribution information of the first metal pattern.

[0078] In this embodiment, all prepared via patterns are of equal size and identical shape. Alternatively, each prepared via pattern includes at least two categories, and the prepared via patterns within the same category are of equal size and identical shape. This means that many of the generated prepared via patterns are of equal size and identical shape. Therefore, unlike existing technologies that use the coordinates of multiple vertices (e.g., the top-left and bottom-right vertices) to identify each prepared via pattern, each prepared via pattern can be identified using the coordinates of its own center point. This is significant for performing design rule checks on each prepared via pattern, as it greatly reduces the computational load of the design rule check.

[0079] For example, in one embodiment of the present invention, after each pre-existing via pattern is identified by its own center point coordinates, the distance calculation between pre-existing via patterns can be simplified to the calculation of the absolute value of the difference between the x-coordinates and the absolute value of the difference between the y-coordinates of the center points of two pre-existing via patterns, i.e., |x1-x2|, |y1-y2|, where x1 is the x-coordinate of the center point of one pre-existing via pattern, y1 is the y-coordinate of the center point of the same pre-existing via pattern, x2 is the x-coordinate of the center point of another pre-existing via pattern, and y2 is the y-coordinate of the center point of the same pre-existing via pattern.

[0080] If each second via pattern can also be identified by its own center point coordinates, then the distance calculation between the prepared via pattern and the second via pattern can be simplified to the calculation of the absolute value of the difference between the x-coordinate of the center point of the prepared via pattern and the x-coordinate of the center point of the second via pattern, and the absolute value of the difference between the y-coordinate of the center point of the prepared via pattern and the y-coordinate of the center point of the second via pattern.

[0081] The calculation of the distance between each prepared via pattern and the edge of the first metal pattern can be simplified to the calculation of the distance from the center point of the prepared via pattern to the edge of the first metal pattern, which is also simplified to the calculation of the distance from a point to a line segment.

[0082] Since the number of first metal patterns, second via patterns, and pre-existing via patterns in the target chip is extremely large, the simplified design rule checking method described above will greatly reduce the complexity and computational load of design rule checking.

[0083] After generating the first via pattern and the second metal pattern based on the original layout information in step S12, the target layout of the target chip can be generated in step S13 based on the first via pattern and the second metal pattern. Specifically, in one embodiment of the present invention, generating the target layout of the target chip based on the first via pattern and the second metal pattern may include: generating the target layout of the target chip based on the first via pattern, the second metal pattern, and the original layout information of the target chip. That is, the newly generated first via pattern and second metal pattern can be merged with the original layout information of the target chip to generate the target layout of the target chip. Using the target layout, a chip that can accommodate both 2D and 3D testing can be manufactured.

[0084] The chip design method provided by the embodiments of the present invention will be described in detail below through a specific example.

[0085] like Figure 6 As shown, the chip design method provided by the embodiments of the present invention may include: S201. Obtain the original layout information of the target chip.

[0086] The original layout information includes the distribution information of the first metal pattern; the first metal pattern is used to form the first metal layer of the target chip, and the first metal layer is the metal layer used to contact the test probe in the first test of the target chip.

[0087] S202. Generate a second metal pattern based on the distribution information of each first metal pattern; S203. Divide the plate layer containing each first metal pattern into at least two plate areas.

[0088] S204. For each map area, based on the distribution information of each first metal pattern in the map area, the first metal patterns that are electrically connected to each other are divided into the same pattern group, and the first metal patterns that are not electrically connected to each other are divided into different pattern groups.

[0089] S205. For each pattern group, generate at least one pre-existing via pattern based on the distribution information of each first metal pattern in the pattern group.

[0090] In this step, the second via pattern corresponding to the pattern group can be copied to obtain the prepared via pattern. Then, a step-by-step translation method is used to try various possible positions for each prepared via pattern. The relevant principle of step-by-step translation has been explained in detail above and will not be repeated here.

[0091] S206. Check whether at least one prepared via pattern conforms to the preset design rules within its pattern group, and obtain the first inspection result; In step S205, when the various positions that each prepared via pattern may be arranged are gradually tried by step translation, this step can check whether each prepared via pattern that is step translated each time conforms to the preset design rules and obtain the corresponding first check result.

[0092] When performing design rule checks, each pre-prepared via pattern can be identified based on its own center point coordinates, which can greatly reduce the amount of calculation.

[0093] S207. Does the first inspection result include a non-compliant via pattern? If yes, proceed to step S208; if no, proceed to step S214. Among them, the non-compliant via pattern is the prepared via pattern that does not conform to the preset design rules; S208. The pattern group corresponding to the non-compliant via pattern is determined as the first pattern group, the layout area where the first pattern group is located is determined as the re-inspection layout area, the layout area adjacent to the re-inspection layout area is determined as the adjacent layout area, and the pattern group in the adjacent layout area is determined as the second pattern group. S209. Check whether there is an interconnection relationship between the first pattern group and the second pattern group; if yes, proceed to step S210; if no, proceed to step S212.

[0094] S210. Based on the interconnection relationship, the first inspection result is corrected to obtain the second inspection result; S211. The prepared via pattern that conforms to the preset design rules in the second inspection result is determined as the first via pattern, and step S213 is executed.

[0095] S212. The prepared via pattern that conforms to the preset design rules in the first inspection result is determined as the first via pattern.

[0096] S213. Adjust the first inspection result and the pre-existing via patterns in the first inspection result that do not conform to the preset design rules until all pre-existing via patterns conform to the preset design rules, and obtain all first via patterns.

[0097] S214. Generate the target layout of the target chip based on the first via pattern, the second metal pattern, and the original layout information of the target chip.

[0098] Accordingly, embodiments of the present invention provide a chip design apparatus that can design chips that can accommodate both 2D and 3D testing with high efficiency.

[0099] like Figure 7As shown, an embodiment of the present invention provides a chip design apparatus, which may include: The acquisition unit 31 is used to acquire the original layout information of the target chip, the original layout information including the distribution information of the first metal pattern; the first metal pattern is used to form the first metal layer of the target chip, the first metal layer being the metal layer used to contact the test probe in the first test of the target chip; The first generation unit 32 is used to generate a first via pattern and a second metal pattern according to the original layout information. The first via pattern conforms to a preset design rule. The first via pattern is used to form a first via of the target chip. The second metal pattern is used to form a second metal layer of the target chip. The first via is used to electrically connect the first metal layer and the second metal layer. The second metal layer is a metal layer used to contact the test probe in the second test of the target chip. The second generation unit 33 is used to generate the target layout of the target chip based on the first via pattern and the second metal pattern.

[0100] The chip design apparatus provided in the embodiments of the present invention can acquire the original layout information of a target chip, generate a first via pattern and a second metal pattern based on the original layout information, wherein the first via pattern conforms to preset design rules; and generate the target layout of the target chip based on the first via pattern and the second metal pattern. In this way, the first via pattern and the second metal pattern can be directly generated based on the original layout information of the target chip, thereby electrically connecting the first metal layer and the second metal layer through the first via. A first test is completed by contacting the test probe through the first metal layer, and a second test is completed by contacting the test probe through the second metal layer. Since no EDA tools are required to participate in the generation of the first via pattern and the second metal pattern, there is no need to set up a complex rule base for the EDA tools, and the already completed 2D chip design work is not forced to be abandoned and the entire routing is redone. Therefore, chips that can accommodate both 2D and 3D testing can be designed with high efficiency.

[0101] In one embodiment, the number of the first metal patterns is at least one; the first generation unit includes: a first generation module, configured to generate a second metal pattern according to the distribution information of each of the first metal patterns; a division module, configured to divide each of the first metal patterns into at least two pattern groups according to the distribution information of each of the first metal patterns; and a second generation module, configured to generate the first via pattern based on each of the pattern groups.

[0102] In one embodiment, the partitioning module is specifically used to: divide the layer containing each of the first metal patterns into at least two pattern areas; for each pattern area, based on the distribution information of each of the first metal patterns in the pattern area, divide the first metal patterns that are electrically connected to each other into the same pattern group, and divide the first metal patterns that are not electrically connected to each other into different pattern groups.

[0103] In one embodiment, the second generation module includes: a generation submodule, configured to generate at least one pre-prepared via pattern for each pattern group based on the distribution information of each of the first metal patterns in the pattern group; a first inspection submodule, configured to inspect whether the at least one pre-prepared via pattern conforms to the preset design rules within its respective pattern group, and obtain a first inspection result; and a first determination submodule, configured to, if the first inspection result includes a non-compliant via pattern, determine the pattern group corresponding to the non-compliant via pattern as the first pattern group, determine the layout area where the first pattern group is located as the re-inspection layout area, and determine the layout adjacent to the re-inspection layout area as the first pattern group. The region is defined as an adjacent layout region, and the pattern group in the adjacent layout region is defined as the second pattern group; wherein, the non-compliant via pattern is the prepared via pattern that does not conform to the preset design rule; a second inspection submodule is used to check whether there is an interconnection relationship between the first pattern group and the second pattern group; a correction submodule is used to correct the first inspection result according to the interconnection relationship when there is an interconnection relationship between the first pattern group and any of the second pattern groups, to obtain a second inspection result; a second determination submodule is used to determine the prepared via pattern that conforms to the preset design rule in the second inspection result as the first via pattern.

[0104] In one implementation, the first determining submodule is specifically configured to: when the first inspection result includes a non-compliant via pattern and the non-compliant via pattern is located within a first preset range of its respective layout area, determine the pattern group corresponding to the non-compliant via pattern as a first pattern group, determine the layout area where the first pattern group is located as a re-inspection layout area, determine the layout area adjacent to the re-inspection layout area as an adjacent layout area, and determine the pattern group within a second preset range of the adjacent layout area as a second pattern group.

[0105] In one embodiment, the ratio of the distance from a point within the first preset range to the first edge of the first layout area to the distance from the first edge of the first layout area to the second edge of the first layout area is less than a first ratio threshold, or the ratio of the distance from a point within the first preset range to the third edge of the first layout area to the distance from the third edge of the first layout area to the fourth edge of the first layout area is less than the first ratio threshold; wherein, the first layout area is the layout area where the non-compliant via pattern is located, the first layout area is a rectangle, the first edge and the second edge are two opposite sides of the rectangle, and the third edge and the fourth edge are two opposite sides of the rectangle; the ratio of the distance from a point within the second preset range to the first edge of the adjacent layout area to the distance from the first edge of the adjacent layout area to the second edge of the adjacent layout area is less than a second ratio threshold, or the ratio of the distance from a point within the second preset range to the third edge of the adjacent layout area to the distance from the third edge of the adjacent layout area to the fourth edge of the adjacent layout area is less than the second ratio threshold; wherein, the adjacent layout area is a rectangle, the first edge and the second edge are two opposite sides of the rectangle, and the third edge and the fourth edge are two opposite sides of the rectangle.

[0106] In one embodiment, the correction submodule is specifically configured to: combine the first pattern group and the second pattern group as a merged pattern group; determine whether the non-compliant via pattern conforms to the preset design rule within the merged pattern group; and, if the non-compliant via pattern conforms to the preset design rule within the merged pattern group, correct the non-compliant via pattern to the prepared via pattern that conforms to the preset design rule.

[0107] In one embodiment, the second generation module further includes a third determining submodule, configured to determine the prepared via pattern that conforms to the preset design rules in the first inspection result as the first via pattern when there is no interconnection relationship between the first pattern group and the second pattern group.

[0108] In one embodiment, the original layout information further includes the distribution information of a second via pattern; the second via pattern is used to form a second via of the target chip, and the second via is used to electrically connect the first metal layer to the internal circuit of the target chip; the first generation unit is specifically used to generate the first via pattern and the second metal pattern according to the distribution information of the first metal pattern and the distribution information of the second via pattern.

[0109] In one embodiment, the number of the second via pattern is at least one; the first generating unit includes: The third generation module is used to generate the second metal pattern according to the distribution information of the first metal pattern, and to generate at least one pre-via pattern according to the distribution information of the second via pattern, wherein the pre-via pattern corresponds one-to-one with the second via pattern. A translation module is used to obtain the first via pattern by translating each of the prepared via patterns relative to the second via pattern.

[0110] In one embodiment, the translation module may include: The fourth determining submodule is used to determine the total number of the at least one pre-prepared via pattern generated; The translation submodule is used to perform step-by-step translation of each of the prepared via patterns along each of at least one preset direction, and to determine the translation efficiency of each step translation. The translation efficiency is equal to the ratio of the number of prepared via patterns that conform to the preset design rules after each step translation to the number of prepared via patterns participating in this translation. The fifth determining submodule is used to determine, among the prepared via patterns obtained in the translation operation with the greatest translation efficiency, the prepared via patterns that conform to the preset design rules as retained patterns, and the prepared via patterns that do not conform to the preset design rules as the remaining prepared via patterns. A fixing submodule is used to fix the position of the retained pattern; The trigger submodule is used to trigger the translation submodule to continue to perform step-by-step translation on the remaining prepared via patterns until a preset condition is met. The preset condition includes: the ratio of the cumulative number of the retained patterns to the total number of the prepared via patterns is greater than a preset ratio threshold, or the number of step-by-step translations is greater than a preset number threshold. The sixth determining submodule is used to determine each of the reserved patterns as the first via pattern when the ratio of the cumulative number of the reserved patterns to the total number of the prepared via patterns is greater than the preset ratio threshold.

[0111] In one embodiment, the translation module further includes: The prompting submodule is used to prompt for manual verification when the ratio of the cumulative number of retained patterns to the total number of prepared via patterns is less than or equal to the preset ratio threshold.

[0112] In one implementation, the first generating unit 32 may include: The fourth generation module is used to generate a pre-existing via pattern and a second metal pattern based on the original layout information; The inspection module is used to check whether the prepared via pattern conforms to the preset design rules; The determining module is used to determine the prepared via pattern as the first via pattern when the prepared via pattern conforms to the preset design rules.

[0113] In one embodiment, the original layout information further includes distribution information of the second via pattern; the second via pattern is used to form the second via of the target chip, and the second via is used to electrically connect the first metal layer to the internal circuitry of the target chip; the prepared via pattern is identified based on its own center point coordinates; each of the prepared via patterns is equal in size and has the same shape, or each of the prepared via patterns includes at least two categories, and each of the prepared via patterns in the same category is equal in size and has the same shape; The inspection module can be specifically used for at least one of the following: Based on the center point coordinates of each of the prepared via patterns, determine whether the spacing between each of the prepared via patterns conforms to the preset design rules; Based on the center point coordinates of each of the prepared via patterns and the distribution information of the second via pattern, determine whether the spacing between each of the prepared via patterns and the second via pattern conforms to the preset design rules; Based on the center point coordinates of each of the prepared via patterns and the distribution information of the first metal pattern, determine whether the relative positional relationship between each of the prepared via patterns and the first metal pattern serves the preset design rule.

[0114] In one embodiment, the second generation unit 33 is specifically used to: generate a target layout of the target chip based on the first via pattern, the second metal pattern, and the original layout information of the target chip.

[0115] Accordingly, embodiments of the present invention also provide an electronic device that can effectively reduce the complexity of chip design.

[0116] like Figure 8 As shown, the electronic device provided in the embodiments of the present invention may include: a processor 71 and a memory 72, wherein the processor 71 and the memory 72 are electrically connected; the memory 72 is used to store executable program code; the processor 71 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 72, so as to implement any of the chip design methods provided in the foregoing embodiments.

[0117] The specific execution process of the above steps by the processor 71, as well as the steps further executed by the processor 71 by running executable program code, can be found in the description of the foregoing embodiments, and will not be repeated here.

[0118] Accordingly, embodiments of the present invention also provide a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement any of the chip design methods provided in the foregoing embodiments, and thus can also achieve the corresponding technical effects. This has been described in detail above and will not be repeated here.

[0119] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0120] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0121] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.

[0122] For ease of description, the above apparatus is described by dividing it into various functional units / modules. Of course, in implementing this invention, the functions of each unit / module can be implemented in one or more software and / or hardware.

[0123] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0124] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A chip design method, characterized in that, include: Obtain the original layout information of the target chip, wherein the original layout information includes the distribution information of the first metal pattern; The first metal pattern is used to form a first metal layer of the target chip, which is a metal layer used to contact the test probe in the first test of the target chip; A first via pattern and a second metal pattern are generated based on the original layout information. The first via pattern conforms to a preset design rule. The first via pattern is used to form a first via of the target chip. The second metal pattern is used to form a second metal layer of the target chip. The first via is used to electrically connect the first metal layer and the second metal layer. The second metal layer is a metal layer used to contact the test probe in the second test of the target chip. A target layout of the target chip is generated based on the first via pattern and the second metal pattern; The step of generating the first via pattern and the second metal pattern based on the original layout information includes: Generate a pre-connection pattern and a second metal pattern based on the original layout information; Check whether the prepared via pattern conforms to the preset design rules; If the prepared via pattern conforms to the preset design rules, the prepared via pattern is determined as the first via pattern; The original layout information also includes the distribution information of the second via pattern; the second via pattern is used to form the second via of the target chip, and the second via is used to electrically connect the first metal layer to the internal circuit of the target chip; The prepared via pattern is identified based on its own center point coordinates; All the prepared via patterns are equal in size and have the same shape, or each of the prepared via patterns includes at least two categories, and the prepared via patterns under the same category are equal in size and have the same shape; The step of checking whether the prepared via pattern conforms to the preset design rules includes at least one of the following: Based on the center point coordinates of each of the prepared via patterns, determine whether the spacing between each of the prepared via patterns conforms to the preset design rules; Based on the center point coordinates of each of the prepared via patterns and the distribution information of the second via pattern, determine whether the spacing between each of the prepared via patterns and the second via pattern conforms to the preset design rules; Based on the center point coordinates of each of the prepared via patterns and the distribution information of the first metal pattern, determine whether the relative positional relationship between each of the prepared via patterns and the first metal pattern conforms to the preset design rules.

2. The method according to claim 1, characterized in that, The number of the first metal pattern is at least one; the step of generating the first via pattern and the second metal pattern according to the original layout information includes: The second metal pattern is generated based on the distribution information of each of the first metal patterns, and each of the first metal patterns is divided into at least two pattern groups based on the distribution information of each of the first metal patterns. The first via pattern is generated based on each of the pattern groups.

3. The method according to claim 2, characterized in that, The step of dividing each of the first metal patterns into at least two pattern groups based on the distribution information of each of the first metal patterns includes: Divide the layer containing each of the first metal patterns into at least two map regions; For each of the layout areas, based on the distribution information of each of the first metal patterns within the layout area, the first metal patterns that are electrically connected to each other are divided into the same pattern group, and the first metal patterns that are not electrically connected to each other are divided into different pattern groups.

4. The method according to claim 3, characterized in that, Generating the first via pattern based on each of the pattern groups includes: For each of the pattern groups, at least one pre-existing via pattern is generated based on the distribution information of each of the first metal patterns in the pattern group. Check whether the at least one prepared via pattern conforms to the preset design rules within its respective pattern group to obtain the first check result; If the first inspection result includes a non-compliant via pattern, the pattern group corresponding to the non-compliant via pattern is determined as the first pattern group, the layout area where the first pattern group is located is determined as the re-inspection layout area, the layout area adjacent to the re-inspection layout area is determined as the adjacent layout area, and the pattern group in the adjacent layout area is determined as the second pattern group; wherein, the non-compliant via pattern is the prepared via pattern that does not conform to the preset design rules; Check whether there is an interconnection between the first pattern group and the second pattern group; If there is an interconnection relationship between the first pattern group and any of the second pattern groups, the first inspection result is corrected according to the interconnection relationship to obtain a second inspection result; The prepared via pattern that conforms to the preset design rules in the second inspection result is determined as the first via pattern.

5. The method according to claim 4, characterized in that, In the case that the first inspection result includes a non-compliant via pattern, determining the pattern group corresponding to the non-compliant via pattern as the first pattern group, determining the layout area where the first pattern group is located as the re-inspection layout area, determining the layout area adjacent to the re-inspection layout area as the adjacent layout area, and determining the pattern group in the adjacent layout area as the second pattern group includes: If the first inspection result includes a non-compliant via pattern and the non-compliant via pattern is located within a first preset range of its respective layout area, the pattern group corresponding to the non-compliant via pattern is determined as the first pattern group, the layout area where the first pattern group is located is determined as the re-inspection layout area, the layout area adjacent to the re-inspection layout area is determined as the adjacent layout area, and the pattern group within a second preset range of the adjacent layout area is determined as the second pattern group.

6. The method according to claim 5, characterized in that, The ratio of the distance from a point within the first preset range to the first edge of the first layout area to the distance from the first edge of the first layout area to the second edge is less than a first ratio threshold; or, the ratio of the distance from a point within the first preset range to the third edge of the first layout area to the distance from the third edge of the first layout area to the fourth edge is less than the first ratio threshold; wherein, the first layout area is the layout area where the non-compliant via pattern is located, the first layout area is a rectangle, the first edge and the second edge are two opposite sides of the rectangle, and the third edge and the fourth edge are two opposite sides of the rectangle; The ratio of the distance from a point within the second preset range to the first edge of the adjacent map region to the distance from the first edge to the second edge of the adjacent map region is less than a second ratio threshold; or, the ratio of the distance from a point within the second preset range to the third edge of the adjacent map region to the distance from the third edge to the fourth edge of the adjacent map region is less than the second ratio threshold; wherein, the adjacent map region is a rectangle, the first edge and the second edge are two opposite sides of the rectangle, and the third edge and the fourth edge are two opposite sides of the rectangle.

7. The method according to claim 4, characterized in that, In the case where there is an interconnection between the first pattern group and the second pattern group, correcting the first inspection result based on the interconnection includes: The first pattern group and the second pattern group are combined into a single pattern group, and it is determined whether the non-compliant via pattern conforms to the preset design rules within the single pattern group. If the non-compliant via pattern conforms to the preset design rules within the merged pattern group, the non-compliant via pattern is corrected to the prepared via pattern that conforms to the preset design rules.

8. The method according to claim 4, characterized in that, After checking whether there is an interconnection relationship between the first pattern group and the second pattern group, the method further includes: If there is no interconnection between the first pattern group and the second pattern group, the prepared via pattern that conforms to the preset design rules in the first inspection result is determined as the first via pattern.

9. The method according to any one of claims 1 to 8, characterized in that, The original layout information also includes the distribution information of the second via pattern; the second via pattern is used to form the second via of the target chip, and the second via is used to electrically connect the first metal layer to the internal circuit of the target chip; The step of generating the first via pattern and the second metal pattern based on the original layout information includes: The first via pattern and the second metal pattern are generated based on the distribution information of the first metal pattern and the distribution information of the second via pattern.

10. The method according to claim 9, characterized in that, The number of the second via pattern is at least one; generating the first via pattern and the second metal pattern based on the distribution information of the first metal pattern and the distribution information of the second via pattern includes: The second metal pattern is generated based on the distribution information of the first metal pattern, and at least one pre-via pattern is generated based on the distribution information of the second via pattern, wherein the pre-via pattern corresponds one-to-one with the second via pattern. The first via pattern is obtained by translating each of the prepared via patterns relative to the second via pattern.

11. The method according to claim 10, characterized in that, The step of translating each of the prepared via patterns relative to the second via pattern to obtain the first via pattern includes: Determine the total number of the at least one pre-prepared via pattern generated; Along at least one preset direction, each of the prepared via patterns is translated in a stepwise manner, and the translation efficiency of each stepwise translation is determined. The translation efficiency is equal to the ratio of the number of prepared via patterns that conform to the preset design rules after each stepwise translation to the number of prepared via patterns participating in this translation. Among the prepared via patterns obtained from the translation operation with the highest translation efficiency, the prepared via patterns that conform to the preset design rules are determined as retained patterns, and the prepared via patterns that do not conform to the preset design rules are determined as the remaining prepared via patterns. The position of the retained pattern is fixed, and the process jumps to each of the preset directions along at least one preset direction. Each of the prepared via patterns is translated stepwise, and the translation efficiency of each stepwise translation is determined. The process continues to translate the remaining prepared via patterns stepwise until a preset condition is met. The preset condition includes: the ratio of the cumulative number of retained patterns to the total number of prepared via patterns is greater than a preset ratio threshold, or the number of stepwise translations is greater than a preset number threshold. If the ratio of the cumulative number of reserved patterns to the total number of prepared via patterns is greater than the preset ratio threshold, each of the reserved patterns will be used as the first via pattern.

12. The method according to claim 11, characterized in that, The method further includes: If the ratio of the cumulative number of retained patterns to the total number of prepared via patterns is less than or equal to the preset ratio threshold, a manual verification is prompted.

13. The method according to any one of claims 1 to 8, characterized in that, The step of generating the target layout of the target chip based on the first via pattern and the second metal pattern includes: The target layout of the target chip is generated based on the first via pattern, the second metal pattern, and the original layout information of the target chip.

14. A chip design apparatus, characterized in that, include: An acquisition unit is used to acquire the original layout information of the target chip, wherein the original layout information includes the distribution information of the first metal pattern; The first metal pattern is used to form a first metal layer of the target chip, which is a metal layer used to contact the test probe in the first test of the target chip; The first generation unit is used to generate a first via pattern and a second metal pattern according to the original layout information, wherein the first via pattern conforms to a preset design rule. The first via pattern is used to form a first via of the target chip, the second metal pattern is used to form a second metal layer of the target chip, the first via is used to electrically connect the first metal layer and the second metal layer, wherein the second metal layer is a metal layer used to contact the test probe in the second test of the target chip; The second generation unit is used to generate a target layout of the target chip based on the first via pattern and the second metal pattern. The first generation unit includes: The fourth generation module is used to generate a pre-existing via pattern and a second metal pattern based on the original layout information; The inspection module is used to check whether the prepared via pattern conforms to the preset design rules; The determining module is used to determine the prepared via pattern as the first via pattern when the prepared via pattern conforms to the preset design rules; The original layout information also includes the distribution information of the second via pattern; the second via pattern is used to form the second via of the target chip, and the second via is used to electrically connect the first metal layer to the internal circuit of the target chip; The prepared via pattern is identified based on its own center point coordinates; All the prepared via patterns are equal in size and have the same shape, or each of the prepared via patterns includes at least two categories, and the prepared via patterns under the same category are equal in size and have the same shape; The inspection module is specifically used for at least one of the following: Based on the center point coordinates of each of the prepared via patterns, determine whether the spacing between each of the prepared via patterns conforms to the preset design rules; Based on the center point coordinates of each of the prepared via patterns and the distribution information of the second via pattern, determine whether the spacing between each of the prepared via patterns and the second via pattern conforms to the preset design rules; Based on the center point coordinates of each of the prepared via patterns and the distribution information of the first metal pattern, determine whether the relative positional relationship between each of the prepared via patterns and the first metal pattern conforms to the preset design rules.

15. The apparatus according to claim 14, characterized in that, The number of the first metal patterns is at least one; the first generating unit includes: The first generation module is used to generate the second metal pattern based on the distribution information of each of the first metal patterns; The division module is used to divide each of the first metal patterns into at least two pattern groups based on the distribution information of each of the first metal patterns. The second generation module is used to generate the first via pattern based on each of the pattern groups.

16. The apparatus according to claim 15, characterized in that, The partitioning module is specifically used for: Divide the layer containing each of the first metal patterns into at least two map regions; For each of the layout areas, based on the distribution information of each of the first metal patterns within the layout area, the first metal patterns that are electrically connected to each other are divided into the same pattern group, and the first metal patterns that are not electrically connected to each other are divided into different pattern groups.

17. The apparatus according to claim 16, characterized in that, The second generation module includes: A generation submodule is used to generate at least one pre-existing via pattern for each of the pattern groups, based on the distribution information of each of the first metal patterns in the pattern group. The first inspection submodule is used to check whether the at least one prepared via pattern conforms to the preset design rules within its respective pattern group, and to obtain the first inspection result; The first determining submodule is configured to, when the first inspection result includes a non-compliant via pattern, determine the pattern group corresponding to the non-compliant via pattern as a first pattern group, determine the layout area where the first pattern group is located as a re-inspection layout area, determine the layout area adjacent to the re-inspection layout area as an adjacent layout area, and determine the pattern group in the adjacent layout area as a second pattern group; wherein, the non-compliant via pattern is the prepared via pattern that does not conform to the preset design rules; The second inspection submodule is used to check whether there is an interconnection relationship between the first pattern group and the second pattern group; The correction submodule is used to correct the first inspection result according to the interconnection relationship when there is an interconnection relationship between the first pattern group and any of the second pattern groups, so as to obtain a second inspection result; The second determining submodule is used to determine the prepared via pattern that conforms to the preset design rules in the second inspection result as the first via pattern.

18. The apparatus according to claim 17, characterized in that, The first determining submodule is specifically used for: If the first inspection result includes a non-compliant via pattern and the non-compliant via pattern is located within a first preset range of its respective layout area, the pattern group corresponding to the non-compliant via pattern is determined as the first pattern group, the layout area where the first pattern group is located is determined as the re-inspection layout area, the layout area adjacent to the re-inspection layout area is determined as the adjacent layout area, and the pattern group within a second preset range of the adjacent layout area is determined as the second pattern group.

19. The apparatus according to claim 18, characterized in that, The ratio of the distance from a point within the first preset range to the first edge of the first layout area to the distance from the first edge of the first layout area to the second edge is less than a first ratio threshold; or, the ratio of the distance from a point within the first preset range to the third edge of the first layout area to the distance from the third edge of the first layout area to the fourth edge is less than the first ratio threshold; wherein, the first layout area is the layout area where the non-compliant via pattern is located, the first layout area is a rectangle, the first edge and the second edge are two opposite sides of the rectangle, and the third edge and the fourth edge are two opposite sides of the rectangle; The ratio of the distance from a point within the second preset range to the first edge of the adjacent map region to the distance from the first edge to the second edge of the adjacent map region is less than a second ratio threshold; or, the ratio of the distance from a point within the second preset range to the third edge of the adjacent map region to the distance from the third edge to the fourth edge of the adjacent map region is less than the second ratio threshold; wherein, the adjacent map region is a rectangle, the first edge and the second edge are two opposite sides of the rectangle, and the third edge and the fourth edge are two opposite sides of the rectangle.

20. The apparatus according to claim 17, characterized in that, The correction submodule is specifically used for: The first pattern group and the second pattern group are combined into a single pattern group. It is then determined whether the non-compliant via pattern conforms to the preset design rules within the combined pattern group. If the non-compliant via pattern conforms to the preset design rules within the merged pattern group, the non-compliant via pattern is corrected to the prepared via pattern that conforms to the preset design rules.

21. The apparatus according to claim 17, characterized in that, The second generation module further includes a third determination submodule, used to determine the prepared via pattern that conforms to the preset design rules in the first inspection result as the first via pattern when there is no interconnection relationship between the first pattern group and the second pattern group.

22. The apparatus according to any one of claims 14 to 21, characterized in that, The original layout information also includes the distribution information of the second via pattern; the second via pattern is used to form the second via of the target chip, and the second via is used to electrically connect the first metal layer to the internal circuit of the target chip; The first generation unit is specifically used to generate the first via pattern and the second metal pattern based on the distribution information of the first metal pattern and the distribution information of the second via pattern.

23. The apparatus according to claim 22, characterized in that, The number of the second via pattern is at least one; the first generation unit includes: The third generation module is used to generate the second metal pattern according to the distribution information of the first metal pattern, and to generate at least one pre-via pattern according to the distribution information of the second via pattern, wherein the pre-via pattern corresponds one-to-one with the second via pattern. A translation module is used to obtain the first via pattern by translating each of the prepared via patterns relative to the second via pattern.

24. The apparatus according to claim 23, characterized in that, The translation module includes: The fourth determining submodule is used to determine the total number of the at least one pre-prepared via pattern generated; The translation submodule is used to perform step-by-step translation of each of the prepared via patterns along each of at least one preset direction, and to determine the translation efficiency of each step translation. The translation efficiency is equal to the ratio of the number of prepared via patterns that conform to the preset design rules after each step translation to the number of prepared via patterns participating in this translation. The fifth determining submodule is used to determine, among the prepared via patterns obtained in the translation operation with the greatest translation efficiency, the prepared via patterns that conform to the preset design rules as retained patterns, and the prepared via patterns that do not conform to the preset design rules as the remaining prepared via patterns. A fixing submodule is used to fix the position of the retained pattern; The trigger submodule is used to trigger the translation submodule to continue to perform step-by-step translation on the remaining prepared via patterns until a preset condition is met. The preset condition includes: the ratio of the cumulative number of the retained patterns to the total number of the prepared via patterns is greater than a preset ratio threshold, or the number of step-by-step translations is greater than a preset number threshold. The sixth determining submodule is used to determine each of the reserved patterns as the first via pattern when the ratio of the cumulative number of the reserved patterns to the total number of the prepared via patterns is greater than the preset ratio threshold.

25. The apparatus according to claim 24, characterized in that, The translation module also includes: The prompting submodule is used to prompt for manual verification when the ratio of the cumulative number of retained patterns to the total number of prepared via patterns is less than or equal to the preset ratio threshold.

26. The apparatus according to any one of claims 14 to 21, characterized in that, The second generation unit is specifically used for: The target layout of the target chip is generated based on the first via pattern, the second metal pattern, and the original layout information of the target chip.

27. An electronic device, characterized in that, The electronic device includes: a processor and a memory, wherein the processor is electrically connected to the memory; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to implement the chip design method of any one of claims 1 to 13.

28. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the chip design method of any one of claims 1 to 13.

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