DC bias suppression apparatus, method, and dual active bridge system for dual active bridges

Abstract

The application relates to a DC bias suppression device, method and dual active bridge system for a dual active bridge, comprising: a high-frequency signal detection module receiving a primary side current and a secondary side current of a high-frequency transformer in the dual active bridge, and converting the primary side current and the secondary side current into voltage signals to obtain a primary side current detection signal and a secondary side current detection signal; a peak detection module detecting maximum and minimum values of the primary side current in the primary side current detection signal and maximum and minimum values of the secondary side current in the secondary side current detection signal; a sampling module sampling the maximum and minimum values of the primary side current and the maximum and minimum values of the secondary side current; and a control module used for calculating a difference between a sum of the maximum and minimum values of the primary side current and zero and a difference between a sum of the maximum and minimum values of the secondary side current and zero, and obtaining a duty cycle adjustment amount of a primary side and a duty cycle adjustment amount of a secondary side by using a PI controller, so as to suppress DC bias currents on both sides of the dual active bridge according to the duty cycle adjustment amounts.

Description

Technical Field

[0001] This application relates to the field of DC-DC conversion technology, and in particular to a DC bias suppression device, method and dual active bridge system for dual active bridges. Background Technology

[0002] Dual Active Bridge (DAB) converters play a crucial role in new energy systems, but their performance is also affected by DC bias issues. DC bias is mainly divided into two types: steady-state DC bias and transient DC bias. Steady-state DC bias is usually caused by parameter asymmetry in the circuit and switches, while transient DC bias is caused by phase shift ratio updates. These bias phenomena can lead to increased magnetic circuit losses, increased switching element losses, and even saturation of magnetic components, affecting the stability and reliability of the entire system.

[0003] Conventional DAB (Digital Transformer Absorption Array) devices employ a DC blocking capacitor connected in series in both the primary and secondary high-frequency circuits to suppress DC current bias on the primary and secondary sides, thereby suppressing transformer magnetization. However, at higher power levels, most commercially available capacitors cannot meet the operating conditions of high frequency and high current. Even if they do, the DC blocking capacitors are bulky, which reduces the power density of the device. Therefore, a control method is desired to suppress magnetization.

[0004] Conventional control methods use the controller's analog-to-digital converter (ADC) to sample and calculate the detected high-frequency current signal. However, the high frequency of the current in the ADC is too high, and extracting a small DC bias from a large current requires high accuracy. This poses a great challenge to the sampling frequency and accuracy of the DSP (Digital Signal Processor), and also places high demands on the performance of the sensor and conditioning circuit. Summary of the Invention

[0005] This application provides a DC bias suppression device, method, and dual active bridge system for dual active bridges to solve problems such as steady-state and transient DC bias on the primary and secondary sides of dual active bridge (DAB) devices, the inability of traditional DC blocking capacitors to meet the high current requirements of high-power DAB devices and their large space requirements, and the difficulty in sampling high-frequency current.

[0006] A first aspect of this application provides a DC bias suppression device for a dual active bridge, comprising: a high-frequency signal detection module for receiving the primary and secondary currents of the high-frequency transformer in the dual active bridge, and converting the primary and secondary currents into voltage signals respectively to obtain a primary current detection signal and a secondary current detection signal; and a peak detection module for receiving the primary current detection signal and the secondary current detection signal, and detecting the maximum and minimum values ​​of the primary current and the maximum value of the secondary current based on the primary current detection signal and the secondary current detection signal respectively. The sampling module is used to sample the maximum and minimum values ​​of the primary current and the secondary current output by the peak detection circuit according to a preset sampling strategy; the control module is used to calculate the difference between the sum of the maximum and minimum values ​​of the primary current and zero, and to calculate the difference between the sum of the maximum and minimum values ​​of the secondary current and zero, and to obtain the duty cycle adjustment amount of the primary side and the duty cycle adjustment amount of the secondary side using a preset PI controller, and to adjust the voltage duty cycle of the primary side bridge circuit and the secondary side bridge circuit to suppress the DC bias current of the primary and secondary sides of the dual active bridge.

[0007] Optionally, the peak detection module includes: an upper peak detection circuit for detecting the maximum value of the primary current and the maximum value of the secondary current of the high-frequency transformer in the dual active bridge in each cycle; and a lower peak detection circuit connected to the upper peak detection circuit for detecting the minimum value of the primary current and the minimum value of the secondary current of the high-frequency transformer in the dual active bridge in each cycle.

[0008] Optionally, the peak detection circuit includes: a first resistor, a first-stage amplifier, a second resistor, a first diode, a second diode, a first voltage follower, a third resistor, a fourth resistor, a first capacitor, and a first RST reset device. The non-inverting input of the first-stage amplifier is connected to one end of the first resistor to receive the high-frequency current detection signal. The inverting input of the first-stage amplifier is connected to the anode of the second diode and one end of the second resistor. The output of the first-stage amplifier is connected to the cathode of the second diode and the anode of the first diode. The cathode of the first diode is connected to one end of the third resistor. The non-inverting input of the first voltage follower is connected to the other end of the third resistor, one end of the fourth resistor, and one end of the first capacitor. The inverting input of the first voltage follower is connected to the other end of the second resistor. The output of the first voltage follower is connected to the inverting input. The other end of the first capacitor is grounded. The input of the first RST reset device is connected to the other end of the fourth resistor. The output and ground of the first RST reset device are both connected to and grounded to the other end of the first capacitor.

[0009] Optionally, the lower peak detection circuit includes: a fifth resistor, a second-stage amplifier, a sixth resistor, a third diode, a fourth diode, a second voltage follower, a seventh resistor, an eighth resistor, a second capacitor, and a second RST reset device. The non-inverting input of the second-stage amplifier is connected to one end of the fifth resistor to receive the high-frequency current detection signal. The other end of the fifth resistor is connected to the other end of the first resistor. The inverting input of the second-stage amplifier is connected to the cathode of the fourth diode and one end of the sixth resistor. The output of the second-stage amplifier is connected to the anode of the fourth diode and the cathode of the third diode. The anode of the third diode is connected to one end of the seventh resistor. The non-inverting input of the second voltage follower is connected to the other end of the seventh resistor, one end of the eighth resistor, and one end of the second capacitor. The inverting input of the second voltage follower is connected to the other end of the sixth resistor. The output of the second voltage follower is connected to the inverting input. The other end of the second capacitor is grounded. The input of the second RST reset device is connected to the other end of the eighth resistor. The output and ground of the second RST reset device are both connected to the other end of the second capacitor and grounded.

[0010] Optionally, the control module includes: a calculation submodule, used to calculate the difference between the sum of the maximum and minimum values ​​of the primary current of the high-frequency transformer in the dual active bridge and zero, and to calculate the difference between the sum of the maximum and minimum values ​​of the secondary current of the high-frequency transformer in the dual active bridge and zero.

[0011] Optionally, the control module further includes a PI control submodule connected to the calculation submodule. The PI control submodule includes a first PI controller and a second PI controller, used to input the difference between the sum of the primary currents of the high-frequency transformer in the dual active bridge and zero to the first PI controller to obtain the duty cycle adjustment amount on the primary side, and input the difference between the sum of the secondary currents of the high-frequency transformer in the dual active bridge and zero to the second PI controller to obtain the duty cycle adjustment amount on the secondary side.

[0012] Optionally, the high-frequency signal detection module includes: a current sensor and a sampling resistor, wherein the current sensor is used to convert the primary current and the secondary current into a small-signal current, and the sampling resistor is used to convert the small-signal current into a voltage signal.

[0013] A second aspect of this application provides a DC bias suppression method for a dual active bridge, comprising the following steps: receiving the primary current and secondary current of the high-frequency transformer in the dual active bridge, and converting the primary current and the secondary current into voltage signals respectively to obtain a primary current detection signal and a secondary current detection signal; receiving the primary current detection signal and the secondary current detection signal, and detecting the maximum and minimum values ​​of the primary current and the secondary current respectively based on the primary current detection signal and the secondary current detection signal; and processing the peak detection circuit according to a preset sampling strategy. The maximum and minimum values ​​of the primary current and the secondary current of the high-frequency transformer in the dual active bridge are sampled. The difference between the sum of the maximum and minimum values ​​of the primary current and the minimum value of the high-frequency transformer in the dual active bridge and zero is calculated, and the difference between the sum of the maximum and minimum values ​​of the secondary current and zero is also calculated. The duty cycle adjustment of the primary side and the secondary side is obtained using a preset PI controller, and the voltage duty cycle of the primary and secondary bridge circuits is adjusted to suppress the DC bias current of the primary and secondary sides of the dual active bridge.

[0014] A third aspect of this application provides a dual active bridge system, which includes the DC bias suppression device for dual active bridges described above.

[0015] In the above embodiments, the primary and secondary currents of the high-frequency transformer in the dual active bridge are received by the high-frequency signal detection module, and the primary and secondary currents are converted into voltage signals to obtain primary current detection signals and secondary current detection signals, respectively. The primary and secondary current detection signals are received by the peak detection module, and the maximum and minimum values ​​of the primary current and the secondary current are detected based on the primary and secondary current detection signals, respectively. The maximum and minimum values ​​of the primary current and the secondary current output by the peak detection circuit are sampled by the sampling module according to the preset sampling strategy. The difference between the sum of the maximum and minimum values ​​of the primary current and the secondary current and the zero value is calculated by the control module, and the difference between the sum of the maximum and minimum values ​​of the secondary current and the zero value is calculated by the control module. The duty cycle adjustment amount of the primary side and the secondary side is obtained by the preset PI controller, and the voltage duty cycle of the primary bridge circuit and the secondary bridge circuit is adjusted to suppress the DC bias current of the primary and secondary sides of the dual active bridge. This solves the problems of steady-state and transient DC bias on the primary and secondary sides of dual active bridge DAB devices, the inability of traditional DC blocking capacitors to meet the high current requirements of high-power DAB devices and their large space requirements, and the difficulty in sampling high-frequency currents. It reduces the requirements for the sampling frequency and accuracy of ADC and the calculation speed of DSP, and can replace DC blocking capacitors in a low-cost and better way, improve power density, and achieve the purpose of suppressing DC bias on the primary and secondary sides respectively.

[0016] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0017] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0018] Figure 1 This is a schematic diagram of a non-resonant DAB topology in related technologies;

[0019] Figure 2 This is a schematic diagram showing the relationship between the DAB inductor voltage and current waveforms and the bridge arm voltage during single-phase-shift modulation in related technologies.

[0020] Figure 3 This is a schematic diagram of DC bias caused by primary-side duty cycle deviation in related technologies.

[0021] Figure 4 This is a schematic diagram of DC bias caused by a positive voltage deviation on the primary side in related technologies.

[0022] Figure 5 This is a schematic diagram of the DC bias caused by an increase in the shift ratio in related technologies;

[0023] Figure 6 This is a schematic diagram of a non-resonant DAB topology with a series DC blocking capacitor in related technologies.

[0024] Figure 7 This is a schematic diagram of a DC bias suppression device for a dual active bridge according to an embodiment of this application;

[0025] Figure 8 This is a schematic diagram of an upper and lower peak detection circuit according to an embodiment of this application;

[0026] Figure 9 This is a schematic diagram of the simulation waveform verification of the upper and lower peak detection circuit according to an embodiment of this application;

[0027] Figure 10 This is a schematic flowchart illustrating DC bias suppression of a dual active bridge according to an embodiment of this application.

[0028] Figure 11 A block diagram illustrating DC bias suppression of a dual active bridge according to an embodiment of this application;

[0029] Figure 12 This is a schematic diagram illustrating the variation of the primary-side DC bias current in various methods according to an embodiment of this application;

[0030] Figure 13 This is a flowchart of a DC bias suppression method for a dual active bridge according to an embodiment of this application. Detailed Implementation

[0031] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0032] The following description, with reference to the accompanying drawings, describes a DC bias suppression device, method, and dual active bridge system for dual active bridges according to embodiments of this application. Addressing the issues mentioned in the background art regarding the existence of steady-state and transient DC bias on the primary and secondary sides of dual active bridge DAB devices, the current-resistance of traditional DC blocking capacitors is insufficient to meet the high-current requirements of high-power DAB devices, they occupy large spaces, and high-frequency current is difficult to sample, this application provides a DC bias suppression device for dual active bridges. In this device, a high-frequency signal detection module receives the primary and secondary currents of the high-frequency transformer in the dual active bridge, and converts the primary and secondary currents into voltage signals respectively, obtaining primary current detection signals and secondary current detection signals. A peak detection module receives the primary current detection signals and secondary current detection signals, and based on the primary current detection... The primary and secondary current detection signals detect the maximum and minimum values ​​of the primary and secondary currents, respectively. The sampling module samples the maximum and minimum values ​​of the primary and secondary currents output by the peak detection circuit according to a preset sampling strategy. The control module calculates the difference between the sum of the maximum and minimum values ​​of the primary current and zero, and the difference between the sum of the maximum and minimum values ​​of the secondary current and zero. The preset PI controller is used to obtain the duty cycle adjustment amount of the primary and secondary sides, and the voltage duty cycle of the primary and secondary bridge circuits is adjusted to suppress the DC bias current of the primary and secondary sides of the dual active bridge. This solves the problems of steady-state and transient DC bias on the primary and secondary sides of dual active bridge DAB devices, the inability of traditional DC blocking capacitors to meet the high current requirements of high-power DAB devices and their large space requirements, and the difficulty in sampling high-frequency currents. It reduces the requirements for the sampling frequency and accuracy of ADC and the calculation speed of DSP, and can replace DC blocking capacitors in a low-cost and better way, improve power density, and achieve the purpose of suppressing DC bias on the primary and secondary sides respectively.

[0033] Dual active bridge DAB circuit model as follows Figure 1 As shown, in DAB, the two switches on the same bridge arm are complementary and conduct with a duty cycle of 0.5. The ratio of the phase shift angle of the bridge arm to π is defined as the shift ratio (i.e., the shift ratio ranges from -1 to 1). The shift ratio between the primary bridge arm and the secondary bridge arm is called the external shift ratio. Here, it is agreed that when S1 and Q1 are in phase, the external shift ratio is 0.

[0034] When converter efficiency is not a critical requirement, single-phase shift control (SPS) is typically used to simplify the DAB control strategy. The DAB switching frequency is denoted as f. s Defining the phase shift of Q1 lagging S1 in single-phase-shift control as D, the expression for the inductor current can be derived. The waveforms of the DAB bridge arm voltage, inductor voltage, and inductor current are shown below. Figure 2 Show.

[0035] When the DAB (Diverterless Voltage Buffer) experiences voltage asymmetry and a duty cycle that is not 0.5 due to asymmetry in switching elements, circuit parameters, etc., resulting in an unbalanced volt-second characteristic, it will cause steady-state DC bias, such as... Figure 3 and Figure 4 As shown, when the DAB changes its operating conditions or shift ratio suddenly, a transient DC bias will occur, such as... Figure 5 As shown.

[0036] According to the transformer model, the DC bias currents on the primary and secondary sides of the DAB are independent of each other. Therefore, it is not possible to modify only the duty cycle on the primary side; the DC bias currents on both sides must be suppressed simultaneously.

[0037] To suppress the effects of DC bias, the current mainstream suppression method is to connect a DC blocking capacitor in series on both the primary and secondary sides of the transformer, such as... Figure 6 As shown, the main function of this DC blocking capacitor is to isolate the DC component, ensuring that only the AC component can pass through. However, this method has some obvious limitations. First, it requires a large capacitance value, which not only occupies a lot of space but also reduces the power density of the device. Second, the capacitor connected in series in the circuit needs to handle a large high-frequency AC current, which places high demands on the capacitor and also means that the capacitor's lifespan may limit the lifespan of the entire device. For high-power DAB devices, it is difficult to find capacitors that meet the requirements. In addition, the introduction of the capacitor may also introduce new resonant frequency points in the circuit, which may cause additional electromagnetic interference problems.

[0038] Researchers have proposed several active DC blocking methods, aiming to suppress potential DC bias in circuits by actively adjusting the trigger pulses of switching transistors according to control strategies through the detection, sampling, and calculation of circuit quantities, thus replacing passive DC blocking capacitors. Active DC blocking research is mainly divided into transient DC bias suppression and steady-state DC bias suppression, with transient DC bias suppression being more widely studied. For example, related technologies propose detecting the induced current i (transformer primary or secondary current) and comparing it with upper and lower thresholds. Once i exceeds the design threshold, the comparator output triggers a monostable multivibrator to generate a fixed-width pulse, thereby limiting the shift ratio. This can limit transient DC bias generated by load changes. However, the improvement effect of this type of transient DC bias suppression method mainly optimizes the transient process and is ineffective for steady-state DC bias caused by device parameter imbalances. There are also some control methods for suppressing steady-state DC bias, all of which rely on the detection of high-frequency current or voltage, presenting several challenges: firstly, high requirements for sensor bandwidth and accuracy; secondly, high requirements for ADC sampling frequency and accuracy; and thirdly, high requirements for DSP calculation speed and latency. As proposed in related technologies, the DC bias current is obtained by detecting and integrating the primary and secondary currents. Closed-loop control is used to adjust the duty cycle of the primary and secondary sides, ensuring the integral of the currents within one cycle is zero, thus achieving zero DC bias. This method not only requires high bandwidth and accuracy from the sensor but also high sampling rate and computation speed from the ADC and DSP. Related technologies also propose an improved sensor method that utilizes the principle of magnetic flux cancellation, using a current transformer and a low-range, high-precision current sensor to achieve high-precision DC bias current detection. However, high-frequency, high-current current transformers with a range of 200kHz and 100A or higher are rare on the market, making them difficult to apply in high-frequency, high-power devices. Related technologies also offer an improved sampling rate method, attempting to use a Δ-Σ modulator to achieve a high sampling frequency with low resolution. However, this method results in low data resolution, requires more digital processing power, and has higher latency.

[0039] To address the problems existing in related technologies, this application proposes an active DC blocking method. It uses analog circuits to maintain and sample the peak value of the inductor current and performs feedback control based on the peak value of the inductor current. This avoids the extremely high sampling rate required by the ADC and the large amount of computation required by the DSP. It can replace the DC blocking capacitor in a low-cost and effective way, improve power density, and reduce the requirements for the sampling frequency and accuracy of the ADC and the computation speed requirements of the DSP compared with ordinary active DC blocking methods.

[0040] Specifically, Figure 7 This is a schematic diagram of a DC bias suppression device for a dual active bridge provided in an embodiment of this application.

[0041] like Figure 7As shown, the DC bias suppression device for dual active bridges includes: a high-frequency signal detection module 100, a peak detection module 200, a sampling module 300, and a control module 400.

[0042] The high-frequency signal detection module 100 receives the primary and secondary currents of the high-frequency transformer in the dual active bridge circuit and converts them into voltage signals to obtain primary and secondary current detection signals, respectively. The peak detection module 200 receives the primary and secondary current detection signals and detects the maximum and minimum values ​​of the primary and secondary currents based on these signals. The sampling module 300 is used to sample according to a preset parameters. The strategy samples the maximum and minimum values ​​of the primary current and the secondary current output by the peak detection circuit. The control module 400 calculates the difference between the sum of the maximum and minimum values ​​of the primary current and zero, and calculates the difference between the sum of the maximum and minimum values ​​of the secondary current and zero. It also uses a preset PI controller to obtain the duty cycle adjustment amount of the primary side and the duty cycle adjustment amount of the secondary side, and adjusts the voltage duty cycle of the primary and secondary bridge circuits to suppress the DC bias current of the primary and secondary sides of the dual active bridge.

[0043] In some embodiments, the high-frequency signal detection module 100 includes a current sensor and a sampling resistor. The current sensor is used to convert the primary current and secondary current into a small-signal current, and the sampling resistor is used to convert the small-signal current into a voltage signal.

[0044] Optionally, in some embodiments, the peak detection module 200 includes: an upper peak detection circuit for detecting the maximum value of the primary current and the maximum value of the secondary current of the high-frequency transformer in the dual active bridge in each cycle; and a lower peak detection circuit connected to the upper peak detection circuit for detecting the minimum value of the primary current and the minimum value of the secondary current of the high-frequency transformer in the dual active bridge in each cycle.

[0045] Alternatively, in some embodiments, such as Figure 8As shown, the peak detection circuit includes: a first resistor, a first-stage amplifier A1, a second resistor, a first diode D1, a second diode D2, a first voltage follower A2, a third resistor, a fourth resistor, a first capacitor C1, and a first RST reset device. The non-inverting input of the first-stage amplifier A1 is connected to one end of the first resistor to receive the high-frequency current detection signal. The inverting input of the first-stage amplifier A1 is connected to the anode of the second diode D2 and one end of the second resistor. The output of the first-stage amplifier A1 is connected to the cathode of the second diode D2 and the first resistor, respectively. The anode of D1 is connected, the cathode of the first diode D1 is connected to one end of the third resistor, the non-inverting input of the first voltage follower A2 is connected to the other end of the third resistor, one end of the fourth resistor and one end of the first capacitor C1, the inverting input of the first voltage follower A2 is connected to the other end of the second resistor, the output of the first voltage follower A2 is connected to the inverting input, the other end of the first capacitor C1 is grounded, the input of the first RST reset device is connected to the other end of the fourth resistor, and the output and ground of the first RST reset device are both connected to the other end of the first capacitor C1 and grounded.

[0046] Alternatively, in some embodiments, such as Figure 8 As shown, the lower peak detection circuit includes: a fifth resistor, a second-stage amplifier A3, a sixth resistor, a third diode D3, a fourth diode D4, a second voltage follower A4, a seventh resistor, an eighth resistor, a second capacitor C2, and a second RST reset device. The non-inverting input of the second-stage amplifier A3 is connected to one end of the fifth resistor to receive the high-frequency current detection signal. The other end of the fifth resistor is connected to the other end of the first resistor. The inverting input of the second-stage amplifier A3 is connected to the cathode of the fourth diode D4 and one end of the sixth resistor. The output of the second-stage amplifier A3 is connected to the fourth diode D4. The anode of the first diode and the cathode of the third diode D3 are connected together. The anode of the third diode D3 is connected to one end of the seventh resistor. The non-inverting input of the second voltage follower A4 is connected to the other end of the seventh resistor, one end of the eighth resistor, and one end of the second capacitor C2. The inverting input of the second voltage follower A4 is connected to the other end of the sixth resistor. The output of the second voltage follower A4 is connected to the inverting input. The other end of the second capacitor C2 is grounded. The input of the second RST reset device is connected to the other end of the eighth resistor. The output and ground of the second RST reset device are both connected to the other end of the second capacitor C2 and grounded.

[0047] In peak detection circuits, such as Figure 8 As shown, the upper part is the upper peak detection circuit, and the lower part is the lower peak detection circuit. Taking the upper peak detection circuit as an example, when a high-frequency current detection signal u is input... ihfDuring the rise, the current passes through the first-stage amplifier A1 and the first diode D1 (Schottky diode) to charge the first capacitor C1. The voltage of the first capacitor C1 is output through the first voltage follower A2 on the right, ensuring that the capacitor voltage is consistent with the input voltage. When the high-frequency current detection signal u is input... ihf During the voltage drop, the first diode D1 ensures that the capacitor current cannot flow back, and the first capacitor C1 cannot discharge, thus maintaining the peak voltage. The upper peak signal is denoted as u. ippeak .

[0048] The second diode D2 (Schottky diode), connected in parallel with the inverting input and output of the first-stage amplifier A1, prevents the first-stage operational amplifier A1 from remaining in negative saturation for an extended period when the input voltage drops. Instead, it ensures the amplifier continues to follow the input signal. When peak detection is performed again to charge the first capacitor C1, the output voltage of the first-stage amplifier A1 does not need to start rising from negative saturation, thus reducing the voltage rise time and accelerating the response speed. The lower peak detection circuit reverses the diode direction, operating on the same principle as the upper peak detection circuit. Figure 9 As shown, Figure 9 The effect of the peak detection circuit under a 20kHz waveform is shown. It can be seen that the peak detection circuit can perform peak holding, reset and multiple detections.

[0049] Optionally, in some embodiments, the control module 400 includes: a calculation submodule, used to calculate the difference between the sum of the maximum and minimum values ​​of the primary current of the high-frequency transformer in the dual active bridge and zero, and to calculate the difference between the sum of the maximum and minimum values ​​of the secondary current of the high-frequency transformer in the dual active bridge and zero.

[0050] Optionally, in some embodiments, the control module 400 further includes: a PI control submodule connected to the calculation submodule. The PI control submodule includes a first PI controller and a second PI controller, used to input the difference between the sum of the primary currents of the high-frequency transformer in the dual active bridge and zero to the first PI controller to obtain the duty cycle adjustment amount on the primary side, and input the difference between the sum of the secondary currents of the high-frequency transformer in the dual active bridge and zero to the second PI controller to obtain the duty cycle adjustment amount on the secondary side.

[0051] To address the problems existing in dual active bridge (DAB) circuits, such as steady-state and transient DC bias, insufficient current withstand capability of DC blocking capacitors with large space requirements, and difficulty in sampling high-frequency current, this application proposes a novel DC bias suppression device. It uses analog circuits to realize peak detection of high-frequency circuits on the primary and secondary sides, and uses PI control to adjust the duty cycle to achieve the purpose of suppressing DC bias on the primary and secondary sides respectively.

[0052] Since the DC bias currents on the primary and secondary sides of the high-frequency transformer in DAB are independent, it is necessary to simultaneously detect and suppress the DC bias currents on both sides. Specific suppression methods are as follows: Figure 10 As shown.

[0053] In this embodiment, the high-frequency high-current on the primary side and the high-frequency high-current on the secondary side of the high-frequency transformer in the dual active bridge are converted into small-signal currents by the current sensor in the high-frequency signal detection module 100. Then, the small-signal currents are converted into voltage signals by the sampling resistor to obtain the primary-side current detection signal and the secondary-side current detection signal.

[0054] Normal operating DAB high-frequency current, such as Figure 2 As shown, the average value of the current in each cycle is the DC bias current. However, the DC bias is calculated by integrating the current waveform within a cycle, which places high demands on the accuracy and calculation speed of the sensor and ADC, and may lead to large errors. Note that when there is no DC bias, the positive and negative half-cycle current waveforms of the primary and secondary current waveforms in each cycle are symmetrical. Therefore, it is only necessary to use a peak detection circuit to sample the peak values ​​of the positive and negative half-cycles and make their sum zero to ensure that the DC bias is zero.

[0055] The primary and secondary current detection signals are sent to the peak detection circuit. The peak detection circuit needs to re-detect at regular intervals, therefore a switch is required to periodically reset the capacitor voltage to zero. Considering that peak detection must complete at least one full cycle, and the capacitor discharge takes time, in every two switching cycles, the first switching cycle completes one detection, and the second cycle resets the capacitor to zero. This process is repeated, allowing the maximum and minimum values ​​of the high-frequency current on the primary and secondary sides to be detected every two switching cycles.

[0056] After the peak detection circuit holds the maximum and minimum values ​​of the primary current and the secondary current, the analog-to-digital converter (ADC) of the DAB controller (i.e., the sampling circuit) samples the maximum and minimum values ​​of the primary current and the secondary current output by the peak detection circuit according to the preset sampling strategy. Specifically, an ADC needs to perform sampling at least once every two cycles, which greatly reduces the requirement for the ADC sampling frequency.

[0057] The maximum value i of the primary current is obtained by sampling. ppeak and minimum value i npeak With the maximum value of the secondary current i ppeak and minimum value i npeak The maximum and minimum values ​​of the primary current are summed, and the sum is compared with zero. The result is then sent to the first PI controller, and the output is the duty cycle adjustment dDuty1 of the primary side. Specifically, as follows... Figure 11As shown, adjusting the duty cycle of the primary side bridge circuit output voltage can suppress the DC current bias on the primary side. Similarly, the sum of the maximum and minimum values ​​of the secondary side current is compared with zero and sent to the second PI controller, which outputs the duty cycle adjustment value dDuty2 on the secondary side. By adjusting the duty cycle of the secondary side bridge circuit, the DC bias current on the primary and secondary sides can be suppressed respectively, thus achieving the purpose of suppressing magnetic bias.

[0058] Furthermore, this application embodiment also establishes a simulation model to verify the effectiveness of the proposed control method. A 1V DC bias voltage is applied to the primary side at 0.1s, and a 1V DC bias voltage is applied to the secondary side at 0.2s. Schematic diagrams of the primary side DC bias current obtained by the three methods are shown. Figure 12 (a) is a schematic diagram of the primary-side DC bias current without suppression measures. Figure 12 (b) is a schematic diagram of the DC bias current of the primary side of a DC blocking capacitor connected in series between the primary and secondary sides. Figure 12 (c) is a schematic diagram of the primary side DC bias current using the active DC blocking method proposed in the embodiments of this application. Simulation results show that the proposed active DC blocking method can achieve a better suppression effect and replace the DC blocking capacitor.

[0059] According to the DC bias suppression device for a dual active bridge proposed in this application, a high-frequency signal detection module receives the primary and secondary currents of the high-frequency transformer in the dual active bridge and converts them into voltage signals to obtain primary and secondary current detection signals. A peak detection module receives the primary and secondary current detection signals and detects the maximum and minimum values ​​of the primary and secondary currents based on them. A sampling module samples the maximum and minimum values ​​of the primary and secondary currents output by the peak detection circuit according to a preset sampling strategy. A control module calculates the difference between the sum of the maximum and minimum values ​​of the primary current and zero, and the difference between the sum of the maximum and minimum values ​​of the secondary current and zero. A preset PI controller is used to obtain the duty cycle adjustment amount of the primary side and the secondary side, and the voltage duty cycle of the primary and secondary bridge circuits is adjusted to suppress the DC bias current of the primary and secondary sides of the dual active bridge. This solves the problems of steady-state and transient DC bias on the primary and secondary sides of dual active bridge DAB devices, the inability of traditional DC blocking capacitors to meet the high current requirements of high-power DAB devices and their large space requirements, and the difficulty in sampling high-frequency currents. It reduces the requirements for the sampling frequency and accuracy of ADC and the calculation speed of DSP, and can replace DC blocking capacitors in a low-cost and better way, improve power density, and achieve the purpose of suppressing DC bias on the primary and secondary sides respectively.

[0060] Next, referring to the accompanying drawings, a DC bias suppression method for a dual active bridge proposed according to an embodiment of this application is described.

[0061] Figure 13 This is a flowchart illustrating a DC bias suppression method for a dual active bridge according to an embodiment of this application.

[0062] like Figure 13 As shown, the DC bias suppression method for a dual active bridge includes the following steps:

[0063] In step S1301, the primary current and secondary current of the high-frequency transformer in the dual active bridge are received, and the primary current and secondary current are converted into voltage signals respectively to obtain the primary current detection signal and the secondary current detection signal.

[0064] In step S1302, the primary current detection signal and the secondary current detection signal are received, and the maximum and minimum values ​​of the primary current and the secondary current are detected based on the primary current detection signal and the secondary current detection signal, respectively.

[0065] In step S1303, the maximum and minimum values ​​of the primary current of the high-frequency transformer in the dual active bridge output by the peak detection circuit and the maximum and minimum values ​​of the secondary current of the high-frequency transformer in the dual active bridge are sampled according to the preset sampling strategy.

[0066] In step S1304, the difference between the sum of the maximum and minimum values ​​of the primary current of the high-frequency transformer in the dual active bridge and zero is calculated, and the difference between the sum of the maximum and minimum values ​​of the secondary current of the high-frequency transformer in the dual active bridge and zero is calculated. The duty cycle adjustment of the primary side and the duty cycle adjustment of the secondary side are obtained using a preset PI controller, and the voltage duty cycle of the primary bridge circuit and the secondary bridge circuit is adjusted to suppress the DC bias current of the primary and secondary sides of the dual active bridge.

[0067] It should be noted that the foregoing explanation of the DC bias suppression device embodiment for dual active bridges also applies to the DC bias suppression method for dual active bridges in this embodiment, and will not be repeated here.

[0068] According to the DC bias suppression method for a dual active bridge proposed in this application, the primary and secondary currents of the high-frequency transformer in the dual active bridge are received, and the primary and secondary currents are converted into voltage signals respectively to obtain primary current detection signals and secondary current detection signals. The method receives the primary and secondary current detection signals and, based on these signals, detects the maximum and minimum values ​​of the primary and secondary currents respectively. The peak detection circuit outputs the high-frequency transformer in the dual active bridge according to a preset sampling strategy. The maximum and minimum values ​​of the primary current and the secondary current of the high-frequency transformer in the dual active bridge are sampled. The difference between the sum of the maximum and minimum values ​​of the primary current and the zero value of the secondary current is calculated. A preset PI controller is used to obtain the duty cycle adjustment values ​​for the primary and secondary sides, and the voltage duty cycles of the primary and secondary bridge circuits are adjusted to suppress the DC bias current on both the primary and secondary sides of the dual active bridge. This solves the problems of steady-state and transient DC bias on the primary and secondary sides of the dual active bridge DAB device, the inability of traditional DC blocking capacitors to meet the high current requirements of high-power DAB devices and their large space requirements, and the difficulty in sampling high-frequency current. It reduces the requirements for the sampling frequency and accuracy of the ADC and the calculation speed of the DSP, and can replace the DC blocking capacitor at low cost and effectively, improving power density and achieving the goal of suppressing the DC bias on both the primary and secondary sides.

[0069] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0070] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0071] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or N executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

Claims

1. A DC bias suppression device for a dual active bridge, characterized in that, include: The high-frequency signal detection module is used to receive the primary current and secondary current of the high-frequency transformer in the dual active bridge, and convert the primary current and the secondary current into voltage signals respectively to obtain the primary current detection signal and the secondary current detection signal. A peak detection module is used to receive the primary-side current detection signal and the secondary-side current detection signal, and to detect the maximum and minimum values ​​of the primary-side current and the secondary-side current based on the primary-side current detection signal and the secondary-side current detection signal, respectively. The sampling module is used to sample the maximum and minimum values ​​of the primary current and the secondary current output by the peak detection module according to a preset sampling strategy. The control module is used to calculate the difference between the sum of the maximum and minimum values ​​of the primary current and zero, and to calculate the difference between the sum of the maximum and minimum values ​​of the secondary current and zero. It also uses a preset PI controller to obtain the duty cycle adjustment amount of the primary side and the duty cycle adjustment amount of the secondary side, and adjusts the voltage duty cycle of the primary side bridge circuit and the secondary side bridge circuit to suppress the DC bias current of the primary and secondary sides of the dual active bridge. The peak detection module includes: The upper peak detection circuit is used to detect the maximum value of the primary current of the high-frequency transformer in the dual active bridge and the maximum value of the secondary current of the high-frequency transformer in the dual active bridge in each cycle. A lower peak detection circuit, connected to the upper peak detection circuit, is used to detect the minimum value of the primary current and the minimum value of the secondary current of the high-frequency transformer in the dual active bridge in each cycle.

2. The apparatus according to claim 1, characterized in that, The upper peak detection circuit includes: The circuit comprises a first resistor, a first-stage amplifier, a second resistor, a first diode, a second diode, a first voltage follower, a third resistor, a fourth resistor, a first capacitor, and a first RST reset element, wherein... The non-inverting input of the first stage amplifier is connected to one end of the first resistor to receive a high-frequency current detection signal. The inverting input of the first stage amplifier is connected to the anode of the second diode and one end of the second resistor. The output of the first stage amplifier is connected to the cathode of the second diode and the anode of the first diode. The cathode of the first diode is connected to one end of the third resistor. The non-inverting input of the first voltage follower is connected to the other end of the third resistor, one end of the fourth resistor, and one end of the first capacitor. The inverting input of the first voltage follower is connected to the other end of the second resistor. The output of the first voltage follower is connected to the inverting input. The other end of the first capacitor is grounded. The input of the first RST reset device is connected to the other end of the fourth resistor. The output and ground of the first RST reset device are both connected to the other end of the first capacitor and grounded.

3. The apparatus according to claim 2, characterized in that, The lower peak detection circuit includes: Fifth resistor, second-stage amplifier, sixth resistor, third diode, fourth diode, second voltage follower, seventh resistor, eighth resistor, second capacitor, and second RST reset device. In this configuration, the non-inverting input of the second-stage amplifier is connected to one end of the fifth resistor to receive the high-frequency current detection signal. The other end of the fifth resistor is connected to the other end of the first resistor. The inverting input of the second-stage amplifier is connected to the cathode of the fourth diode and one end of the sixth resistor. The output of the second-stage amplifier is connected to the anode of the fourth diode and the cathode of the third diode. The anode of the third diode is connected to one end of the seventh resistor. The non-inverting input of the second voltage follower is connected to the other end of the seventh resistor, one end of the eighth resistor, and one end of the second capacitor. The inverting input of the second voltage follower is connected to the other end of the sixth resistor. The output of the second voltage follower is connected to the inverting input. The other end of the second capacitor is grounded. The input of the second RST reset device is connected to the other end of the eighth resistor. The output and ground of the second RST reset device are both connected to the other end of the second capacitor and grounded.

4. The apparatus according to claim 1, characterized in that, The control module includes: The calculation submodule is used to calculate the difference between the sum of the maximum and minimum values ​​of the primary current of the high-frequency transformer in the dual active bridge and zero, and to calculate the difference between the sum of the maximum and minimum values ​​of the secondary current of the high-frequency transformer in the dual active bridge and zero.

5. The apparatus according to claim 4, characterized in that, The control module further includes: The PI control submodule connected to the calculation submodule includes a first PI controller and a second PI controller. The first PI controller is used to input the difference between the sum of the primary currents of the high-frequency transformer in the dual active bridge and zero to the first PI controller to obtain the duty cycle adjustment amount on the primary side, and the second PI controller is used to input the difference between the sum of the secondary currents of the high-frequency transformer in the dual active bridge and zero to the second PI controller to obtain the duty cycle adjustment amount on the secondary side.

6. The apparatus according to claim 1, characterized in that, The high-frequency signal detection module includes: A current sensor and a sampling resistor are provided, wherein the current sensor is used to convert the primary current and the secondary current into a small-signal current, and the sampling resistor is used to convert the small-signal current into a voltage signal.

7. A dual active bridge system, characterized in that, Includes a DC bias suppression device for a dual active bridge as described in any one of claims 1 to 6.

8. A method for suppressing DC bias in a dual active bridge, characterized in that, The DC bias suppression device for a dual active bridge as described in any one of claims 1-6 comprises the following steps: The primary and secondary currents of the dual active bridge high-frequency transformer are received, and the primary and secondary currents are converted into voltage signals respectively to obtain the primary current detection signal and the secondary current detection signal. Receive the primary-side current detection signal and the secondary-side current detection signal, and detect the maximum and minimum values ​​of the primary-side current and the secondary-side current based on the primary-side current detection signal and the secondary-side current detection signal, respectively; According to the preset sampling strategy, the maximum and minimum values ​​of the primary current and the secondary current of the high-frequency transformer in the dual active bridge output by the peak detection module are sampled. The difference between the sum of the maximum and minimum values ​​of the primary current of the high-frequency transformer in the dual active bridge and zero is calculated, and the difference between the sum of the maximum and minimum values ​​of the secondary current of the high-frequency transformer in the dual active bridge and zero is also calculated. The duty cycle adjustment of the primary side and the secondary side is obtained using a preset PI controller, and the voltage duty cycle of the primary and secondary bridge circuits is adjusted to suppress the DC bias current of the primary and secondary sides of the dual active bridge.

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