A non-volatile storage unit and memory thereof

Abstract

The present application relates to a non-volatile memory cell and a memory thereof, wherein the memory cell comprises: a first well and a second well of different types adjacently arranged; a first transistor located in the first well, the first transistor comprising a floating gate and a gate oxide thereof; a capacitor located in the second well, the capacitor comprising a coupling region located in the second well, the floating gate and the gate oxide thereof extending from the first well to the second well, forming the gate and the gate oxide thereof of the capacitor; the floating gate comprises two electrically different parts, a PN junction is formed at the junction of the two parts, and the distance between the PN junction and the adjacent floating gate end is less than 150nm. The PN junction in the floating gate of the memory cell of the present application is adjacent to the floating gate end, which can weaken or eliminate the adverse effect of the PN junction on the floating gate, increase the coupling potential obtained by the floating gate, improve the uniformity and stability of the coupling potential obtained by the floating gate, and help improve the stability and reliability of the memory.

Description

Technical Field

[0001] The present invention generally relates to a nonvolatile storage unit and a memory thereof, and in particular to a multi-time electrically programmable and erasable nonvolatile storage unit and a memory thereof. Background Art

[0002] As semiconductor manufacturing processes continue to scale down, the number of transistors integrated on silicon chips continues to increase. Integrating the entire system onto a single chip enables many applications. However, multiple systems contain many independent components, such as EEPROM, DRAM, and FLASH, which are generally manufactured using special processes. These special processes are incompatible with the general logic processes used to prepare logic components such as microprocessors and system logic devices.

[0003] In order to integrate these special memory parts (such as EEPROM, DRAM and FLASH) under the logic process, it is usually necessary to add additional manufacturing processes based on the original logic process. The added process steps will increase the manufacturing cost of the entire chip, including the logic circuit part, which is inconsistent with the chip manufacturers' usual compression of the manufacturing process to the maximum extent. Based on this, the memory circuit needs to be designed to be compatible with the logic process, especially for chips where the logic circuit occupies most of the area, this compatibility becomes particularly necessary.

[0004] A logic process is used to prepare a non-volatile memory (such as EEPROM and FLASH) compatible with it, wherein an effective scheme and structure is described in US7983081B2: a deep well is used to isolate the storage unit from the substrate, and the substrate is grounded or 0v in most cases; the storage unit includes a MOS transistor and a MOS capacitor, which are respectively constructed in two different types of wells, and the two wells are adjacent and placed in the deep well; the transistor and the capacitor share a floating gate and a gate oxide layer below it; the MOS capacitor includes a lightly doped region located in the well and an adjacent coupling region; the end of the shared floating gate close to the capacitor partially overlaps with the lightly doped region of the capacitor in the well, and the structure of the coupling capacitor consists of a floating gate of the capacitor doped region in the partially overlapping well and the gate oxide and MOS channel below it; the coupling region of the capacitor connects the control word line (CWL) to the control gate of the storage unit, and the control gate is formed by the channel region of the MOS capacitor. In order to improve the efficiency of the coupling gate, the coupling capacitor needs to be much larger than the capacitance of the MOS gate.

[0005] This solution is compatible with logic processes, does not require special circuits, is simple to prepare, and has a small storage unit size and excellent performance. However, in this structure, since the MOS transistor and the MOS capacitor share a floating gate, the two ends of the floating gate are adjacent to the transistor active area and the capacitor active area with different electrical properties in different wells. When the active area is formed, the corresponding doping ions will penetrate from the side of the floating gate adjacent to the active area, resulting in the formation of two parts with different electrical properties in the floating gate, and a PN junction is formed at the junction of the two parts, making the potential in the floating gate unstable, thereby affecting the performance, stability and reliability of the storage unit and its memory during operation.

[0006] Therefore, a new nonvolatile storage unit and memory thereof that can solve the above problems are needed. Summary of the invention

[0007] The first aspect of the present application relates to a non-volatile memory cell, which comprises: a first well and a second well of different types adjacently juxtaposed; a first transistor located in the first well, the first transistor comprising a floating gate and a gate oxide thereof; a capacitor located in the second well, the capacitor comprising a coupling region located in the second well, the floating gate and the gate oxide thereof extending from the first well to the second well, constituting the gate and the gate oxide thereof of the capacitor; the floating gate comprising two electrically different portions, the junction of the two electrically different portions being adjacent to one end of the floating gate, the distance between the junction and the adjacent floating gate end being less than 150nm, preferably the distance being 5-100nm, more preferably 10-70nm.

[0008] In a preferred embodiment, the floating gate end adjacent to the junction of the two electrically different portions of the floating gate is the end of the floating gate close to the capacitor and away from the first transistor. More preferably, the first transistor includes a source and a drain, each of which includes a heavily doped ion region, and / or the coupling region of the capacitor is a lightly doped ion region.

[0009] In another preferred embodiment, the non-volatile memory cell further comprises a second transistor, which is of the same type as the first transistor, is co-located in the first well, and is connected in series with the first transistor.

[0010] In another preferred embodiment, the first well and the second well in the nonvolatile memory cell are respectively an N well and a P well, the first transistor is a PMOS transistor, the capacitor is an NMOS capacitor, and the coupling region of the capacitor in the second well is an N coupling region.

[0011] The second aspect of the present application relates to a non-volatile memory, which comprises: at least one of the above-mentioned non-volatile memory cells constructed on a substrate, the substrate comprising a deep well, the first well and the second well in the non-volatile memory cell being located in the deep well. Preferably, the substrate is a P-type substrate, the deep well is a deep N-well, the first well and the second well are respectively an N-well and a P-well, the first transistor is a PMOS transistor, the capacitor is an NMOS capacitor, and the coupling region of the capacitor in the second well is an N-coupling region.

[0012] In a preferred embodiment, the non-volatile memory is a multi-time electrically programmable and erasable non-volatile memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A top view of a non-volatile memory cell in one embodiment of the present invention is shown.

[0014] Figure 2 Shows Figure 1 A cross-sectional view of a memory cell along section line AA in the illustrated embodiment.

[0015] Figure 3 Shows Figure 1 A cross-sectional view of a memory cell along section line BB in the illustrated embodiment.

[0016] Figure 4 Shows Figure 1 A cross-sectional view of a memory cell along section line CC in the illustrated embodiment.

[0017] Figure 5 Shows Figure 1 A partial top view of the memory cell including the floating gate is shown.

[0018] Figure 6 Shows the structure and Figure 1 A partial top view of a floating gate of a prior art memory cell similar to the memory cell shown.

[0019] Figure 7 Shows Figure 5-6 The volt-ampere characteristic curves of the floating gate of the two memory cells are shown.

[0020] Figure 8-10 They are shown respectively Figure 1 The steps for forming the active area of ​​the memory cell are shown in sequence.

[0021] Figure numerals: 100-storage cell; 101-substrate; 102-N well; 103-P well; 104-deep N well; 110-first transistor; 111-source, 111A-source lightly doped region, 111B-source heavily doped P+ contact region; 112-drain, 112A-drain lightly doped region, 112B-drain heavily doped P+ contact region; 113-channel; 114-thick field oxide; 115-gate oxide; 116-floating gate; 117-sidewall isolation; 120-capacitor; 121-capacitor channel region; 122-capacitor active region.

[0022] The same numbers in the drawings indicate the same or similar elements. DETAILED DESCRIPTION

[0023] The nonvolatile storage unit and the memory thereof of the present application are preferably a nonvolatile storage unit and the memory thereof which are electrically programmable and erasable multiple times.

[0024] In the non-volatile memory cell described in the present application, the first transistor includes a floating gate and a gate oxide thereunder, and the floating gate is preferably a polysilicon gate. The floating gate and its gate oxide extend from the first well to the second well, forming the gate and its gate oxide of the capacitor. The floating gate slightly overlaps the edge portion of the active area (capacitive coupling area) in the second well. The capacitive coupling area connects the control word line (WL) to the control gate of the memory cell. The control gate is formed by the channel area of ​​the capacitor. Thus, the structure of the coupling capacitor consists of a floating gate slightly overlapping the active area in the second well, a gate oxide thereunder, and a capacitor channel. In order to improve the efficiency of the coupling gate, the coupling capacitor is made much larger than the capacitance of the first transistor gate.

[0025] The programming and erasing of the memory cell are performed in the first transistor, and the programming is performed by tunneling hot electrons (or holes) from the first transistor channel to the floating gate. The erasing operation is based on the FN tunneling mechanism, which tunnels electrons (or holes) in the floating gate into the channel. The tunneling oxide used for both programming and erasing operations is the gate oxide located above the channel region of the first transistor. In operation, the potential applied to the capacitive coupling region by the control word line is capacitively coupled to the floating gate, so that the floating gate obtains the required potential.

[0026] In the prior art, in a non-volatile memory cell with a structure similar to that of the present application, a first transistor and a capacitor located in different types of wells share a floating gate, and the source and drain of the first transistor have different electrical properties from the coupling region of the capacitor. When doping ions are injected into the active region on both sides of the floating gate to form the coupling region of the source and drain of the transistor and the capacitor, the side of the floating gate adjacent to the active region will infiltrate the corresponding doping ions, resulting in the formation of two parts of the floating gate with different electrical properties, and a PN junction is formed at the junction of the two parts (approximately in the middle of the floating gate). In particular, in the case where the source and drain of the first transistor and the capacitor coupling region contain a heavily doped ion region, it is necessary to repeatedly inject doping ions into the predetermined active region on both sides of the floating gate during the preparation process, so that more doping ions are infiltrated into the side of the floating gate, and a larger PN junction is formed in the floating gate. When the memory cell is working, an electric potential is applied to the capacitor coupling region, and the coupling capacitor is larger than the gate capacitance of the first transistor, thereby coupling the applied electric potential to the floating gate through the capacitor, so that the floating gate obtains the required electric potential. The existence of the PN junction in the middle of the floating gate makes the floating gate body no longer a net electrically P-type or N-type gate, and there is an internal electric field in the PN junction in the floating gate, which causes the coupling potential obtained by the floating gate and its uniformity to decrease, and the stability of the coupling potential also decreases.

[0027] The present application moves the position of the junction (PN junction) of two different electrical properties in the floating gate from the middle of the floating gate to the end of the floating gate, so that the floating gate body presents a P or N net electrical property, thereby weakening or eliminating the adverse effects of the PN junction on the floating gate. The PN junction can be located at the end of the floating gate adjacent to the capacitor side or the end adjacent to the first transistor side, preferably adjacent to the end of the capacitor side.

[0028] The PN junction in the floating gate of the present application is made adjacent to one end of the floating gate, which can be achieved by the following method:

[0029] The source and drain of the first transistor and the capacitor coupling region are respectively located in the active regions of their respective wells, and there is a thick field oxide (FOX) isolation region between the two active regions for isolation, and the thick field oxide isolation region is located at the junction of the two wells. In the process of preparing the memory cell, when forming the active region of the capacitor and the first transistor, the boundary of the adjacent isolation region of the capacitor active region is close to the capacitor side end of the floating gate, or the boundary of the adjacent isolation region of the first transistor active region is close to the first transistor side end of the floating gate, and the corresponding ion implantation of the predetermined region is performed accordingly to realize that the PN junction in the floating gate is close to the end of the floating gate.

[0030] The nonvolatile memory cell of the present invention comprises: a first well and a second well of different types adjacently arranged, wherein a first transistor and a capacitor are respectively located in the first well and the second well, wherein the first transistor and the capacitor share a floating gate and a gate oxide thereof, wherein the floating gate comprises two parts with different electrical properties, wherein a junction (i.e., a PN junction) between the two parts is adjacent to an end of the floating gate, and a distance between the junction (PN junction) and the adjacent floating gate end is greater than 0 and less than 150 nm, preferably 2-130 nm, more preferably 5-100 nm, and even more preferably 10-70 nm.

[0031] The distance between the PN junction in the floating gate and the adjacent floating gate end refers to the distance along the length direction of the floating gate. The length direction of the floating gate is the direction from the first transistor side end to the capacitor side end of the floating gate, which is perpendicular to the length direction of the first transistor (the direction from the source to the drain of the first transistor).

[0032] In the present application, the length of the floating gate, that is, the length from the first transistor-side end to the capacitor-side end of the floating gate, is 1000-6000 nm.

[0033] The PN junction in the floating gate may be adjacent to either of the two ends of the floating gate, preferably the end of the floating gate adjacent to the capacitor side, that is, the end of the floating gate close to the capacitor and away from the first transistor.

[0034] The first embodiment of the present application relates to a storage unit: the PN junction in the floating gate is adjacent to the end of the capacitor side of the floating gate, wherein the source and drain of the first transistor preferably each contain a heavily doped ion region, or the coupling region of the capacitor is a lightly doped ion region. This can further enhance the net electrical properties of the floating gate body, and the net electrical properties of the floating gate body are the same as the type of heavily doped ions in the source and drain of the first transistor. It is more preferred that the source and drain of the first transistor each contain a heavily doped ion region, and the coupling region of the capacitor is a lightly doped ion region.

[0035] In this embodiment, it is also preferred that: the first well and the second well are respectively an N well and a P well, the first transistor is a PMOS transistor, the source and drain include a P+ heavily doped ion region, the capacitor is an NMOS capacitor, and its coupling region in the second well is an N-type lightly doped ion region. In this case, the PN junction in the floating gate is adjacent to the end of the floating gate close to the capacitor, and the floating gate body is P+ net electrical. The working mode of the memory cell is as follows: when the memory cell is programmed, a positive potential is applied to the N coupling region of the NMOS capacitor, and the floating gate with a main body of P+ net electrical property is forward biased through capacitive coupling; opposite potentials are applied to the source and drain of the PMOS transistor, so that a strong lateral electric field is formed between the source and drain, and holes are accelerated along the channel of the first transistor in the strong electric field, and collision ionization occurs in the drain depletion region, and the generated hot electrons are attracted by the forward biased floating gate and injected into the floating gate. The electrons are injected into the floating gate, resulting in a decrease in the threshold voltage of the PMOS transistor, making it easy to turn on, and causing the read current during the read operation to increase. When the memory cell is erased, a negative potential is applied to the N coupling region of the NMOS capacitor, and the floating gate with a P+ net electrical property obtains the required negative potential through capacitive coupling: its absolute value is smaller than the potential value applied by the capacitive coupling region; the same positive potential is applied to the source and drain of the PMOS transistor, thereby forming a high electric field on both sides of the gate oxide layer of the first transistor, which is sufficient to cause the electrons trapped in the floating gate to tunnel into the channel of the PMOS transistor. The electrons are removed from the floating gate, causing the threshold voltage of the first transistor to increase, making it difficult to turn on, and causing the read current to decrease.

[0036] In this embodiment, the first well and the second well can also be a P well and an N well respectively, the first transistor is an NMOS transistor, the source and drain include an N+ heavily doped ion region, the capacitor is a PMOS capacitor, and its coupling region in the second well is a P-type lightly doped ion region. In such a case, the PN junction in the floating gate is still adjacent to the end of the capacitor side of the floating gate, and at this time, the floating gate body is N+ net electrical. The working mode of the memory cell is different from the above. When the memory cell is programmed, a negative potential is applied to the P coupling region of the PMOS capacitor, and the floating gate with a main body of N+ net electrical property is negatively biased through capacitive coupling; opposite potentials are applied to the source and drain of the NMOS transistor, respectively, so that a strong lateral electric field is formed between the source and drain, and the electrons are accelerated along the channel of the first transistor in the strong electric field, and collision ionization occurs in the terminal (such as the source) depletion region, and the generated holes are attracted by the negatively biased floating gate and injected into the floating gate. The hole injection into the floating gate causes the threshold voltage of the NMOS transistor to decrease, making it easy to turn on, and causing the read current during the read operation to increase. When the memory cell is erased, a positive potential is applied to the P coupling region of the PMOS capacitor, and the floating gate with a main body of N+ net electrical property obtains the required positive potential through capacitive coupling: its absolute value is smaller than the potential value applied by the capacitive coupling region; the same negative potential is applied to the source and drain of the NMOS transistor, thereby forming a high electric field on both sides of the gate oxide layer of the first transistor, which is sufficient to cause the holes trapped in the floating gate to tunnel into the channel of the NMOS transistor. The holes are removed from the floating gate, causing the threshold voltage of the first transistor to increase, making it difficult to conduct, and causing the read current to decrease.

[0037] In the second embodiment of the memory cell of the present application, the PN junction in the floating gate may also be adjacent to the transistor-side end of the floating gate, that is, the floating gate is close to the first transistor and away from the end of the capacitor. In this case, it is preferred that the source and drain of the first transistor are lightly doped ion regions, or the coupling region of the capacitor includes a heavily doped ion region. This can further enhance the net electrical properties of the floating gate body, in which case the net electrical properties of the floating gate body are the same type as the heavily doped ions of the capacitor coupling region. It is more preferred that the source and drain of the first transistor are lightly doped ion regions, and the capacitor coupling region includes a heavily doped ion region.

[0038] In this embodiment, it is also preferred that: the first well and the second well are N well and P well respectively, the first transistor is a PMOS transistor, the source and drain are P lightly doped ion regions, the capacitor is an NMOS capacitor, and the coupling region is an N+ heavily doped ion region. In this case, the PN junction in the floating gate is adjacent to the end of the first transistor side on the floating gate, and the floating gate body is N+ net electrical property. The structure of this memory cell is similar to the first memory cell in the first embodiment described above (that is, the first well and the second well are N well and P well respectively, the first transistor is a PMOS transistor, the source and drain include P+ heavily doped ion regions, the capacitor is an NMOS capacitor, and its coupling region is an N lightly doped ion region), except that the PN junction positions in the floating gates of the two are different, that is, they are adjacent to different ends of the floating gates respectively, and one of the floating gate bodies is N+ net electrical property and the other is P+ net electrical property. Compared with the memory cell in the first embodiment, the distance between the PN junction in the floating gate and the end of the floating gate (the end on the first transistor side) in this embodiment cannot be too small, otherwise it will cause the active area of ​​the first transistor to be too narrow, which will affect the performance of the first transistor. In this case, the distance between the PN junction in the floating gate and the end of the floating gate on the transistor side is preferably 30-150nm, more preferably 50-130nm. This embodiment can partially weaken the adverse effect of the PN junction on the floating gate, but the effect is not as good as that of the first embodiment. In addition, the working mode of this embodiment is similar to the first structure memory cell in the first embodiment above, although one of the floating gate bodies is N+ net electrical property and the other is P+ net electrical property, and the specific value of the potential applied to the capacitive coupling region during programming or erasing operations is slightly different, but the working principles and modes of the two are similar.

[0039] In this embodiment, the first well and the second well can also be a P well and an N well respectively, the first transistor is an NMOS transistor, the source and drain include an N lightly doped ion region, the capacitor is a PMOS capacitor, and its coupling region in the second well is a P+ heavily doped ion region. In this case, the PN junction in the floating gate is still adjacent to the end of the first transistor side of the floating gate, and the floating gate body is P+ net electrical property. The structure of this embodiment is similar to the second structure memory cell in the first embodiment mentioned above (that is, the first well and the second well are P well and N well respectively, the first transistor is an NMOS transistor, the source and drain include an N+ heavily doped ion region, the capacitor is a PMOS capacitor, and the coupling region is a P lightly doped ion region). The difference is that the PN junction positions in the floating gates of the two are different, that is, they are adjacent to different ends of the floating gate respectively, and one of the floating gate bodies is P+ net electrical property and the other is N+ net electrical property. Compared with the memory cell with a similar structure in the first embodiment, the distance between the PN junction in the floating gate and the end of the first transistor side of the floating gate in this embodiment cannot be too small, otherwise it will cause the active area of ​​the first transistor to be too narrow, which will affect the performance of the first transistor. In this case, the distance between the PN junction in the floating gate and the first transistor side end of the floating gate is preferably 30-150nm, more preferably 50-130nm. This embodiment can partially weaken the adverse effect of the PN junction on the floating gate, but the effect is not as good as the first embodiment. In addition, the working mode of this embodiment is similar to the first memory cell in the first embodiment above, although one of the floating gate bodies is P+ net electrical property and the other is N+ net electrical property, and the specific value of the potential applied to the capacitive coupling region during programming or erasing operations is slightly different, but the working principles and modes of the two are similar.

[0040] The nonvolatile memory cell of the present application may further include a second transistor, which is of the same type as the first transistor and is located in the first well and connected in series with the first transistor. The second transistor serves as a gate transistor for the programmable first transistor to minimize the programming disturbance problem.

[0041] The present application also relates to a non-volatile memory, which comprises: at least one of the above-mentioned non-volatile memory cells constructed on a substrate, wherein there is a deep well in the substrate, and the first well and the second well are located in the deep well. Preferably, the substrate is a P-type substrate, and the deep well is a deep N-well. More preferably, the first well and the second well are respectively an N-well and a P-well, the first transistor is a PMOS transistor, the capacitor is an NMOS capacitor, and the coupling region of the capacitor in the second well is an N-coupling region. The memory is preferably a multi-time programmable and erasable non-volatile memory.

[0042] The storage unit and the memory of the present application are prepared by conventional methods in the prior art. Only when forming the active area of ​​the capacitor and the first transistor, the boundary of the adjacent isolation area of ​​the capacitor active area is adjacent to the capacitor side end of the floating gate, or the boundary of the adjacent isolation area of ​​the first transistor active area is adjacent to the first transistor side end of the floating gate, and the doping ion implantation of the predetermined active area is performed accordingly to realize that the PN junction in the floating gate is adjacent to the capacitor side end of the floating gate, or the first transistor side end. In the case where the boundary of the adjacent isolation area of ​​the capacitor active area is adjacent to the capacitor side end of the floating gate, if the boundary of the adjacent capacitor of the isolation area also moves toward the capacitor side end of the floating gate along with the above-mentioned boundary of the capacitor active area, then the size of the capacitor coupling area along the length direction of the floating gate will be narrowed, resulting in a decrease in the capacitor coupling rate. In order not to reduce the coupling rate of the capacitor, it is preferred that: the boundary of the adjacent capacitor of the isolation area does not move with the above-mentioned boundary of the capacitor active area and is adjacent to the capacitor side end of the floating gate, but between the isolation area and the capacitor active area, an ion doping area of ​​the same type as the first transistor active area (source and drain) is added in parallel. This can ensure that the effective area and coupling rate of the capacitor do not decrease, and can further enhance the net electrical properties of the floating gate body. At this time, the net electrical properties of the floating gate body are the same as the electrical properties of the source and drain of the first transistor.

[0043] In the storage unit of the present application, the PN junction in the floating gate is adjacent to the end of the floating gate, which can weaken or eliminate the adverse effects of the PN junction on the floating gate, increase the coupling potential obtained by the floating gate, improve the uniformity and stability of the coupling potential obtained by the floating gate, reduce the discreteness of the coupling, and improve the average value of the threshold voltage of the first transistor after erasure, all of which help to improve the stability and reliability of the memory.

[0044] The storage unit and the memory thereof of the present application are described in detail below with reference to a specific embodiment. Obviously, various adjustments and changes can be made to the embodiment without departing from the purpose and scope of the present application.

[0045] Figure 1 A top view of the nonvolatile memory cell 100 of the present application is shown. Figure 2-4 Along Figure 1 1 and 1. The cross-sectional view of the cross-sectional lines AA, BB, and CC in FIG. The cross-sectional line CC in the figure is the boundary line between two different electrical parts in the floating gate 116, and is also the position line of the PN junction, which is adjacent to the end of the capacitor 120 side of the floating gate 116. The left and right sides of the CC line are the P-type and N-type electrical parts of the floating gate 116, respectively, which are called P gate and N gate.

[0046] In this embodiment, the nonvolatile memory cell 100 is constructed in a P-type silicon substrate 101. A deep N-well 104 is provided in the P-substrate 101, and the deep N-well 104 electrically isolates the memory cell 100 from the substrate 101. The N-well 102 and the P-well 103 are adjacent to each other and are placed in the deep N-well 104. A first transistor 110 (a PMOS readout transistor in this embodiment) is provided in the N-well 102, and a capacitor 120 (an NMOS capacitor in this embodiment of the present invention) is provided in the P-well 103. The first transistor 110 includes a P-type drain 112 and a source 111. The drain 112 includes a drain lightly doped region 112A and a drain heavily doped P+ contact region 112B. The source 111 includes a source lightly doped region 111A and a source heavily doped P+ contact region 111B.

[0047] The source 111 is connected to the common line (COM), and the drain 112 is connected to the bit line (BL). The first transistor 110 is surrounded by a shallow trench filled with a thick field oxide 114 (FOX). Between the source 111 and the drain 112 is a channel 113 region. The thickness of the gate oxide 115 covering the channel 113 is 7nm. A conductively doped polysilicon gate is placed on top of the gate oxide 115 to form a floating gate 116 of the first transistor 110.

[0048] The floating gate 116 and the gate oxide 115 extend to the P-well 103, forming the upper plate and dielectric of the capacitor 120. In the P-well 103, the three boundaries of the N-gate portion of the floating gate 116 adjacent to the capacitor active region 122 all slightly overlap with the edge portion of the capacitor active region 122 (overlap width h). The capacitor active region 122 is also the coupling region of the capacitor 120, which can also be called a charge injection element, and is an N lightly doped region. The gate capacitance value of the capacitor 120 is almost 2.5 times the gate capacitance value of the first transistor 110.

[0049] The charge injection element is connected to the word line (WL), which is also connected to the P well 103 through a P+ contact region (not shown). During storage operation, the word line WL is used to control the voltage of the floating gate 116. During operation, when the potential of the floating gate 116 is greater than that of WL, the voltage difference is greater than the threshold voltage of the capacitor 120, and the capacitor channel region 121 below the floating gate 116 in the P well 103 region is inverted, and the electrons emitted by the charge injection element form an electron inversion layer in the capacitor channel region 121, thereby forming the capacitor channel region 121 The lower plate of the capacitor 120. The lower plate is connected to WL through the charge injection element.

[0050] The floating gate 116 is surrounded by a sidewall isolation 117, which is generally formed of silicon nitride or silicon oxide. When forming the P+ region, the sidewall isolation 117 prevents the P+ implant from entering the lightly doped P region.

[0051] Figure 5 yes Figure 1 A partial top view of the memory cell 100 including the floating gate 116 is shown. Figure 6 It is a partial top view including a floating gate of a memory cell having a structure similar to the memory cell 100 in the prior art.

[0052] and Figure 6 Compared with the prior art memory cell shown, Figure 5 The position of the PN junction in the floating gate 116 of the memory cell 100 of the present application (at the CC boundary) is moved from the middle of the floating gate 116 to the end of the capacitor 120 side adjacent to the floating gate 116, and the distance between the PN junction and the end of the floating gate 116 adjacent to the capacitor 120 side is H, specifically 30nm. Along the length direction of the floating gate 116, the size of the P gate portion in the floating gate 116 is much larger than the N gate portion, so that the main body of the floating gate 116 presents a P+ net electrical property, which can also be called an approximate P gate. The P+ heavily doped ion region located in the N well 102 (NW) is the active region of the first transistor 110, and the N lightly doped ion region located in the P well 103 (PW) is a capacitive coupling region, and there is a thick field oxide 114 (FOX) isolation region located at the junction of the two wells, and a newly added P+ heavily doped ion region in the P well 103. The newly added P+ heavily doped ion region is located between the isolation region and the capacitor coupling region, which can not only ensure that the effective area and coupling rate of the capacitor 120 do not decrease, but also help to make the floating gate 116 body present P+ net electrical properties.

[0053] from Figure 5 It can also be seen that in the P-well 103, the three borders of the N gate portion of the floating gate 116 of the memory cell 100 adjacent to the capacitive coupling region slightly overlap with the edge portion of the N coupling region of the capacitor 120, and the overlapping width is h. This overlapping width is conducive to the capacitive coupling region (i.e., the charge injection element) injecting electrons into the capacitor channel region 121 during the erase operation to form a stable inversion layer, which is convenient for coupling potential to the floating gate 116.

[0054] Figure 7 Shows Figure 5-6 The volt-ampere characteristic curves of the floating gates of the two memory cells shown in FIG. 1 , that is, the relationship between the current I and the voltage U from the N gate to the P gate, are also resistance characteristic curves. Figure 7 It can be seen that in the floating gate of the prior art memory cell, the resistance distribution from the N gate to the P gate is uneven, and is significantly higher than the floating gate 116 of the memory cell 100 in the present application. This is because there is a PN junction located in the middle of the floating gate between the P gate and the N gate in the prior art floating gate. The PN junction has an internal electric field, which also causes an initial potential of 0.5V to be displayed on the volt-ampere curve. Only when this initial potential is overcome can current (electrons) move in the floating gate. These will cause the potential obtained by coupling within the floating gate to be low and poorly uniform. Figure 7It can also be seen that the resistance in the floating gate 116 of the memory cell 100 in the present application is constant and evenly distributed, and its resistance value is significantly lower than the resistance value of the floating gate in the prior art. This is because the PN junction in the floating gate 116 of the memory cell 100 of the present application is adjacent to the end, the floating gate 116 body is P+ net electrical property, and the floating gate 116 is approximately a P-type gate. This makes the potential obtained by coupling in the floating gate 116 of the present application higher and more uniform, and the coupling degree, as well as the uniformity and stability of the potential obtained by coupling can be improved, which is conducive to uniform erasing during the erase operation.

[0055] The memory cell 100 described in this embodiment is manufactured using a 130nm logic process. All processing steps required to form the memory cell 100 are existing steps used to form other on-chip circuits in the logic process, and no additional processing steps are required. Moreover, the manufacturing process of the memory cell 100 is compatible with the standard CMOS process.

[0056] The preparation process of the storage unit 100 of the present application is similar to Figure 6 The preparation process of the prior art memory cell shown is basically the same, and the only difference is that: when forming the active area of ​​the NMOS capacitor 120 and the first transistor 110, the boundary of the capacitor active area 122 adjacent to the FOX isolation area is close to the end of the floating gate 116 on the capacitor 120 side, and the distance between the boundary of the capacitor active area 122 and the end of the floating gate 116 on the capacitor side is 30nm, and a P+ active area is added between the FOX isolation area and the capacitor active area 122 in the P well 103, and doping ions are implanted in the predetermined active area accordingly. Figure 8-10 As shown, they are partial top views of the memory cell 100 including the floating gate 116 in the steps of sequentially forming active regions (the active region of the first transistor 110 and the capacitor active region 122).

[0057] like Figure 8 As shown, before the step of injecting doping ions, a gate oxide 115 and a floating gate 116 are formed on the N well 102 and the P well 103, and then Figure 8 The positions of the predetermined FOX region (i.e., isolation region) and active region (P+ region and N region) are shown to form a layout. Figure 8 In the figure, the P+ region in the N-well 102 is the active region of the first transistor 110, the middle FOX region spans the N-well 102 and the P-well 103, the N-region in the P-well 103 is the N-active region of the NMOS capacitor 120, and the P+ region in the P-well 103 is the added P+ active region between the middle FOX region and the N-active region of the NMOS capacitor 120.

[0058] Use a photomask to expose the area where doping ions need to be implanted, and then implant corresponding types of doping ions into each predetermined active area, such as Fig. 9As shown, the P+ source and drain of the first transistor 110 , the N coupling region of the NMOS capacitor 120 , and the P+ active region in the newly added P well 103 are formed.

[0059] In the process of injecting dopant ions into the active region, ions injected from the surface of the floating gate 116 directly above the portion of the floating gate 116 adjacent to the active region rarely penetrate into the floating gate 116, which is determined by the material of the floating gate 116. However, dopant ions injected from both sides of the portion of the floating gate 116 adjacent to the active region can penetrate into the floating gate 116 from the side of the floating gate 116. Fig.10 As shown, the P+ doped ions injected into the two P+ active regions penetrate into the floating gate 116 from the side of the adjacent active region of the floating gate 116, move in the conductor of the floating gate 116, and form the P gate portion of the floating gate 116. The N doped ions injected into the N active region penetrate into the floating gate 116 from the side of the floating gate 116, and form the N gate portion of the floating gate 116. The CC line is the boundary between the P gate and the N gate in the floating gate 116, and is also the location of the PN junction in the floating gate 116. The distance H between the CC line and the end of the floating gate 116 adjacent to the capacitor 120 is 30 nm.

[0060] After the doping ions are injected into the active area, the formed NMOS capacitive coupling region is adjacent to the three boundaries of the N gate. The doping ions at the edge of the NMOS capacitive coupling region adjacent to the N gate boundary undergo rapid thermal annealing, thermal side diffusion occurs, and penetrates into the P well 103 region below the three boundaries of the N gate, forming an overlapping region of the floating gate 116 with a width of h and the NMOS capacitive coupling region.

[0061] During programming of the memory cell 100, electrons are injected into the floating gate 116 of the first transistor 110, causing the threshold voltage of the first transistor 110 to decrease, making it easier to turn on and causing the read current to increase during the read operation. For example, the memory cell 100 can be programmed by driving WL to 2v, BL to 2.5v and COM to -2v. At the same time, the N well 102 and the deep N well 104 are driven to a potential of 3.3v. In the first transistor 110, the voltage difference between the source 111 and the drain 112 is 4.5v, and the lateral electric field from the source 111 to the drain 112 is much stronger than the longitudinal electric field from the source 111 to the floating gate 116. Therefore, holes are accelerated from one side of the channel 113 to the other side (for example, Figure 2-3 The negative source 111 bias (-2.0 V) attracts most of the hot holes, causing very few hot holes to tunnel into the floating gate 116. Therefore, the number of electrons in the floating gate 116 is greatly increased during programming.

[0062] During the erase operation of the memory cell 100, electrons are removed from the floating gate 116 of the first transistor 110, causing the threshold voltage of the first transistor 110 to increase, making it more difficult to turn on, and causing the read current during the read operation to decrease. For example, the memory cell 100 performs an erase operation by driving WL to -4v, BL and COM to 5v. Under this bias condition, the lower plate of the NMOS capacitor 120 forms an inversion layer, and the floating gate 116 is coupled to a potential of approximately -3.5v. When the source 111 and the drain 112 of the first transistor 110 are driven to 5v, an inversion layer is also formed in the channel region of the first transistor 110. The inverted channel connects the source 111 and the drain 112, and receives a 5v voltage. Thus, the total voltage applied to the gate oxide 115 of the first transistor 110 is about 8.5V, forming a high electric field sufficient to cause the electrons trapped in the floating gate 116 to tunnel to the inversion channel filled with positive carriers. The high electric field can exceed about 10MeV, and the tunneling mechanism is direct tunneling and / or Fowler-Nordheim tunneling. In this operation, the P-well 103 can be driven to a less negative potential value than the substrate 101 bias (0V) because the P-well 103 is separated from the deep N-well 104 by the substrate 101. The N-well 102 and the deep N-well 104 are driven to 5V during erase.

[0063] In the read operation, the first transistor 110 in the programmed and erased memory cells 100 has a threshold voltage of approximately 0v and -1.5v, respectively. For example, when the memory cell 100 is in a programmed state, the common line (COM) is driven to 1.2v, the bit line (BL) is precharged to 0v, the N well 102 and the deep N well 104 are driven to 1.5v, and the word line WL is driven to 0v. The first transistor 110 of the memory cell 100 is turned on, pulling BL up to 1.2v. The high voltage in BL is then detected by the sense amplifier and driven to output a data signal of state "1".

[0064] In practical applications, a plurality of non-volatile memory cells 100 may be put together to form a memory array or a memory.

[0065] In the memory array, the WL lines of the memory cells 100 in each row are connected, and the common lines (COM) and bit lines (BL) of the memory cells 100 in each column are connected respectively. The memory array is constructed in a P-type substrate 101. The deep N-wells 104 of the memory cells 100 are merged to form a single deep N-well. The N-well 102 and P-well 103 of the memory cells 100 in a memory row are merged respectively. Thus, each memory row contains an N-well and a P-well. By merging the wells in a row, the memory cells 100 in the array can be more tightly packaged because most of the space between the wells is eliminated. The memory array is constructed in the same substrate 101 as the logic circuits on other chips, and the logic circuits require the substrate 101 to be grounded or 0v.

[0066] The memory cell 100 may further include a second PMOS transistor, which is located in the N well 102 and connected in series with the first transistor 110. The drain of the second PMOS transistor is connected to the BL word line, and its source coincides with the drain 112 of the first transistor 110. The source 111 of the first transistor 110 is still connected to the COM common line. The gate of the second PMOS transistor is connected to the word line WL, and the NMOS capacitive coupling region is connected to the control gate signal CG. During the storage operation, the control gate signal CG is used to control the voltage of the floating gate 116.

[0067] In the case where the memory cell 100 includes a second PMOS transistor, the operation process and principle of programming, erasing and reading are the same as those of the above case where the second PMOS transistor is not included. That is, the memory cell 100 is programmed by tunneling the channel hot electrons of the first transistor 110 from the channel to the floating gate 116, and the erasing operation is completed by tunneling the electrons from the floating gate 116 of the first transistor 110 into the channel 113 through the FN mechanism. For example, in the programming operation, programming is performed by driving WL to 0v, BL to 2.5v, CG to 2v and COM to -2v. At the same time, the N well 102 and the deep N well 104 are driven to a potential of 2.5v. In the erasing operation, erasing is performed by driving WL to 5v, BL to 3.3v, CG to -4v, COM to 5v, and the N well 102 and the deep N well 104 to 5v. In a read operation, when the memory cell 100 is in a programmed state, WL, BL and CG are driven to 0v, COM to 1.2v, and N-well 102 and deep N-well 104 to 1.5v.

[0068] In applications, a plurality of memory cells 100 including the second PMOS transistor may also form a memory array or a memory.

[0069] In the memory array, the WL and CG lines of the memory cells 100 in each row are connected respectively, and the common lines and bit lines of the memory cells 100 in each column are connected respectively. The memory array is constructed in a P-type substrate 101. The deep N-wells 104 of the memory cells 100 are merged to form a single deep N-well. The N-well 102 and P-well 103 of the memory cells 100 in a memory row are merged respectively. Thus, each memory row contains an N-well and a P-well. By merging the wells in a row, the memory cells 100 in the array can be more tightly packed because most of the space between the wells is eliminated. The memory array is constructed in the same substrate 101 as the logic circuits on other chips, and the logic circuits require the substrate 101 to be grounded or at 0v.

[0070] This specific embodiment is merely illustrative and not restrictive of the protection scope of the technical solution of the present application.

Claims

1. A non-volatile storage unit, characterized in that: It contains: First wells and second wells of different types are adjacently juxtaposed; A first transistor is located in the first well, the first transistor comprising a floating gate and a gate oxide thereof; A capacitor is located in the second well, the capacitor comprises a coupling region located in the second well, the floating gate and its gate oxide extend from the first well to the second well, forming a gate and its gate oxide of the capacitor; The floating gate includes two electrically different portions, a junction of the two electrically different portions is adjacent to one end of the floating gate, and a distance between the junction and the adjacent floating gate end is less than 150 nm.

2. The non-volatile memory cell according to claim 1, wherein: The distance between the junction of the two electrically different parts of the floating gate and the adjacent end of the floating gate is 5-100 nm.

3. The non-volatile memory cell according to claim 1, wherein: The distance between the junction of the two electrically different parts of the floating gate and the adjacent end of the floating gate is 10-70 nm.

4. The nonvolatile memory cell according to claim 1, wherein: The end of the floating gate adjacent to the boundary of the two electrically different portions of the floating gate is an end of the floating gate close to the capacitor and far away from the first transistor.

5. The non-volatile memory cell according to claim 4, wherein: The first transistor includes a source and a drain, each of the source and the drain includes a heavily doped ion region, and / or the coupling region of the capacitor is a lightly doped ion region.

6. The non-volatile memory cell according to any one of claims 1 to 5, characterized in that: The invention also comprises a second transistor, which is of the same type as the first transistor, is co-located in the first well and is connected in series with the first transistor.

7. The non-volatile memory cell according to any one of claims 1 to 5, characterized in that: The first well and the second well are respectively an N well and a P well, the first transistor is a PMOS transistor, the capacitor is an NMOS capacitor, and the coupling region of the capacitor in the second well is an N coupling region.

8. A non-volatile memory, characterized in that: It comprises: at least one non-volatile memory cell as claimed in claim 1 constructed on a substrate, wherein the substrate comprises a deep well, and the first well and the second well in the non-volatile memory cell are located in the deep well.

9. The non-volatile memory according to claim 8, wherein: The substrate is a P-type substrate, the deep well is a deep N-well; the first well and the second well are an N-well and a P-well respectively, the first transistor is a PMOS transistor, the capacitor is an NMOS capacitor, and the coupling region of the capacitor in the second well is an N-coupling region.

10. The non-volatile memory according to any one of claims 8 to 9, characterized in that: The nonvolatile memory is a multi-time programmable and erasable nonvolatile memory.

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