A super junction diode and a method for manufacturing the same

Abstract

The present application provides a super junction diode and a method for making the same, and relates to the field of semiconductor technology. The super junction diode comprises: an N-type epitaxial wafer; a terminal region and an active region located on the surface of the N-type epitaxial wafer; wherein the active region comprises at least two first P columns, each of which comprises a P-type sidewall and a low-doped N-type ion region located in the P-type sidewall, a first insulating dielectric layer, and a second insulating dielectric layer; the first insulating dielectric layer and the second insulating dielectric layer are made of different materials; the first insulating dielectric layer is made of a material with a low dielectric constant or a high dielectric strength; a passivation protective layer located on the surface of the terminal region; a first metal layer located on the surface of the active region, and a second metal layer located on the back of the epitaxial wafer. The super junction diode and the method for making the same provided by the present application have the advantages of reducing the probability of thermal failure of the device, improving the breakdown voltage, reliability, and robustness of the device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a super junction diode and a method for manufacturing the same. Background Art

[0002] The performance of power devices with traditional structures is already very close to their one-dimensional theoretical limit. How to break the performance shackles and further reduce the on-resistance and conduction loss of power devices is a huge challenge facing power devices.

[0003] Super junction power devices are an important type of devices with a super junction voltage-withstand layer. The super junction technology used is to introduce a lateral P / N structure composed of alternating P-type doped regions and N-type doped regions into a conventional "resistance-type" voltage-withstand layer to achieve charge balance, thereby changing it into a "junction-type voltage-withstand layer". This qualitative change breaks through the theoretical limit relationship between the forward on-resistance and reverse voltage resistance of traditional power devices, making super junction power devices not only have super strong blocking capability and high reverse breakdown voltage, but also have ultra-low forward on-resistance and forward on-voltage drop VF. At the same time, smaller and therefore lower cost and cheaper chips can be manufactured for specific forward on-resistance.

[0004] However, the super junction power devices in the prior art have problems such as thermal failure risk, low device reliability and robustness. Summary of the invention

[0005] The purpose of the present application is to provide a super junction diode and a method for manufacturing the same, so as to solve the problems existing in the prior art such as the risk of thermal failure of super junction power devices and low device reliability and robustness.

[0006] In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0007] In one aspect, an embodiment of the present application provides a super junction diode; the super junction diode includes:

[0008] N-type epitaxial wafer;

[0009] The terminal area and the active area are located on the surface of the N-type epitaxial wafer; wherein the active area includes at least two first P columns, each of which includes a P-type sidewall and a low-doped N-type ion region located in the P-type sidewall, a first insulating dielectric layer and a second insulating dielectric layer; the low-doped N-type ion region is arranged between the first insulating dielectric layer and the P-type sidewall, and the low-doped N-type ion region has the same height as the first insulating dielectric layer; the second insulating dielectric layer is located above the low-doped N-type ion region and the first insulating dielectric layer, and the first insulating dielectric layer and the second insulating dielectric layer are made of different materials, and the first insulating dielectric layer is made of a material with a low dielectric constant or a high dielectric strength;

[0010] A passivation protection layer located on the surface of the terminal region;

[0011] A first metal layer is located on the surface of the active area and a second metal layer is located on the back side of the epitaxial wafer.

[0012] Optionally, side walls of the low-doped N-type ion region, the first insulating dielectric layer, and the second insulating dielectric layer are all inclined side walls.

[0013] Optionally, the angle between the side wall of the first insulating dielectric layer and the horizontal plane is greater than the angle between the side wall of the second insulating dielectric layer and the horizontal plane; and the angle between the side wall of the first insulating dielectric layer and the horizontal plane is (30°, 60°], and the angle between the side wall of the second insulating dielectric layer and the horizontal plane is [30°, 60°).

[0014] Optionally, an angle between a side wall of the first insulating dielectric layer and a horizontal plane is 45° to 60°; an angle between a side wall of the second insulating dielectric layer and a horizontal plane is 30° to 45°.

[0015] Optionally, the vertical height of the first insulating medium layer is greater than the vertical height of the second insulating medium layer;

[0016] The sum of the vertical heights of the first insulating dielectric layer and the second insulating dielectric layer is greater than two-thirds of the vertical height of the P-type sidewall.

[0017] Optionally, a top surface width of the first insulating dielectric layer is less than or equal to a bottom surface width of the second insulating dielectric layer;

[0018] The relative size between the first insulating dielectric layer and the second insulating dielectric layer satisfies the formula:

[0019] 0≤W L / W R <X;

[0020] W Lrepresents the horizontal distance between the left side of the top surface of the first insulating dielectric layer and the left side of the bottom surface of the second insulating dielectric layer, W R represents the horizontal distance between the right side of the top surface of the first insulating dielectric layer and the right side of the bottom surface of the second insulating dielectric layer, and X represents the horizontal distance between the left side of the top surface of the first insulating dielectric layer and the left side of the P-type side wall or the horizontal distance between the right side of the top surface of the first insulating dielectric layer and the right side of the P-type side wall.

[0021] Optionally, a depth of each of the first P columns is greater than 6 μm, and a ratio of the depth to the width of each of the first P columns is greater than 2.

[0022] Optionally, the active area further includes a second P column, the depth of the second P column is the same as the depth of the first P column, and the second P column is a P-type doping region; the first P columns and the second P columns are arranged alternately, and the two outermost P columns are first P columns.

[0023] On the other hand, an embodiment of the present application further provides a method for manufacturing a super junction diode, which is used to manufacture the above-mentioned super junction diode, and the method comprises:

[0024] Provide N-type epitaxial wafers;

[0025] A terminal region and an active region are fabricated based on the surface of the N-type epitaxial wafer; wherein the active region comprises at least two first P columns, each of which comprises a P-type sidewall and a low-doped N-type ion region located within the P-type sidewall, a first insulating dielectric layer, and a second insulating dielectric layer; the low-doped N-type ion region is disposed between the first insulating dielectric layer and the P-type sidewall, and the low-doped N-type ion region has the same height as the first insulating dielectric layer; the second insulating dielectric layer is located above the low-doped N-type ion region and the first insulating dielectric layer, and the first insulating dielectric layer and the second insulating dielectric layer are made of different materials; the first insulating dielectric layer is made of a material with a low dielectric constant or a material with a high dielectric strength;

[0026] Making a passivation protection layer based on the surface of the terminal area;

[0027] Fabricating a first metal layer based on the surface of the active area;

[0028] A second metal layer is formed based on a side of the epitaxial wafer away from the active area.

[0029] Optionally, the step of defining a terminal region and an active region based on the N-type epitaxial wafer includes:

[0030] Performing P+ ion implantation based on the active area position of the epitaxial wafer;

[0031] Performing a first etching on the region after the P+ ion implantation to form a first trench, wherein the region after the etching forms a P-type sidewall;

[0032] Performing N-ion implantation based on the sidewall of the first trench to form a low-doped N-type ion region;

[0033] Fabricating the terminal region and annealing;

[0034] Filling the first trench with a first insulating medium and etching back to perform a second etching to form a first insulating medium layer and a second trench;

[0035] A second insulating dielectric is filled in the second trench and then etched back to form a second insulating dielectric layer above the low-doped N-type ion region and the first insulating dielectric layer.

[0036] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0037] The embodiment of the present application provides a super junction diode and a manufacturing method thereof, wherein the super junction diode comprises: an N-type epitaxial wafer; a terminal region and an active region located on the surface of the N-type epitaxial wafer; wherein the active region comprises at least two first P columns, each of which comprises a P-type sidewall and a low-doped N-type ion region located within the P-type sidewall, a first insulating dielectric layer and a second insulating dielectric layer; the low-doped N-type ion region is arranged between the first insulating dielectric layer and the P-type sidewall, and the low-doped N-type ion region has the same height as the first insulating dielectric layer; the second insulating dielectric layer is located above the low-doped N-type ion region and the first insulating dielectric layer, and the materials of the first insulating dielectric layer and the second insulating dielectric layer are different, and the first insulating dielectric layer is made of a material with a low dielectric constant or a high dielectric strength; a passivation protective layer located on the surface of the terminal region; a first metal layer located on the surface of the active region and a second metal layer located on the back of the epitaxial wafer. On the one hand, since the super junction diode provided by the present application is provided with a first insulating dielectric layer and a second insulating dielectric layer of different materials, by adjusting the parameters of the two insulating dielectric layers, the high temperature thermal stress of the device can be flexibly adjusted and improved, greatly reducing the probability of thermal failure of the device, while improving the mechanical properties and stable chemical inertness of the filler, thereby greatly stabilizing the electrical performance of the device and improving the reliability and robustness of the device. In addition, after filling the first insulating dielectric layer material with a low dielectric constant or high dielectric strength, according to Gauss's theorem, the groove area can withstand the largest possible peak electric field, thereby greatly improving the breakdown voltage of the device. On the other hand, by setting a low-doped N-type ion region on the side wall, the interface state density caused by the etching of the groove side wall can be reduced, the device leakage current can be reduced, and the device reliability and robustness can be improved. At the same time, the low-doped N-type ion region introduces a two-dimensional charge slowly varying field modulation effect, reduces the parasitic charge sensitivity, reduces the device breakdown electric field peak and optimizes the electric field distribution in the device body, greatly reducing the device loss and increasing the safe working area of ​​the device.

[0038] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1 A schematic diagram of a first cross-sectional structure of a super junction diode provided in an embodiment of the present application.

[0041] Figure 2A schematic diagram of a second cross-sectional structure of a super junction diode provided in an embodiment of the present application.

[0042] Figure 3 A schematic diagram of parameters of the active region provided in an embodiment of the present application.

[0043] Figure 4 An exemplary flow chart of a method for manufacturing a super junction diode provided in an embodiment of the present application.

[0044] Figure 5 This is a schematic diagram of the cross-sectional structure corresponding to S102 provided in an embodiment of the present application.

[0045] Figure 6 This is a schematic diagram of the cross-sectional structure corresponding to S1041 provided in an embodiment of the present application.

[0046] Figure 7 This is a schematic diagram of the cross-sectional structure corresponding to S1042 provided in an embodiment of the present application.

[0047] Figure 8 A schematic diagram of the cross-sectional structure corresponding to the production of a low-doped N-type ion region provided in an embodiment of the present application.

[0048] Fig. 9 This is a schematic diagram of the cross-sectional structure corresponding to the filling of the first insulating medium provided in an embodiment of the present application.

[0049] Fig.10 A schematic diagram of the cross-sectional structure corresponding to the second groove etching provided in an embodiment of the present application.

[0050] Fig.11 This is a schematic diagram of the cross-sectional structure corresponding to S1046 provided in an embodiment of the present application.

[0051] In the figure:

[0052] 101-substrate; 102-epitaxial layer; 103-P-type sidewall; 104-first insulating dielectric layer; 105-second insulating dielectric layer; 106-low-doped N-type ion region; 107-ohmic contact layer; 108-terminal region; 109-passivation protection layer; 110-first metal layer; 111-second metal layer; 112-P+ region; 113-N+ region; 114-first trench. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0054] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0055] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0056] It should be noted that, in this document, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0057] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0058] As described in the background technology, the super junction diode in the prior art has problems such as large thermal stress at high temperature, risk of thermal failure, and low reliability and robustness of the device.

[0059] In view of this, the present application provides a super junction diode, which improves high-temperature thermal stress, reduces the probability of device thermal failure, and improves device reliability and robustness by setting a low-doped N-type ion region and two insulating dielectric layers.

[0060] The following is an exemplary description of the super junction diode provided in this application:

[0061] As an implementation, see Figure 1 , the super junction diode comprises:

[0062] An N-type epitaxial wafer; a terminal region and an active region located on the surface of the N-type epitaxial wafer; wherein the active region includes at least two first P columns, each of which includes a P-type sidewall and a low-doped N-type ion region located in the P-type sidewall, a first insulating dielectric layer and a second insulating dielectric layer; the low-doped N-type ion region is arranged between the first insulating dielectric layer and the P-type sidewall, and the low-doped N-type ion region is at the same height as the first insulating dielectric layer; the second insulating dielectric layer is located above the low-doped N-type ion region and the first insulating dielectric layer, and the first insulating dielectric layer and the second insulating dielectric layer are made of different materials, and the first insulating dielectric layer is made of a material with a low dielectric constant or a high dielectric strength; a passivation protective layer located on the surface of the terminal region; a first metal layer located on the surface of the active region and a second metal layer located on the back of the epitaxial wafer.

[0063] Since the P-type side wall 103 provided in the present application is provided with a first insulating dielectric layer 104 and a second insulating dielectric layer 105 made of different materials, by flexibly adjusting parameters such as the material type, height ratio, angle ratio, and relative size of the two insulating layers, the high-temperature thermal stress of the device can be flexibly adjusted and improved, greatly reducing the probability of thermal failure of the device, while improving the mechanical properties and stable chemical inertness of the filler, thereby greatly stabilizing the electrical performance of the device and improving the reliability and robustness of the device.

[0064] In addition, the low-doped N-type ion region introduces a two-dimensional charge slowly varying field modulation effect, reduces parasitic charge sensitivity, reduces the device breakdown electric field peak, and optimizes the electric field distribution in the device, greatly reducing device loss and increasing the safe operating area of ​​the device. In addition, the low-doped N-type ion region can reduce the interface state density caused by trench sidewall etching, reduce device leakage current, and improve device reliability and robustness.

[0065] The N-type epitaxial wafer provided in the present application includes a substrate 101 and an epitaxial layer 102. The substrate 101 may be a SiC substrate 101, and the epitaxial layer 102 may be an N - Of course, the substrate 101 and the epitaxial layer 102 can also be made of other materials, for example, they can be made of Si material.

[0066] When the first P column is made in the active area, the number of the first P column is not limited. Generally, the number of the first P column in the active area is at least 2, for example, the number can be 2, 3, etc. In addition, the area other than the first P column in the active area adopts N + In a specific process, N doping can be performed after or before P+ ion implantation. +Ion implantation is performed to form the first P columns and the N+ region between the first P columns in the active area. Due to the introduction of heterotype doping (P-type layer) in the conventional voltage-resistant layer (N-type layer), the charge depletion layer of the device expands in both the longitudinal direction (forward current conduction direction) and the lateral direction at the time of reverse blocking voltage. Since the longitudinal thickness of the voltage-resistant layer is much larger than the lateral width of the alternating P / N-type regions, the voltage-resistant layer is completely depleted due to the extension of the lateral depletion layer under very low reverse voltage. At this time, the voltage-resistant layer can be regarded as a high-resistance intrinsic semiconductor layer on a macro scale, so that when the device voltage-resistant target is increased, the doping concentration of the voltage-resistant layer can be kept almost constant or even further increased in the N-type region (N+ ion implantation region in the figure), which is equivalent to reducing the forward on-resistance and forward on-voltage drop of the device.

[0067] In order to achieve the super junction effect, the parameters of the first P column need to be limited. Generally, the depth of each first P column is greater than 6μm, and the ratio of the depth to the width of each first P column is greater than 2. By setting this parameter, the device can more easily achieve charge balance, thereby achieving the super junction effect.

[0068] When manufacturing the first P column, P-type ion implantation is used to form the first P column region, and then the first trench 114 is etched at the position of the first P column by etching, and the P-type sidewall 103 is formed after etching, and the insulating dielectric layer is filled inside.

[0069] It should be noted that the present application does not impose any restrictions on the material of the low-doped N-type ion region. In one implementation, the low-doped N-type ion region may be N-type SiC, that is, the low-doped N-type ion region is formed by N-ion implantation. In another implementation, the low-doped N-type ion region may also be made of low-doped N - Poly is made by depositing low-doped N - Poly forms a low-doped N-type ion region.

[0070] By providing a low-doped N-type ion region 106 in a thin layer on the sidewall of the first trench 114, the interface state density caused by etching the sidewall of the first trench 114 can be reduced, the device leakage current can be reduced, and the device reliability and robustness can be improved. At the same time, the low-doped N-type ion region 106 introduces a two-dimensional charge slowly varying field modulation effect, reduces the parasitic charge sensitivity, reduces the device breakdown electric field peak and optimizes the electric field distribution in the device, greatly reduces the device loss and increases the safe working area of ​​the device.

[0071] Moreover, in one implementation, before filling the first insulating dielectric layer 104, a thermal oxide layer may be added. The thickness of the thermal oxide layer is relatively thin, generally 10 to 100 angstroms, which can further repair the damage to the sidewalls of the first trench 114 etched, improve the roughness and morphology of the sidewalls of the first trench 114, reduce the surface state density and surface trap charge density, and further reduce the device leakage current, thereby improving the device reliability and robustness.

[0072] In order to improve the device performance, the P column provided in the present application includes two types, namely the first P column and the second P column. Figure 1 and Figure 2 In the first P column, the side walls of the low-doped N-type ion region 106, the first insulating dielectric layer 104, and the second insulating dielectric layer 105 can all be inclined side walls. Of course, the side walls of the low-doped N-type ion region 106, the first insulating dielectric layer 104, and the second insulating dielectric layer 105 can all be vertical side walls. In the second P column, all are P-type doped areas, that is, the low-doped N-type ion region 106, the first insulating dielectric layer 104, and the second insulating dielectric layer 105 are not provided in the second P column. It should be noted that the depth of the second P column provided in the present application is the same as the depth of the first P column. That is, the depth of each second P column also satisfies the requirement of being greater than 6μm, and the ratio of the depth to the width of each second P column is greater than 2.

[0073] For the super junction diode as a whole, the total number of the first P columns needs to be greater than or equal to two, and the two P columns located on the outermost sides are the first P columns.

[0074] On this basis, in the super junction diode, all P columns can be set as the first P column, or the first P column and the second P column can be arranged alternately, and the alternating arrangement of this structure is conducive to achieving the best device performance, reliability, thermal stress and mechanical stress.

[0075] It should be noted that when the number of the first P columns is equal to 2, the two first P columns are arranged at the outermost side. Since the electric field of the outermost cylindrical junction or spherical junction of the device is very concentrated, avalanche breakdown is likely to occur here. Therefore, when the first P column is arranged at the outermost side, it is beneficial to improve the device breakdown voltage.

[0076] Therefore, if the first P-pillar and the second P-pillar are arranged alternately, the total number of P-pillars is generally set to an odd number, and the total number of P-pillars is greater than or equal to 3, so that the two outermost P-pillars are the first P-pillars. For example, if the total number of P-pillars is 3, the P-pillars on the left and right sides use the first P-pillar, and the P-pillar in the middle uses the second P-pillar. For another example, when the total number of P-pillars is 5, the first, third, and fifth P-pillars use the first P-pillar, and the second and fourth P-pillars use the second P-pillar, thereby ensuring that the two outermost P-pillars (the first P-pillar and the fifth P-pillar) are both the first P-pillars.

[0077] As an implementation, see Figure 3 In the first P column, the vertical height of the first insulating dielectric layer 104 is greater than the vertical height of the second insulating dielectric layer 105, that is, H1>H2. The sum of the vertical heights of the first insulating dielectric layer 104 and the second insulating dielectric layer 105 is greater than two-thirds of the vertical height of the sidewall, that is, H1+H2>2 / 3Hp.

[0078] When the vertical height of the first insulating dielectric layer 104 disposed in the first P column is greater than the vertical height of the second insulating dielectric layer 105, due to the narrow sidewall N of the first trench 114 at the bottom, - The ion-occupied area is increased, further reducing the interface state density caused by the etching of the sidewall of the first trench 114, further reducing the leakage current of the device, and further improving the reliability and robustness of the device; at the same time, the two-dimensional charge slowly varying field modulation effect is better, further reducing the parasitic charge sensitivity and optimizing the electric field distribution in the device, thereby further reducing the device loss and further increasing the safe operating area SOA of the device. At the same time, the sum of the vertical heights of the first insulating dielectric layer 104 and the second insulating dielectric layer 105 is set to be greater than two-thirds of the vertical height of the sidewall, which increases the internal double-layer insulating dielectric filling area, can more flexibly adjust and improve the high-temperature thermal stress of the device and the mechanical properties and stable chemical inertness of the filler, further stabilize the electrical performance of the device and improve the reliability and robustness of the device.

[0079] Furthermore, in the first P column, the angle between the side wall of the first insulating dielectric layer 104 and the horizontal plane is greater than the angle between the side wall of the second insulating dielectric layer 105 and the horizontal plane, that is, Figure 3 b>a. The angle between the side wall of the first insulating dielectric layer and the horizontal plane is (30°, 60°], and the angle between the side wall of the second insulating dielectric layer and the horizontal plane is [30°, 60°). Exemplarily, the angle between the side wall of the first insulating dielectric layer 104 and the horizontal plane is 45°~60°; the angle between the side wall of the second insulating dielectric layer 105 and the horizontal plane is 30°~45°.

[0080] When the angle between the side wall of the first insulating dielectric layer 104 and the horizontal plane is greater than the angle between the side wall of the second insulating dielectric layer 105 and the horizontal plane, an arc can be formed at the connection position along the narrow and wide first grooves 114, and an inward concave angle can be formed. When the device is in a reverse blocking condition, in the entire structure from the bottom groove to the top wide groove, the equivalent lateral PN junction used for withstand voltage occupies a larger proportion at the bottom narrow groove. At the same time, the P+ region under the inward concave angle increases the area that can be covered by the electric line, the electric line is more dispersed, the electric field strength distribution is flat, and the peak electric field is reduced, which can greatly improve the device breakdown voltage and device reliability.

[0081] Moreover, when the angle between the side wall of the first insulating dielectric layer 104 and the horizontal plane is 45°~60°; the angle between the side wall of the second insulating dielectric layer 105 and the horizontal plane is 30°~45°, the device breakdown voltage is improved more significantly, and the device BFOM (quality factor) is improved, further improving the device reliability and robustness.

[0082] In addition, in the first P column, the top surface width of the first insulating dielectric layer 104 is less than or equal to the bottom surface width of the second insulating dielectric layer 105; and the relative size between the first insulating dielectric layer 104 and the second insulating dielectric layer 105 satisfies the formula:

[0083] 0≤W L / W R <X;

[0084] W L represents the horizontal distance between the left side of the top surface of the first insulating dielectric layer 104 and the left side of the bottom surface of the second insulating dielectric layer 105, W R represents the horizontal distance between the right side of the top surface of the first insulating dielectric layer 104 and the right side of the bottom surface of the second insulating dielectric layer 105, and X represents the horizontal distance between the left side of the top surface of the first insulating dielectric layer 104 and the left side of the P-type side wall 103 or the horizontal distance between the right side of the top surface of the first insulating dielectric layer and the right side of the P-type side wall.

[0085] By adjusting the relative size between the first insulating dielectric layer 104 and the second insulating dielectric layer 105, the thermal performance and mechanical stability of the device can be flexibly adjusted and improved. L , W R and angle a, so that the area S ( Figure 3 The smaller the area of ​​the shaded part S) is, the smaller the area M ( Figure 3 The larger the area of ​​the shaded part M in the middle), the larger the space for heat dissipation when the device is in the forward conduction state, especially the better the thermal performance under large forward current, which can greatly reduce the thermal failure rate of the device and improve the reliability and robustness of the device. At the same time, the smaller the area S, the more uniform the mechanical stress of the upper and lower insulating dielectrics, which greatly improves the mechanical stability of the device, can greatly reduce problems such as dielectric cracks caused by internal stress, greatly reduce the probability of device failure, and greatly improve the reliability and robustness of the device.

[0086] Based on the above implementation, the present application also provides a method for manufacturing a super junction diode, which is used to manufacture the above super junction diode. Figure 4 , the method comprising:

[0087] S102, providing an N-type epitaxial wafer.

[0088] S104, manufacturing a terminal region and an active region based on the surface of an N-type epitaxial wafer; wherein the active region includes at least two first P columns, each of which includes a P-type sidewall and a low-doped N-type ion region located within the P-type sidewall, a first insulating dielectric layer, and a second insulating dielectric layer; the low-doped N-type ion region is disposed between the first insulating dielectric layer and the P-type sidewall, and the low-doped N-type ion region is at the same height as the first insulating dielectric layer; the second insulating dielectric layer is located above the low-doped N-type ion region and the first insulating dielectric layer, and the materials of the first insulating dielectric layer and the second insulating dielectric layer are different; the first insulating dielectric layer is made of a material with a low dielectric constant or a high dielectric strength.

[0089] S106, manufacturing a passivation protection layer based on the surface of the terminal region.

[0090] S108, manufacturing a first metal layer based on the surface of the active area.

[0091] S110, manufacturing a second metal layer 111 based on the back side of the epitaxial wafer.

[0092] Among them, S104 includes:

[0093] S1041, performing P+ ion implantation based on the active area position of the epitaxial wafer.

[0094] S1042, performing a first etching on the region after the P+ ion implantation to form a first trench, wherein the region after the etching forms a P-type sidewall.

[0095] S1043, performing N-ion implantation based on the sidewall of the first trench to form a low-doped N-type ion region.

[0096] S1044, fabricate the termination region and anneal.

[0097] S1045, filling the first trench with a first insulating medium and etching back to perform a second etching to form a first insulating medium layer and a second trench.

[0098] S1046, filling the second insulating dielectric based on the second trench and etching back to form a second insulating dielectric layer above the low-doped N-type ion region and the first insulating dielectric layer.

[0099] The following is an exemplary description of the super junction diode manufacturing method provided by the present application in conjunction with the accompanying drawings:

[0100] First, see Figure 5 , providing an N-type epitaxial wafer, the N-type epitaxial wafer comprising a substrate 101 and an epitaxial layer 102. Figure 6, an active area and a terminal area are divided on the N-type epitaxial wafer, and a P+ area 112 is formed in the active area by P+ ion implantation. It should be noted that before or after the P+ ion implantation, N+ ion implantation can be performed in the active area to form an N+ area 113, so that the P+ area 112 and the N+ area 113 are alternately arranged.

[0101] Afterwards, see Figure 7 , an etching process is used to form a first trench 114 with inclined sidewalls in the P+ region 112, and a P-type sidewall 103 is formed after etching.

[0102] See also Figure 8 After forming the first trench 114, as an implementation method, a low-doped N-type ion region 106 can be formed based on the sidewall of the first trench 114 by N- ion implantation, and then a terminal region 108 is manufactured and a high-temperature furnace tube annealing process is performed.

[0103] In another implementation, the terminal region 108 may be fabricated first and subjected to high temperature furnace annealing, and then low-doped N-type polysilicon may be filled in the first trench 114 and etched, thereby forming a low-doped N-type ion region on the sidewall of the first trench 114 through a deposition process.

[0104] See also Fig. 9 , continue to fill the first trench 114 with the first insulating dielectric layer 104 .

[0105] See also Fig.10 , the low-doped N-type ion region 106 and the first insulating dielectric layer 104 are etched back, and at the same time, a second trench etching is performed to form a second trench after etching, and the second trench is wider than the first trench.

[0106] See also Fig.11 , fill the second insulating dielectric layer 105 and etch back.

[0107] Next, an ohmic contact layer 107 , a first metal layer 110 on the front side, a passivation protection layer 109 and a second metal layer 111 on the back side may be fabricated to complete the fabrication of the super junction diode.

[0108] In summary, the embodiments of the present application provide a super junction diode and a method for manufacturing the same, the super junction diode comprising: an N-type epitaxial wafer; a terminal region and an active region located on the surface of the N-type epitaxial wafer; wherein the active region comprises at least two first P columns, each of which comprises a P-type sidewall and a low-doped N-type ion region located within the P-type sidewall, a first insulating dielectric layer and a second insulating dielectric layer; the low-doped N-type ion region is disposed between the first insulating dielectric layer and the P-type sidewall, and the low-doped N-type ion region is at the same height as the first insulating dielectric layer; the second insulating dielectric layer is located above the low-doped N-type ion region and the first insulating dielectric layer, and the materials of the first insulating dielectric layer and the second insulating dielectric layer are different, and the first insulating dielectric layer is made of a material with a low dielectric constant or a high dielectric strength; a passivation protective layer located on the surface of the terminal region; a first metal layer located on the surface of the active region, and a second metal layer located on the back of the epitaxial wafer. On the one hand, since the super junction diode provided by the present application is provided with a first insulating dielectric layer and a second insulating dielectric layer of different materials, by adjusting the parameters of the two insulating dielectric layers, the high temperature thermal stress of the device can be flexibly adjusted and improved, greatly reducing the probability of thermal failure of the device, while improving the mechanical properties and stable chemical inertness of the filler, thereby greatly stabilizing the electrical performance of the device and improving the reliability and robustness of the device. In addition, after filling the first insulating dielectric layer material with a low dielectric constant or high dielectric strength, according to Gauss's theorem, the groove area can withstand the largest possible peak electric field, thereby greatly improving the breakdown voltage of the device. On the other hand, by setting a low-doped N-type ion region on the side wall, the interface state density caused by the etching of the groove side wall can be reduced, the device leakage current can be reduced, and the device reliability and robustness can be improved. At the same time, the low-doped N-type ion region introduces a two-dimensional charge slowly varying field modulation effect, reduces the parasitic charge sensitivity, reduces the device breakdown electric field peak and optimizes the electric field distribution in the device body, greatly reducing the device loss and increasing the safe working area of ​​the device.

[0109] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0110] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A super junction diode, characterized in that: The super junction diode comprises: N-type epitaxial wafer; The terminal area and the active area are located on the surface of the N-type epitaxial wafer; wherein the active area includes at least two first P columns, each of which includes a P-type sidewall and a low-doped N-type ion region located in the P-type sidewall, a first insulating dielectric layer and a second insulating dielectric layer; the low-doped N-type ion region is arranged between the first insulating dielectric layer and the P-type sidewall, and the low-doped N-type ion region has the same height as the first insulating dielectric layer; the second insulating dielectric layer is located above the low-doped N-type ion region and the first insulating dielectric layer, and the first insulating dielectric layer and the second insulating dielectric layer are made of different materials, and the first insulating dielectric layer is made of a material with a low dielectric constant or a high dielectric strength; A passivation protection layer located on the surface of the terminal region; A first metal layer is located on the surface of the active area and a second metal layer is located on the back side of the epitaxial wafer.

2. The super junction diode according to claim 1, characterized in that: The side walls of the low-doped N-type ion region, the first insulating dielectric layer, and the second insulating dielectric layer are all inclined side walls.

3. The super junction diode according to claim 2, wherein: The angle between the side wall of the first insulating dielectric layer and the horizontal plane is greater than the angle between the side wall of the second insulating dielectric layer and the horizontal plane; and the angle between the side wall of the first insulating dielectric layer and the horizontal plane is (30°, 60°], and the angle between the side wall of the second insulating dielectric layer and the horizontal plane is [30°, 60°].

4. The super junction diode according to claim 3, characterized in that: The included angle between the side wall of the first insulating dielectric layer and the horizontal plane is 45° to 60°; the included angle between the side wall of the second insulating dielectric layer and the horizontal plane is 30° to 45°.

5. The super junction diode according to claim 1, wherein: The vertical height of the first insulating medium layer is greater than the vertical height of the second insulating medium layer; The sum of the vertical heights of the first insulating dielectric layer and the second insulating dielectric layer is greater than two-thirds of the vertical height of the P-type sidewall.

6. The super junction diode according to claim 1, wherein: The top surface width of the first insulating dielectric layer is less than or equal to the bottom surface width of the second insulating dielectric layer; The relative size between the first insulating dielectric layer and the second insulating dielectric layer satisfies the formula: 0≤W L / W R <X; W L represents the horizontal distance between the left side of the top surface of the first insulating dielectric layer and the left side of the bottom surface of the second insulating dielectric layer, W R represents the horizontal distance between the right side of the top surface of the first insulating dielectric layer and the right side of the bottom surface of the second insulating dielectric layer, and X represents the horizontal distance between the left side of the top surface of the first insulating dielectric layer and the left side of the P-type side wall or the horizontal distance between the right side of the top surface of the first insulating dielectric layer and the right side of the P-type side wall.

7. The super junction diode according to claim 1, wherein: The depth of each of the first P columns is greater than 6 μm, and the ratio of the depth to the width of each of the first P columns is greater than 2.

8. The super junction diode according to claim 1, wherein: The active area also includes a second P column, the depth of the second P column is the same as the depth of the first P column, and the second P column is a P-type doping region; the first P column and the second P column are arranged alternately, and the two outermost P columns are first P columns.

9. A method for manufacturing a super junction diode, characterized in that: For manufacturing the super junction diode according to any one of claims 1 to 8, the method comprises: Provide N-type epitaxial wafers; A terminal region and an active region are fabricated based on the surface of the N-type epitaxial wafer; wherein the active region comprises at least two first P columns, each of which comprises a P-type sidewall and a low-doped N-type ion region located within the P-type sidewall, a first insulating dielectric layer, and a second insulating dielectric layer; the low-doped N-type ion region is disposed between the first insulating dielectric layer and the P-type sidewall, and the low-doped N-type ion region has the same height as the first insulating dielectric layer; the second insulating dielectric layer is located above the low-doped N-type ion region and the first insulating dielectric layer, and the first insulating dielectric layer and the second insulating dielectric layer are made of different materials; the first insulating dielectric layer is made of a material with a low dielectric constant or a material with a high dielectric strength; Making a passivation protection layer based on the surface of the terminal area; Fabricating a first metal layer based on the surface of the active area; A second metal layer is formed based on a side of the epitaxial wafer away from the active area.

10. The method for manufacturing a super junction diode according to claim 9, wherein: The steps of defining the terminal area and the active area based on the N-type epitaxial wafer include: Performing P+ ion implantation based on the active area position of the epitaxial wafer; Performing a first etching on the region after the P+ ion implantation to form a first trench, wherein the region after the etching forms a P-type sidewall; Performing N-ion implantation based on the sidewall of the first trench to form a low-doped N-type ion region; Fabricating the terminal region and annealing; Filling the first trench with a first insulating medium and etching back to perform a second etching to form a first insulating medium layer and a second trench; A second insulating dielectric is filled in the second trench and then etched back to form a second insulating dielectric layer above the low-doped N-type ion region and the first insulating dielectric layer.

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