A method for preparing a low-voltage and low-leakage planar voltage regulator tube

Abstract

A method for preparing a low-voltage and low-leakage planar voltage regulator, the steps of which include: performing chlorine-doped oxidation on a substrate to grow silicon dioxide as an initial shielding layer; performing boron diffusion on the front side of a silicon wafer to form a P+A region with a boron junction; performing surface gettering on the front and back sides of the silicon wafer to form a phosphorus-silicon glass layer on both sides of the silicon wafer; evaporating aluminum on the front side of the silicon wafer and retaining the aluminum layer on the boron diffusion region; then performing rapid annealing on the front side of the silicon wafer to form a P+B region in the diffusion region on the front side of the silicon wafer; then performing vacuum evaporation on the front and back sides of the silicon wafer to obtain a metal layer; then removing the metal layer on the front shielding oxide layer by photolithography to obtain a voltage regulator diode with low voltage and low leakage. The present application can obtain a diode chip with a low reverse breakdown voltage, improve the product current density, effectively reduce the leakage current problem, especially the leakage current at high temperature, and improve the product reliability; it can also increase the junction area of ​​its PN junction, reduce the curvature, and improve the quality of the finished product.

Description

Technical Field

[0001] The present application belongs to the technical field of semiconductor diode chips, and in particular, relates to a method for preparing a low-voltage and low-leakage planar voltage regulator. Background Art

[0002] When the reverse voltage applied to an ordinary PN junction diode is large enough, the diode will be broken down and generate a large reverse current, which will eventually cause the device to fail. The Zener diode uses the reverse breakdown of the PN junction to provide a stable voltage Vz. The main function of the Zener diode is to act as a voltage regulator to provide a stable reference voltage. It can be used in power supplies, voltmeters and other instruments. The Zener diode is a silicon PN junction element. It is different from a rectifier diode because it is designed for the reverse breakdown region. The breakdown voltage of the Zener diode can be set by controlling the degree of doping during manufacturing.

[0003] This new 2-6V low voltage planar chip is a diode device for low voltage regulation and transient protection applications in the defense, aerospace, industrial and medical markets. The low rated capacitance and low rated leakage current also make these new diodes suitable for high-speed and high-frequency electrostatic discharge (ESD) applications and portable applications to ensure longer battery life. In addition, these Zener diodes can also be used in certain transient voltage protection (TVS) applications that require low impedance and low voltage.

[0004] When the reverse voltage applied to the existing low-voltage ordinary PN junction diode is large enough, the diode will be broken down and generate a large reverse current, which will eventually lead to device failure. Therefore, how to design a method for preparing a low-voltage Zener diode that can use the reverse breakdown of the PN junction to provide a stable voltage Vz is a technical problem that needs to be solved urgently. Summary of the invention

[0005] The present application provides a method for preparing a low-voltage and low-leakage planar voltage regulator tube, which solves the technical problem in the prior art that ordinary diodes are easily broken down and generate a large reverse current when the external reverse voltage is large enough.

[0006] In order to solve at least one of the above technical problems, the technical solution adopted in this application is:

[0007] A method for preparing a low-voltage and low-leakage planar voltage regulator tube comprises the following steps:

[0008] Chlorine-doped oxidation is performed on the substrate to grow silicon dioxide as an initial shielding layer;

[0009] Boron diffusion is performed on the front side of the silicon wafer to form a P+A region with a boron junction;

[0010] Performing surface gettering on the front and back sides of the silicon wafer to form a phosphorus-silicate glass layer on both sides of the silicon wafer;

[0011] Aluminum is evaporated on the front side of the silicon wafer, and the aluminum layer on the boron diffusion area is retained; then rapid annealing is performed on the front side of the silicon wafer to form a P+B area in the diffusion area on the front side of the silicon wafer;

[0012] Vacuum evaporation is then performed on the front and back sides of the silicon wafer to obtain a metal layer; the metal layer on the front shielding oxide layer is then removed by photolithography to obtain a voltage-stabilizing diode with low voltage and low leakage.

[0013] Furthermore, the substrate is an N-type silicon substrate with a resistivity of 0.0030-0.0364Ω and a crystal orientation of (100).

[0014] Furthermore, when growing the silicon dioxide shielding layer, the double sides of the silicon wafer are treated with dry oxygen-wet oxygen-dry oxygen in sequence at 800-1200° C., wherein the first dry oxygen time is shorter than the second dry oxygen time; and the wet oxygen time is the longest; and the second dry oxygen density is higher than the wet oxygen density.

[0015] Furthermore, the first dry oxygen time is 1-3 hours; the second dry oxygen time is 2-4 hours; and the wet oxygen time is 5-10 hours.

[0016] Furthermore, before boron diffusion, photolithography is required on the shielding layer on the front side of the silicon wafer, and BOE is used to remove the shielding layer on the diffusion area window, leaving only the shielding layer on the non-diffusion area to form an isolation ring.

[0017] Furthermore, it also includes replacing BN with B2O3 through N2 / O2 at 900-1200°C and depositing it on the front side of the silicon wafer; then performing high-temperature diffusion at 1000-1260°C to form a P+A area with a boron junction on the diffusion area, and at the same time forming a thinner borosilicate glass layer on the isolation ring of the non-diffusion area.

[0018] Further, the surface gettering of the front and back sides of the silicon wafer includes:

[0019] First, the inversion layer on the back side caused by diffusion is removed by grinding and thinning method;

[0020] Then remove the silicon dioxide shielding layer on the back side;

[0021] The front and back sides of the silicon wafer are then subjected to phosphorus gettering treatment. At 1000-1200°C, a gas carrying POCL3 is deposited on the front and back sides of the silicon wafer to form a layer of phosphorus silicon glass on both the front and back sides of the silicon wafer.

[0022] Furthermore, aluminum is evaporated on the front side of the silicon wafer by selective photolithography to remove the phosphosilicate glass layer in the diffusion area on the front side of the silicon wafer; then an aluminum layer is formed on the P+ layer by high vacuum electron beam evaporation, and the aluminum layer on the non-diffusion area is removed by photolithography, leaving only the aluminum layer on the boron diffusion area.

[0023] Furthermore, the rapid annealing is to process the AL on the front side of the silicon wafer at a high temperature of 800-1000° C. to form a P+B region in the diffusion region in the front side of the silicon wafer.

[0024] Furthermore, high vacuum electron beam evaporation of metal is performed on the front and back sides of the silicon wafer to sequentially stack three metal layers of titanium, nickel and silver on both sides of the silicon wafer; and then the metal layer on the front shielding oxide layer is removed by photolithography to obtain the Zener diode.

[0025] The method for preparing a low-voltage and low-leakage planar Zener diode designed in the present application is particularly suitable for a 2-6V low-voltage and low-leakage Zener diode, and can obtain a diode chip with a low reverse breakdown voltage, thereby improving the current density of the product. This not only effectively reduces the leakage current problem, especially the leakage current at high temperature, and improves product reliability; it can also increase the junction area of ​​the PN junction, reduce the curvature, and improve the quality of the finished product. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a flow chart of a method for preparing a low-voltage and low-leakage planar voltage regulator tube in the present application;

[0027] Figure 2 is a cross-sectional view of a silicon wafer with a shielding oxide layer in the present application;

[0028] Figure 3 is a cross-sectional view of a silicon wafer after boron diffusion in this application;

[0029] Figure 4 is a cross-sectional view of a silicon wafer after phosphorus gettering in the present application;

[0030] Figure 5 is a cross-sectional view of a silicon wafer after RTA in this application;

[0031] Figure 6 is a cross-sectional view of a finished silicon wafer in this application;

[0032] Figure 7 This is a diagram of the Silvano simulation breakdown process of a diode obtained using this method;

[0033] Figure 8 This is a simulation curve of the breakdown characteristics of the diode obtained by this method when the diffusion time Time=30s and the diffusion temperature T=950K;

[0034] Fig. 9This is a simulation curve of the breakdown characteristics of the diode obtained by this method when the diffusion time Time=30s and the diffusion temperature T=1000K;

[0035] Fig.10 This is a simulation curve of the breakdown characteristics of the diode obtained by this method when the diffusion time Time=30s and the diffusion temperature T=1100K;

[0036] Fig.11 This is a simulation curve of the breakdown characteristics of the diode obtained by this method when the diffusion time Time=30s and the diffusion temperature T=1200K;

[0037] Fig.12 This is a simulation curve of the breakdown characteristics of the diode obtained by this method when the diffusion time Time=60s and the diffusion temperature T=1000K;

[0038] Fig.13 This is a simulation curve of the breakdown characteristics of the diode obtained by this method when the diffusion time Time=120s and the diffusion temperature T=1000K;

[0039] Fig.14 This is a simulation curve of the breakdown characteristics of the diode obtained by this method when the diffusion time Time=300s and the diffusion temperature T=1000K.

[0040] In the figure: 10, silicon substrate; 20, shielding layer; 30, non-diffusion area; 40, P+A area; 50, phosphosilicate glass layer; 60, P+B area; 70, metal layer. DETAILED DESCRIPTION

[0041] The present application is described in detail below with reference to the accompanying drawings and specific embodiments.

[0042] This embodiment provides a method for preparing a low-voltage and low-leakage planar voltage regulator. Figure 1 As shown,

[0043] A method for preparing a low-voltage and low-leakage planar voltage regulator tube comprises the following steps:

[0044] First, a silicon substrate 10 is obtained, wherein the silicon substrate 10 is an N-type original silicon wafer with a resistivity of 0.0030-0.0364Ω. Since the junction required for reverse breakdown is very shallow, a polished silicon wafer with a crystal orientation of (100) is selected as the substrate.

[0045] Chlorine-doped oxidation is performed on the substrate to grow silicon dioxide as an initial shielding layer 20, with the aim of forming a dense and uniform oxide layer on both sides of the substrate as a protective layer.

[0046] like Figure 2As shown, when growing the silicon dioxide shielding layer 20, the double sides of the silicon wafer are treated with dry oxygen-wet oxygen-dry oxygen in sequence at 800-1200°C, wherein the first dry oxygen time is less than the second dry oxygen time, in order to ensure the thickness of the oxide layer; and the wet oxygen time is the longest. At the same time, the density during the second dry oxygen is higher than the density during the wet oxygen, mainly to shield the impurity pollution brought by the outside world. Preferably, the first dry oxygen time is 1-3h; the second dry oxygen time is 2-4h; and the wet oxygen time is 5-10h. The first layer of dry oxygen is mainly to ensure the compactness of the oxide layer and play a role in surface passivation. The second layer of wet oxygen increases its thickness in a sufficient time, which plays a role in blocking subsequent metal ions from penetrating the entire oxide layer. Growing another layer of dry oxygen on the basis of the second layer of wet oxygen can further improve the compactness of the entire oxide layer and play a shielding role. When the second layer of wet oxygen oxide layer is treated, chlorine-doped oxidation is used during the operation to play a role in combining with metal ions, thereby reducing the leakage current effect of metal pollution.

[0047] Boron diffusion is performed on the front side of the silicon wafer to form a P+A region 40 having a boron junction.

[0048] Specifically, before boron diffusion, photolithography is required on the shielding layer 20 on the front side of the silicon wafer. BOE is used to remove the shielding layer 20 on the diffusion area window, leaving only the silicon dioxide shielding layer 20 on the non-diffusion area 30, and making the shielding layer 20 on the non-diffusion area 30 on the front side serve as an isolation ring. At this time, the position of the shielding layer 20 on the back side remains unchanged.

[0049] like Figure 3 As shown, BN is replaced with B2O3 by N2 / O2 at 900-1200°C and deposited on the front side of the silicon wafer. Then, high-temperature diffusion is performed at 1000-1260°C to form a P+A region 40 with a boron junction on the diffusion region, which can be used as an electrode. At the same time, a thin borosilicate glass layer 50 is formed on the isolation ring in the non-diffusion region 30.

[0050] Surface gettering is performed on the front and back sides of the silicon wafer to form a phosphorus-silicate glass layer 50 on both sides of the silicon wafer. Specifically, a grinding and thinning method is first used to remove the inversion layer generated by diffusion on the back side of the silicon wafer, that is, the borosilicate glass layer 50 generated during boron diffusion. At this time, there is still a silicon dioxide shielding layer 20 on the back side of the silicon wafer. When performing surface phosphorus gettering, both the front and back sides of the silicon wafer need to be treated with gettering. Therefore, it is necessary to remove the silicon dioxide shielding layer 20 on the back side by a photolithography method, and then perform phosphorus gettering on the front and back sides of the silicon wafer.

[0051] like Figure 4As shown, during the phosphorus gettering treatment, at 1000-1200°C, a gas carrying POCL3 is deposited on the front and back of the silicon wafer to form a phosphosilicate glass layer 50 on both the front and back of the silicon wafer. That is, an N+ layer, a phosphosilicate glass layer 50, is deposited on the back of the silicon wafer; accordingly, the phosphosilicate glass layer 50 formed on the front can play a role in gettering, and harmful ions such as sodium and potassium ions on the surface are adsorbed into the phosphosilicate glass layer 50, and then after the phosphosilicate glass layer 50 is removed later, these harmful ions can be removed together with the phosphosilicate glass layer 50.

[0052] First, aluminum is evaporated on the front side of the silicon wafer, and the aluminum layer on the boron diffusion region is retained; then, rapid annealing is performed on the front side of the silicon wafer to form a P+B region 60 in the diffusion region on the front side of the silicon wafer.

[0053] like Figure 5 As shown, the aluminum vaporization on the front side of the silicon wafer is to first remove the phosphorus silicon glass layer 50 in the diffusion area of ​​the front side of the silicon wafer through selective photolithography; then form an aluminum layer on the P+ layer through high vacuum electron beam evaporation, and at the same time remove the aluminum layer on the non-diffusion area 30 through photolithography, and only retain the aluminum layer on the boron diffusion area, that is, only retain the aluminum layer in the P+A area 40. Then the silicon wafer is rapidly annealed, that is, the AL alloy layer on the front side of the silicon wafer is processed at a high temperature of 800-1000°C, so as to form a P+B area 60 with a breakdown characteristic, a voltage reduction and a first-level leakage prevention function in the diffusion area of ​​the front side of the silicon wafer.

[0054] like Figure 6 As shown, finally, vacuum evaporation is performed on the front and back of the silicon wafer, and the application of three metal layers of titanium, nickel and silver makes the chip have good metal layer uniformity and surface ohmic contact. Then the metal layer on the front shielding oxide layer is removed by photolithography, and finally a voltage regulator diode with low voltage and low leakage is obtained. High vacuum electron beam evaporation of metal is performed on the front and back of the silicon wafer to sequentially stack three metal layers 70 of titanium, nickel and silver on both sides of the silicon wafer, which is the voltage regulator diode, so that the chip has a good metal layer 70, so as to improve its uniformity and surface ohmic contact, reduce the ZZK / ZZT dynamic resistance, and make its surface easy to make ohmic contact.

[0055] In this embodiment, the surface of the silicon wafer is first oxidized by the dry oxygen-wet oxygen-dry oxygen method to form a SiO2 protective layer on both sides of the silicon wafer, and a window of the diffusion area is photoetched on the front side. Boron diffusion is performed in the window of the diffusion area to form a P+A coating area with P-type diffusion on the surface of the front side of the silicon wafer. This process using shallow junction diffusion not only has a short diffusion time, a long product life and good performance; but also the silicon wafer does not warp and the product fragmentation rate is low. In addition, there is no need to dig grooves during the entire production process, which can improve the utilization rate of the silicon wafer and the current density of the product. At the same time, the glass passivation layer is not scratched, which avoids the generation of glass passivation film stress, is conducive to the firmness of the structure, reduces leakage current, especially leakage current at high temperature, and further improves the reliability of the product. Finally, the technology of high vacuum electron beam evaporation of metal is used to obtain a multi-layer metallization coating layer, which is completed in one time, with simple process and high reliability.

[0056] This method reduces leakage current mainly from three aspects, namely, initial oxidation layer, rapid annealing and phosphorus N+ layer gettering process. The initial oxidation layer is the diffusion shielding layer, gettering layer and surface passivation layer of the diode, which greatly reduces its reverse leakage current.

[0057] In the diode obtained by the preparation method of the present application, the AL alloy layer is critical to the formation of a 2-6V low voltage. At the same time, the Silvano software is used to simulate the Zener diode, so that the breakdown characteristic curve of the Zener diode under different diffusion temperatures, diffusion times and other conditions can be simulated.

[0058] like Figure 7 As shown in FIG. 1 , it is a diagram of the breakdown process of a Zener diode using Silvano simulation, where the diffusion time is time=30s and the diffusion temperature is T=1000K. It can be seen from this figure that the Zener breakdown will be formed after adopting this method, which plays a role in reducing leakage.

[0059] Furthermore, the breakdown characteristic curve of the diode obtained by the preparation method of the present application is simulated under different diffusion times and different diffusion temperatures. The results are as follows: Figure 8-Figure 14 shown.

[0060] from Figure 8-Figure 14 As shown in the figure, the curve changes very steeply during breakdown; the current increases while the voltage remains almost unchanged, and the breakdown voltage is the stable voltage Vz. This verifies the voltage-stabilizing characteristics of the Zener diode and also illustrates the correctness of the simulation program.

[0061] Figure 8 , Fig.10 , Fig.11 and Fig. 9By comparison, we can see the influence of diffusion temperature on the breakdown characteristics of Zener diodes when the diffusion time is constant. That is, within a certain range (such as T=1000-1100K in the experiment), as the temperature increases, the lattice vibration of the semiconductor is strengthened, the energy lost by the collision between the carrier and the lattice also increases, and the rate of energy accumulation from the electric field becomes slower; therefore, a stronger electric field is required to achieve the kinetic energy that can cause collision ionization. Therefore, the stable voltage (i.e., breakdown voltage) Vz of the Zener diode increases with increasing temperature. However, at T=950K and T=1200K, it is obvious that the Zener diode no longer has the voltage stabilization capability or does not fully have the voltage stabilization capability.

[0062] Fig.12 , Fig.13 and Fig. 9 By comparison, it can be seen that when the temperature is constant, the diffusion time affects the breakdown characteristics of the Zener tube. That is, the longer the diffusion time, the greater the stable voltage Vz will be. This is because the increase in diffusion time will cause the junction area of ​​the PN junction to increase, the curvature to decrease, and it will be closer to the plane junction, which will reduce the collision ionization rate and increase the breakdown voltage Vz. Of course, the increase in diffusion time cannot increase the junction area too much, so it can be seen from the comparison in the figure that the diffusion time has never been particularly important for the breakdown characteristics.

[0063] By adopting the preparation method of a low-voltage and low-leakage planar voltage regulator designed in the present application, a diode chip with a low reverse breakdown voltage can be obtained, and the current density of the product can be improved. It can not only effectively reduce the leakage current problem, especially the leakage current at high temperature, and improve the product reliability; but also increase the junction area of ​​its PN junction, reduce the curvature, and improve the quality of the finished product.

[0064] The above detailed description of the embodiments of the present application is only a preferred embodiment of the present application and cannot be considered to limit the scope of implementation of the present application. All equivalent changes and improvements made within the scope of the present application should still fall within the scope of the patent coverage of the present application.

Claims

1. A method for preparing a low-voltage and low-leakage planar voltage regulator, characterized in that the steps include: Chlorine-doped oxidation is performed on the substrate to grow silicon dioxide as an initial shielding layer; Boron diffusion is performed on the front side of the silicon wafer to form a P+A region with a boron junction; Performing surface gettering on the front and back sides of the silicon wafer to form a phosphorus-silicate glass layer on both sides of the silicon wafer; Evaporating aluminum on the front side of the silicon wafer and retaining the aluminum layer on the boron diffusion area; Then, a rapid annealing is performed on the front side of the silicon wafer to form a P+B region in the diffusion region on the front side of the silicon wafer; Then vacuum evaporation is performed on the front and back of the silicon wafer to obtain a metal layer; The metal layer on the front shielding oxide layer is then removed by photolithography to obtain a voltage-stabilizing diode with low voltage and low leakage.

2. The method for preparing a low-voltage and low-leakage planar voltage regulator according to claim 1, characterized in that: The substrate is an N-type silicon substrate with a resistivity of 0.0030-0.0364Ω and a crystal orientation of (100).

3. A method for preparing a low-voltage and low-leakage planar voltage regulator according to claim 1 or 2, characterized in that: When growing the silicon dioxide shielding layer, the double sides of the silicon wafer are treated with dry oxygen-wet oxygen-dry oxygen in sequence at 800-1200°C, wherein the first dry oxygen time is shorter than the second dry oxygen time; and the wet oxygen time is the longest; and the second dry oxygen density is higher than the wet oxygen density.

4. The method for preparing a low-voltage and low-leakage planar voltage regulator according to claim 3, characterized in that: The first dry oxygen time is 1-3h; the second dry oxygen time is 2-4h; the wet oxygen time is 5-10h.

5. A method for preparing a low-voltage and low-leakage planar voltage regulator according to any one of claims 1 to 2 and 4, characterized in that: Before boron diffusion, photolithography is required on the shielding layer on the front side of the silicon wafer. BOE is used to remove the shielding layer on the diffusion area window, leaving only the shielding layer on the non-diffusion area to form an isolation ring.

6. The method for preparing a low-voltage and low-leakage planar voltage regulator tube according to claim 5, characterized in that: It also includes replacing BN with B2O3 through N2 / O2 at 900-1200°C and depositing it on the front side of the silicon wafer; then performing high-temperature diffusion at 1000-1260°C to form a P+A area with a boron junction on the diffusion area, and at the same time forming a thinner borosilicate glass layer on the isolation ring in the non-diffusion area.

7. A method for preparing a low-voltage and low-leakage planar voltage regulator according to any one of claims 1-2, 4 and 6, characterized in that: The method of performing surface gettering on the front and back sides of the silicon wafer comprises: First, the inversion layer on the back side caused by diffusion is removed by grinding and thinning method; Then remove the silicon dioxide shielding layer on the back side; The front and back sides of the silicon wafer are then subjected to phosphorus gettering treatment. At 1000-1200°C, a gas carrying POCL3 is deposited on the front and back sides of the silicon wafer to form a layer of phosphorus silicon glass on both the front and back sides of the silicon wafer.

8. The method for preparing a low-voltage and low-leakage planar voltage regulator tube according to claim 7, characterized in that: Aluminum is evaporated on the front side of the silicon wafer through selective photolithography to remove the phosphosilicate glass layer in the diffusion area on the front side of the silicon wafer; then an aluminum layer is formed on the P+ layer through high vacuum electron beam evaporation, and the aluminum layer on the non-diffusion area is removed by photolithography, leaving only the aluminum layer on the boron diffusion area.

9. The method for preparing a low-voltage and low-leakage planar voltage regulator tube according to claim 8, characterized in that: The rapid annealing is to process the AL on the front side of the silicon wafer at a high temperature of 800-1000° C. to form a P+B region in the diffusion region in the front side of the silicon wafer.

10. The method for preparing a low-voltage and low-leakage planar voltage regulator tube according to claim 9, characterized in that: High vacuum electron beam evaporation of metal is then performed on the front and back sides of the silicon wafer to sequentially stack three metal layers of titanium, nickel and silver on both sides of the silicon wafer; the metal layer on the front shielding oxide layer is then removed by photolithography to obtain the voltage regulator diode.

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