MOSFET with Improved Reverse Recovery Characteristics, Its Fabrication Method, and Chip

Abstract

This application belongs to the technical field of power devices, and provides a MOSFET for improving reverse recovery characteristics, a preparation method thereof, and a chip. By arranging a first diode between the source layer and the control gate polysilicon layer, and arranging second diodes on both sides of the first diode between the gate layer and the control gate polysilicon layer, during the reverse conduction process of the device, a high potential is provided by the source, the diode connected to the source conducts normally, and the channel of the device is opened accordingly. At this time, the diode connected to the gate is reverse-biased to prevent leakage current from being generated. Moreover, since the voltage drop at the channel is smaller, most of the current flows through the channel, and the current passing through the PN junction between the P-type base region and the N-type drift region decreases, resulting in less minority carrier storage in the PN junction, and further reducing the reverse recovery charge, thereby optimizing the reverse recovery characteristics of the device and reducing the loss of the device during the state switching process.

Description

Technical Field

[0001] This application belongs to the technical field of power devices, and particularly relates to a MOSFET for improving reverse recovery characteristics, a preparation method thereof, and a chip. Background Art

[0002] The shielded-gate MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, SJMOSFET) has the advantages of low internal resistance, large saturation current, strong output ability, low power consumption, etc., and is widely used in the fields of digital circuits, analog circuits, power management, radio frequency applications, etc.

[0003] During the use of power devices, there will be a reverse recovery stage. The main reason for this stage is that when a reverse voltage is applied to the device, that is, the source is connected to a high potential and the drain is connected to a low potential, the PN junction between the P-type base region and the N-type drift region is forward-biased, generating a current from the source to the drain. Due to the characteristics of the PN junction, it is inevitable to store minority carrier charges in the P-type base region and the N-type drift region. When the device switches from reverse conduction to forward cut-off, this stored charge needs to flow out from the source, thereby generating a current flowing out from the source. The existence of reverse recovery charge will affect the normal use of the device and increase the loss of the device during the state switching process. Summary of the Invention

[0004] In order to solve the above technical problems, the embodiments of this application provide a MOSFET for improving reverse recovery characteristics, a preparation method thereof, and a chip, which can optimize the reverse recovery characteristics of the MOSFET device and reduce the loss of the device during the state switching process.

[0005] The first aspect of the embodiments of this application provides a MOSFET for improving reverse recovery characteristics, including:

[0006] An N-type substrate;

[0007] An N-type drift region, where the N-type drift region is a concave structure;

[0008] A first dielectric material layer and a shielded-gate polysilicon layer, where the first dielectric material layer is disposed on the inner wall of the groove of the N-type drift region, and the first dielectric material layer is used to wrap the shielded-gate polysilicon layer;

[0009] A control gate dielectric material layer and a control gate polysilicon layer, formed in the groove of the N-type drift region, and the control gate dielectric material layer wraps the control gate polysilicon layer;

[0010] A first P-type base region and a second P-type base region, where the first P-type base region and the second P-type base region are in an L-shaped structure and are respectively disposed on both sides of the N-type drift region;

[0011] A first N-type doped region and a second N-type doped region, where the first N-type doped region is located on the horizontal portion of the first P-type base region of the L-shaped structure and is in contact with the control gate dielectric material layer, and the second N-type doped region is located on the horizontal portion of the second P-type base region of the L-shaped structure and is in contact with the control gate dielectric material layer;

[0012] A drain layer, which is disposed on the back surface of the N-type substrate;

[0013] A source layer, which is in contact with the first N-type doped region, the second N-type doped region, the first P-type base region, and the second P-type base region. Moreover, a first diode is further disposed between the source layer and the control gate polysilicon layer;

[0014] A gate layer, which is in contact with the control gate polysilicon layer through a first gate via hole and a second gate via hole on the control gate dielectric material layer; a second diode is further disposed between the gate layer and the control gate polysilicon layer.

[0015] In some embodiments, a first Schottky metal layer is disposed between the source layer and the control gate polysilicon layer, and a Schottky contact is formed between the first Schottky metal layer and the control gate polysilicon layer to form the first diode; a second Schottky metal layer is disposed between the gate layer and the control gate polysilicon layer, and a Schottky contact is formed between the second Schottky metal layer and the control gate polysilicon layer to form the second diode.

[0016] In some embodiments, a first P-type doped layer is disposed between the source layer and the control gate polysilicon layer, and a PN junction is formed between the first P-type doped layer and the control gate polysilicon layer to form the first diode; a second P-type doped layer is disposed between the gate layer and the control gate polysilicon layer, and a PN junction is formed between the second P-type doped layer and the control gate polysilicon layer to form the second diode.

[0017] In some embodiments, a second dielectric material layer is further disposed between the first dielectric material layer and the shield gate polysilicon layer, and the dielectric constant of the second dielectric material layer is greater than that of the first dielectric material layer.

[0018] In some embodiments, the dielectric constant of the dielectric material on both sides of the shield gate polysilicon layer is greater than that of the dielectric material on both sides of the control gate polysilicon layer.

[0019] In some embodiments, the thickness of the dielectric material on both sides of the shield gate polysilicon layer is greater than that of the dielectric material on both sides of the control gate polysilicon layer.

[0020] In some embodiments, the width of the control gate polysilicon layer is greater than the width of the shield gate polysilicon layer.

[0021] In some embodiments, the shield gate polysilicon layer has a stepped structure, and the width of the shield gate polysilicon layer gradually increases from the drain layer to the source layer.

[0022] A second aspect of the embodiments of the present application further provides a method for manufacturing a MOSFET for improving reverse recovery characteristics, the manufacturing method including:

[0023] Epitaxially form an N-type drift layer on the front surface of the N-type substrate;

[0024] Form a first deep groove in the central region of the N-type drift layer through an etching process to form a concave N-type drift region;

[0025] Form a first dielectric material layer in sequence along the inner wall of the N-type drift region to obtain a second deep groove, and fill the second deep groove with a polysilicon layer material to obtain a shield gate polysilicon layer; the first dielectric material layer is used to wrap the shield gate polysilicon layer;

[0026] Continue to form a control gate dielectric material layer and a control gate polysilicon layer in the groove of the N-type drift region; the control gate dielectric material layer wraps the control gate polysilicon layer;

[0027] Inject P-type doping ions into the sides of the N-type drift region to form a first P-type base region and a second P-type base region; the first P-type base region and the second P-type base region are respectively arranged on both sides of the N-type drift region;

[0028] Inject N-type doping ions into partial regions of the first P-type base region and the second P-type base region to form a first N-type doped region and a second N-type doped region, and make the first P-type base region and the second P-type base region in an L-shaped structure; the first N-type doped region is located on the horizontal part of the L-shaped first P-type base region and is in contact with the control gate dielectric material layer, and the second N-type doped region is located on the horizontal part of the L-shaped second P-type base region and is in contact with the control gate dielectric material layer;

[0029] Form a source layer in contact with the first N-type doped region, the second N-type doped region, the first P-type base region, and the second P-type base region; a first diode is formed between the source layer and the control gate polysilicon layer;

[0030] Form a gate layer in contact with the control gate polysilicon layer through a first gate via hole and a second gate via hole on the control gate dielectric material layer; a second diode is formed between the gate layer and the control gate polysilicon layer;

[0031] Form a drain layer on the back surface of the N-type substrate.

[0032] In a third aspect of the embodiments of the present application, a chip is further provided, including a MOSFET for improving reverse recovery characteristics as described in any one of the above embodiments.

[0033] Advantages of the embodiments of the present application: By providing a first diode between the source layer and the control gate polysilicon layer, and providing second diodes on both sides of the first diode between the gate layer and the control gate polysilicon layer, during the reverse conduction of the device, a high potential is provided by the source, the diode connected to the source conducts normally, and the channel of the device is opened accordingly. At this time, the diode connected to the gate is reverse-biased, preventing leakage current from being generated. Moreover, since the voltage drop at the channel is smaller, most of the current flows through the channel, and the current passing through the PN junction between the P-type base region and the N-type drift region decreases, resulting in less minority carrier storage in the PN junction, and further reducing the reverse recovery charge, thereby optimizing the reverse recovery characteristics of the device and reducing the loss of the device during the state switching process. Description of the Drawings

[0034] Figure 1 is a first schematic structural diagram of a MOSFET for improving reverse recovery characteristics provided by an embodiment of the present application;

[0035] Figure 2 is a second schematic structural diagram of a MOSFET for improving reverse recovery characteristics provided by an embodiment of the present application;

[0036] Figure 3 is a third schematic structural diagram of a MOSFET for improving reverse recovery characteristics provided by an embodiment of the present application;

[0037] Figure 4 is a schematic flowchart of a manufacturing method of a MOSFET for improving reverse recovery characteristics provided by an embodiment of the present application;

[0038] Figure 5 is a schematic diagram of forming an N-type drift layer on an N-type substrate layer provided by an embodiment of the present application;

[0039] Figure 6 is a schematic diagram of forming an N-type drift region provided by an embodiment of the present application;

[0040] Figure 7 is a schematic diagram of forming a first dielectric material layer in a first deep trench provided by an embodiment of the present application;

[0041] Figure 8 is a schematic diagram of forming a shielding gate polysilicon layer provided by an embodiment of the present application;

[0042] Figure 9 is a schematic diagram of forming a control gate dielectric material layer provided by an embodiment of the present application;

[0043] Figure 10 It is a schematic diagram of forming a control gate polysilicon layer, a first P-type base region, a second P-type base region, a first N-type doping region, and a second N-type doping region provided by an embodiment of the present application;

[0044] Figure 11 It is a schematic diagram of forming a source layer and a drain layer provided by an embodiment of the present application. Detailed implementation manners

[0045] In order to make the technical problems, technical solutions, and beneficial effects to be solved by the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0046] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0047] It should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application.

[0048] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality" means one or more than one, unless otherwise specifically defined.

[0049] The shield-gate MOSFET has the advantages of low internal resistance, large saturation current, strong output ability, low power consumption, etc., and is widely used in the fields of digital circuits, analog circuits, power management, radio frequency applications, etc. During the use of power devices, there will be a reverse recovery stage. The main reason for this stage is that when a reverse voltage is applied to the device, that is, the source is connected to a high potential and the drain is connected to a low potential, the PN junction between the P-type base region and the N-type drift region is forward-biased, generating a current from the source to the drain. Due to the characteristics of the PN junction, it is inevitable to store minority carrier charges in the P-type base region and the N-type drift region. When the device switches from reverse conduction to forward cutoff, this stored charge needs to flow out from the source, thereby generating a current flowing out from the source. The existence of reverse recovery charge will affect the normal use of the device and increase the loss of the device during the state transition process.

[0050] An embodiment of the present application provides a MOSFET for improving reverse recovery characteristics. Refer to Figure 1 As shown, the MOSFET structure in the embodiment of the present application includes: an N-type substrate 210, an N-type drift region 220, a first dielectric material layer 310, a shield-gate polysilicon layer 311, a control-gate dielectric material layer 320, a control-gate polysilicon layer 321, a first P-type base region 411, a second P-type base region 412, a first N-type doped region 421, a second N-type doped region 422, a drain layer 110, a source layer 121, and a gate layer 131.

[0051] Among them, the N-type drift region 220 is a concave structure, the first dielectric material layer 310 is disposed on the inner wall of the groove of the N-type drift region 220, and the first dielectric material layer 310 is used to wrap the shield-gate polysilicon layer 311; the control-gate dielectric material layer 320 and the control-gate polysilicon layer 321 are formed in the groove of the N-type drift region 220, and the control-gate dielectric material layer 320 wraps the control-gate polysilicon layer 321; the first P-type base region 411 and the second P-type base region 412 are in an L-shaped structure and are respectively disposed on both sides of the N-type drift region 220; the first N-type doped region 421 is located on the horizontal part of the first P-type base region 411 of the L-shaped structure and is in contact with the control-gate dielectric material layer 320, and the second N-type doped region 422 is located on the horizontal part of the second P-type base region 412 of the L-shaped structure and is in contact with the control-gate dielectric material layer 320; the drain layer 110 is disposed on the back surface of the N-type substrate 210; the source layer 121 is in contact with the first N-type doped region 421, the second N-type doped region 422, the first P-type base region 411, and the second P-type base region 412, and a first diode 512 is further disposed between the source layer 121 and the control-gate polysilicon layer 321; the gate layer 131 is in contact with the control-gate polysilicon layer 321 through a first gate via hole and a second gate via hole on the control-gate dielectric material layer 320; a second diode 511 is further disposed between the gate layer 131 and the control-gate polysilicon layer 321.

[0052] In the present application, a first diode 512 is provided between the source layer 121 and the control gate polysilicon layer 321, and second diodes 511 located on both sides of the first diode 512 are provided between the gate layer 131 and the control gate polysilicon layer 321. During the reverse conduction of the device, a high potential is provided by the source, the diode connected to the source conducts normally, and the channel of the device is opened accordingly. At this time, the diode connected to the gate is reverse-biased, preventing leakage current from being generated. Moreover, since the voltage drop at the channel is smaller, most of the current flows through the channel, and the current passing through the PN junction between the P-type base region and the N-type drift region 220 decreases, resulting in less minority carrier storage in the PN junction, and further reducing the reverse recovery charge, thereby optimizing the reverse recovery characteristics of the device and reducing the loss of the device during the state transition process.

[0053] In an embodiment of the present application, a first Schottky metal layer is provided between the source layer 121 and the control gate polysilicon layer 321, and a Schottky contact is formed between the first Schottky metal layer and the control gate polysilicon layer 321 to form the first diode 512. That is, the first diode 512 is a Schottky diode.

[0054] In an embodiment of the present application, a second Schottky metal layer is provided between the gate layer 131 and the control gate polysilicon layer 321, and a Schottky contact is formed between the second Schottky metal layer and the control gate polysilicon layer 321 to form the second diode 511. That is, the second diode 511 can also be a Schottky diode.

[0055] In this embodiment, a control gate-source via and a control gate-gate via are provided on the first dielectric material layer 310. A first Schottky metal layer is formed in the control gate-source via, and a second Schottky metal layer is formed in the control gate-gate via. Schottky contacts are formed between the first Schottky metal layer and the second Schottky metal layer and the control gate polysilicon layer 321. During the reverse conduction of the device, a high potential is provided by the source, and the Schottky junction connected to the source can conduct normally, and the channel of the device is opened accordingly. At this time, the Schottky junction connected to the gate is reverse-biased, preventing leakage current from being generated. In this case, although due to the inherent properties of the PN junction, the PN junction between the P-type base region (i.e., the first P-type base region 411 and the second P-type base region 412) and the N-type drift region 220 is forward-biased and still has a voltage drop of about 0.6 - 0.8V, however, the voltage drop at the channel is smaller. Therefore, most of the current flows through the channel, and the current passing through the PN junction between the P-type base region (i.e., the first P-type base region 411 and the second P-type base region 412) and the N-type drift region 220 decreases. As the current passing through the PN junction between the P-type base region (i.e., the first P-type base region 411 and the second P-type base region 412) and the N-type drift region 220 decreases, the minority carrier storage in the PN junction becomes less, and further the reverse recovery charge decreases, optimizing the reverse recovery characteristics of the device.

[0056] Moreover, in the forward conduction state of the device, the Schottky junction connected to the gate metal can normally access the gate signal to turn on the device. At the same time, the Schottky junction connected to the source is reverse-biased to prevent gate leakage, so that the forward conduction of the device is not affected.

[0057] As shown in Table 1 below, when the MOSFET (improved structure) provided by the embodiment of the present application for improving the reverse recovery characteristics is simulated and compared with the traditional structure (the structure without the first diode 512 and the second diode 511), it can be seen that the on-resistance Ron, saturation current Idsat, and breakdown voltage BV of the MOSFET provided by the embodiment of the present application for improving the reverse recovery characteristics remain unchanged compared with those of the traditional structure. However, the reverse current Irr and reverse recovery time Tr are reduced by 33.85% and 12.20% respectively, and the reverse recovery charge Qrr is reduced by 42.11%. From the simulation results, the structure proposed in the present application can significantly optimize the reverse recovery characteristics of the device without affecting the conduction characteristics and turn-off characteristics of the device.

[0058] Table 1:

[0059]

[0060] In the embodiment of the present application, in addition to using the Schottky diode to improve the reverse recovery characteristics of the device, the PN junction can also be used to shield the signal to optimize the reverse recovery characteristics of the device.

[0061] Specifically, in one embodiment, a first P-type doping layer is provided between the source layer 121 and the control gate polysilicon layer 321, and a PN junction is formed between the first P-type doping layer and the control gate polysilicon layer 321 to form the first diode 512.

[0062] In one embodiment, a second P-type doping layer is provided between the gate layer 131 and the control gate polysilicon layer 321, and a PN junction is formed between the second P-type doping layer and the control gate polysilicon layer 321 to form the second diode 511.

[0063] In this embodiment, a control gate source via and a control gate via are provided on the first dielectric material layer 310. A first P-type doped layer is formed in the control gate source via, and a second P-type doped layer is formed in the control gate via. A PN junction is formed between the first P-type doped layer and the second P-type doped layer and the control gate polysilicon layer 321. During the reverse conduction of the device, the source provides a high potential, and the PN junction connected to the source can conduct normally, causing the channel of the device to open. At this time, the PN junction connected to the gate is reverse-biased to prevent leakage current. In this case, although due to the inherent properties of the PN junction, the PN junction between the P-type base region (i.e., the first P-type base region 411 and the second P-type base region 412) and the N-type drift region 220 is forward-biased and there is still a voltage drop of about 0.6 - 0.8V, the voltage drop at the channel is smaller. Therefore, most of the current flows through the channel, and the current passing through the PN junction between the P-type base region (i.e., the first P-type base region 411 and the second P-type base region 412) and the N-type drift region 220 decreases. As the current passing through the PN junction between the P-type base region (i.e., the first P-type base region 411 and the second P-type base region 412) and the N-type drift region 220 decreases, the minority carrier storage in the PN junction becomes less, and thus the reverse recovery charge decreases, optimizing the reverse recovery characteristics of the device.

[0064] Moreover, in the forward conduction state of the device, the Schottky junction connected to the gate metal can normally access the gate signal to turn on the device, while the Schottky junction connected to the source is reverse-biased to prevent gate leakage, so that the forward conduction of the device is not affected.

[0065] Since traditional shield-gate MOSFETs usually use silicon dioxide (SiO 2 ) as the gate oxide layer of the shield gate. This design can improve the breakdown voltage of the device to a certain extent. However, due to the physical property of the relatively low dielectric constant of silicon dioxide, the thickness of the gate oxide layer of the shield gate cannot be too thick, otherwise the depletion of the drift region by the shield gate cannot be achieved. And although the thin SiO 2 layer can achieve a good auxiliary depletion effect, it will cause breakdown at the thin SiO 2 of the device. For the above two reasons, the breakdown voltage of the device is relatively low.

[0066] To increase the breakdown voltage of the device, as Figure 2 shown, in an embodiment of the present application, a second dielectric material layer 312 may further be provided between the first dielectric material layer 310 and the shield gate polysilicon layer 311, and the dielectric constant of the second dielectric material layer 312 is greater than that of the first dielectric material layer 310.

[0067] In an embodiment of the present application, by disposing a second dielectric material layer 312 between the first dielectric material layer 310 and the shield gate polysilicon layer 311, and the dielectric constant of the second dielectric material layer 312 is greater than that of the first dielectric material layer 310, the composite dielectric material layer formed by combining the first dielectric material layer 310 and the second dielectric material layer 312 is achieved to isolate the shield gate polysilicon layer 311 from the bottom and both side walls of the groove of the N-type drift region 220, and the same auxiliary depletion effect can be achieved in the case of a thicker shield gate oxide layer, thereby enhancing the breakdown voltage at the bottom of the shield gate. Moreover, due to the proximity of the auxiliary depletion effect, the influence on the on-resistance of the device is relatively low.

[0068] In an embodiment of the present application, the dielectric constant of the first dielectric material layer or the second dielectric material layer on both sides of the shield gate polysilicon layer 311 is greater than that of the control gate dielectric material layer on both sides of the control gate polysilicon layer 321.

[0069] In an embodiment of the present application, the dielectric constant of the control gate dielectric material layer 320 may be equal to that of the dielectric material of the first dielectric material layer 310.

[0070] In an embodiment of the present application, as Figure 1 shown, the thickness of the dielectric material on both sides of the shield gate polysilicon layer 311 is greater than that of the dielectric material on both sides of the control gate polysilicon layer 321.

[0071] In an embodiment of the present application, as Figure 1 shown, the width of the control gate polysilicon layer 321 is greater than that of the shield gate polysilicon layer 311.

[0072] In an embodiment of the present application, as combined with Figure 3 shown, the shield gate polysilicon layer 311 may be a stepped structure, and the width of the shield gate polysilicon layer 311 gradually increases in the direction from the drain layer 110 to the source layer 121; correspondingly, the thickness of the second dielectric material layer 312 gradually decreases in the direction from the drain layer 110 to the source layer 121 to further optimize the electric field of the N-type drift layer.

[0073] For example, as Figure 3 shown, the shield gate polysilicon layer 311 is a stepped structure including one step, and the width of the shield gate polysilicon layer 311 near the drain layer 110 is smaller than the width near the source layer 121.

[0074] In an embodiment of the present application, the first dielectric material layer 310 and the second dielectric material layer 312 are in a stepped structure. That is, the thickness change of the first dielectric material layer 310 changes with the thickness change of the second dielectric material layer 312, so that the thickness difference between the first dielectric material layer 310 and the second dielectric material layer 312 at different depths is the same.

[0075] In some embodiments, the thickness of the second dielectric material layer 312 is less than the thickness of the first dielectric material layer 310.

[0076] In one embodiment of the present application, as Figure 1 shown, the control gate dielectric material layer 320 may be located on the upper side of the first dielectric material layer 310 and the shield gate polysilicon layer 311, such that the control gate polysilicon layer 321 and the shield gate polysilicon layer 311 are arranged in an up-and-down distribution structure. Moreover, the bottom of the control gate dielectric material layer 320 may form a closed cavity with the first dielectric material layer 310, and the shield gate polysilicon layer 311 and the second dielectric material layer 312 are located within this closed cavity.

[0077] In the embodiments of the present application, in addition to the up-and-down distribution structure, the control gate polysilicon layer 321 and the shield gate polysilicon layer 311 may also be arranged in a left-middle-right distribution structure. The present application does not limit the distribution manner of the shield gate polysilicon layer 311 and the control gate polysilicon layer 321.

[0078] In the embodiments of the present application, the shield gate polysilicon layer 311 and the control gate polysilicon layer 321 are made of N-type polysilicon material.

[0079] As Figure 4 shown, in the second aspect of the embodiments of the present application, a method for manufacturing a MOSFET with improved reverse recovery characteristics is further provided, and this manufacturing method includes step 100 to step 900.

[0080] Step 100, epitaxially form an N-type drift layer 221 on the front surface of the N-type substrate 210.

[0081] As Figure 5 shown, an N-type drift layer 221 with a thickness greater than that of the N-type substrate 210 can be formed by epitaxy on the front surface of the N-type substrate 210.

[0082] In one embodiment of the present application, the thickness of the N-type substrate 210 is 1 - 3 um, the concentration of N-type doping ions is 1e21 - 1.5e21 cm -3 , the thickness of the N-type drift layer 221 is 10 - 15 um, and the concentration of N-type doping ions is 1e15 ~ 2e17 cm-3.

[0083] Step 200, form a first deep trench in the central region of the N-type drift layer through an etching process to form a concave-shaped N-type drift region 220.

[0084] As Figure 6 shown, the depth of the first deep trench may be greater than one-half of the depth of the N-type drift layer 221.

[0085] In one embodiment of the present application, the depth of the first deep trench is 4.5 - 7.5 um, and the width is 0.7 - 1.2 um.

[0086] Step 300: Sequentially form a first dielectric material layer 310 along the inner wall of the N-type drift region 220 to obtain a second deep trench, and fill the second deep trench with a polysilicon layer material to obtain a shield gate polysilicon layer 311; the first dielectric material layer 310 is used to wrap the shield gate polysilicon layer 311.

[0087] As Figure 7 shown, when the control gate polysilicon layer 321 and the shield gate polysilicon layer 311 are in an up-and-down distribution structure, the first dielectric material layer 310 can be formed first through the inner wall of the N-type drift region 220 by thermal oxidation process and deposition process to obtain a second deep trench, that is, Figure 7 the structure of, wherein, the thickness of the first dielectric material layer 310 can be 0.1 - 0.3 um. Then, form a shield gate polysilicon layer 311 in the groove of the second deep trench, and etch the first deep trench by an etching process to obtain Figure 8 the structure of. Among them, the thickness of the shield gate polysilicon layer 311 formed in the groove of the first dielectric material layer 310 can be 0.5 - 5 um, and the back-etching depth is about 1.5 um to obtain Figure 8 the structure of.

[0088] Step 400: Continuously form a control gate dielectric layer 320 and a control gate polysilicon layer 321 in the groove of the N-type drift region 220; the control gate dielectric layer 320 wraps the control gate polysilicon layer 321.

[0089] Form a concave control gate dielectric layer 320 in the first deep trench to obtain Figure 9 the structure of, then, as Figure 10 shown, fill the concave structure of the control gate dielectric layer 320 with a polysilicon layer material to obtain a control gate polysilicon layer 321.

[0090] For example, first fill the first deep trench with SiO 2 and back-etch to form an oxide layer with a sidewall thickness of 0.2 - 0.4 um, then form a gate oxide layer with a bottom thickness of about 0.5 - 1 um through a gate oxidation process, and further obtain Figure 9 the control gate dielectric layer 320 in, finally, deposit N-type polysilicon material in the control gate dielectric layer 320 to form a control gate polysilicon layer 321, wherein, the thickness of the control gate polysilicon layer 321 can be 0.5 - 5 um, and the doping concentration is 1e18 - 1e21 cm -3 .

[0091] It should be noted that in the embodiments of the present application, in addition to the vertical distribution structure between the control gate polysilicon layer 321 and the shielding gate polysilicon layer 311, a left-middle-right distribution structure can also be adopted. For example, the control gate dielectric material layer 320 can be located on the left and right sides of the first dielectric material layer 310 and the shielding gate polysilicon layer 311, and the control gate polysilicon layer 321 is located on both sides of the shielding gate polysilicon layer 311, so that a left-middle-right distribution structure is formed between the control gate polysilicon layer 321 and the shielding gate polysilicon layer 311. The present application does not limit the distribution manner of the shielding gate polysilicon layer 311 and the control gate polysilicon layer 321.

[0092] Step 500: Inject P-type doping ions into the side portions of the N-type drift region 220 to form a first P-type base region 411 and a second P-type base region 412, and the first P-type base region 411 and the second P-type base region 412 are respectively arranged on both sides of the N-type drift region 220.

[0093] In the embodiments of the present application, as Figure 10 shown, the widths of the first P-type base region 411 and the second P-type base region 412 can be equal to the widths of the two side portions of the N-type drift region 220 having a concave structure, and the depths of the first P-type base region 411 and the second P-type base region 412 can be equal to the depth of the control gate polysilicon layer 321.

[0094] Step 600: Inject N-type doping ions into partial regions of the first P-type base region 411 and the second P-type base region 412 to form a first N-type doped region 421 and a second N-type doped region 422, and make the first P-type base region and the second P-type base region have an L-shaped structure; the first N-type doped region is located on the horizontal portion of the L-shaped first P-type base region and is in contact with the control gate dielectric material layer 320, and the second N-type doped region 422 is located on the horizontal portion of the L-shaped second P-type base region 412 and is in contact with the control gate dielectric material layer 320.

[0095] As Figure 10 shown, in an embodiment of the present application, the first N-type doped region 421 and the second N-type doped region 422 are located on both sides of the control gate dielectric material layer 320, and the widths of the first N-type doped region 421 and the second N-type doped region 422 are greater than one half of the widths of the first P-type base region 411 and the second P-type base region 412.

[0096] Step 700: Form a source electrode layer 121 in contact with the first N-type doped region 421, the second N-type doped region 422, the first P-type base region 411, and the second P-type base region 412; a first diode 512 is formed between the source electrode layer 121 and the control gate polysilicon layer 321.

[0097] Step 800: Form a gate layer 131 in which a first gate via hole and a second gate via hole on the control gate dielectric material layer 320 are in contact with the control gate polysilicon layer 321; a second diode 511 is formed between the gate layer 131 and the control gate polysilicon layer 321.

[0098] As Figure 11 and Figure 1 shown, in an embodiment of the present application, a control gate dielectric material may be deposited on the control gate dielectric material layer 320 and the control gate polysilicon layer 321 to form a new control gate dielectric material layer 320 covering the control gate polysilicon layer 321 and communicating with the control gate dielectric material layer 320 formed in step 400. Then, by drilling holes in the new control gate dielectric material layer 320, a gate layer 131 in which a first gate via hole and a second gate via hole on the control gate dielectric material layer 320 are in contact with the control gate polysilicon layer 321 is formed, a first diode 512 is formed between the source layer 121 and the control gate polysilicon layer 321, and a second diode 511 is disposed between the gate layer 131 and the control gate polysilicon layer 321.

[0099] Step 900: Form a drain layer 110 on the back surface of the N-type substrate 210.

[0100] A third aspect of the embodiments of the present application further provides a chip, including a MOSFET with improved reverse recovery characteristics as described in any one of the above embodiments.

[0101] The beneficial effects of the embodiments of the present application: By providing a first diode between the source layer and the control gate polysilicon layer, and providing a second diode on both sides of the first diode between the gate layer and the control gate polysilicon layer, during the reverse conduction of the device, a high potential is provided by the source, the diode connected to the source conducts normally, and the channel of the device is opened accordingly. At this time, the diode connected to the gate is reverse-biased to prevent leakage current. Moreover, since the voltage drop at the channel is smaller, most of the current flows through the channel, and the current passing through the PN junction between the P-type base region and the N-type drift region decreases, resulting in less minority carrier storage in the PN junction, and thus reducing the reverse recovery charge, thereby optimizing the reverse recovery characteristics of the device and reducing the loss of the device during the state switching process.

[0102] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, only the above-mentioned division of each doping region and device is used as an example. In actual applications, the above functions can be allocated to different doping regions and devices as needed, that is, the internal structure of the device is divided into different doping regions to complete all or part of the functions described above. Each doping region and device in the embodiments can be integrated in one unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0103] In addition, the specific names of the respective doped regions and devices are only for the convenience of mutual distinction and are not used to limit the protection scope of this application.

[0104] In the above embodiments, the descriptions of the respective embodiments each have their own focuses. For the parts not detailed or recorded in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0105] In addition, in each embodiment of this application, the respective doped regions may be integrated in one unit, may exist physically separately for each unit, or two or more units may be integrated in one unit.

[0106] The above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit the same; although this application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they may still modify the technical solutions recorded in the foregoing respective embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of each embodiment of this application and should all be included within the protection scope of this application.

Claims

1. A MOSFET with improved reverse recovery characteristics, characterized in that: include: N-type substrate; An N-type drift region, wherein a groove is provided in the N-type drift region; A first dielectric material layer and a shielding gate polysilicon layer, wherein the first dielectric material layer is disposed on an inner wall of the groove of the N-type drift region, and the first dielectric material layer is used to wrap the shielding gate polysilicon layer; A control gate dielectric material layer and a control gate polysilicon layer are formed in the groove of the N-type drift region, and the control gate dielectric material layer wraps the control gate polysilicon layer; A first P-type base region and a second P-type base region, wherein the first P-type base region and the second P-type base region are in an L-shaped structure and are respectively disposed on two sides of the N-type drift region; a first N-type doping region and a second N-type doping region, wherein the first N-type doping region is located on a horizontal portion of the first P-type base region of the L-shaped structure and contacts the control gate dielectric material layer, and the second N-type doping region is located on a horizontal portion of the second P-type base region of the L-shaped structure and contacts the control gate dielectric material layer; A drain layer, wherein the drain layer is disposed on the back side of the N-type substrate; a source layer, contacting the first N-type doping region, the second N-type doping region, the first P-type base region, and the second P-type base region, and a first diode is further provided between the source layer and the control gate polysilicon layer; A gate layer, which contacts the control gate polysilicon layer through a first gate through hole and a second gate through hole on the control gate dielectric material layer; a second diode is also provided between the gate layer and the control gate polysilicon layer; A first Schottky metal layer is disposed between the source layer and the control gate polysilicon layer, and a Schottky contact is formed between the first Schottky metal layer and the control gate polysilicon layer to form the first diode; a second Schottky metal layer is disposed between the gate layer and the control gate polysilicon layer, and a Schottky contact is formed between the second Schottky metal layer and the control gate polysilicon layer to form the second diode; The shielding gate polysilicon layer is a stepped structure, and the width of the shielding gate polysilicon layer gradually increases from the drain layer to the source layer.

2. The MOSFET with improved reverse recovery characteristics according to claim 1, wherein: A second dielectric material layer is further disposed between the first dielectric material layer and the shielding gate polysilicon layer, and the dielectric constant of the second dielectric material layer is greater than the dielectric constant of the first dielectric material layer.

3. The MOSFET with improved reverse recovery characteristics according to claim 1, wherein: The dielectric constant of the first dielectric material layer on both sides of the shielding gate polysilicon layer is greater than the dielectric constant of the control gate dielectric material layer on both sides of the control gate polysilicon layer.

4. The MOSFET with improved reverse recovery characteristics according to claim 3, characterized in that: The thickness of the first dielectric material layer on both sides of the shielding gate polysilicon layer is greater than the thickness of the control gate dielectric material layer on both sides of the control gate polysilicon layer.

5. The MOSFET with improved reverse recovery characteristics according to claim 1, wherein: The width of the control gate polysilicon layer is greater than the width of the shield gate polysilicon layer.

6. A method for preparing a MOSFET with improved reverse recovery characteristics, characterized in that: The preparation method comprises: Epitaxially forming an N-type drift layer on the front side of the N-type substrate; Forming a first deep trench in the central region of the N-type drift layer by etching to form an N-type drift region with a concave structure; A first dielectric material layer is sequentially formed along the inner wall of the first deep groove to obtain a second deep groove, and a polysilicon layer material is filled in the second deep groove to obtain a shielding gate polysilicon layer; the first dielectric material layer is used to wrap the shielding gate polysilicon layer; Continue to form a control gate dielectric material layer and a control gate polysilicon layer in the first deep trench; the control gate dielectric material layer wraps the control gate polysilicon layer; Implanting P-type doping ions into the side of the N-type drift region to form a first P-type base region and a second P-type base region; the first P-type base region and the second P-type base region are respectively arranged on both sides of the N-type drift region; N-type doping ions are implanted into partial regions of the first P-type base region and the second P-type base region to form a first N-type doping region and a second N-type doping region, and the first P-type base region and the second P-type base region are formed into an L-shaped structure; the first N-type doping region is located on a horizontal portion of the first P-type base region of the L-shaped structure and is in contact with the control gate dielectric material layer, and the second N-type doping region is located on a horizontal portion of the second P-type base region of the L-shaped structure and is in contact with the control gate dielectric material layer; forming a source layer in contact with the first N-type doping region, the second N-type doping region, the first P-type base region, and the second P-type base region; a first diode is formed between the source layer and the control gate polysilicon layer; forming a gate layer contacting the control gate polysilicon layer through a first gate through hole and a second gate through hole on the control gate dielectric material layer; a second diode is formed between the gate layer and the control gate polysilicon layer; A drain layer is formed on the back side of the N-type substrate; wherein a first Schottky metal layer is arranged between the source layer and the control gate polysilicon layer, and a Schottky contact is formed between the first Schottky metal layer and the control gate polysilicon layer to form the first diode; and a second Schottky metal layer is arranged between the gate layer and the control gate polysilicon layer, and a Schottky contact is formed between the second Schottky metal layer and the control gate polysilicon layer to form the second diode.

7. A chip, characterized in that: A MOSFET with improved reverse recovery characteristics comprising the MOSFET according to any one of claims 1 to 5.

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